CC1101.cpp

00001 
00002 #include "CC1101.h"
00003 
00004 #define RF_0db
00005 //#define RF_10db
00006 ///////////////////////////////////////////////////////////////////////////////////////
00007 CC1101::CC1101(PinName mosi, PinName miso, PinName clk, PinName csn, PinName RDmiso, PinName gdo0, PinName gdo2):
00008     _spi(mosi, miso, clk), _csn(csn),  _RDmiso(RDmiso), _gdo0(gdo0), _gdo2(gdo2)
00009 {
00010     _csn = 1;
00011 
00012     // Setup the spi for 8 bit data, high steady state clock,
00013     // second edge capture, with a 1MHz clock rate
00014     _spi.format(8,0);
00015     _spi.frequency(1000000);
00016 
00017     POWER_UP_RESET_CCxxx0();
00018     Strobe(CCxxx0_SRX);
00019 }
00020 ///////////////////////////////////////////////////////////////////////////////////////
00021 RF_SETTINGS rfSettings = {      // 433Mhz, 9600Bauds
00022     0x06,  // FSCTRL1       Frequency Synthesizer Control - IF:152.343Khz
00023     0x07,  // IOCFG0        GDO0 Output Pin Configuration - Packet received and CRC OK
00024     0x00,  // FSCTRL0       Frequency Synthesizer Control - Freq offset
00025     0x10,  // FREQ2         Frequency Control Word, High Byte - 433.999 Mhz
00026     0xB1,  // FREQ1         Frequency Control Word, Middle Byte
00027     0x3B,  // FREQ0         Frequency Control Word, Low Byte
00028     0xF8,  // MDMCFG4       Modem Configuration - BW: 58.035Khz
00029     0x83,  // MDMCFG3       Modem Configuration - 9595 Baud
00030     0x13,  // MDMCFG2       Modem Configuration - 30/32 sync word bits - Manchester disable - GFSK - Digital DC filter enable
00031     0x22,  // MDMCFG1       Modem Configuration - num of preamble bytes:4 - FEC disable
00032     0xF8,  // MDMCFG0       Modem Configuration - Channel spacing: 199.951Khz
00033     0x00,  // CHANNR        Channel Number
00034     0x15,  // DEVIATN       Modem Deviation Setting - 5.157Khz
00035     0x56,  // FREND1        Front End RX Configuration
00036     0x10,  // FREND0        Front End TX Configuration
00037     0x18,  // MCSM0         Main Radio Control State Machine Configuration - PO timeout: 64(149-155us) - Auto calibrate from idle to rx/tx
00038     0x16,  // FOCCFG        Frequency Offset Compensation Configuration
00039     0x6C,  // BSCFG         Bit Synchronization Configuration
00040     0x03,  // AGCCTRL2      AGC Control - target amplitude: 33dB - Maximum possible LNA + LNA 2 gain - All gain settings can be used
00041     0x40,  // AGCCTRL1      AGC Control - LNA gain decreased first
00042     0x91,  // AGCCTRL0      AGC Control - Medium hysterisis - Filter Samples: 16 - Normal AGC operation
00043     0xE9,  // FSCAL3        Frequency Synthesizer Calibration
00044     0x2A,  // FSCAL2        Frequency Synthesizer Calibration
00045     0x00,  // FSCAL1        Frequency Synthesizer Calibration
00046     0x1F,  // FSCAL0        Frequency Synthesizer Calibration
00047     0x59,  // FSTEST        Frequency Synthesizer Calibration Control
00048     0x88,  // TEST2         Various Test Settings
00049     0x31,  // TEST1         Various Test Settings
00050     0x09,  // TEST0         Various Test Settings
00051     0x07,  // FIFOTHR       RX FIFO and TX FIFO Thresholds - Bytes in TX FIFO:33 - Bytes in RX FIFO:32
00052     0x06,  // IOCFG2        GDO2 Output Pin Configuration - Sync word received/sent - end of packet
00053     0x04,  // PKTCTRL1      Packet Automation Control - No address check - Automatic flush of RX FIFO is disable - sync word is always accepted
00054     0x05,  // PKTCTRL0      Packet Automation Control - whitening is off - RX/TX data normal mode - CRC calculation in TX and CRC check in RX - Variable packet length
00055     0x00,  // ADDR          Device Address
00056     0xFF,  // PKTLEN        Packet Length
00057     0x3F,  // MCSM1         Main Radio Control State Machine Configuration
00058 };
00059 #ifdef RF_0db
00060 // PATABLE (0 dBm output power)
00061 char paTable[] = {0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
00062 #endif
00063 #ifdef RF_10db
00064 // PATABLE (10 dBm output power)
00065 char paTable[] = {0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
00066 #endif
00067 ///////////////////////////////////////////////////////////////////////////////////////
00068 ///////////////////////////////////////////////////////////////////////////////////////
00069 // Macro to reset the CCxxx0 and wait for it to be ready
00070 void CC1101::RESET_CCxxx0(void)
00071 {
00072 //  while (_RDmiso);
00073     _csn = 0;
00074     wait(0.000002);
00075     while (_RDmiso);
00076     _spi.write(CCxxx0_SRES);
00077     wait(0.000002);
00078     _csn = 1;
00079 }
00080 ///////////////////////////////////////////////////////////////////////////////////////
00081 // Macro to reset the CCxxx0 after power_on and wait for it to be ready
00082 // IMPORTANT NOTICE:
00083 // The file Wait.c must be included if this macro shall be used
00084 // The file is located under: ..\Lib\Chipcon\Hal\CCxx00
00085 //
00086 //                 min 40 us
00087 //             <----------------------->
00088 // CSn      |--|  |--------------------|          |-----------
00089 //          |  |  |                    |          |
00090 //              --                      ----------
00091 //
00092 // MISO                                       |---------------
00093 //          - - - - - - - - - - - - - - - -|  |
00094 //                                          --
00095 //               Unknown / don't care
00096 //
00097 // MOSI     - - - - - - - - - - - - - - - ---------- - - - - -
00098 //                                         | SRES |
00099 //          - - - - - - - - - - - - - - - ---------- - - - - -
00100 //
00101 void CC1101::POWER_UP_RESET_CCxxx0(void)
00102 {
00103     _csn = 1;
00104     wait(1e-6);
00105     _csn = 0;
00106     wait(1e-6);
00107     _csn = 1;
00108     wait(41e-6);
00109     RESET_CCxxx0();
00110 }
00111 ///////////////////////////////////////////////////////////////////////////////////////
00112 //  void Strobe(unsigned char strobe)
00113 //
00114 //  DESCRIPTION:
00115 //      Function for writing a strobe command to the CCxxx0
00116 //
00117 //  ARGUMENTS:
00118 //      unsigned char strobe
00119 //          Strobe command
00120 ///////////////////////////////////////////////////////////////////////////////////////
00121 unsigned char CC1101::Strobe(unsigned char strobe)
00122 {
00123     unsigned char x;
00124     wait(0.000005);
00125     _csn = 0;
00126     wait(0.000002);
00127     while (_RDmiso);
00128     x = _spi.write(strobe);
00129     wait(0.000002);
00130     _csn = 1;
00131     return x;
00132 }// Strobe
00133 ///////////////////////////////////////////////////////////////////////////////////////
00134 //  unsigned char ReadStatus(unsigned char addr)
00135 //
00136 //  DESCRIPTION:
00137 //      This function reads a CCxxx0 status register.
00138 //
00139 //  ARGUMENTS:
00140 //      unsigned char addr
00141 //          Address of the CCxxx0 status register to be accessed.
00142 //
00143 //  RETURN VALUE:
00144 //      unsigned char
00145 //          Value of the accessed CCxxx0 status register.
00146 ///////////////////////////////////////////////////////////////////////////////////////
00147 unsigned char CC1101::ReadStatus(unsigned char addr)
00148 {
00149     unsigned char x;
00150     wait(0.000005);
00151     _csn = 0;
00152     wait(0.000002);
00153     while (_RDmiso);
00154     _spi.write(addr | READ_BURST);
00155     x = _spi.write(0);
00156     wait(0.000002);
00157     _csn = 1;
00158     return x;
00159 }// ReadStatus
00160 ///////////////////////////////////////////////////////////////////////////////////////
00161 //  void WriteRfSettings(RF_SETTINGS *pRfSettings)
00162 //
00163 //  DESCRIPTION:
00164 //      This function is used to configure the CCxxx0 based on a given rf setting
00165 //
00166 //  ARGUMENTS:
00167 //      RF_SETTINGS *pRfSettings
00168 //          Pointer to a struct containing rf register settings
00169 ///////////////////////////////////////////////////////////////////////////////////////
00170 void CC1101::WriteRfSettings(RF_SETTINGS *pRfSettings)
00171 {
00172     // Write register settings
00173     WriteReg(CCxxx0_FSCTRL1,  pRfSettings->FSCTRL1);
00174     WriteReg(CCxxx0_FSCTRL0,  pRfSettings->FSCTRL0);
00175     WriteReg(CCxxx0_FREQ2,    pRfSettings->FREQ2);
00176     WriteReg(CCxxx0_FREQ1,    pRfSettings->FREQ1);
00177     WriteReg(CCxxx0_FREQ0,    pRfSettings->FREQ0);
00178     WriteReg(CCxxx0_MDMCFG4,  pRfSettings->MDMCFG4);
00179     WriteReg(CCxxx0_MDMCFG3,  pRfSettings->MDMCFG3);
00180     WriteReg(CCxxx0_MDMCFG2,  pRfSettings->MDMCFG2);
00181     WriteReg(CCxxx0_MDMCFG1,  pRfSettings->MDMCFG1);
00182     WriteReg(CCxxx0_MDMCFG0,  pRfSettings->MDMCFG0);
00183     WriteReg(CCxxx0_CHANNR,   pRfSettings->CHANNR);
00184     WriteReg(CCxxx0_DEVIATN,  pRfSettings->DEVIATN);
00185     WriteReg(CCxxx0_FREND1,   pRfSettings->FREND1);
00186     WriteReg(CCxxx0_FREND0,   pRfSettings->FREND0);
00187     WriteReg(CCxxx0_MCSM0 ,   pRfSettings->MCSM0 );
00188     WriteReg(CCxxx0_FOCCFG,   pRfSettings->FOCCFG);
00189     WriteReg(CCxxx0_BSCFG,    pRfSettings->BSCFG);
00190     WriteReg(CCxxx0_AGCCTRL2, pRfSettings->AGCCTRL2);
00191     WriteReg(CCxxx0_AGCCTRL1, pRfSettings->AGCCTRL1);
00192     WriteReg(CCxxx0_AGCCTRL0, pRfSettings->AGCCTRL0);
00193     WriteReg(CCxxx0_FSCAL3,   pRfSettings->FSCAL3);
00194     WriteReg(CCxxx0_FSCAL2,   pRfSettings->FSCAL2);
00195     WriteReg(CCxxx0_FSCAL1,   pRfSettings->FSCAL1);
00196     WriteReg(CCxxx0_FSCAL0,   pRfSettings->FSCAL0);
00197     WriteReg(CCxxx0_FSTEST,   pRfSettings->FSTEST);
00198     WriteReg(CCxxx0_TEST2,    pRfSettings->TEST2);
00199     WriteReg(CCxxx0_TEST1,    pRfSettings->TEST1);
00200     WriteReg(CCxxx0_TEST0,    pRfSettings->TEST0);
00201     WriteReg(CCxxx0_FIFOTHR,  pRfSettings->FIFOTHR);
00202     WriteReg(CCxxx0_IOCFG2,   pRfSettings->IOCFG2);
00203     WriteReg(CCxxx0_IOCFG0,   pRfSettings->IOCFG0);
00204     WriteReg(CCxxx0_PKTCTRL1, pRfSettings->PKTCTRL1);
00205     WriteReg(CCxxx0_PKTCTRL0, pRfSettings->PKTCTRL0);
00206     WriteReg(CCxxx0_ADDR,     pRfSettings->ADDR);
00207     WriteReg(CCxxx0_PKTLEN,   pRfSettings->PKTLEN);
00208     WriteReg(CCxxx0_MCSM1 ,   pRfSettings->MCSM1 );
00209     RXMode();
00210 
00211 }// WriteRfSettings
00212 ///////////////////////////////////////////////////////////////////////////////////////
00213 void CC1101::init(void)
00214 {
00215     WriteRfSettings(&rfSettings);
00216     WriteReg(CCxxx0_PATABLE, paTable[0]);
00217 }
00218 ///////////////////////////////////////////////////////////////////////////////////////
00219 //  unsigned char ReadReg(unsigned char addr)
00220 //
00221 //  DESCRIPTION:
00222 //      This function gets the value of a single specified CCxxx0 register.
00223 //
00224 //  ARGUMENTS:
00225 //      unsigned char addr
00226 //          Address of the CCxxx0 register to be accessed.
00227 //
00228 //  RETURN VALUE:
00229 //      unsigned char
00230 //          Value of the accessed CCxxx0 register.
00231 ///////////////////////////////////////////////////////////////////////////////////////
00232 unsigned char CC1101::ReadReg(unsigned char addr)
00233 {
00234     unsigned char x;
00235     wait(0.000005);
00236     _csn = 0;
00237     wait(0.000002);
00238     while (_RDmiso);
00239     _spi.write(addr | READ_SINGLE);
00240     x = _spi.write(0);
00241     wait(0.000002);
00242     _csn = 1;
00243     return x;
00244 }// ReadReg
00245 ///////////////////////////////////////////////////////////////////////////////////////
00246 //  void ReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
00247 //
00248 //  DESCRIPTION:
00249 //      This function reads multiple CCxxx0 register, using SPI burst access.
00250 //
00251 //  ARGUMENTS:
00252 //      unsigned char addr
00253 //          Address of the first CCxxx0 register to be accessed.
00254 //      unsigned char *buffer
00255 //          Pointer to a byte array which stores the values read from a
00256 //          corresponding range of CCxxx0 registers.
00257 //      unsigned char count
00258 //          Number of bytes to be read from the subsequent CCxxx0 registers.
00259 ///////////////////////////////////////////////////////////////////////////////////////
00260 void CC1101::ReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
00261 {
00262     unsigned char i;
00263     wait(0.000005);
00264     _csn = 0;
00265     wait(0.000002);
00266     while (_RDmiso);
00267     _spi.write(addr | READ_BURST);
00268     for (i = 0; i < count; i++) {
00269         buffer[i] = _spi.write(0);
00270     }
00271     wait(0.000002);
00272     _csn = 1;
00273 }// ReadBurstReg
00274 ///////////////////////////////////////////////////////////////////////////////////////
00275 //  void WriteReg(unsigned char addr, unsigned char value)
00276 //
00277 //  DESCRIPTION:
00278 //      Function for writing to a single CCxxx0 register
00279 //
00280 //  ARGUMENTS:
00281 //      unsigned char addr
00282 //          Address of a specific CCxxx0 register to accessed.
00283 //      unsigned char value
00284 //          Value to be written to the specified CCxxx0 register.
00285 ///////////////////////////////////////////////////////////////////////////////////////
00286 void CC1101::WriteReg(unsigned char addr, unsigned char value)
00287 {
00288     wait(0.000005);
00289     _csn = 0;
00290     wait(0.000002);
00291     while (_RDmiso);
00292     _spi.write(addr);
00293     _spi.write(value);
00294     wait(0.000002);
00295     _csn = 1;
00296 }// WriteReg
00297 ///////////////////////////////////////////////////////////////////////////////////////
00298 //  void WriteBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
00299 //
00300 //  DESCRIPTION:
00301 //      This function writes to multiple CCxxx0 register, using SPI burst access.
00302 //
00303 //  ARGUMENTS:
00304 //      unsigned char addr
00305 //          Address of the first CCxxx0 register to be accessed.
00306 //      unsigned char *buffer
00307 //          Array of bytes to be written into a corresponding range of
00308 //          CCxx00 registers, starting by the address specified in _addr_.
00309 //      unsigned char count
00310 //          Number of bytes to be written to the subsequent CCxxx0 registers.
00311 ///////////////////////////////////////////////////////////////////////////////////////
00312 void CC1101::WriteBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
00313 {
00314     unsigned char i;
00315     wait(0.000005);
00316     _csn = 0;
00317     wait(0.000002);
00318     while (_RDmiso);
00319     _spi.write(addr | WRITE_BURST);
00320     for (i = 0; i < count; i++) {
00321         _spi.write(buffer[i]);
00322     }
00323     wait(0.000002);
00324     _csn = 1;
00325 }// WriteBurstReg
00326 ///////////////////////////////////////////////////////////////////////////////////////
00327 unsigned char CC1101::RdRSSI(void)
00328 {
00329     unsigned char crssi;
00330 
00331 
00332     if (rssi >= 128) {
00333         crssi = 255 - rssi;
00334         crssi /= 2;
00335         crssi += 74;
00336     } else {
00337         crssi = rssi/2;
00338         crssi += 74;
00339     }
00340     return crssi;
00341 }
00342 ///////////////////////////////////////////////////////////////////////////////////////
00343 unsigned char CC1101::RdLQI(void)
00344 {
00345     unsigned char clqi;
00346     clqi = 0x3F - (lqi & 0x3F);
00347 
00348     return clqi;
00349 }
00350 ///////////////////////////////////////////////////////////////////////////////////////
00351 unsigned char CC1101::RxFifoEmpty(void)
00352 {
00353     unsigned char RxFifoStatus;
00354 
00355     Strobe(CCxxx0_SRX);
00356     RxFifoStatus = ReadStatus(CCxxx0_RXBYTES);
00357 
00358     if (RxFifoStatus & 0x80) {    // check for RXFIFO overflow
00359         // Make sure that the radio is in IDLE state before flushing the FIFO
00360         // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)
00361         Strobe(CCxxx0_SIDLE);
00362 
00363         // Flush RX FIFO
00364         Strobe(CCxxx0_SFRX);
00365     }
00366     if (RxFifoStatus & ~0x80) {
00367         return 0;
00368     } else
00369         return 1;
00370 }
00371 ///////////////////////////////////////////////////////////////////////////////////////
00372 //-------------------------------------------------------------------------------------------------------
00373 //  BOOL ReceivePacket(unsigned char *rxBuffer, unsigned char *length)
00374 //
00375 //  DESCRIPTION:
00376 //      This function can be used to receive a packet of variable packet length (first byte in the packet
00377 //      must be the length byte). The packet length should not exceed the RX FIFO size.
00378 //
00379 //  ARGUMENTS:
00380 //      unsigned char *rxBuffer
00381 //          Pointer to the buffer where the incoming data should be stored
00382 //      unsigned char *length
00383 //          Pointer to a variable containing the size of the buffer where the incoming data should be
00384 //          stored. After this function returns, that variable holds the packet length.
00385 //
00386 //  RETURN VALUE:
00387 //      BOOL
00388 //          1:   CRC OK
00389 //          0:  CRC NOT OK (or no packet was put in the RX FIFO due to filtering)
00390 ///////////////////////////////////////////////////////////////////////////////////////
00391 
00392 int CC1101::ReceivePacket(unsigned char *rxBuffer, unsigned char *length)
00393 {
00394     unsigned char status[2];
00395     unsigned char packetLength, bytes;
00396 
00397     bytes = packetLength = ReadStatus(CCxxx0_RXBYTES);
00398     if (packetLength & BYTES_IN_RXFIFO) {
00399         // Read length byte
00400         packetLength = ReadReg(CCxxx0_RXFIFO);
00401 
00402         // Read data from RX FIFO and store in rxBuffer
00403         if (packetLength <= *length) {
00404             ReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength);
00405             *length = packetLength;
00406 
00407             // Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
00408             ReadBurstReg(CCxxx0_RXFIFO, status, 2);
00409 
00410             rssi = status[RSSI];
00411             lqi = status[LQI];
00412             // MSB of LQI is the CRC_OK bit
00413 //            return (status[LQI] & CRC_OK);
00414             if(status[LQI] & CRC_OK) {
00415                 return 1;
00416             }
00417         } else {
00418             printf("too big packet length=%u/%u RXBYTES=%u\r\n", packetLength, *length, bytes);
00419             *length = packetLength;
00420 
00421             // Make sure that the radio is in IDLE state before flushing the FIFO
00422             // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)
00423             Strobe(CCxxx0_SIDLE);
00424 
00425             // Flush RX FIFO
00426             Strobe(CCxxx0_SFRX);
00427             return 0;
00428         }
00429     } else
00430         return 0;
00431     return 0;
00432 }// halRfReceivePacket
00433 ///////////////////////////////////////////////////////////////////////////////////////
00434 unsigned char CC1101::TxFifoEmpty(void)
00435 {
00436     unsigned char TxFifoStatus;
00437 
00438     Strobe(CCxxx0_STX);
00439     TxFifoStatus = ReadStatus(CCxxx0_TXBYTES);
00440 
00441     if (TxFifoStatus & 0x80) {    // check for TXFIFO underflow
00442         // Make sure that the radio is in IDLE state before flushing the FIFO
00443         Strobe(CCxxx0_SIDLE);
00444 
00445         // Flush TX FIFO
00446         Strobe(CCxxx0_SFTX);
00447     }
00448     if (TxFifoStatus & ~0x80) {
00449         return 0;
00450     } else
00451         return 1;
00452 }
00453 ///////////////////////////////////////////////////////////////////////////////////////
00454 //  void halRfSendPacket(unsigned char *txBuffer, unsigned char size)
00455 //
00456 //  DESCRIPTION:
00457 //      This function can be used to transmit a packet with packet length up to 63 bytes.
00458 //
00459 //  ARGUMENTS:
00460 //      unsigned char *txBuffer
00461 //          Pointer to a buffer containing the data that are going to be transmitted
00462 //
00463 //      unsigned char size
00464 //          The size of the txBuffer
00465 ///////////////////////////////////////////////////////////////////////////////////////
00466 void CC1101::SendPacket(const unsigned char *txBuffer, unsigned char size)
00467 {
00468     unsigned char i;
00469     unsigned char buf[64];
00470 
00471     buf[0] = size;
00472     for (i = 0; i < size; i++)
00473         buf[i+1] = txBuffer[i];
00474 
00475     WriteBurstReg(CCxxx0_TXFIFO, buf, size+1);
00476     Strobe(CCxxx0_SIDLE);
00477     Strobe(CCxxx0_STX);
00478 
00479     //////////////////////////////////////////////////////////////////////////////////////////////
00480     // To send subsequent packet we should ensure packet is sent before return this function
00481     //////////////////////////////////////////////////////////////////////////////////////////////
00482     // Following check routine is valid when IOCFG2=0x06 is set.
00483     unsigned t;
00484     const unsigned safe_check_count = 1000000;
00485 
00486     t = 0;
00487     // Wait for GDO2 to be set -> sync transmitted
00488     while (!_gdo2 && t++ < safe_check_count);
00489     if (t == safe_check_count) {
00490         printf("check timeout 1\r\n");
00491     }
00492 
00493     // Wait for GDO2 to be cleared -> end of packet
00494     t = 0;
00495     while (_gdo2 && t++ < safe_check_count);
00496 
00497     if (t == safe_check_count) {
00498         printf("check timeout 2\r\n");
00499     }
00500 
00501 }// halRfSendPacket
00502 
00503 ///////////////////////////////////////////////////////////////////////////////////////
00504 unsigned char CC1101::ReadChipStatusTX(void)
00505 {
00506     unsigned char x;
00507 
00508     x = Strobe(CCxxx0_SNOP);
00509     return x;
00510 }
00511 ///////////////////////////////////////////////////////////////////////////////////////
00512 unsigned char CC1101::ReadChipStatusRX(void)
00513 {
00514     unsigned char x;
00515     wait(0.000005);
00516     _csn = 0;
00517     wait(0.000002);
00518     while (_RDmiso);
00519     x = _spi.write(CCxxx0_PARTNUM | READ_BURST);
00520     wait(0.000002);
00521     _csn = 1;
00522     return x;
00523 }
00524 ///////////////////////////////////////////////////////////////////////////////////////
00525 void CC1101::FlushRX(void)
00526 {
00527     // Make sure that the radio is in IDLE state before flushing the FIFO
00528     Strobe(CCxxx0_SIDLE);
00529 
00530     // Flush RX FIFO
00531     Strobe(CCxxx0_SFRX);
00532 }
00533 ///////////////////////////////////////////////////////////////////////////////////////
00534 void CC1101::FlushTX(void)
00535 {
00536     // Make sure that the radio is in IDLE state before flushing the FIFO
00537     Strobe(CCxxx0_SIDLE);
00538 
00539     // Flush TX FIFO
00540     Strobe(CCxxx0_SFTX);
00541 }
00542 ///////////////////////////////////////////////////////////////////////////////////////
00543 void CC1101::RXMode(void)
00544 {
00545     Strobe(CCxxx0_SIDLE);
00546     Strobe(CCxxx0_SRX);
00547 }
00548 ///////////////////////////////////////////////////////////////////////////////////////
00549 int CC1101::GetGDO0(void)
00550 {
00551     return _gdo0;
00552 }
00553 ///////////////////////////////////////////////////////////////////////////////////////
00554 int CC1101::GetGDO2(void)
00555 {
00556     return _gdo2;
00557 }
00558 ///////////////////////////////////////////////////////////////////////////////////////
00559 
00560