CMSIS DSP library
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arm_scale_q15.c
00001 /* ---------------------------------------------------------------------- 00002 * Copyright (C) 2010-2013 ARM Limited. All rights reserved. 00003 * 00004 * $Date: 17. January 2013 00005 * $Revision: V1.4.1 00006 * 00007 * Project: CMSIS DSP Library 00008 * Title: arm_scale_q15.c 00009 * 00010 * Description: Multiplies a Q15 vector by a scalar. 00011 * 00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 00013 * 00014 * Redistribution and use in source and binary forms, with or without 00015 * modification, are permitted provided that the following conditions 00016 * are met: 00017 * - Redistributions of source code must retain the above copyright 00018 * notice, this list of conditions and the following disclaimer. 00019 * - Redistributions in binary form must reproduce the above copyright 00020 * notice, this list of conditions and the following disclaimer in 00021 * the documentation and/or other materials provided with the 00022 * distribution. 00023 * - Neither the name of ARM LIMITED nor the names of its contributors 00024 * may be used to endorse or promote products derived from this 00025 * software without specific prior written permission. 00026 * 00027 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 00028 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00029 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00030 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 00031 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00032 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00033 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00034 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00036 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 00037 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00038 * POSSIBILITY OF SUCH DAMAGE. 00039 * -------------------------------------------------------------------- */ 00040 00041 #include "arm_math.h" 00042 00043 /** 00044 * @ingroup groupMath 00045 */ 00046 00047 /** 00048 * @addtogroup scale 00049 * @{ 00050 */ 00051 00052 /** 00053 * @brief Multiplies a Q15 vector by a scalar. 00054 * @param[in] *pSrc points to the input vector 00055 * @param[in] scaleFract fractional portion of the scale value 00056 * @param[in] shift number of bits to shift the result by 00057 * @param[out] *pDst points to the output vector 00058 * @param[in] blockSize number of samples in the vector 00059 * @return none. 00060 * 00061 * <b>Scaling and Overflow Behavior:</b> 00062 * \par 00063 * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.15 format. 00064 * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. 00065 */ 00066 00067 00068 void arm_scale_q15( 00069 q15_t * pSrc, 00070 q15_t scaleFract, 00071 int8_t shift, 00072 q15_t * pDst, 00073 uint32_t blockSize) 00074 { 00075 int8_t kShift = 15 - shift; /* shift to apply after scaling */ 00076 uint32_t blkCnt; /* loop counter */ 00077 00078 #ifndef ARM_MATH_CM0_FAMILY 00079 00080 /* Run the below code for Cortex-M4 and Cortex-M3 */ 00081 q15_t in1, in2, in3, in4; 00082 q31_t inA1, inA2; /* Temporary variables */ 00083 q31_t out1, out2, out3, out4; 00084 00085 00086 /*loop Unrolling */ 00087 blkCnt = blockSize >> 2u; 00088 00089 /* First part of the processing with loop unrolling. Compute 4 outputs at a time. 00090 ** a second loop below computes the remaining 1 to 3 samples. */ 00091 while(blkCnt > 0u) 00092 { 00093 /* Reading 2 inputs from memory */ 00094 inA1 = *__SIMD32(pSrc)++; 00095 inA2 = *__SIMD32(pSrc)++; 00096 00097 /* C = A * scale */ 00098 /* Scale the inputs and then store the 2 results in the destination buffer 00099 * in single cycle by packing the outputs */ 00100 out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); 00101 out2 = (q31_t) ((q15_t) inA1 * scaleFract); 00102 out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); 00103 out4 = (q31_t) ((q15_t) inA2 * scaleFract); 00104 00105 /* apply shifting */ 00106 out1 = out1 >> kShift; 00107 out2 = out2 >> kShift; 00108 out3 = out3 >> kShift; 00109 out4 = out4 >> kShift; 00110 00111 /* saturate the output */ 00112 in1 = (q15_t) (__SSAT(out1, 16)); 00113 in2 = (q15_t) (__SSAT(out2, 16)); 00114 in3 = (q15_t) (__SSAT(out3, 16)); 00115 in4 = (q15_t) (__SSAT(out4, 16)); 00116 00117 /* store the result to destination */ 00118 *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16); 00119 *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16); 00120 00121 /* Decrement the loop counter */ 00122 blkCnt--; 00123 } 00124 00125 /* If the blockSize is not a multiple of 4, compute any remaining output samples here. 00126 ** No loop unrolling is used. */ 00127 blkCnt = blockSize % 0x4u; 00128 00129 while(blkCnt > 0u) 00130 { 00131 /* C = A * scale */ 00132 /* Scale the input and then store the result in the destination buffer. */ 00133 *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16)); 00134 00135 /* Decrement the loop counter */ 00136 blkCnt--; 00137 } 00138 00139 #else 00140 00141 /* Run the below code for Cortex-M0 */ 00142 00143 /* Initialize blkCnt with number of samples */ 00144 blkCnt = blockSize; 00145 00146 while(blkCnt > 0u) 00147 { 00148 /* C = A * scale */ 00149 /* Scale the input and then store the result in the destination buffer. */ 00150 *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16)); 00151 00152 /* Decrement the loop counter */ 00153 blkCnt--; 00154 } 00155 00156 #endif /* #ifndef ARM_MATH_CM0_FAMILY */ 00157 00158 } 00159 00160 /** 00161 * @} end of scale group 00162 */
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