CMSIS DSP library
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Fork of mbed-dsp by
cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c@1:fdd22bb7aa52, 2012-11-28 (annotated)
- Committer:
- emilmont
- Date:
- Wed Nov 28 12:30:09 2012 +0000
- Revision:
- 1:fdd22bb7aa52
- Child:
- 2:da51fb522205
DSP library code
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
emilmont | 1:fdd22bb7aa52 | 1 | /* ---------------------------------------------------------------------- |
emilmont | 1:fdd22bb7aa52 | 2 | * Copyright (C) 2010 ARM Limited. All rights reserved. |
emilmont | 1:fdd22bb7aa52 | 3 | * |
emilmont | 1:fdd22bb7aa52 | 4 | * $Date: 15. February 2012 |
emilmont | 1:fdd22bb7aa52 | 5 | * $Revision: V1.1.0 |
emilmont | 1:fdd22bb7aa52 | 6 | * |
emilmont | 1:fdd22bb7aa52 | 7 | * Project: CMSIS DSP Library |
emilmont | 1:fdd22bb7aa52 | 8 | * Title: arm_biquad_cascade_df1_32x64_init_q31.c |
emilmont | 1:fdd22bb7aa52 | 9 | * |
emilmont | 1:fdd22bb7aa52 | 10 | * Description: High precision Q31 Biquad cascade filter initialization function. |
emilmont | 1:fdd22bb7aa52 | 11 | * |
emilmont | 1:fdd22bb7aa52 | 12 | * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 |
emilmont | 1:fdd22bb7aa52 | 13 | * |
emilmont | 1:fdd22bb7aa52 | 14 | * Version 1.1.0 2012/02/15 |
emilmont | 1:fdd22bb7aa52 | 15 | * Updated with more optimizations, bug fixes and minor API changes. |
emilmont | 1:fdd22bb7aa52 | 16 | * |
emilmont | 1:fdd22bb7aa52 | 17 | * Version 1.0.10 2011/7/15 |
emilmont | 1:fdd22bb7aa52 | 18 | * Big Endian support added and Merged M0 and M3/M4 Source code. |
emilmont | 1:fdd22bb7aa52 | 19 | * |
emilmont | 1:fdd22bb7aa52 | 20 | * Version 1.0.3 2010/11/29 |
emilmont | 1:fdd22bb7aa52 | 21 | * Re-organized the CMSIS folders and updated documentation. |
emilmont | 1:fdd22bb7aa52 | 22 | * |
emilmont | 1:fdd22bb7aa52 | 23 | * Version 1.0.2 2010/11/11 |
emilmont | 1:fdd22bb7aa52 | 24 | * Documentation updated. |
emilmont | 1:fdd22bb7aa52 | 25 | * |
emilmont | 1:fdd22bb7aa52 | 26 | * Version 1.0.1 2010/10/05 |
emilmont | 1:fdd22bb7aa52 | 27 | * Production release and review comments incorporated. |
emilmont | 1:fdd22bb7aa52 | 28 | * |
emilmont | 1:fdd22bb7aa52 | 29 | * Version 1.0.0 2010/09/20 |
emilmont | 1:fdd22bb7aa52 | 30 | * Production release and review comments incorporated. |
emilmont | 1:fdd22bb7aa52 | 31 | * |
emilmont | 1:fdd22bb7aa52 | 32 | * Version 0.0.7 2010/06/10 |
emilmont | 1:fdd22bb7aa52 | 33 | * Misra-C changes done |
emilmont | 1:fdd22bb7aa52 | 34 | * -------------------------------------------------------------------- */ |
emilmont | 1:fdd22bb7aa52 | 35 | |
emilmont | 1:fdd22bb7aa52 | 36 | #include "arm_math.h" |
emilmont | 1:fdd22bb7aa52 | 37 | |
emilmont | 1:fdd22bb7aa52 | 38 | /** |
emilmont | 1:fdd22bb7aa52 | 39 | * @ingroup groupFilters |
emilmont | 1:fdd22bb7aa52 | 40 | */ |
emilmont | 1:fdd22bb7aa52 | 41 | |
emilmont | 1:fdd22bb7aa52 | 42 | /** |
emilmont | 1:fdd22bb7aa52 | 43 | * @addtogroup BiquadCascadeDF1_32x64 |
emilmont | 1:fdd22bb7aa52 | 44 | * @{ |
emilmont | 1:fdd22bb7aa52 | 45 | */ |
emilmont | 1:fdd22bb7aa52 | 46 | |
emilmont | 1:fdd22bb7aa52 | 47 | /** |
emilmont | 1:fdd22bb7aa52 | 48 | * @details |
emilmont | 1:fdd22bb7aa52 | 49 | * |
emilmont | 1:fdd22bb7aa52 | 50 | * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. |
emilmont | 1:fdd22bb7aa52 | 51 | * @param[in] numStages number of 2nd order stages in the filter. |
emilmont | 1:fdd22bb7aa52 | 52 | * @param[in] *pCoeffs points to the filter coefficients. |
emilmont | 1:fdd22bb7aa52 | 53 | * @param[in] *pState points to the state buffer. |
emilmont | 1:fdd22bb7aa52 | 54 | * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format. |
emilmont | 1:fdd22bb7aa52 | 55 | * @return none |
emilmont | 1:fdd22bb7aa52 | 56 | * |
emilmont | 1:fdd22bb7aa52 | 57 | * <b>Coefficient and State Ordering:</b> |
emilmont | 1:fdd22bb7aa52 | 58 | * |
emilmont | 1:fdd22bb7aa52 | 59 | * \par |
emilmont | 1:fdd22bb7aa52 | 60 | * The coefficients are stored in the array <code>pCoeffs</code> in the following order: |
emilmont | 1:fdd22bb7aa52 | 61 | * <pre> |
emilmont | 1:fdd22bb7aa52 | 62 | * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...} |
emilmont | 1:fdd22bb7aa52 | 63 | * </pre> |
emilmont | 1:fdd22bb7aa52 | 64 | * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage, |
emilmont | 1:fdd22bb7aa52 | 65 | * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage, |
emilmont | 1:fdd22bb7aa52 | 66 | * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values. |
emilmont | 1:fdd22bb7aa52 | 67 | * |
emilmont | 1:fdd22bb7aa52 | 68 | * \par |
emilmont | 1:fdd22bb7aa52 | 69 | * The <code>pState</code> points to state variables array and size of each state variable is 1.63 format. |
emilmont | 1:fdd22bb7aa52 | 70 | * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>. |
emilmont | 1:fdd22bb7aa52 | 71 | * The state variables are arranged in the state array as: |
emilmont | 1:fdd22bb7aa52 | 72 | * <pre> |
emilmont | 1:fdd22bb7aa52 | 73 | * {x[n-1], x[n-2], y[n-1], y[n-2]} |
emilmont | 1:fdd22bb7aa52 | 74 | * </pre> |
emilmont | 1:fdd22bb7aa52 | 75 | * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. |
emilmont | 1:fdd22bb7aa52 | 76 | * The state array has a total length of <code>4*numStages</code> values. |
emilmont | 1:fdd22bb7aa52 | 77 | * The state variables are updated after each block of data is processed; the coefficients are untouched. |
emilmont | 1:fdd22bb7aa52 | 78 | */ |
emilmont | 1:fdd22bb7aa52 | 79 | |
emilmont | 1:fdd22bb7aa52 | 80 | void arm_biquad_cas_df1_32x64_init_q31( |
emilmont | 1:fdd22bb7aa52 | 81 | arm_biquad_cas_df1_32x64_ins_q31 * S, |
emilmont | 1:fdd22bb7aa52 | 82 | uint8_t numStages, |
emilmont | 1:fdd22bb7aa52 | 83 | q31_t * pCoeffs, |
emilmont | 1:fdd22bb7aa52 | 84 | q63_t * pState, |
emilmont | 1:fdd22bb7aa52 | 85 | uint8_t postShift) |
emilmont | 1:fdd22bb7aa52 | 86 | { |
emilmont | 1:fdd22bb7aa52 | 87 | /* Assign filter stages */ |
emilmont | 1:fdd22bb7aa52 | 88 | S->numStages = numStages; |
emilmont | 1:fdd22bb7aa52 | 89 | |
emilmont | 1:fdd22bb7aa52 | 90 | /* Assign postShift to be applied to the output */ |
emilmont | 1:fdd22bb7aa52 | 91 | S->postShift = postShift; |
emilmont | 1:fdd22bb7aa52 | 92 | |
emilmont | 1:fdd22bb7aa52 | 93 | /* Assign coefficient pointer */ |
emilmont | 1:fdd22bb7aa52 | 94 | S->pCoeffs = pCoeffs; |
emilmont | 1:fdd22bb7aa52 | 95 | |
emilmont | 1:fdd22bb7aa52 | 96 | /* Clear state buffer and size is always 4 * numStages */ |
emilmont | 1:fdd22bb7aa52 | 97 | memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t)); |
emilmont | 1:fdd22bb7aa52 | 98 | |
emilmont | 1:fdd22bb7aa52 | 99 | /* Assign state pointer */ |
emilmont | 1:fdd22bb7aa52 | 100 | S->pState = pState; |
emilmont | 1:fdd22bb7aa52 | 101 | } |
emilmont | 1:fdd22bb7aa52 | 102 | |
emilmont | 1:fdd22bb7aa52 | 103 | /** |
emilmont | 1:fdd22bb7aa52 | 104 | * @} end of BiquadCascadeDF1_32x64 group |
emilmont | 1:fdd22bb7aa52 | 105 | */ |