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targets/TARGET_Maxim/TARGET_MAX32630/device/icc_regs.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the Instruction Cache Controller.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-10-10 19:01:16 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24662 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 *************************************************************************** */
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 43 #ifndef _MXC_ICC_REGS_H_
<> 157:ff67d9f36b67 44 #define _MXC_ICC_REGS_H_
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 /* **** Includes **** */
<> 157:ff67d9f36b67 47 #include <stdint.h>
<> 157:ff67d9f36b67 48
<> 157:ff67d9f36b67 49 #ifdef __cplusplus
<> 157:ff67d9f36b67 50 extern "C" {
<> 157:ff67d9f36b67 51 #endif
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 /// @cond
<> 157:ff67d9f36b67 54 /*
<> 157:ff67d9f36b67 55 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 56 */
<> 157:ff67d9f36b67 57 #ifndef __IO
<> 157:ff67d9f36b67 58 #define __IO volatile
<> 157:ff67d9f36b67 59 #endif
<> 157:ff67d9f36b67 60 #ifndef __I
<> 157:ff67d9f36b67 61 #define __I volatile const
<> 157:ff67d9f36b67 62 #endif
<> 157:ff67d9f36b67 63 #ifndef __O
<> 157:ff67d9f36b67 64 #define __O volatile
<> 157:ff67d9f36b67 65 #endif
<> 157:ff67d9f36b67 66 #ifndef __RO
<> 157:ff67d9f36b67 67 #define __RO volatile const
<> 157:ff67d9f36b67 68 #endif
<> 157:ff67d9f36b67 69 ///@endcond
<> 157:ff67d9f36b67 70
<> 157:ff67d9f36b67 71 /* **** Definitions **** */
<> 157:ff67d9f36b67 72
<> 157:ff67d9f36b67 73 /**
<> 157:ff67d9f36b67 74 * @ingroup icc
<> 157:ff67d9f36b67 75 * @defgroup icc_registers Registers
<> 157:ff67d9f36b67 76 * @brief Registers, Bit Masks and Bit Positions for the ICC.
<> 157:ff67d9f36b67 77 * @{
<> 157:ff67d9f36b67 78 */
<> 157:ff67d9f36b67 79
<> 157:ff67d9f36b67 80 /**
<> 157:ff67d9f36b67 81 * Structure type to access the ICC Registers.
<> 157:ff67d9f36b67 82 */
<> 157:ff67d9f36b67 83 typedef struct {
<> 157:ff67d9f36b67 84 __IO uint32_t id; /**< <tt>\b 0x0000: </tt> ICC_ID Register \warning INTERNAL USE ONLY, DO NOT MODIFY */
<> 157:ff67d9f36b67 85 __IO uint32_t mem_cfg; /**< <tt>\b 0x0004: </tt> ICC_MEM_CFG Register */
<> 157:ff67d9f36b67 86 __RO uint32_t rsv008[62]; /**< <tt>\b 0x0008-0x00FC: </tt> RESERVED */
<> 157:ff67d9f36b67 87 __IO uint32_t ctrl_stat; /**< <tt>\b 0x0100: </tt> ICC_CTRL_STAT Register */
<> 157:ff67d9f36b67 88 __RO uint32_t rsv104[383]; /**< <tt>\b 0x0104-0x06FC: </tt> RESERVED */
<> 157:ff67d9f36b67 89 __IO uint32_t invdt_all; /**< <tt>\b 0x0700: </tt> ICC_INVDT_ALL Register */
<> 157:ff67d9f36b67 90 } mxc_icc_regs_t;
<> 157:ff67d9f36b67 91 /**@} end of group icc_registers*/
<> 157:ff67d9f36b67 92
<> 157:ff67d9f36b67 93
<> 157:ff67d9f36b67 94
<> 157:ff67d9f36b67 95
<> 157:ff67d9f36b67 96
<> 157:ff67d9f36b67 97 /*
<> 157:ff67d9f36b67 98 Register offsets for module ICC.
<> 157:ff67d9f36b67 99 */
<> 157:ff67d9f36b67 100 /**
<> 157:ff67d9f36b67 101 * @ingroup icc_registers
<> 157:ff67d9f36b67 102 * @defgroup ICC_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 103 * @brief Instruction Cache Controller Register Offsets from the ICC Base Address.
<> 157:ff67d9f36b67 104 * @{
<> 157:ff67d9f36b67 105 */
<> 157:ff67d9f36b67 106 #define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 107 #define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt>\b 0x0004</tt> */
<> 157:ff67d9f36b67 108 #define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt>\b 0x0100</tt> */
<> 157:ff67d9f36b67 109 #define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt>\b 0x0700</tt> */
<> 157:ff67d9f36b67 110 /**@} end of group icc_registers */
<> 157:ff67d9f36b67 111
<> 157:ff67d9f36b67 112 /*
<> 157:ff67d9f36b67 113 Field positions and masks for module ICC.
<> 157:ff67d9f36b67 114 */
<> 157:ff67d9f36b67 115 /**
<> 157:ff67d9f36b67 116 * @ingroup icc_registers
<> 157:ff67d9f36b67 117 * @defgroup ICC_ID_Register ICC_ID
<> 157:ff67d9f36b67 118 * @brief Field Positions and Bit Masks for the ICC_ID register
<> 157:ff67d9f36b67 119 * @{
<> 157:ff67d9f36b67 120 */
<> 157:ff67d9f36b67 121 #define MXC_F_ICC_ID_RTL_VERSION_POS 0 /**< RTL_VERSION Position */
<> 157:ff67d9f36b67 122 #define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS)) /**< RTL_VERSION Mask */
<> 157:ff67d9f36b67 123 #define MXC_F_ICC_ID_PART_NUM_POS 6 /**< PART_NUM Position */
<> 157:ff67d9f36b67 124 #define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS)) /**< PART_NUM Mask */
<> 157:ff67d9f36b67 125 #define MXC_F_ICC_ID_CACHE_ID_POS 10 /**< CACHE_ID Position */
<> 157:ff67d9f36b67 126 #define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS)) /**< CACHE_ID Mask */
<> 157:ff67d9f36b67 127 /**@} end of group ICC_ID_register */
<> 157:ff67d9f36b67 128 /**
<> 157:ff67d9f36b67 129 * @ingroup icc_registers
<> 157:ff67d9f36b67 130 * @defgroup ICC_MEM_CFG_Register ICC_MEM_CFG
<> 157:ff67d9f36b67 131 * @brief Field Positions and Bit Masks for the ICC_MEM_CFG register
<> 157:ff67d9f36b67 132 * @{
<> 157:ff67d9f36b67 133 */
<> 157:ff67d9f36b67 134 #define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0 /**< CACHE_SIZE Position */
<> 157:ff67d9f36b67 135 #define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS)) /**< CACHE_SIZE Mask */
<> 157:ff67d9f36b67 136 #define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16 /**< MAIN_MEMORY_SIZE Position */
<> 157:ff67d9f36b67 137 #define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS)) /**< MAIN_MEMORY_SIZE Mask */
<> 157:ff67d9f36b67 138 /**@} end of group ICC_MEM_CFG_register */
<> 157:ff67d9f36b67 139 /**
<> 157:ff67d9f36b67 140 * @ingroup icc_registers
<> 157:ff67d9f36b67 141 * @defgroup ICC_CTRL_STAT_Register ICC_CTRL_STAT
<> 157:ff67d9f36b67 142 * @brief Field Positions and Bit Masks for the ICC_CTRL_STAT register
<> 157:ff67d9f36b67 143 * @{
<> 157:ff67d9f36b67 144 */
<> 157:ff67d9f36b67 145 #define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0 /**< ENABLE Position */
<> 157:ff67d9f36b67 146 #define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS)) /**< ENABLE Mask */
<> 157:ff67d9f36b67 147 #define MXC_F_ICC_CTRL_STAT_READY_POS 16 /**< READY Position */
<> 157:ff67d9f36b67 148 #define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS)) /**< READY Mask */
<> 157:ff67d9f36b67 149 /**@} end of group ICC_CTRL_STAT_register */
<> 157:ff67d9f36b67 150
<> 157:ff67d9f36b67 151
<> 157:ff67d9f36b67 152 #ifdef __cplusplus
<> 157:ff67d9f36b67 153 }
<> 157:ff67d9f36b67 154 #endif
<> 157:ff67d9f36b67 155
<> 157:ff67d9f36b67 156 #endif /* _MXC_ICC_REGS_H_ */
<> 157:ff67d9f36b67 157