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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
149:156823d33999 
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_rcc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief RCC LL module driver.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #include "stm32l4xx_ll_rcc.h"
<> 144:ef7eb2e8f9f7 41 #ifdef USE_FULL_ASSERT
<> 144:ef7eb2e8f9f7 42 #include "stm32_assert.h"
<> 144:ef7eb2e8f9f7 43 #else
<> 144:ef7eb2e8f9f7 44 #define assert_param(expr) ((void)0U)
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 #if defined(RCC)
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @addtogroup RCC_LL
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /** @addtogroup RCC_LL_Private_Macros
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63 #if defined(RCC_CCIPR_USART3SEL)
<> 144:ef7eb2e8f9f7 64 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
<> 144:ef7eb2e8f9f7 65 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
<> 144:ef7eb2e8f9f7 66 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
<> 144:ef7eb2e8f9f7 67 #else
<> 144:ef7eb2e8f9f7 68 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
<> 144:ef7eb2e8f9f7 69 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 #endif /* RCC_CCIPR_USART3SEL */
<> 144:ef7eb2e8f9f7 72 #if defined(RCC_CCIPR_UART4SEL) && defined(RCC_CCIPR_UART5SEL)
<> 144:ef7eb2e8f9f7 73 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
<> 144:ef7eb2e8f9f7 74 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
<> 144:ef7eb2e8f9f7 75 #elif defined(RCC_CCIPR_UART4SEL)
AnnaBridge 167:e84263d55307 76 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
<> 144:ef7eb2e8f9f7 77 #elif defined(RCC_CCIPR_UART5SEL)
AnnaBridge 167:e84263d55307 78 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
<> 144:ef7eb2e8f9f7 79 #endif /* RCC_CCIPR_UART4SEL && RCC_CCIPR_UART5SEL*/
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #if defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL)
<> 144:ef7eb2e8f9f7 84 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
<> 144:ef7eb2e8f9f7 85 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
<> 144:ef7eb2e8f9f7 86 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #elif !defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL)
<> 144:ef7eb2e8f9f7 89 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
<> 144:ef7eb2e8f9f7 90 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #else
<> 144:ef7eb2e8f9f7 93 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 #endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL */
<> 144:ef7eb2e8f9f7 96 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
<> 144:ef7eb2e8f9f7 97 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #if defined(RCC_CCIPR_SAI2SEL)
<> 144:ef7eb2e8f9f7 100 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
<> 144:ef7eb2e8f9f7 101 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
<> 144:ef7eb2e8f9f7 102 #else
<> 144:ef7eb2e8f9f7 103 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
<> 144:ef7eb2e8f9f7 104 #endif /* RCC_CCIPR_SAI2SEL */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #if defined(USB_OTG_FS) || defined(USB)
<> 144:ef7eb2e8f9f7 111 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
<> 144:ef7eb2e8f9f7 112 #endif /* USB_OTG_FS || USB */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
<> 144:ef7eb2e8f9f7 115
AnnaBridge 167:e84263d55307 116 #if defined(SWPMI1)
<> 144:ef7eb2e8f9f7 117 #define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))
AnnaBridge 167:e84263d55307 118 #endif /* SWPMI1 */
<> 144:ef7eb2e8f9f7 119
AnnaBridge 167:e84263d55307 120 #if defined(DFSDM1_Channel0)
<> 144:ef7eb2e8f9f7 121 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
AnnaBridge 167:e84263d55307 122 #endif /* DFSDM1_Channel0 */
AnnaBridge 167:e84263d55307 123
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @}
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 130 /** @defgroup RCC_LL_Private_Functions RCC Private functions
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133 uint32_t RCC_GetSystemClockFreq(void);
<> 144:ef7eb2e8f9f7 134 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
<> 144:ef7eb2e8f9f7 135 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
<> 144:ef7eb2e8f9f7 136 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
<> 144:ef7eb2e8f9f7 137 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
<> 144:ef7eb2e8f9f7 138 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
<> 144:ef7eb2e8f9f7 139 uint32_t RCC_PLL_GetFreqDomain_48M(void);
<> 144:ef7eb2e8f9f7 140 uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
<> 144:ef7eb2e8f9f7 141 uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
<> 144:ef7eb2e8f9f7 142 uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
<> 144:ef7eb2e8f9f7 143 #if defined(RCC_PLLSAI2_SUPPORT)
<> 144:ef7eb2e8f9f7 144 uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);
<> 144:ef7eb2e8f9f7 145 uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void);
<> 144:ef7eb2e8f9f7 146 #endif /*RCC_PLLSAI2_SUPPORT*/
<> 144:ef7eb2e8f9f7 147 /**
<> 144:ef7eb2e8f9f7 148 * @}
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 153 /** @addtogroup RCC_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @addtogroup RCC_LL_EF_Init
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @brief Reset the RCC clock configuration to the default reset state.
<> 144:ef7eb2e8f9f7 163 * @note The default reset state of the clock configuration is given below:
<> 144:ef7eb2e8f9f7 164 * - MSI ON and used as system clock source
<> 144:ef7eb2e8f9f7 165 * - HSE, HSI, PLL and PLLSAIxSource OFF
<> 144:ef7eb2e8f9f7 166 * - AHB, APB1 and APB2 prescaler set to 1.
<> 144:ef7eb2e8f9f7 167 * - CSS, MCO OFF
<> 144:ef7eb2e8f9f7 168 * - All interrupts disabled
<> 144:ef7eb2e8f9f7 169 * @note This function doesn't modify the configuration of the
<> 144:ef7eb2e8f9f7 170 * - Peripheral clocks
<> 144:ef7eb2e8f9f7 171 * - LSI, LSE and RTC clocks
<> 144:ef7eb2e8f9f7 172 * @retval An ErrorStatus enumeration value:
<> 144:ef7eb2e8f9f7 173 * - SUCCESS: RCC registers are de-initialized
<> 144:ef7eb2e8f9f7 174 * - ERROR: not applicable
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 ErrorStatus LL_RCC_DeInit(void)
<> 144:ef7eb2e8f9f7 177 {
AnnaBridge 167:e84263d55307 178 uint32_t vl_mask = 0U;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Set MSION bit */
<> 144:ef7eb2e8f9f7 181 LL_RCC_MSI_Enable();
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
AnnaBridge 167:e84263d55307 184 while (LL_RCC_MSI_IsReady() == 0U)
<> 144:ef7eb2e8f9f7 185 {
<> 144:ef7eb2e8f9f7 186 __NOP();
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Set MSIRANGE default value */
<> 144:ef7eb2e8f9f7 190 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
<> 144:ef7eb2e8f9f7 191 /* Set MSITRIM bits to the reset value*/
<> 144:ef7eb2e8f9f7 192 LL_RCC_MSI_SetCalibTrimming(0);
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Set HSITRIM bits to the reset value*/
AnnaBridge 167:e84263d55307 195 LL_RCC_HSI_SetCalibTrimming(0x10U);
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Reset CFGR register */
AnnaBridge 167:e84263d55307 198 LL_RCC_WriteReg(CFGR, 0x00000000U);
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 vl_mask = 0xFFFFFFFFU;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */
<> 144:ef7eb2e8f9f7 203 CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON |
<> 144:ef7eb2e8f9f7 204 RCC_CR_PLLON));
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Reset PLLSAI1ON bit */
<> 144:ef7eb2e8f9f7 207 CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON);
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 #if defined(RCC_PLLSAI2_SUPPORT)
<> 144:ef7eb2e8f9f7 210 /* Reset PLLSAI2ON bit */
<> 144:ef7eb2e8f9f7 211 CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON);
<> 144:ef7eb2e8f9f7 212 #endif /*RCC_PLLSAI2_SUPPORT*/
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Write new mask in CR register */
<> 144:ef7eb2e8f9f7 215 LL_RCC_WriteReg(CR, vl_mask);
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Reset PLLCFGR register */
AnnaBridge 167:e84263d55307 218 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Reset PLLSAI1CFGR register */
AnnaBridge 167:e84263d55307 221 LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #if defined(RCC_PLLSAI2_SUPPORT)
<> 144:ef7eb2e8f9f7 224 /* Reset PLLSAI2CFGR register */
AnnaBridge 167:e84263d55307 225 LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
<> 144:ef7eb2e8f9f7 226 #endif /*RCC_PLLSAI2_SUPPORT*/
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 229 LL_RCC_HSE_DisableBypass();
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* Disable all interrupts */
AnnaBridge 167:e84263d55307 232 LL_RCC_WriteReg(CIER, 0x00000000U);
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 return SUCCESS;
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @}
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /** @addtogroup RCC_LL_EF_Get_Freq
<> 144:ef7eb2e8f9f7 242 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<> 144:ef7eb2e8f9f7 243 * and different peripheral clocks available on the device.
<> 144:ef7eb2e8f9f7 244 * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
<> 144:ef7eb2e8f9f7 245 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
<> 144:ef7eb2e8f9f7 246 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
<> 144:ef7eb2e8f9f7 247 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
<> 144:ef7eb2e8f9f7 248 * or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 249 * @note (*) MSI_VALUE is a constant defined in this file (default value
<> 144:ef7eb2e8f9f7 250 * 4 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 251 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 252 * @note (**) HSI_VALUE is a constant defined in this file (default value
<> 144:ef7eb2e8f9f7 253 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 254 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 255 * @note (***) HSE_VALUE is a constant defined in this file (default value
<> 144:ef7eb2e8f9f7 256 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 257 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 258 * have wrong result.
<> 144:ef7eb2e8f9f7 259 * @note The result of this function could be incorrect when using fractional
<> 144:ef7eb2e8f9f7 260 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 261 * @note This function can be used by the user application to compute the
<> 144:ef7eb2e8f9f7 262 * baud-rate for the communication peripherals or configure other parameters.
<> 144:ef7eb2e8f9f7 263 * @{
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<> 144:ef7eb2e8f9f7 268 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
<> 144:ef7eb2e8f9f7 269 * must be called to update structure fields. Otherwise, any
<> 144:ef7eb2e8f9f7 270 * configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 271 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
<> 144:ef7eb2e8f9f7 272 * @retval None
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 /* Get SYSCLK frequency */
<> 144:ef7eb2e8f9f7 277 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* HCLK clock frequency */
<> 144:ef7eb2e8f9f7 280 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* PCLK1 clock frequency */
<> 144:ef7eb2e8f9f7 283 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* PCLK2 clock frequency */
<> 144:ef7eb2e8f9f7 286 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @brief Return USARTx clock frequency
<> 144:ef7eb2e8f9f7 291 * @param USARTxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 292 * @arg @ref LL_RCC_USART1_CLKSOURCE
<> 144:ef7eb2e8f9f7 293 * @arg @ref LL_RCC_USART2_CLKSOURCE
<> 144:ef7eb2e8f9f7 294 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
<> 144:ef7eb2e8f9f7 295 *
<> 144:ef7eb2e8f9f7 296 * (*) value not defined in all devices.
<> 144:ef7eb2e8f9f7 297 * @retval USART clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 298 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Check parameter */
<> 144:ef7eb2e8f9f7 305 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 /* USART1CLK clock frequency */
<> 144:ef7eb2e8f9f7 310 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
<> 144:ef7eb2e8f9f7 313 usart_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 314 break;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 317 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 usart_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321 break;
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
<> 144:ef7eb2e8f9f7 324 if (LL_RCC_LSE_IsReady())
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 usart_frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328 break;
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
<> 144:ef7eb2e8f9f7 331 default:
<> 144:ef7eb2e8f9f7 332 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 333 break;
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 /* USART2CLK clock frequency */
<> 144:ef7eb2e8f9f7 339 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
<> 144:ef7eb2e8f9f7 342 usart_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 343 break;
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 346 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 usart_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350 break;
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
<> 144:ef7eb2e8f9f7 353 if (LL_RCC_LSE_IsReady())
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 usart_frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357 break;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 360 default:
<> 144:ef7eb2e8f9f7 361 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 362 break;
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365 else
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 #if defined(RCC_CCIPR_USART3SEL)
<> 144:ef7eb2e8f9f7 368 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 /* USART3CLK clock frequency */
<> 144:ef7eb2e8f9f7 371 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
<> 144:ef7eb2e8f9f7 374 usart_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 375 break;
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 378 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 379 {
<> 144:ef7eb2e8f9f7 380 usart_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 381 }
<> 144:ef7eb2e8f9f7 382 break;
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
<> 144:ef7eb2e8f9f7 385 if (LL_RCC_LSE_IsReady())
<> 144:ef7eb2e8f9f7 386 {
<> 144:ef7eb2e8f9f7 387 usart_frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389 break;
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 392 default:
<> 144:ef7eb2e8f9f7 393 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 394 break;
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397 #endif /* RCC_CCIPR_USART3SEL */
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399 return usart_frequency;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
<> 144:ef7eb2e8f9f7 403 /**
<> 144:ef7eb2e8f9f7 404 * @brief Return UARTx clock frequency
<> 144:ef7eb2e8f9f7 405 * @param UARTxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 406 * @arg @ref LL_RCC_UART4_CLKSOURCE
<> 144:ef7eb2e8f9f7 407 * @arg @ref LL_RCC_UART5_CLKSOURCE
<> 144:ef7eb2e8f9f7 408 * @retval UART clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 409 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Check parameter */
<> 144:ef7eb2e8f9f7 416 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 #if defined(RCC_CCIPR_UART4SEL)
<> 144:ef7eb2e8f9f7 419 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
<> 144:ef7eb2e8f9f7 420 {
<> 144:ef7eb2e8f9f7 421 /* UART4CLK clock frequency */
<> 144:ef7eb2e8f9f7 422 switch (LL_RCC_GetUARTClockSource(UARTxSource))
<> 144:ef7eb2e8f9f7 423 {
<> 144:ef7eb2e8f9f7 424 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
<> 144:ef7eb2e8f9f7 425 uart_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 426 break;
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 429 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 uart_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433 break;
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
<> 144:ef7eb2e8f9f7 436 if (LL_RCC_LSE_IsReady())
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 uart_frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440 break;
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 443 default:
<> 144:ef7eb2e8f9f7 444 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 445 break;
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448 #endif /* RCC_CCIPR_UART4SEL */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 #if defined(RCC_CCIPR_UART5SEL)
<> 144:ef7eb2e8f9f7 451 if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
<> 144:ef7eb2e8f9f7 452 {
<> 144:ef7eb2e8f9f7 453 /* UART5CLK clock frequency */
<> 144:ef7eb2e8f9f7 454 switch (LL_RCC_GetUARTClockSource(UARTxSource))
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
<> 144:ef7eb2e8f9f7 457 uart_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 458 break;
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 461 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 462 {
<> 144:ef7eb2e8f9f7 463 uart_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465 break;
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
<> 144:ef7eb2e8f9f7 468 if (LL_RCC_LSE_IsReady())
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 uart_frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472 break;
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 475 default:
<> 144:ef7eb2e8f9f7 476 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 477 break;
<> 144:ef7eb2e8f9f7 478 }
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480 #endif /* RCC_CCIPR_UART5SEL */
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 return uart_frequency;
<> 144:ef7eb2e8f9f7 483 }
<> 144:ef7eb2e8f9f7 484 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /**
<> 144:ef7eb2e8f9f7 487 * @brief Return I2Cx clock frequency
<> 144:ef7eb2e8f9f7 488 * @param I2CxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 489 * @arg @ref LL_RCC_I2C1_CLKSOURCE
<> 144:ef7eb2e8f9f7 490 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
AnnaBridge 167:e84263d55307 491 * @arg @ref LL_RCC_I2C3_CLKSOURCE
AnnaBridge 167:e84263d55307 492 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
<> 144:ef7eb2e8f9f7 493 *
<> 144:ef7eb2e8f9f7 494 * (*) value not defined in all devices.
<> 144:ef7eb2e8f9f7 495 * @retval I2C clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 496 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
<> 144:ef7eb2e8f9f7 497 */
<> 144:ef7eb2e8f9f7 498 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Check parameter */
<> 144:ef7eb2e8f9f7 503 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 /* I2C1 CLK clock frequency */
<> 144:ef7eb2e8f9f7 508 switch (LL_RCC_GetI2CClockSource(I2CxSource))
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
<> 144:ef7eb2e8f9f7 511 i2c_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 512 break;
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 515 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 i2c_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 break;
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 522 default:
<> 144:ef7eb2e8f9f7 523 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 524 break;
<> 144:ef7eb2e8f9f7 525 }
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527 #if defined(RCC_CCIPR_I2C2SEL)
<> 144:ef7eb2e8f9f7 528 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
<> 144:ef7eb2e8f9f7 529 {
<> 144:ef7eb2e8f9f7 530 /* I2C2 CLK clock frequency */
<> 144:ef7eb2e8f9f7 531 switch (LL_RCC_GetI2CClockSource(I2CxSource))
<> 144:ef7eb2e8f9f7 532 {
<> 144:ef7eb2e8f9f7 533 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
<> 144:ef7eb2e8f9f7 534 i2c_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 535 break;
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 538 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 i2c_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542 break;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 545 default:
<> 144:ef7eb2e8f9f7 546 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 547 break;
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550 #endif /*RCC_CCIPR_I2C2SEL*/
<> 144:ef7eb2e8f9f7 551 else
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 /* I2C3 CLK clock frequency */
<> 144:ef7eb2e8f9f7 556 switch (LL_RCC_GetI2CClockSource(I2CxSource))
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
<> 144:ef7eb2e8f9f7 559 i2c_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 560 break;
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 563 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 i2c_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 566 }
<> 144:ef7eb2e8f9f7 567 break;
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 570 default:
<> 144:ef7eb2e8f9f7 571 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 572 break;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 }
AnnaBridge 167:e84263d55307 575 #if defined(RCC_CCIPR2_I2C4SEL)
AnnaBridge 167:e84263d55307 576 else
AnnaBridge 167:e84263d55307 577 {
AnnaBridge 167:e84263d55307 578 if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
AnnaBridge 167:e84263d55307 579 {
AnnaBridge 167:e84263d55307 580 /* I2C4 CLK clock frequency */
AnnaBridge 167:e84263d55307 581 switch (LL_RCC_GetI2CClockSource(I2CxSource))
AnnaBridge 167:e84263d55307 582 {
AnnaBridge 167:e84263d55307 583 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
AnnaBridge 167:e84263d55307 584 i2c_frequency = RCC_GetSystemClockFreq();
AnnaBridge 167:e84263d55307 585 break;
AnnaBridge 167:e84263d55307 586
AnnaBridge 167:e84263d55307 587 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
AnnaBridge 167:e84263d55307 588 if (LL_RCC_HSI_IsReady())
AnnaBridge 167:e84263d55307 589 {
AnnaBridge 167:e84263d55307 590 i2c_frequency = HSI_VALUE;
AnnaBridge 167:e84263d55307 591 }
AnnaBridge 167:e84263d55307 592 break;
AnnaBridge 167:e84263d55307 593
AnnaBridge 167:e84263d55307 594 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
AnnaBridge 167:e84263d55307 595 default:
AnnaBridge 167:e84263d55307 596 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
AnnaBridge 167:e84263d55307 597 break;
AnnaBridge 167:e84263d55307 598 }
AnnaBridge 167:e84263d55307 599 }
AnnaBridge 167:e84263d55307 600 }
AnnaBridge 167:e84263d55307 601 #endif /*RCC_CCIPR2_I2C4SEL*/
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 return i2c_frequency;
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /**
<> 144:ef7eb2e8f9f7 608 * @brief Return LPUARTx clock frequency
<> 144:ef7eb2e8f9f7 609 * @param LPUARTxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 610 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
<> 144:ef7eb2e8f9f7 611 * @retval LPUART clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 612 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Check parameter */
<> 144:ef7eb2e8f9f7 619 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* LPUART1CLK clock frequency */
<> 144:ef7eb2e8f9f7 622 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
<> 144:ef7eb2e8f9f7 625 lpuart_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 626 break;
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 629 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 630 {
<> 144:ef7eb2e8f9f7 631 lpuart_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633 break;
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
<> 144:ef7eb2e8f9f7 636 if (LL_RCC_LSE_IsReady())
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 lpuart_frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640 break;
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 643 default:
<> 144:ef7eb2e8f9f7 644 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 645 break;
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 return lpuart_frequency;
<> 144:ef7eb2e8f9f7 649 }
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /**
<> 144:ef7eb2e8f9f7 652 * @brief Return LPTIMx clock frequency
<> 144:ef7eb2e8f9f7 653 * @param LPTIMxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 654 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
<> 144:ef7eb2e8f9f7 655 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
<> 144:ef7eb2e8f9f7 656 * @retval LPTIM clock frequency (in Hz)
AnnaBridge 167:e84263d55307 657 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
<> 144:ef7eb2e8f9f7 658 */
<> 144:ef7eb2e8f9f7 659 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
<> 144:ef7eb2e8f9f7 660 {
<> 144:ef7eb2e8f9f7 661 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Check parameter */
<> 144:ef7eb2e8f9f7 664 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 /* LPTIM1CLK clock frequency */
<> 144:ef7eb2e8f9f7 669 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
<> 144:ef7eb2e8f9f7 672 if (LL_RCC_LSI_IsReady())
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 lptim_frequency = LSI_VALUE;
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676 break;
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 679 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 lptim_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683 break;
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
<> 144:ef7eb2e8f9f7 686 if (LL_RCC_LSE_IsReady())
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 lptim_frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690 break;
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 693 default:
<> 144:ef7eb2e8f9f7 694 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 695 break;
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698 else
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 /* LPTIM2CLK clock frequency */
<> 144:ef7eb2e8f9f7 703 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
<> 144:ef7eb2e8f9f7 706 if (LL_RCC_LSI_IsReady())
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 lptim_frequency = LSI_VALUE;
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710 break;
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 713 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 lptim_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717 break;
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
<> 144:ef7eb2e8f9f7 720 if (LL_RCC_LSE_IsReady())
<> 144:ef7eb2e8f9f7 721 {
<> 144:ef7eb2e8f9f7 722 lptim_frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 723 }
<> 144:ef7eb2e8f9f7 724 break;
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 727 default:
<> 144:ef7eb2e8f9f7 728 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 729 break;
<> 144:ef7eb2e8f9f7 730 }
AnnaBridge 167:e84263d55307 731 }
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 return lptim_frequency;
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /**
<> 144:ef7eb2e8f9f7 738 * @brief Return SAIx clock frequency
<> 144:ef7eb2e8f9f7 739 * @param SAIxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 740 * @arg @ref LL_RCC_SAI1_CLKSOURCE
<> 144:ef7eb2e8f9f7 741 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
<> 144:ef7eb2e8f9f7 742 *
<> 144:ef7eb2e8f9f7 743 * (*) value not defined in all devices.
<> 144:ef7eb2e8f9f7 744 * @retval SAI clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 745 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
<> 144:ef7eb2e8f9f7 746 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
<> 144:ef7eb2e8f9f7 747 */
<> 144:ef7eb2e8f9f7 748 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Check parameter */
<> 144:ef7eb2e8f9f7 753 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 /* SAI1CLK clock frequency */
<> 144:ef7eb2e8f9f7 758 switch (LL_RCC_GetSAIClockSource(SAIxSource))
<> 144:ef7eb2e8f9f7 759 {
<> 144:ef7eb2e8f9f7 760 case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
<> 144:ef7eb2e8f9f7 761 if (LL_RCC_PLLSAI1_IsReady())
<> 144:ef7eb2e8f9f7 762 {
<> 144:ef7eb2e8f9f7 763 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
<> 144:ef7eb2e8f9f7 764 }
<> 144:ef7eb2e8f9f7 765 break;
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 #if defined(RCC_PLLSAI2_SUPPORT)
<> 144:ef7eb2e8f9f7 768 case LL_RCC_SAI1_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI1 clock source */
<> 144:ef7eb2e8f9f7 769 if (LL_RCC_PLLSAI2_IsReady())
<> 144:ef7eb2e8f9f7 770 {
<> 144:ef7eb2e8f9f7 771 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773 break;
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 #endif /* RCC_PLLSAI2_SUPPORT */
<> 144:ef7eb2e8f9f7 776 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
<> 144:ef7eb2e8f9f7 777 if (LL_RCC_PLL_IsReady())
<> 144:ef7eb2e8f9f7 778 {
<> 144:ef7eb2e8f9f7 779 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781 break;
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
<> 144:ef7eb2e8f9f7 784 default:
<> 144:ef7eb2e8f9f7 785 sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<> 144:ef7eb2e8f9f7 786 break;
<> 144:ef7eb2e8f9f7 787 }
<> 144:ef7eb2e8f9f7 788 }
<> 144:ef7eb2e8f9f7 789 else
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 #if defined(RCC_CCIPR_SAI2SEL)
<> 144:ef7eb2e8f9f7 792 if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 /* SAI2CLK clock frequency */
<> 144:ef7eb2e8f9f7 795 switch (LL_RCC_GetSAIClockSource(SAIxSource))
<> 144:ef7eb2e8f9f7 796 {
<> 144:ef7eb2e8f9f7 797 case LL_RCC_SAI2_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI2 clock source */
<> 144:ef7eb2e8f9f7 798 if (LL_RCC_PLLSAI1_IsReady())
<> 144:ef7eb2e8f9f7 799 {
<> 144:ef7eb2e8f9f7 800 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
<> 144:ef7eb2e8f9f7 801 }
<> 144:ef7eb2e8f9f7 802 break;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 #if defined(RCC_PLLSAI2_SUPPORT)
<> 144:ef7eb2e8f9f7 805 case LL_RCC_SAI2_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI2 clock source */
<> 144:ef7eb2e8f9f7 806 if (LL_RCC_PLLSAI2_IsReady())
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810 break;
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 #endif /* RCC_PLLSAI2_SUPPORT */
<> 144:ef7eb2e8f9f7 813 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
<> 144:ef7eb2e8f9f7 814 if (LL_RCC_PLL_IsReady())
<> 144:ef7eb2e8f9f7 815 {
<> 144:ef7eb2e8f9f7 816 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
<> 144:ef7eb2e8f9f7 817 }
<> 144:ef7eb2e8f9f7 818 break;
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
<> 144:ef7eb2e8f9f7 821 default:
<> 144:ef7eb2e8f9f7 822 sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<> 144:ef7eb2e8f9f7 823 break;
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825 }
AnnaBridge 167:e84263d55307 826 #endif /* RCC_CCIPR_SAI2SEL */
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 return sai_frequency;
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /**
<> 144:ef7eb2e8f9f7 833 * @brief Return SDMMCx clock frequency
<> 144:ef7eb2e8f9f7 834 * @param SDMMCxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 835 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
<> 144:ef7eb2e8f9f7 836 * @retval SDMMC clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 837 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
<> 144:ef7eb2e8f9f7 838 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
<> 144:ef7eb2e8f9f7 839 */
<> 144:ef7eb2e8f9f7 840 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
<> 144:ef7eb2e8f9f7 841 {
<> 144:ef7eb2e8f9f7 842 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Check parameter */
<> 144:ef7eb2e8f9f7 845 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* SDMMC1CLK clock frequency */
<> 144:ef7eb2e8f9f7 848 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
<> 144:ef7eb2e8f9f7 849 {
<> 144:ef7eb2e8f9f7 850 case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */
<> 144:ef7eb2e8f9f7 851 if (LL_RCC_PLLSAI1_IsReady())
<> 144:ef7eb2e8f9f7 852 {
<> 144:ef7eb2e8f9f7 853 sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
<> 144:ef7eb2e8f9f7 854 }
<> 144:ef7eb2e8f9f7 855 break;
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */
<> 144:ef7eb2e8f9f7 858 if (LL_RCC_PLL_IsReady())
<> 144:ef7eb2e8f9f7 859 {
<> 144:ef7eb2e8f9f7 860 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
<> 144:ef7eb2e8f9f7 861 }
<> 144:ef7eb2e8f9f7 862 break;
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */
<> 144:ef7eb2e8f9f7 865 if (LL_RCC_MSI_IsReady())
<> 144:ef7eb2e8f9f7 866 {
<> 144:ef7eb2e8f9f7 867 sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 868 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 869 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 870 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872 break;
<> 144:ef7eb2e8f9f7 873
AnnaBridge 167:e84263d55307 874 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 167:e84263d55307 875 case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */
AnnaBridge 167:e84263d55307 876 if (LL_RCC_HSI48_IsReady())
AnnaBridge 167:e84263d55307 877 {
AnnaBridge 167:e84263d55307 878 sdmmc_frequency = HSI48_VALUE;
AnnaBridge 167:e84263d55307 879 }
AnnaBridge 167:e84263d55307 880 break;
AnnaBridge 167:e84263d55307 881 #else
<> 144:ef7eb2e8f9f7 882 case LL_RCC_SDMMC1_CLKSOURCE_NONE: /* No clock used as SDMMC1 clock source */
AnnaBridge 167:e84263d55307 883 #endif
<> 144:ef7eb2e8f9f7 884 default:
<> 144:ef7eb2e8f9f7 885 sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<> 144:ef7eb2e8f9f7 886 break;
<> 144:ef7eb2e8f9f7 887 }
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 return sdmmc_frequency;
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /**
<> 144:ef7eb2e8f9f7 893 * @brief Return RNGx clock frequency
<> 144:ef7eb2e8f9f7 894 * @param RNGxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 895 * @arg @ref LL_RCC_RNG_CLKSOURCE
<> 144:ef7eb2e8f9f7 896 * @retval RNG clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 897 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
<> 144:ef7eb2e8f9f7 898 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
<> 144:ef7eb2e8f9f7 899 */
<> 144:ef7eb2e8f9f7 900 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /* Check parameter */
<> 144:ef7eb2e8f9f7 905 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* RNGCLK clock frequency */
<> 144:ef7eb2e8f9f7 908 switch (LL_RCC_GetRNGClockSource(RNGxSource))
<> 144:ef7eb2e8f9f7 909 {
<> 144:ef7eb2e8f9f7 910 case LL_RCC_RNG_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as RNG clock source */
<> 144:ef7eb2e8f9f7 911 if (LL_RCC_PLLSAI1_IsReady())
<> 144:ef7eb2e8f9f7 912 {
<> 144:ef7eb2e8f9f7 913 rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
<> 144:ef7eb2e8f9f7 914 }
<> 144:ef7eb2e8f9f7 915 break;
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
<> 144:ef7eb2e8f9f7 918 if (LL_RCC_PLL_IsReady())
<> 144:ef7eb2e8f9f7 919 {
<> 144:ef7eb2e8f9f7 920 rng_frequency = RCC_PLL_GetFreqDomain_48M();
<> 144:ef7eb2e8f9f7 921 }
<> 144:ef7eb2e8f9f7 922 break;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */
<> 144:ef7eb2e8f9f7 925 if (LL_RCC_MSI_IsReady())
<> 144:ef7eb2e8f9f7 926 {
<> 144:ef7eb2e8f9f7 927 rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 928 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 929 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 930 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932 break;
<> 144:ef7eb2e8f9f7 933
AnnaBridge 167:e84263d55307 934
AnnaBridge 167:e84263d55307 935 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 167:e84263d55307 936 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */
AnnaBridge 167:e84263d55307 937 if (LL_RCC_HSI48_IsReady())
AnnaBridge 167:e84263d55307 938 {
AnnaBridge 167:e84263d55307 939 rng_frequency = HSI48_VALUE;
AnnaBridge 167:e84263d55307 940 }
AnnaBridge 167:e84263d55307 941 break;
AnnaBridge 167:e84263d55307 942 #else
AnnaBridge 167:e84263d55307 943 case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as SDMMC1 clock source */
AnnaBridge 167:e84263d55307 944 #endif
<> 144:ef7eb2e8f9f7 945 default:
<> 144:ef7eb2e8f9f7 946 rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<> 144:ef7eb2e8f9f7 947 break;
AnnaBridge 167:e84263d55307 948
<> 144:ef7eb2e8f9f7 949 }
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 return rng_frequency;
<> 144:ef7eb2e8f9f7 952 }
<> 144:ef7eb2e8f9f7 953
AnnaBridge 167:e84263d55307 954
AnnaBridge 167:e84263d55307 955 #if defined(USB_OTG_FS)||defined(USB)
<> 144:ef7eb2e8f9f7 956 /**
<> 144:ef7eb2e8f9f7 957 * @brief Return USBx clock frequency
<> 144:ef7eb2e8f9f7 958 * @param USBxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 959 * @arg @ref LL_RCC_USB_CLKSOURCE
<> 144:ef7eb2e8f9f7 960 * @retval USB clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 961 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
<> 144:ef7eb2e8f9f7 962 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
<> 144:ef7eb2e8f9f7 963 */
<> 144:ef7eb2e8f9f7 964 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /* Check parameter */
<> 144:ef7eb2e8f9f7 969 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /* USBCLK clock frequency */
<> 144:ef7eb2e8f9f7 972 switch (LL_RCC_GetUSBClockSource(USBxSource))
<> 144:ef7eb2e8f9f7 973 {
<> 144:ef7eb2e8f9f7 974 case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */
<> 144:ef7eb2e8f9f7 975 if (LL_RCC_PLLSAI1_IsReady())
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
<> 144:ef7eb2e8f9f7 978 }
<> 144:ef7eb2e8f9f7 979 break;
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
<> 144:ef7eb2e8f9f7 982 if (LL_RCC_PLL_IsReady())
<> 144:ef7eb2e8f9f7 983 {
<> 144:ef7eb2e8f9f7 984 usb_frequency = RCC_PLL_GetFreqDomain_48M();
<> 144:ef7eb2e8f9f7 985 }
<> 144:ef7eb2e8f9f7 986 break;
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */
<> 144:ef7eb2e8f9f7 989 if (LL_RCC_MSI_IsReady())
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 992 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 993 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 994 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 break;
<> 144:ef7eb2e8f9f7 997
AnnaBridge 167:e84263d55307 998 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 167:e84263d55307 999 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */
AnnaBridge 167:e84263d55307 1000 if (LL_RCC_HSI48_IsReady())
AnnaBridge 167:e84263d55307 1001 {
AnnaBridge 167:e84263d55307 1002 usb_frequency = HSI48_VALUE;
AnnaBridge 167:e84263d55307 1003 }
AnnaBridge 167:e84263d55307 1004 break;
AnnaBridge 167:e84263d55307 1005 #else
AnnaBridge 167:e84263d55307 1006 case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */
AnnaBridge 167:e84263d55307 1007 #endif
<> 144:ef7eb2e8f9f7 1008 default:
<> 144:ef7eb2e8f9f7 1009 usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<> 144:ef7eb2e8f9f7 1010 break;
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 return usb_frequency;
<> 144:ef7eb2e8f9f7 1014 }
<> 144:ef7eb2e8f9f7 1015 #endif /* USB_OTG_FS || USB */
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /**
<> 144:ef7eb2e8f9f7 1018 * @brief Return ADCx clock frequency
<> 144:ef7eb2e8f9f7 1019 * @param ADCxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1020 * @arg @ref LL_RCC_ADC_CLKSOURCE
<> 144:ef7eb2e8f9f7 1021 * @retval ADC clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1022 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
<> 144:ef7eb2e8f9f7 1023 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
<> 144:ef7eb2e8f9f7 1024 */
<> 144:ef7eb2e8f9f7 1025 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
<> 144:ef7eb2e8f9f7 1026 {
<> 144:ef7eb2e8f9f7 1027 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* Check parameter */
<> 144:ef7eb2e8f9f7 1030 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /* ADCCLK clock frequency */
<> 144:ef7eb2e8f9f7 1033 switch (LL_RCC_GetADCClockSource(ADCxSource))
<> 144:ef7eb2e8f9f7 1034 {
<> 144:ef7eb2e8f9f7 1035 case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
<> 144:ef7eb2e8f9f7 1036 if (LL_RCC_PLLSAI1_IsReady())
<> 144:ef7eb2e8f9f7 1037 {
<> 144:ef7eb2e8f9f7 1038 adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
<> 144:ef7eb2e8f9f7 1039 }
<> 144:ef7eb2e8f9f7 1040 break;
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 #if defined(RCC_PLLSAI2_SUPPORT)
<> 144:ef7eb2e8f9f7 1043 case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */
<> 144:ef7eb2e8f9f7 1044 if (LL_RCC_PLLSAI2_IsReady())
<> 144:ef7eb2e8f9f7 1045 {
<> 144:ef7eb2e8f9f7 1046 adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC();
<> 144:ef7eb2e8f9f7 1047 }
<> 144:ef7eb2e8f9f7 1048 break;
<> 144:ef7eb2e8f9f7 1049 #endif /* RCC_PLLSAI2_SUPPORT */
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
<> 144:ef7eb2e8f9f7 1052 adc_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 1053 break;
<> 144:ef7eb2e8f9f7 1054 case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */
<> 144:ef7eb2e8f9f7 1055 default:
<> 144:ef7eb2e8f9f7 1056 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<> 144:ef7eb2e8f9f7 1057 break;
<> 144:ef7eb2e8f9f7 1058 }
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 return adc_frequency;
<> 144:ef7eb2e8f9f7 1061 }
<> 144:ef7eb2e8f9f7 1062
AnnaBridge 167:e84263d55307 1063 #if defined(SWPMI1)
<> 144:ef7eb2e8f9f7 1064 /**
<> 144:ef7eb2e8f9f7 1065 * @brief Return SWPMIx clock frequency
<> 144:ef7eb2e8f9f7 1066 * @param SWPMIxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1067 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE
<> 144:ef7eb2e8f9f7 1068 * @retval SWPMI clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1069 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready
<> 144:ef7eb2e8f9f7 1070 */
<> 144:ef7eb2e8f9f7 1071 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)
<> 144:ef7eb2e8f9f7 1072 {
<> 144:ef7eb2e8f9f7 1073 uint32_t swpmi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Check parameter */
<> 144:ef7eb2e8f9f7 1076 assert_param(IS_LL_RCC_SWPMI_CLKSOURCE(SWPMIxSource));
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* SWPMI1CLK clock frequency */
<> 144:ef7eb2e8f9f7 1079 switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource))
<> 144:ef7eb2e8f9f7 1080 {
<> 144:ef7eb2e8f9f7 1081 case LL_RCC_SWPMI1_CLKSOURCE_HSI: /* SWPMI1 Clock is HSI Osc. */
<> 144:ef7eb2e8f9f7 1082 if (LL_RCC_HSI_IsReady())
<> 144:ef7eb2e8f9f7 1083 {
<> 144:ef7eb2e8f9f7 1084 swpmi_frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1085 }
<> 144:ef7eb2e8f9f7 1086 break;
<> 144:ef7eb2e8f9f7 1087
AnnaBridge 167:e84263d55307 1088 case LL_RCC_SWPMI1_CLKSOURCE_PCLK1: /* SWPMI1 Clock is PCLK1 */
<> 144:ef7eb2e8f9f7 1089 default:
<> 144:ef7eb2e8f9f7 1090 swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 1091 break;
<> 144:ef7eb2e8f9f7 1092 }
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 return swpmi_frequency;
<> 144:ef7eb2e8f9f7 1095 }
AnnaBridge 167:e84263d55307 1096 #endif /* SWPMI1 */
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 #if defined(DFSDM1_Channel0)
<> 144:ef7eb2e8f9f7 1099 /**
<> 144:ef7eb2e8f9f7 1100 * @brief Return DFSDMx clock frequency
<> 144:ef7eb2e8f9f7 1101 * @param DFSDMxSource This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1102 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
<> 144:ef7eb2e8f9f7 1103 * @retval DFSDM clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1104 */
<> 144:ef7eb2e8f9f7 1105 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
<> 144:ef7eb2e8f9f7 1106 {
<> 144:ef7eb2e8f9f7 1107 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 /* Check parameter */
<> 144:ef7eb2e8f9f7 1110 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 /* DFSDM1CLK clock frequency */
<> 144:ef7eb2e8f9f7 1113 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
<> 144:ef7eb2e8f9f7 1114 {
<> 144:ef7eb2e8f9f7 1115 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
<> 144:ef7eb2e8f9f7 1116 dfsdm_frequency = RCC_GetSystemClockFreq();
<> 144:ef7eb2e8f9f7 1117 break;
<> 144:ef7eb2e8f9f7 1118
AnnaBridge 167:e84263d55307 1119 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
<> 144:ef7eb2e8f9f7 1120 default:
AnnaBridge 167:e84263d55307 1121 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<> 144:ef7eb2e8f9f7 1122 break;
<> 144:ef7eb2e8f9f7 1123 }
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 return dfsdm_frequency;
<> 144:ef7eb2e8f9f7 1126 }
<> 144:ef7eb2e8f9f7 1127 #endif /* DFSDM1_Channel0 */
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 /**
<> 144:ef7eb2e8f9f7 1130 * @}
<> 144:ef7eb2e8f9f7 1131 */
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 /**
<> 144:ef7eb2e8f9f7 1134 * @}
<> 144:ef7eb2e8f9f7 1135 */
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 /** @addtogroup RCC_LL_Private_Functions
<> 144:ef7eb2e8f9f7 1138 * @{
<> 144:ef7eb2e8f9f7 1139 */
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 /**
<> 144:ef7eb2e8f9f7 1142 * @brief Return SYSTEM clock frequency
<> 144:ef7eb2e8f9f7 1143 * @retval SYSTEM clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1144 */
<> 144:ef7eb2e8f9f7 1145 uint32_t RCC_GetSystemClockFreq(void)
<> 144:ef7eb2e8f9f7 1146 {
AnnaBridge 167:e84263d55307 1147 uint32_t frequency = 0U;
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1150 switch (LL_RCC_GetSysClkSource())
<> 144:ef7eb2e8f9f7 1151 {
<> 144:ef7eb2e8f9f7 1152 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
<> 144:ef7eb2e8f9f7 1153 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1154 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1155 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1156 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1157 break;
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 1160 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1161 break;
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
<> 144:ef7eb2e8f9f7 1164 frequency = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1165 break;
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
<> 144:ef7eb2e8f9f7 1168 frequency = RCC_PLL_GetFreqDomain_SYS();
<> 144:ef7eb2e8f9f7 1169 break;
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 default:
<> 144:ef7eb2e8f9f7 1172 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1173 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1174 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1175 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1176 break;
<> 144:ef7eb2e8f9f7 1177 }
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 return frequency;
<> 144:ef7eb2e8f9f7 1180 }
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /**
<> 144:ef7eb2e8f9f7 1183 * @brief Return HCLK clock frequency
<> 144:ef7eb2e8f9f7 1184 * @param SYSCLK_Frequency SYSCLK clock frequency
<> 144:ef7eb2e8f9f7 1185 * @retval HCLK clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1186 */
<> 144:ef7eb2e8f9f7 1187 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
<> 144:ef7eb2e8f9f7 1188 {
<> 144:ef7eb2e8f9f7 1189 /* HCLK clock frequency */
<> 144:ef7eb2e8f9f7 1190 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /**
<> 144:ef7eb2e8f9f7 1194 * @brief Return PCLK1 clock frequency
<> 144:ef7eb2e8f9f7 1195 * @param HCLK_Frequency HCLK clock frequency
<> 144:ef7eb2e8f9f7 1196 * @retval PCLK1 clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1197 */
<> 144:ef7eb2e8f9f7 1198 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
<> 144:ef7eb2e8f9f7 1199 {
<> 144:ef7eb2e8f9f7 1200 /* PCLK1 clock frequency */
<> 144:ef7eb2e8f9f7 1201 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
<> 144:ef7eb2e8f9f7 1202 }
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /**
<> 144:ef7eb2e8f9f7 1205 * @brief Return PCLK2 clock frequency
<> 144:ef7eb2e8f9f7 1206 * @param HCLK_Frequency HCLK clock frequency
<> 144:ef7eb2e8f9f7 1207 * @retval PCLK2 clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1208 */
<> 144:ef7eb2e8f9f7 1209 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
<> 144:ef7eb2e8f9f7 1210 {
<> 144:ef7eb2e8f9f7 1211 /* PCLK2 clock frequency */
<> 144:ef7eb2e8f9f7 1212 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
<> 144:ef7eb2e8f9f7 1213 }
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 /**
<> 144:ef7eb2e8f9f7 1216 * @brief Return PLL clock frequency used for system domain
<> 144:ef7eb2e8f9f7 1217 * @retval PLL clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1218 */
<> 144:ef7eb2e8f9f7 1219 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
<> 144:ef7eb2e8f9f7 1220 {
AnnaBridge 167:e84263d55307 1221 uint32_t pllinputfreq = 0U, pllsource = 0U;
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
<> 144:ef7eb2e8f9f7 1224 SYSCLK = PLL_VCO / PLLR
<> 144:ef7eb2e8f9f7 1225 */
<> 144:ef7eb2e8f9f7 1226 pllsource = LL_RCC_PLL_GetMainSource();
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 switch (pllsource)
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 1231 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1232 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1233 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1234 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1235 break;
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 1238 pllinputfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1239 break;
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 1242 pllinputfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1243 break;
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 default:
<> 144:ef7eb2e8f9f7 1246 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1247 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1248 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1249 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1250 break;
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<> 144:ef7eb2e8f9f7 1253 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
<> 144:ef7eb2e8f9f7 1254 }
<> 144:ef7eb2e8f9f7 1255 /**
<> 144:ef7eb2e8f9f7 1256 * @brief Return PLL clock frequency used for SAI domain
<> 144:ef7eb2e8f9f7 1257 * @retval PLL clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1258 */
<> 144:ef7eb2e8f9f7 1259 uint32_t RCC_PLL_GetFreqDomain_SAI(void)
<> 144:ef7eb2e8f9f7 1260 {
AnnaBridge 167:e84263d55307 1261 uint32_t pllinputfreq = 0U, pllsource = 0U;
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
<> 144:ef7eb2e8f9f7 1264 SAI Domain clock = PLL_VCO / PLLP
<> 144:ef7eb2e8f9f7 1265 */
<> 144:ef7eb2e8f9f7 1266 pllsource = LL_RCC_PLL_GetMainSource();
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 switch (pllsource)
<> 144:ef7eb2e8f9f7 1269 {
<> 144:ef7eb2e8f9f7 1270 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 1271 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1272 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1273 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1274 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1275 break;
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 1278 pllinputfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1279 break;
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 1282 pllinputfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1283 break;
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 default:
<> 144:ef7eb2e8f9f7 1286 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1287 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1288 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1289 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1290 break;
<> 144:ef7eb2e8f9f7 1291 }
<> 144:ef7eb2e8f9f7 1292 return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<> 144:ef7eb2e8f9f7 1293 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
<> 144:ef7eb2e8f9f7 1294 }
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /**
<> 144:ef7eb2e8f9f7 1297 * @brief Return PLL clock frequency used for 48 MHz domain
<> 144:ef7eb2e8f9f7 1298 * @retval PLL clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1299 */
<> 144:ef7eb2e8f9f7 1300 uint32_t RCC_PLL_GetFreqDomain_48M(void)
<> 144:ef7eb2e8f9f7 1301 {
AnnaBridge 167:e84263d55307 1302 uint32_t pllinputfreq = 0U, pllsource = 0U;
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
<> 144:ef7eb2e8f9f7 1305 48M Domain clock = PLL_VCO / PLLQ
<> 144:ef7eb2e8f9f7 1306 */
<> 144:ef7eb2e8f9f7 1307 pllsource = LL_RCC_PLL_GetMainSource();
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 switch (pllsource)
<> 144:ef7eb2e8f9f7 1310 {
<> 144:ef7eb2e8f9f7 1311 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 1312 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1313 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1314 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1315 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1316 break;
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 1319 pllinputfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1320 break;
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 1323 pllinputfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1324 break;
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 default:
<> 144:ef7eb2e8f9f7 1327 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1328 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1329 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1330 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1331 break;
<> 144:ef7eb2e8f9f7 1332 }
<> 144:ef7eb2e8f9f7 1333 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<> 144:ef7eb2e8f9f7 1334 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
<> 144:ef7eb2e8f9f7 1335 }
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /**
<> 144:ef7eb2e8f9f7 1338 * @brief Return PLLSAI1 clock frequency used for SAI domain
<> 144:ef7eb2e8f9f7 1339 * @retval PLLSAI1 clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1340 */
<> 144:ef7eb2e8f9f7 1341 uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
<> 144:ef7eb2e8f9f7 1342 {
AnnaBridge 167:e84263d55307 1343 uint32_t pllinputfreq = 0U, pllsource = 0U;
<> 144:ef7eb2e8f9f7 1344
AnnaBridge 167:e84263d55307 1345 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
AnnaBridge 167:e84263d55307 1346 /* SAI Domain clock = PLLSAI1_VCO / PLLSAI1P */
<> 144:ef7eb2e8f9f7 1347 pllsource = LL_RCC_PLL_GetMainSource();
<> 144:ef7eb2e8f9f7 1348
<> 144:ef7eb2e8f9f7 1349 switch (pllsource)
<> 144:ef7eb2e8f9f7 1350 {
<> 144:ef7eb2e8f9f7 1351 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
<> 144:ef7eb2e8f9f7 1352 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1353 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1354 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1355 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1356 break;
<> 144:ef7eb2e8f9f7 1357
<> 144:ef7eb2e8f9f7 1358 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
<> 144:ef7eb2e8f9f7 1359 pllinputfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1360 break;
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
<> 144:ef7eb2e8f9f7 1363 pllinputfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1364 break;
<> 144:ef7eb2e8f9f7 1365
<> 144:ef7eb2e8f9f7 1366 default:
<> 144:ef7eb2e8f9f7 1367 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1368 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1369 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1370 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1371 break;
<> 144:ef7eb2e8f9f7 1372 }
<> 144:ef7eb2e8f9f7 1373 return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<> 144:ef7eb2e8f9f7 1374 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
<> 144:ef7eb2e8f9f7 1375 }
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 /**
<> 144:ef7eb2e8f9f7 1378 * @brief Return PLLSAI1 clock frequency used for 48Mhz domain
<> 144:ef7eb2e8f9f7 1379 * @retval PLLSAI1 clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1380 */
<> 144:ef7eb2e8f9f7 1381 uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
<> 144:ef7eb2e8f9f7 1382 {
AnnaBridge 167:e84263d55307 1383 uint32_t pllinputfreq = 0U, pllsource = 0U;
<> 144:ef7eb2e8f9f7 1384
AnnaBridge 167:e84263d55307 1385 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
AnnaBridge 167:e84263d55307 1386 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1Q */
<> 144:ef7eb2e8f9f7 1387 pllsource = LL_RCC_PLL_GetMainSource();
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 switch (pllsource)
<> 144:ef7eb2e8f9f7 1390 {
<> 144:ef7eb2e8f9f7 1391 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
<> 144:ef7eb2e8f9f7 1392 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1393 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1394 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1395 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1396 break;
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
<> 144:ef7eb2e8f9f7 1399 pllinputfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1400 break;
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
<> 144:ef7eb2e8f9f7 1403 pllinputfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1404 break;
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 default:
<> 144:ef7eb2e8f9f7 1407 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1408 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1409 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1410 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1411 break;
<> 144:ef7eb2e8f9f7 1412 }
<> 144:ef7eb2e8f9f7 1413 return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<> 144:ef7eb2e8f9f7 1414 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
<> 144:ef7eb2e8f9f7 1415 }
<> 144:ef7eb2e8f9f7 1416
<> 144:ef7eb2e8f9f7 1417 /**
<> 144:ef7eb2e8f9f7 1418 * @brief Return PLLSAI1 clock frequency used for ADC domain
<> 144:ef7eb2e8f9f7 1419 * @retval PLLSAI1 clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1420 */
<> 144:ef7eb2e8f9f7 1421 uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
<> 144:ef7eb2e8f9f7 1422 {
AnnaBridge 167:e84263d55307 1423 uint32_t pllinputfreq = 0U, pllsource = 0U;
<> 144:ef7eb2e8f9f7 1424
AnnaBridge 167:e84263d55307 1425 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
AnnaBridge 167:e84263d55307 1426 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1R */
<> 144:ef7eb2e8f9f7 1427 pllsource = LL_RCC_PLL_GetMainSource();
<> 144:ef7eb2e8f9f7 1428
<> 144:ef7eb2e8f9f7 1429 switch (pllsource)
<> 144:ef7eb2e8f9f7 1430 {
<> 144:ef7eb2e8f9f7 1431 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
<> 144:ef7eb2e8f9f7 1432 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1433 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1434 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1435 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1436 break;
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
<> 144:ef7eb2e8f9f7 1439 pllinputfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1440 break;
<> 144:ef7eb2e8f9f7 1441
<> 144:ef7eb2e8f9f7 1442 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
<> 144:ef7eb2e8f9f7 1443 pllinputfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1444 break;
<> 144:ef7eb2e8f9f7 1445
<> 144:ef7eb2e8f9f7 1446 default:
<> 144:ef7eb2e8f9f7 1447 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1448 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1449 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1450 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1451 break;
<> 144:ef7eb2e8f9f7 1452 }
<> 144:ef7eb2e8f9f7 1453 return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<> 144:ef7eb2e8f9f7 1454 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
<> 144:ef7eb2e8f9f7 1455 }
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 #if defined(RCC_PLLSAI2_SUPPORT)
<> 144:ef7eb2e8f9f7 1458 /**
<> 144:ef7eb2e8f9f7 1459 * @brief Return PLLSAI2 clock frequency used for SAI domain
<> 144:ef7eb2e8f9f7 1460 * @retval PLLSAI2 clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1461 */
<> 144:ef7eb2e8f9f7 1462 uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)
<> 144:ef7eb2e8f9f7 1463 {
AnnaBridge 167:e84263d55307 1464 uint32_t pllinputfreq = 0U, pllsource = 0U;
<> 144:ef7eb2e8f9f7 1465
AnnaBridge 167:e84263d55307 1466 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
AnnaBridge 167:e84263d55307 1467 /* SAI Domain clock = PLLSAI2_VCO / PLLSAI2P */
<> 144:ef7eb2e8f9f7 1468 pllsource = LL_RCC_PLL_GetMainSource();
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 switch (pllsource)
<> 144:ef7eb2e8f9f7 1471 {
<> 144:ef7eb2e8f9f7 1472 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
<> 144:ef7eb2e8f9f7 1473 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1474 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1475 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1476 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1477 break;
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
<> 144:ef7eb2e8f9f7 1480 pllinputfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1481 break;
<> 144:ef7eb2e8f9f7 1482
<> 144:ef7eb2e8f9f7 1483 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
<> 144:ef7eb2e8f9f7 1484 pllinputfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1485 break;
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 default:
<> 144:ef7eb2e8f9f7 1488 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1489 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1490 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1491 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1492 break;
<> 144:ef7eb2e8f9f7 1493 }
<> 144:ef7eb2e8f9f7 1494 return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<> 144:ef7eb2e8f9f7 1495 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
<> 144:ef7eb2e8f9f7 1496 }
<> 144:ef7eb2e8f9f7 1497
AnnaBridge 167:e84263d55307 1498 /**
<> 144:ef7eb2e8f9f7 1499 * @brief Return PLLSAI2 clock frequency used for ADC domain
<> 144:ef7eb2e8f9f7 1500 * @retval PLLSAI2 clock frequency (in Hz)
<> 144:ef7eb2e8f9f7 1501 */
<> 144:ef7eb2e8f9f7 1502 uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void)
<> 144:ef7eb2e8f9f7 1503 {
AnnaBridge 167:e84263d55307 1504 uint32_t pllinputfreq = 0U, pllsource = 0U;
<> 144:ef7eb2e8f9f7 1505
AnnaBridge 167:e84263d55307 1506 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
AnnaBridge 167:e84263d55307 1507 /* 48M Domain clock = PLLSAI2_VCO / PLLSAI2R */
<> 144:ef7eb2e8f9f7 1508 pllsource = LL_RCC_PLL_GetMainSource();
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 switch (pllsource)
<> 144:ef7eb2e8f9f7 1511 {
<> 144:ef7eb2e8f9f7 1512 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
<> 144:ef7eb2e8f9f7 1513 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1514 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1515 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1516 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1517 break;
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
<> 144:ef7eb2e8f9f7 1520 pllinputfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1521 break;
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
<> 144:ef7eb2e8f9f7 1524 pllinputfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1525 break;
<> 144:ef7eb2e8f9f7 1526
<> 144:ef7eb2e8f9f7 1527 default:
<> 144:ef7eb2e8f9f7 1528 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
<> 144:ef7eb2e8f9f7 1529 (LL_RCC_MSI_IsEnabledRangeSelect() ?
<> 144:ef7eb2e8f9f7 1530 LL_RCC_MSI_GetRange() :
<> 144:ef7eb2e8f9f7 1531 LL_RCC_MSI_GetRangeAfterStandby()));
<> 144:ef7eb2e8f9f7 1532 break;
<> 144:ef7eb2e8f9f7 1533 }
<> 144:ef7eb2e8f9f7 1534 return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<> 144:ef7eb2e8f9f7 1535 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
<> 144:ef7eb2e8f9f7 1536 }
AnnaBridge 167:e84263d55307 1537 #endif /*RCC_PLLSAI2_SUPPORT*/
<> 144:ef7eb2e8f9f7 1538
AnnaBridge 167:e84263d55307 1539
<> 144:ef7eb2e8f9f7 1540 /**
<> 144:ef7eb2e8f9f7 1541 * @}
<> 144:ef7eb2e8f9f7 1542 */
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /**
<> 144:ef7eb2e8f9f7 1545 * @}
<> 144:ef7eb2e8f9f7 1546 */
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 #endif /* defined(RCC) */
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /**
<> 144:ef7eb2e8f9f7 1551 * @}
<> 144:ef7eb2e8f9f7 1552 */
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/