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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.c@180:d79f997829d6, 2017-12-18 (annotated)

Committer:: Anythingconnected
Date:: Mon Dec 18 10:14:27 2017 +0000
Revision:: 180:d79f997829d6
Parent:: 153:fa9ff456f731

Getting byte by byte read to work

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	149:156823d33999	1	/**
<>	149:156823d33999	2	******************************************************************************
<>	149:156823d33999	3	* @file stm32l1xx_hal_spi.c
<>	149:156823d33999	4	* @author MCD Application Team
<>	149:156823d33999	5	* @version V1.2.0
<>	149:156823d33999	6	* @date 01-July-2016
<>	149:156823d33999	7	* @brief SPI HAL module driver.
<>	149:156823d33999	8	*
<>	149:156823d33999	9	* This file provides firmware functions to manage the following
<>	149:156823d33999	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
<>	149:156823d33999	11	* + Initialization and de-initialization functions
<>	149:156823d33999	12	* + IO operation functions
<>	149:156823d33999	13	* + Peripheral Control functions
<>	149:156823d33999	14	* + Peripheral State functions
<>	149:156823d33999	15	@verbatim
<>	149:156823d33999	16	==============================================================================
<>	149:156823d33999	17	##### How to use this driver #####
<>	149:156823d33999	18	==============================================================================
<>	149:156823d33999	19	[..]
<>	149:156823d33999	20	The SPI HAL driver can be used as follows:
<>	149:156823d33999	21
<>	149:156823d33999	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
<>	149:156823d33999	23	SPI_HandleTypeDef hspi;
<>	149:156823d33999	24
<>	149:156823d33999	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
<>	149:156823d33999	26	(##) Enable the SPIx interface clock
<>	149:156823d33999	27	(##) SPI pins configuration
<>	149:156823d33999	28	(+++) Enable the clock for the SPI GPIOs
<>	149:156823d33999	29	(+++) Configure these SPI pins as alternate function push-pull
<>	149:156823d33999	30	(##) NVIC configuration if you need to use interrupt process
<>	149:156823d33999	31	(+++) Configure the SPIx interrupt priority
<>	149:156823d33999	32	(+++) Enable the NVIC SPI IRQ handle
<>	149:156823d33999	33	(##) DMA Configuration if you need to use DMA process
<>	149:156823d33999	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
<>	149:156823d33999	35	(+++) Enable the DMAx clock
<>	149:156823d33999	36	(+++) Configure the DMA handle parameters
<>	149:156823d33999	37	(+++) Configure the DMA Tx or Rx Channel
<>	149:156823d33999	38	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
<>	149:156823d33999	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
<>	149:156823d33999	40
<>	149:156823d33999	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
<>	149:156823d33999	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<>	149:156823d33999	43
<>	149:156823d33999	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<>	149:156823d33999	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<>	149:156823d33999	46	by calling the customed HAL_SPI_MspInit() API.
<>	149:156823d33999	47	[..]
<>	149:156823d33999	48	Circular mode restriction:
<>	149:156823d33999	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<>	149:156823d33999	50	(##) Master 2Lines RxOnly
<>	149:156823d33999	51	(##) Master 1Line Rx
<>	149:156823d33999	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
<>	149:156823d33999	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<>	149:156823d33999	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
<>	149:156823d33999	55
<>	149:156823d33999	56
<>	149:156823d33999	57
<>	149:156823d33999	58	@endverbatim
<>	149:156823d33999	59	******************************************************************************
<>	149:156823d33999	60	* @attention
<>	149:156823d33999	61	*
<>	149:156823d33999	62	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	149:156823d33999	63	*
<>	149:156823d33999	64	* Redistribution and use in source and binary forms, with or without modification,
<>	149:156823d33999	65	* are permitted provided that the following conditions are met:
<>	149:156823d33999	66	* 1. Redistributions of source code must retain the above copyright notice,
<>	149:156823d33999	67	* this list of conditions and the following disclaimer.
<>	149:156823d33999	68	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	149:156823d33999	69	* this list of conditions and the following disclaimer in the documentation
<>	149:156823d33999	70	* and/or other materials provided with the distribution.
<>	149:156823d33999	71	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	149:156823d33999	72	* may be used to endorse or promote products derived from this software
<>	149:156823d33999	73	* without specific prior written permission.
<>	149:156823d33999	74	*
<>	149:156823d33999	75	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	149:156823d33999	76	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	149:156823d33999	77	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	149:156823d33999	78	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	149:156823d33999	79	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	149:156823d33999	80	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	149:156823d33999	81	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	149:156823d33999	82	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	149:156823d33999	83	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	149:156823d33999	84	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	149:156823d33999	85	*
<>	149:156823d33999	86	******************************************************************************
<>	149:156823d33999	87	*/
<>	149:156823d33999	88
<>	149:156823d33999	89	/* Includes ------------------------------------------------------------------*/
<>	149:156823d33999	90	#include "stm32l1xx_hal.h"
<>	149:156823d33999	91
<>	149:156823d33999	92	/** @addtogroup STM32L1xx_HAL_Driver
<>	149:156823d33999	93	* @{
<>	149:156823d33999	94	*/
<>	149:156823d33999	95
<>	149:156823d33999	96	/** @defgroup SPI SPI
<>	149:156823d33999	97	* @brief SPI HAL module driver
<>	149:156823d33999	98	* @{
<>	149:156823d33999	99	*/
<>	149:156823d33999	100
<>	149:156823d33999	101	#ifdef HAL_SPI_MODULE_ENABLED
<>	149:156823d33999	102
<>	149:156823d33999	103	/* Private typedef -----------------------------------------------------------*/
<>	149:156823d33999	104	/* Private define ------------------------------------------------------------*/
<>	149:156823d33999	105	/** @defgroup SPI_Private_Constants SPI Private Constants
<>	149:156823d33999	106	* @{
<>	149:156823d33999	107	*/
<>	149:156823d33999	108	#define SPI_TIMEOUT_VALUE 10
<>	153:fa9ff456f731	109	#define SPI_DEFAULT_TIMEOUT 100U
<>	153:fa9ff456f731	110
<>	149:156823d33999	111	/**
<>	149:156823d33999	112	* @}
<>	149:156823d33999	113	*/
<>	149:156823d33999	114
<>	149:156823d33999	115	/* Private macro -------------------------------------------------------------*/
<>	149:156823d33999	116	/* Private variables ---------------------------------------------------------*/
<>	149:156823d33999	117	/* Private function prototypes -----------------------------------------------*/
<>	149:156823d33999	118	/** @defgroup SPI_Private_Functions SPI Private Functions
<>	149:156823d33999	119	* @{
<>	149:156823d33999	120	*/
<>	153:fa9ff456f731	121	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
<>	153:fa9ff456f731	122	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	123	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	124	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	125	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	126	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	127	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	128	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	129	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	130	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	131	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	132	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	133	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	134	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	135	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	136	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	137	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
<>	153:fa9ff456f731	138	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
<>	149:156823d33999	139	static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	140	static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	141	static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	142	static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	143	static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	144	static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	145	static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma);
<>	149:156823d33999	146	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<>	149:156823d33999	147	/**
<>	149:156823d33999	148	* @}
<>	149:156823d33999	149	*/
<>	149:156823d33999	150
<>	149:156823d33999	151	/* Exported functions ---------------------------------------------------------*/
<>	149:156823d33999	152
<>	149:156823d33999	153	/** @defgroup SPI_Exported_Functions SPI Exported Functions
<>	149:156823d33999	154	* @{
<>	149:156823d33999	155	*/
<>	149:156823d33999	156
<>	149:156823d33999	157	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<>	149:156823d33999	158	* @brief Initialization and Configuration functions
<>	149:156823d33999	159	*
<>	149:156823d33999	160	@verbatim
<>	149:156823d33999	161	===============================================================================
<>	149:156823d33999	162	##### Initialization and de-initialization functions #####
<>	149:156823d33999	163	===============================================================================
<>	149:156823d33999	164	[..] This subsection provides a set of functions allowing to initialize and
<>	149:156823d33999	165	de-initialiaze the SPIx peripheral:
<>	149:156823d33999	166
<>	149:156823d33999	167	(+) User must implement HAL_SPI_MspInit() function in which he configures
<>	149:156823d33999	168	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<>	149:156823d33999	169
<>	149:156823d33999	170	(+) Call the function HAL_SPI_Init() to configure the selected device with
<>	149:156823d33999	171	the selected configuration:
<>	149:156823d33999	172	(++) Mode
<>	149:156823d33999	173	(++) Direction
<>	149:156823d33999	174	(++) Data Size
<>	149:156823d33999	175	(++) Clock Polarity and Phase
<>	149:156823d33999	176	(++) NSS Management
<>	149:156823d33999	177	(++) BaudRate Prescaler
<>	149:156823d33999	178	(++) FirstBit
<>	149:156823d33999	179	(++) TIMode
<>	149:156823d33999	180	(++) CRC Calculation
<>	149:156823d33999	181	(++) CRC Polynomial if CRC enabled
<>	149:156823d33999	182
<>	149:156823d33999	183	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
<>	149:156823d33999	184	of the selected SPIx periperal.
<>	149:156823d33999	185
<>	149:156823d33999	186	@endverbatim
<>	149:156823d33999	187	* @{
<>	149:156823d33999	188	*/
<>	149:156823d33999	189
<>	149:156823d33999	190	/**
<>	149:156823d33999	191	* @brief Initializes the SPI according to the specified parameters
<>	149:156823d33999	192	* in the SPI_InitTypeDef and create the associated handle.
<>	149:156823d33999	193	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	194	* the configuration information for SPI module.
<>	149:156823d33999	195	* @retval HAL status
<>	149:156823d33999	196	*/
<>	149:156823d33999	197	__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	198	{
<>	149:156823d33999	199	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	200	UNUSED(hspi);
<>	149:156823d33999	201
<>	149:156823d33999	202	return HAL_ERROR;
<>	149:156823d33999	203	}
<>	149:156823d33999	204
<>	149:156823d33999	205	/**
<>	149:156823d33999	206	* @brief DeInitializes the SPI peripheral
<>	149:156823d33999	207	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	208	* the configuration information for SPI module.
<>	149:156823d33999	209	* @retval HAL status
<>	149:156823d33999	210	*/
<>	149:156823d33999	211	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	212	{
<>	149:156823d33999	213	/* Check the SPI handle allocation */
<>	149:156823d33999	214	if(hspi == NULL)
<>	149:156823d33999	215	{
<>	149:156823d33999	216	return HAL_ERROR;
<>	149:156823d33999	217	}
<>	149:156823d33999	218
<>	149:156823d33999	219	/* Disable the SPI Peripheral Clock */
<>	149:156823d33999	220	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	221
<>	149:156823d33999	222	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<>	149:156823d33999	223	HAL_SPI_MspDeInit(hspi);
<>	149:156823d33999	224
<>	149:156823d33999	225	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	226	hspi->State = HAL_SPI_STATE_RESET;
<>	149:156823d33999	227
<>	149:156823d33999	228	/* Release Lock */
<>	149:156823d33999	229	__HAL_UNLOCK(hspi);
<>	149:156823d33999	230
<>	149:156823d33999	231	return HAL_OK;
<>	149:156823d33999	232	}
<>	149:156823d33999	233
<>	149:156823d33999	234	/**
<>	149:156823d33999	235	* @brief SPI MSP Init
<>	149:156823d33999	236	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	237	* the configuration information for SPI module.
<>	149:156823d33999	238	* @retval None
<>	149:156823d33999	239	*/
<>	149:156823d33999	240	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	241	{
<>	149:156823d33999	242	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	243	UNUSED(hspi);
<>	149:156823d33999	244
<>	149:156823d33999	245	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	246	the HAL_SPI_MspInit could be implenetd in the user file
<>	149:156823d33999	247	*/
<>	149:156823d33999	248	}
<>	149:156823d33999	249
<>	149:156823d33999	250	/**
<>	149:156823d33999	251	* @brief SPI MSP DeInit
<>	149:156823d33999	252	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	253	* the configuration information for SPI module.
<>	149:156823d33999	254	* @retval None
<>	149:156823d33999	255	*/
<>	149:156823d33999	256	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	257	{
<>	149:156823d33999	258	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	259	UNUSED(hspi);
<>	149:156823d33999	260
<>	149:156823d33999	261	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	262	the HAL_SPI_MspDeInit could be implenetd in the user file
<>	149:156823d33999	263	*/
<>	149:156823d33999	264	}
<>	149:156823d33999	265
<>	149:156823d33999	266	/**
<>	149:156823d33999	267	* @}
<>	149:156823d33999	268	*/
<>	149:156823d33999	269
<>	149:156823d33999	270	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
<>	149:156823d33999	271	* @brief Data transfers functions
<>	149:156823d33999	272	*
<>	149:156823d33999	273	@verbatim
<>	149:156823d33999	274	==============================================================================
<>	149:156823d33999	275	##### IO operation functions #####
<>	149:156823d33999	276	===============================================================================
<>	149:156823d33999	277	This subsection provides a set of functions allowing to manage the SPI
<>	149:156823d33999	278	data transfers.
<>	149:156823d33999	279
<>	149:156823d33999	280	[..] The SPI supports master and slave mode :
<>	149:156823d33999	281
<>	149:156823d33999	282	(#) There are two modes of transfer:
<>	149:156823d33999	283	(++) Blocking mode: The communication is performed in polling mode.
<>	149:156823d33999	284	The HAL status of all data processing is returned by the same function
<>	149:156823d33999	285	after finishing transfer.
<>	149:156823d33999	286	(++) No-Blocking mode: The communication is performed using Interrupts
<>	149:156823d33999	287	or DMA, These APIs return the HAL status.
<>	149:156823d33999	288	The end of the data processing will be indicated through the
<>	149:156823d33999	289	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
<>	149:156823d33999	290	using DMA mode.
<>	149:156823d33999	291	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
<>	149:156823d33999	292	will be executed respectivelly at the end of the transmit or Receive process
<>	149:156823d33999	293	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<>	149:156823d33999	294
<>	149:156823d33999	295	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
<>	149:156823d33999	296	exist for 1Line (simplex) and 2Lines (full duplex) modes.
<>	149:156823d33999	297
<>	149:156823d33999	298	@endverbatim
<>	149:156823d33999	299	* @{
<>	149:156823d33999	300	*/
<>	149:156823d33999	301
<>	149:156823d33999	302	/**
<>	149:156823d33999	303	* @brief Transmit an amount of data in blocking mode
<>	149:156823d33999	304	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	305	* the configuration information for SPI module.
<>	149:156823d33999	306	* @param pData: pointer to data buffer
<>	149:156823d33999	307	* @param Size: amount of data to be sent
<>	149:156823d33999	308	* @param Timeout: Timeout duration
<>	149:156823d33999	309	* @retval HAL status
<>	149:156823d33999	310	*/
<>	149:156823d33999	311	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	149:156823d33999	312	{
<>	149:156823d33999	313
<>	149:156823d33999	314	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	315	{
<>	149:156823d33999	316	if((pData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	317	{
<>	149:156823d33999	318	return HAL_ERROR;
<>	149:156823d33999	319	}
<>	149:156823d33999	320
<>	149:156823d33999	321	/* Check the parameters */
<>	149:156823d33999	322	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	149:156823d33999	323
<>	149:156823d33999	324	/* Process Locked */
<>	149:156823d33999	325	__HAL_LOCK(hspi);
<>	149:156823d33999	326
<>	149:156823d33999	327	/* Configure communication */
<>	149:156823d33999	328	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	149:156823d33999	329	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	330
<>	149:156823d33999	331	hspi->pTxBuffPtr = pData;
<>	149:156823d33999	332	hspi->TxXferSize = Size;
<>	149:156823d33999	333	hspi->TxXferCount = Size;
<>	149:156823d33999	334
<>	149:156823d33999	335	/Init field not used in handle to zero /
<>	149:156823d33999	336	hspi->TxISR = 0;
<>	149:156823d33999	337	hspi->RxISR = 0;
<>	149:156823d33999	338	hspi->pRxBuffPtr = NULL;
<>	149:156823d33999	339	hspi->RxXferSize = 0;
<>	149:156823d33999	340	hspi->RxXferCount = 0;
<>	149:156823d33999	341
<>	149:156823d33999	342	/* Reset CRC Calculation */
<>	149:156823d33999	343	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	344	{
<>	149:156823d33999	345	SPI_RESET_CRC(hspi);
<>	149:156823d33999	346	}
<>	149:156823d33999	347
<>	149:156823d33999	348	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	349	{
<>	149:156823d33999	350	/* Configure communication direction : 1Line */
<>	149:156823d33999	351	SPI_1LINE_TX(hspi);
<>	149:156823d33999	352	}
<>	149:156823d33999	353
<>	149:156823d33999	354	/* Check if the SPI is already enabled */
<>	149:156823d33999	355	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	356	{
<>	149:156823d33999	357	/* Enable SPI peripheral */
<>	149:156823d33999	358	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	359	}
<>	149:156823d33999	360
<>	149:156823d33999	361	/* Transmit data in 8 Bit mode */
<>	149:156823d33999	362	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	363	{
<>	149:156823d33999	364	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
<>	149:156823d33999	365	{
<>	149:156823d33999	366	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	367	hspi->TxXferCount--;
<>	149:156823d33999	368	}
<>	149:156823d33999	369	while(hspi->TxXferCount > 0)
<>	149:156823d33999	370	{
<>	149:156823d33999	371	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	372	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	373	{
<>	149:156823d33999	374	return HAL_TIMEOUT;
<>	149:156823d33999	375	}
<>	149:156823d33999	376	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	377	hspi->TxXferCount--;
<>	149:156823d33999	378	}
<>	149:156823d33999	379	/* Enable CRC Transmission */
<>	149:156823d33999	380	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	381	{
<>	149:156823d33999	382	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	383	}
<>	149:156823d33999	384	}
<>	149:156823d33999	385	/* Transmit data in 16 Bit mode */
<>	149:156823d33999	386	else
<>	149:156823d33999	387	{
<>	149:156823d33999	388	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
<>	149:156823d33999	389	{
<>	149:156823d33999	390	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	391	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	392	hspi->TxXferCount--;
<>	149:156823d33999	393	}
<>	149:156823d33999	394	while(hspi->TxXferCount > 0)
<>	149:156823d33999	395	{
<>	149:156823d33999	396	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	397	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	398	{
<>	149:156823d33999	399	return HAL_TIMEOUT;
<>	149:156823d33999	400	}
<>	149:156823d33999	401	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	402	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	403	hspi->TxXferCount--;
<>	149:156823d33999	404	}
<>	149:156823d33999	405	/* Enable CRC Transmission */
<>	149:156823d33999	406	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	407	{
<>	149:156823d33999	408	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	409	}
<>	149:156823d33999	410	}
<>	149:156823d33999	411
<>	149:156823d33999	412	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	413	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	414	{
<>	149:156823d33999	415	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	416	return HAL_TIMEOUT;
<>	149:156823d33999	417	}
<>	149:156823d33999	418
<>	149:156823d33999	419	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	420	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<>	149:156823d33999	421	{
<>	149:156823d33999	422	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	423	return HAL_TIMEOUT;
<>	149:156823d33999	424	}
<>	149:156823d33999	425
<>	149:156823d33999	426	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<>	149:156823d33999	427	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	149:156823d33999	428	{
<>	149:156823d33999	429	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	149:156823d33999	430	}
<>	149:156823d33999	431
<>	149:156823d33999	432	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	433
<>	149:156823d33999	434	/* Process Unlocked */
<>	149:156823d33999	435	__HAL_UNLOCK(hspi);
<>	149:156823d33999	436
<>	149:156823d33999	437	return HAL_OK;
<>	149:156823d33999	438	}
<>	149:156823d33999	439	else
<>	149:156823d33999	440	{
<>	149:156823d33999	441	return HAL_BUSY;
<>	149:156823d33999	442	}
<>	149:156823d33999	443	}
<>	149:156823d33999	444
<>	149:156823d33999	445	/**
<>	149:156823d33999	446	* @brief Receive an amount of data in blocking mode
<>	149:156823d33999	447	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	448	* the configuration information for SPI module.
<>	149:156823d33999	449	* @param pData: pointer to data buffer
<>	149:156823d33999	450	* @param Size: amount of data to be sent
<>	149:156823d33999	451	* @param Timeout: Timeout duration
<>	149:156823d33999	452	* @retval HAL status
<>	149:156823d33999	453	*/
<>	149:156823d33999	454	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	149:156823d33999	455	{
<>	149:156823d33999	456	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	457
<>	149:156823d33999	458	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	459	{
<>	149:156823d33999	460	if((pData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	461	{
<>	149:156823d33999	462	return HAL_ERROR;
<>	149:156823d33999	463	}
<>	149:156823d33999	464
<>	149:156823d33999	465	/* Process Locked */
<>	149:156823d33999	466	__HAL_LOCK(hspi);
<>	149:156823d33999	467
<>	149:156823d33999	468	/* Configure communication */
<>	149:156823d33999	469	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	149:156823d33999	470	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	471
<>	149:156823d33999	472	hspi->pRxBuffPtr = pData;
<>	149:156823d33999	473	hspi->RxXferSize = Size;
<>	149:156823d33999	474	hspi->RxXferCount = Size;
<>	149:156823d33999	475
<>	149:156823d33999	476	/Init field not used in handle to zero /
<>	149:156823d33999	477	hspi->RxISR = 0;
<>	149:156823d33999	478	hspi->TxISR = 0;
<>	149:156823d33999	479	hspi->pTxBuffPtr = NULL;
<>	149:156823d33999	480	hspi->TxXferSize = 0;
<>	149:156823d33999	481	hspi->TxXferCount = 0;
<>	149:156823d33999	482
<>	149:156823d33999	483	/* Configure communication direction : 1Line */
<>	149:156823d33999	484	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	485	{
<>	149:156823d33999	486	SPI_1LINE_RX(hspi);
<>	149:156823d33999	487	}
<>	149:156823d33999	488
<>	149:156823d33999	489	/* Reset CRC Calculation */
<>	149:156823d33999	490	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	491	{
<>	149:156823d33999	492	SPI_RESET_CRC(hspi);
<>	149:156823d33999	493	}
<>	149:156823d33999	494
<>	149:156823d33999	495	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<>	149:156823d33999	496	{
<>	149:156823d33999	497	/* Process Unlocked */
<>	149:156823d33999	498	__HAL_UNLOCK(hspi);
<>	149:156823d33999	499
<>	149:156823d33999	500	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	149:156823d33999	501	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<>	149:156823d33999	502	}
<>	149:156823d33999	503
<>	149:156823d33999	504	/* Check if the SPI is already enabled */
<>	149:156823d33999	505	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	506	{
<>	149:156823d33999	507	/* Enable SPI peripheral */
<>	149:156823d33999	508	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	509	}
<>	149:156823d33999	510
<>	149:156823d33999	511	/* Receive data in 8 Bit mode */
<>	149:156823d33999	512	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	513	{
<>	149:156823d33999	514	while(hspi->RxXferCount > 1)
<>	149:156823d33999	515	{
<>	149:156823d33999	516	/* Wait until RXNE flag is set */
<>	149:156823d33999	517	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	518	{
<>	149:156823d33999	519	return HAL_TIMEOUT;
<>	149:156823d33999	520	}
<>	149:156823d33999	521
<>	149:156823d33999	522	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	523	hspi->RxXferCount--;
<>	149:156823d33999	524	}
<>	149:156823d33999	525	/* Enable CRC Transmission */
<>	149:156823d33999	526	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	527	{
<>	149:156823d33999	528	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	529	}
<>	149:156823d33999	530	}
<>	149:156823d33999	531	/* Receive data in 16 Bit mode */
<>	149:156823d33999	532	else
<>	149:156823d33999	533	{
<>	149:156823d33999	534	while(hspi->RxXferCount > 1)
<>	149:156823d33999	535	{
<>	149:156823d33999	536	/* Wait until RXNE flag is set to read data */
<>	149:156823d33999	537	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	538	{
<>	149:156823d33999	539	return HAL_TIMEOUT;
<>	149:156823d33999	540	}
<>	149:156823d33999	541
<>	149:156823d33999	542	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	543	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	544	hspi->RxXferCount--;
<>	149:156823d33999	545	}
<>	149:156823d33999	546	/* Enable CRC Transmission */
<>	149:156823d33999	547	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	548	{
<>	149:156823d33999	549	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	550	}
<>	149:156823d33999	551	}
<>	149:156823d33999	552
<>	149:156823d33999	553	/* Wait until RXNE flag is set */
<>	149:156823d33999	554	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	555	{
<>	149:156823d33999	556	return HAL_TIMEOUT;
<>	149:156823d33999	557	}
<>	149:156823d33999	558
<>	149:156823d33999	559	/* Receive last data in 8 Bit mode */
<>	149:156823d33999	560	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	149:156823d33999	561	{
<>	149:156823d33999	562	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	563	}
<>	149:156823d33999	564	/* Receive last data in 16 Bit mode */
<>	149:156823d33999	565	else
<>	149:156823d33999	566	{
<>	149:156823d33999	567	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	568	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	569	}
<>	149:156823d33999	570	hspi->RxXferCount--;
<>	149:156823d33999	571
<>	149:156823d33999	572	/* Wait until RXNE flag is set: CRC Received */
<>	149:156823d33999	573	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	574	{
<>	149:156823d33999	575	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	576	{
<>	149:156823d33999	577	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	578	return HAL_TIMEOUT;
<>	149:156823d33999	579	}
<>	149:156823d33999	580
<>	149:156823d33999	581	/* Read CRC to Flush RXNE flag */
<>	149:156823d33999	582	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	583	UNUSED(tmpreg);
<>	149:156823d33999	584	}
<>	149:156823d33999	585
<>	149:156823d33999	586	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	149:156823d33999	587	{
<>	149:156823d33999	588	/* Disable SPI peripheral */
<>	149:156823d33999	589	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	590	}
<>	149:156823d33999	591
<>	149:156823d33999	592	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	593
<>	149:156823d33999	594	/* Check if CRC error occurred */
<>	149:156823d33999	595	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<>	149:156823d33999	596	{
<>	149:156823d33999	597	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	598
<>	149:156823d33999	599	/* Reset CRC Calculation */
<>	149:156823d33999	600	SPI_RESET_CRC(hspi);
<>	149:156823d33999	601
<>	149:156823d33999	602	/* Process Unlocked */
<>	149:156823d33999	603	__HAL_UNLOCK(hspi);
<>	149:156823d33999	604
<>	149:156823d33999	605	return HAL_ERROR;
<>	149:156823d33999	606	}
<>	149:156823d33999	607
<>	149:156823d33999	608	/* Process Unlocked */
<>	149:156823d33999	609	__HAL_UNLOCK(hspi);
<>	149:156823d33999	610
<>	149:156823d33999	611	return HAL_OK;
<>	149:156823d33999	612	}
<>	149:156823d33999	613	else
<>	149:156823d33999	614	{
<>	149:156823d33999	615	return HAL_BUSY;
<>	149:156823d33999	616	}
<>	149:156823d33999	617	}
<>	149:156823d33999	618
<>	149:156823d33999	619	/**
<>	149:156823d33999	620	* @brief Transmit and Receive an amount of data in blocking mode
<>	149:156823d33999	621	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	622	* the configuration information for SPI module.
<>	149:156823d33999	623	* @param pTxData: pointer to transmission data buffer
<>	149:156823d33999	624	* @param pRxData: pointer to reception data buffer to be
<>	149:156823d33999	625	* @param Size: amount of data to be sent
<>	149:156823d33999	626	* @param Timeout: Timeout duration
<>	149:156823d33999	627	* @retval HAL status
<>	149:156823d33999	628	*/
<>	149:156823d33999	629	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<>	149:156823d33999	630	{
<>	149:156823d33999	631	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	632
<>	149:156823d33999	633	if((hspi->State == HAL_SPI_STATE_READY) \|\| (hspi->State == HAL_SPI_STATE_BUSY_RX))
<>	149:156823d33999	634	{
<>	149:156823d33999	635	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	636	{
<>	149:156823d33999	637	return HAL_ERROR;
<>	149:156823d33999	638	}
<>	149:156823d33999	639
<>	149:156823d33999	640	/* Check the parameters */
<>	149:156823d33999	641	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	149:156823d33999	642
<>	149:156823d33999	643	/* Process Locked */
<>	149:156823d33999	644	__HAL_LOCK(hspi);
<>	149:156823d33999	645
<>	149:156823d33999	646	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	149:156823d33999	647	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	648	{
<>	149:156823d33999	649	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	149:156823d33999	650	}
<>	149:156823d33999	651
<>	149:156823d33999	652	/* Configure communication */
<>	149:156823d33999	653	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	654
<>	149:156823d33999	655	hspi->pRxBuffPtr = pRxData;
<>	149:156823d33999	656	hspi->RxXferSize = Size;
<>	149:156823d33999	657	hspi->RxXferCount = Size;
<>	149:156823d33999	658
<>	149:156823d33999	659	hspi->pTxBuffPtr = pTxData;
<>	149:156823d33999	660	hspi->TxXferSize = Size;
<>	149:156823d33999	661	hspi->TxXferCount = Size;
<>	149:156823d33999	662
<>	149:156823d33999	663	/Init field not used in handle to zero /
<>	149:156823d33999	664	hspi->RxISR = 0;
<>	149:156823d33999	665	hspi->TxISR = 0;
<>	149:156823d33999	666
<>	149:156823d33999	667	/* Reset CRC Calculation */
<>	149:156823d33999	668	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	669	{
<>	149:156823d33999	670	SPI_RESET_CRC(hspi);
<>	149:156823d33999	671	}
<>	149:156823d33999	672
<>	149:156823d33999	673	/* Check if the SPI is already enabled */
<>	149:156823d33999	674	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	675	{
<>	149:156823d33999	676	/* Enable SPI peripheral */
<>	149:156823d33999	677	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	678	}
<>	149:156823d33999	679
<>	149:156823d33999	680	/* Transmit and Receive data in 16 Bit mode */
<>	149:156823d33999	681	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<>	149:156823d33999	682	{
<>	149:156823d33999	683	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
<>	149:156823d33999	684	{
<>	149:156823d33999	685	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	686	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	687	hspi->TxXferCount--;
<>	149:156823d33999	688	}
<>	149:156823d33999	689	if(hspi->TxXferCount == 0)
<>	149:156823d33999	690	{
<>	149:156823d33999	691	/* Enable CRC Transmission */
<>	149:156823d33999	692	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	693	{
<>	149:156823d33999	694	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	695	}
<>	149:156823d33999	696
<>	149:156823d33999	697	/* Wait until RXNE flag is set */
<>	149:156823d33999	698	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	699	{
<>	149:156823d33999	700	return HAL_TIMEOUT;
<>	149:156823d33999	701	}
<>	149:156823d33999	702
<>	149:156823d33999	703	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	704	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	705	hspi->RxXferCount--;
<>	149:156823d33999	706	}
<>	149:156823d33999	707	else
<>	149:156823d33999	708	{
<>	149:156823d33999	709	while(hspi->TxXferCount > 0)
<>	149:156823d33999	710	{
<>	149:156823d33999	711	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	712	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	713	{
<>	149:156823d33999	714	return HAL_TIMEOUT;
<>	149:156823d33999	715	}
<>	149:156823d33999	716
<>	149:156823d33999	717	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	149:156823d33999	718	hspi->pTxBuffPtr+=2;
<>	149:156823d33999	719	hspi->TxXferCount--;
<>	149:156823d33999	720
<>	149:156823d33999	721	/* Enable CRC Transmission */
<>	149:156823d33999	722	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	149:156823d33999	723	{
<>	149:156823d33999	724	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	725	}
<>	149:156823d33999	726
<>	149:156823d33999	727	/* Wait until RXNE flag is set */
<>	149:156823d33999	728	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	729	{
<>	149:156823d33999	730	return HAL_TIMEOUT;
<>	149:156823d33999	731	}
<>	149:156823d33999	732
<>	149:156823d33999	733	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	734	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	735	hspi->RxXferCount--;
<>	149:156823d33999	736	}
<>	149:156823d33999	737	/* Receive the last byte */
<>	149:156823d33999	738	if(hspi->Init.Mode == SPI_MODE_SLAVE)
<>	149:156823d33999	739	{
<>	149:156823d33999	740	/* Wait until RXNE flag is set */
<>	149:156823d33999	741	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	742	{
<>	149:156823d33999	743	return HAL_TIMEOUT;
<>	149:156823d33999	744	}
<>	149:156823d33999	745
<>	149:156823d33999	746	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	747	hspi->pRxBuffPtr+=2;
<>	149:156823d33999	748	hspi->RxXferCount--;
<>	149:156823d33999	749	}
<>	149:156823d33999	750	}
<>	149:156823d33999	751	}
<>	149:156823d33999	752	/* Transmit and Receive data in 8 Bit mode */
<>	149:156823d33999	753	else
<>	149:156823d33999	754	{
<>	149:156823d33999	755	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
<>	149:156823d33999	756	{
<>	149:156823d33999	757	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	758	hspi->TxXferCount--;
<>	149:156823d33999	759	}
<>	149:156823d33999	760	if(hspi->TxXferCount == 0)
<>	149:156823d33999	761	{
<>	149:156823d33999	762	/* Enable CRC Transmission */
<>	149:156823d33999	763	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	764	{
<>	149:156823d33999	765	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	766	}
<>	149:156823d33999	767
<>	149:156823d33999	768	/* Wait until RXNE flag is set */
<>	149:156823d33999	769	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	770	{
<>	149:156823d33999	771	return HAL_TIMEOUT;
<>	149:156823d33999	772	}
<>	149:156823d33999	773
<>	149:156823d33999	774	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	149:156823d33999	775	hspi->RxXferCount--;
<>	149:156823d33999	776	}
<>	149:156823d33999	777	else
<>	149:156823d33999	778	{
<>	149:156823d33999	779	while(hspi->TxXferCount > 0)
<>	149:156823d33999	780	{
<>	149:156823d33999	781	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	782	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	783	{
<>	149:156823d33999	784	return HAL_TIMEOUT;
<>	149:156823d33999	785	}
<>	149:156823d33999	786
<>	149:156823d33999	787	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	149:156823d33999	788	hspi->TxXferCount--;
<>	149:156823d33999	789
<>	149:156823d33999	790	/* Enable CRC Transmission */
<>	149:156823d33999	791	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	149:156823d33999	792	{
<>	149:156823d33999	793	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	794	}
<>	149:156823d33999	795
<>	149:156823d33999	796	/* Wait until RXNE flag is set */
<>	149:156823d33999	797	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	798	{
<>	149:156823d33999	799	return HAL_TIMEOUT;
<>	149:156823d33999	800	}
<>	149:156823d33999	801
<>	149:156823d33999	802	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	803	hspi->RxXferCount--;
<>	149:156823d33999	804	}
<>	149:156823d33999	805	if(hspi->Init.Mode == SPI_MODE_SLAVE)
<>	149:156823d33999	806	{
<>	149:156823d33999	807	/* Wait until RXNE flag is set */
<>	149:156823d33999	808	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	809	{
<>	149:156823d33999	810	return HAL_TIMEOUT;
<>	149:156823d33999	811	}
<>	149:156823d33999	812
<>	149:156823d33999	813	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	149:156823d33999	814	hspi->RxXferCount--;
<>	149:156823d33999	815	}
<>	149:156823d33999	816	}
<>	149:156823d33999	817	}
<>	149:156823d33999	818
<>	149:156823d33999	819	/* Read CRC from DR to close CRC calculation process */
<>	149:156823d33999	820	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	821	{
<>	149:156823d33999	822	/* Wait until RXNE flag is set */
<>	149:156823d33999	823	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	149:156823d33999	824	{
<>	149:156823d33999	825	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	826	return HAL_TIMEOUT;
<>	149:156823d33999	827	}
<>	149:156823d33999	828	/* Read CRC */
<>	149:156823d33999	829	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	830	UNUSED(tmpreg);
<>	149:156823d33999	831	}
<>	149:156823d33999	832
<>	149:156823d33999	833	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	834	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<>	149:156823d33999	835	{
<>	149:156823d33999	836	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	837	return HAL_TIMEOUT;
<>	149:156823d33999	838	}
<>	149:156823d33999	839
<>	149:156823d33999	840	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	841
<>	149:156823d33999	842	/* Check if CRC error occurred */
<>	149:156823d33999	843	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<>	149:156823d33999	844	{
<>	149:156823d33999	845	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	846
<>	149:156823d33999	847	/* Reset CRC Calculation */
<>	149:156823d33999	848	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	849	{
<>	149:156823d33999	850	SPI_RESET_CRC(hspi);
<>	149:156823d33999	851	}
<>	149:156823d33999	852
<>	149:156823d33999	853	/* Process Unlocked */
<>	149:156823d33999	854	__HAL_UNLOCK(hspi);
<>	149:156823d33999	855
<>	149:156823d33999	856	return HAL_ERROR;
<>	149:156823d33999	857	}
<>	149:156823d33999	858
<>	149:156823d33999	859	/* Process Unlocked */
<>	149:156823d33999	860	__HAL_UNLOCK(hspi);
<>	149:156823d33999	861
<>	149:156823d33999	862	return HAL_OK;
<>	149:156823d33999	863	}
<>	149:156823d33999	864	else
<>	149:156823d33999	865	{
<>	149:156823d33999	866	return HAL_BUSY;
<>	149:156823d33999	867	}
<>	149:156823d33999	868	}
<>	149:156823d33999	869
<>	149:156823d33999	870	/**
<>	149:156823d33999	871	* @brief Transmit an amount of data in no-blocking mode with Interrupt
<>	149:156823d33999	872	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	873	* the configuration information for SPI module.
<>	149:156823d33999	874	* @param pData: pointer to data buffer
<>	149:156823d33999	875	* @param Size: amount of data to be sent
<>	149:156823d33999	876	* @retval HAL status
<>	149:156823d33999	877	*/
<>	149:156823d33999	878	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	879	{
<>	149:156823d33999	880	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	881	{
<>	149:156823d33999	882	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	883	{
<>	149:156823d33999	884	return HAL_ERROR;
<>	149:156823d33999	885	}
<>	149:156823d33999	886
<>	149:156823d33999	887	/* Check the parameters */
<>	149:156823d33999	888	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	149:156823d33999	889
<>	149:156823d33999	890	/* Process Locked */
<>	149:156823d33999	891	__HAL_LOCK(hspi);
<>	149:156823d33999	892
<>	149:156823d33999	893	/* Configure communication */
<>	149:156823d33999	894	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	149:156823d33999	895	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	896
<>	153:fa9ff456f731	897	/* Set the function for IT treatment */
<>	153:fa9ff456f731	898	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<>	153:fa9ff456f731	899	{
<>	153:fa9ff456f731	900	hspi->TxISR = SPI_TxISR_16BIT;
<>	153:fa9ff456f731	901	}
<>	153:fa9ff456f731	902	else
<>	153:fa9ff456f731	903	{
<>	153:fa9ff456f731	904	hspi->TxISR = SPI_TxISR_8BIT;
<>	153:fa9ff456f731	905	}
<>	153:fa9ff456f731	906
<>	149:156823d33999	907	hspi->pTxBuffPtr = pData;
<>	149:156823d33999	908	hspi->TxXferSize = Size;
<>	149:156823d33999	909	hspi->TxXferCount = Size;
<>	149:156823d33999	910
<>	149:156823d33999	911	/Init field not used in handle to zero /
<>	149:156823d33999	912	hspi->RxISR = 0;
<>	149:156823d33999	913	hspi->pRxBuffPtr = NULL;
<>	149:156823d33999	914	hspi->RxXferSize = 0;
<>	149:156823d33999	915	hspi->RxXferCount = 0;
<>	149:156823d33999	916
<>	149:156823d33999	917	/* Configure communication direction : 1Line */
<>	149:156823d33999	918	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	919	{
<>	149:156823d33999	920	SPI_1LINE_TX(hspi);
<>	149:156823d33999	921	}
<>	149:156823d33999	922
<>	149:156823d33999	923	/* Reset CRC Calculation */
<>	149:156823d33999	924	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	925	{
<>	149:156823d33999	926	SPI_RESET_CRC(hspi);
<>	149:156823d33999	927	}
<>	149:156823d33999	928
<>	149:156823d33999	929	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	149:156823d33999	930	{
<>	149:156823d33999	931	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
<>	149:156823d33999	932	}else
<>	149:156823d33999	933	{
<>	149:156823d33999	934	/* Enable TXE and ERR interrupt */
<>	149:156823d33999	935	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
<>	149:156823d33999	936	}
<>	149:156823d33999	937	/* Process Unlocked */
<>	149:156823d33999	938	__HAL_UNLOCK(hspi);
<>	149:156823d33999	939
<>	149:156823d33999	940	/* Check if the SPI is already enabled */
<>	149:156823d33999	941	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	942	{
<>	149:156823d33999	943	/* Enable SPI peripheral */
<>	149:156823d33999	944	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	945	}
<>	149:156823d33999	946
<>	149:156823d33999	947	return HAL_OK;
<>	149:156823d33999	948	}
<>	149:156823d33999	949	else
<>	149:156823d33999	950	{
<>	149:156823d33999	951	return HAL_BUSY;
<>	149:156823d33999	952	}
<>	149:156823d33999	953	}
<>	149:156823d33999	954
<>	149:156823d33999	955	/**
<>	149:156823d33999	956	* @brief Receive an amount of data in no-blocking mode with Interrupt
<>	149:156823d33999	957	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	958	* the configuration information for SPI module.
<>	149:156823d33999	959	* @param pData: pointer to data buffer
<>	149:156823d33999	960	* @param Size: amount of data to be sent
<>	149:156823d33999	961	* @retval HAL status
<>	149:156823d33999	962	*/
<>	149:156823d33999	963	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	964	{
<>	149:156823d33999	965	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	966	{
<>	149:156823d33999	967	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	968	{
<>	149:156823d33999	969	return HAL_ERROR;
<>	149:156823d33999	970	}
<>	149:156823d33999	971
<>	149:156823d33999	972	/* Process Locked */
<>	149:156823d33999	973	__HAL_LOCK(hspi);
<>	149:156823d33999	974
<>	149:156823d33999	975	/* Configure communication */
<>	149:156823d33999	976	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	149:156823d33999	977	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	978
<>	153:fa9ff456f731	979	/* Set the function for IT treatment */
<>	153:fa9ff456f731	980	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<>	153:fa9ff456f731	981	{
<>	153:fa9ff456f731	982	hspi->RxISR = SPI_RxISR_16BIT;
<>	153:fa9ff456f731	983	}
<>	153:fa9ff456f731	984	else
<>	153:fa9ff456f731	985	{
<>	153:fa9ff456f731	986	hspi->RxISR = SPI_RxISR_8BIT;
<>	153:fa9ff456f731	987	}
<>	149:156823d33999	988	hspi->pRxBuffPtr = pData;
<>	149:156823d33999	989	hspi->RxXferSize = Size;
<>	149:156823d33999	990	hspi->RxXferCount = Size ;
<>	149:156823d33999	991
<>	149:156823d33999	992	/Init field not used in handle to zero /
<>	149:156823d33999	993	hspi->TxISR = 0;
<>	149:156823d33999	994	hspi->pTxBuffPtr = NULL;
<>	149:156823d33999	995	hspi->TxXferSize = 0;
<>	149:156823d33999	996	hspi->TxXferCount = 0;
<>	149:156823d33999	997
<>	149:156823d33999	998	/* Configure communication direction : 1Line */
<>	149:156823d33999	999	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	1000	{
<>	149:156823d33999	1001	SPI_1LINE_RX(hspi);
<>	149:156823d33999	1002	}
<>	149:156823d33999	1003	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<>	149:156823d33999	1004	{
<>	149:156823d33999	1005	/* Process Unlocked */
<>	149:156823d33999	1006	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1007
<>	149:156823d33999	1008	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	149:156823d33999	1009	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
<>	149:156823d33999	1010	}
<>	149:156823d33999	1011
<>	149:156823d33999	1012	/* Reset CRC Calculation */
<>	149:156823d33999	1013	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1014	{
<>	149:156823d33999	1015	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1016	}
<>	149:156823d33999	1017
<>	149:156823d33999	1018	/* Enable TXE and ERR interrupt */
<>	149:156823d33999	1019	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	1020
<>	149:156823d33999	1021	/* Process Unlocked */
<>	149:156823d33999	1022	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1023
<>	149:156823d33999	1024	/* Note : The SPI must be enabled after unlocking current process
<>	149:156823d33999	1025	to avoid the risk of SPI interrupt handle execution before current
<>	149:156823d33999	1026	process unlock */
<>	149:156823d33999	1027
<>	149:156823d33999	1028	/* Check if the SPI is already enabled */
<>	149:156823d33999	1029	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1030	{
<>	149:156823d33999	1031	/* Enable SPI peripheral */
<>	149:156823d33999	1032	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1033	}
<>	149:156823d33999	1034
<>	149:156823d33999	1035	return HAL_OK;
<>	149:156823d33999	1036	}
<>	149:156823d33999	1037	else
<>	149:156823d33999	1038	{
<>	149:156823d33999	1039	return HAL_BUSY;
<>	149:156823d33999	1040	}
<>	149:156823d33999	1041	}
<>	149:156823d33999	1042
<>	149:156823d33999	1043	/**
<>	149:156823d33999	1044	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
<>	149:156823d33999	1045	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1046	* the configuration information for SPI module.
<>	149:156823d33999	1047	* @param pTxData: pointer to transmission data buffer
<>	149:156823d33999	1048	* @param pRxData: pointer to reception data buffer to be
<>	149:156823d33999	1049	* @param Size: amount of data to be sent
<>	149:156823d33999	1050	* @retval HAL status
<>	149:156823d33999	1051	*/
<>	149:156823d33999	1052	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	149:156823d33999	1053	{
<>	149:156823d33999	1054
<>	149:156823d33999	1055	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
<>	149:156823d33999	1056	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<>	149:156823d33999	1057	{
<>	149:156823d33999	1058	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	1059	{
<>	149:156823d33999	1060	return HAL_ERROR;
<>	149:156823d33999	1061	}
<>	149:156823d33999	1062
<>	149:156823d33999	1063	/* Check the parameters */
<>	149:156823d33999	1064	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	149:156823d33999	1065
<>	149:156823d33999	1066	/* Process locked */
<>	149:156823d33999	1067	__HAL_LOCK(hspi);
<>	149:156823d33999	1068
<>	149:156823d33999	1069	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	149:156823d33999	1070	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	149:156823d33999	1071	{
<>	149:156823d33999	1072	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	149:156823d33999	1073	}
<>	149:156823d33999	1074
<>	149:156823d33999	1075	/* Configure communication */
<>	149:156823d33999	1076	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1077
<>	149:156823d33999	1078	hspi->pTxBuffPtr = pTxData;
<>	149:156823d33999	1079	hspi->TxXferSize = Size;
<>	149:156823d33999	1080	hspi->TxXferCount = Size;
<>	149:156823d33999	1081
<>	149:156823d33999	1082	hspi->pRxBuffPtr = pRxData;
<>	149:156823d33999	1083	hspi->RxXferSize = Size;
<>	149:156823d33999	1084	hspi->RxXferCount = Size;
<>	149:156823d33999	1085
<>	153:fa9ff456f731	1086	/* Set the function for IT treatment */
<>	153:fa9ff456f731	1087	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
<>	153:fa9ff456f731	1088	{
<>	153:fa9ff456f731	1089	hspi->RxISR = SPI_2linesRxISR_16BIT;
<>	153:fa9ff456f731	1090	hspi->TxISR = SPI_2linesTxISR_16BIT;
<>	153:fa9ff456f731	1091	}
<>	153:fa9ff456f731	1092	else
<>	153:fa9ff456f731	1093	{
<>	153:fa9ff456f731	1094	hspi->RxISR = SPI_2linesRxISR_8BIT;
<>	153:fa9ff456f731	1095	hspi->TxISR = SPI_2linesTxISR_8BIT;
<>	153:fa9ff456f731	1096	}
<>	153:fa9ff456f731	1097
<>	149:156823d33999	1098	/* Reset CRC Calculation */
<>	149:156823d33999	1099	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1100	{
<>	149:156823d33999	1101	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1102	}
<>	149:156823d33999	1103
<>	149:156823d33999	1104	/* Enable TXE, RXNE and ERR interrupt */
<>	149:156823d33999	1105	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	1106
<>	149:156823d33999	1107	/* Process Unlocked */
<>	149:156823d33999	1108	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1109
<>	149:156823d33999	1110	/* Check if the SPI is already enabled */
<>	149:156823d33999	1111	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1112	{
<>	149:156823d33999	1113	/* Enable SPI peripheral */
<>	149:156823d33999	1114	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1115	}
<>	149:156823d33999	1116
<>	149:156823d33999	1117	return HAL_OK;
<>	149:156823d33999	1118	}
<>	149:156823d33999	1119	else
<>	149:156823d33999	1120	{
<>	149:156823d33999	1121	return HAL_BUSY;
<>	149:156823d33999	1122	}
<>	149:156823d33999	1123	}
<>	149:156823d33999	1124
<>	149:156823d33999	1125	/**
<>	149:156823d33999	1126	* @brief Transmit an amount of data in no-blocking mode with DMA
<>	149:156823d33999	1127	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1128	* the configuration information for SPI module.
<>	149:156823d33999	1129	* @param pData: pointer to data buffer
<>	149:156823d33999	1130	* @param Size: amount of data to be sent
<>	149:156823d33999	1131	* @retval HAL status
<>	149:156823d33999	1132	*/
<>	149:156823d33999	1133	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	1134	{
<>	149:156823d33999	1135	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	1136	{
<>	149:156823d33999	1137	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	1138	{
<>	149:156823d33999	1139	return HAL_ERROR;
<>	149:156823d33999	1140	}
<>	149:156823d33999	1141
<>	149:156823d33999	1142	/* Check the parameters */
<>	149:156823d33999	1143	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	149:156823d33999	1144
<>	149:156823d33999	1145	/* Process Locked */
<>	149:156823d33999	1146	__HAL_LOCK(hspi);
<>	149:156823d33999	1147
<>	149:156823d33999	1148	/* Configure communication */
<>	149:156823d33999	1149	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	149:156823d33999	1150	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1151
<>	149:156823d33999	1152	hspi->pTxBuffPtr = pData;
<>	149:156823d33999	1153	hspi->TxXferSize = Size;
<>	149:156823d33999	1154	hspi->TxXferCount = Size;
<>	149:156823d33999	1155
<>	149:156823d33999	1156	/Init field not used in handle to zero /
<>	149:156823d33999	1157	hspi->TxISR = 0;
<>	149:156823d33999	1158	hspi->RxISR = 0;
<>	149:156823d33999	1159	hspi->pRxBuffPtr = NULL;
<>	149:156823d33999	1160	hspi->RxXferSize = 0;
<>	149:156823d33999	1161	hspi->RxXferCount = 0;
<>	149:156823d33999	1162
<>	149:156823d33999	1163	/* Configure communication direction : 1Line */
<>	149:156823d33999	1164	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	1165	{
<>	149:156823d33999	1166	SPI_1LINE_TX(hspi);
<>	149:156823d33999	1167	}
<>	149:156823d33999	1168
<>	149:156823d33999	1169	/* Reset CRC Calculation */
<>	149:156823d33999	1170	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1171	{
<>	149:156823d33999	1172	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1173	}
<>	149:156823d33999	1174
<>	149:156823d33999	1175	/* Set the SPI TxDMA Half transfer complete callback */
<>	149:156823d33999	1176	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<>	149:156823d33999	1177
<>	149:156823d33999	1178	/* Set the SPI TxDMA transfer complete callback */
<>	149:156823d33999	1179	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<>	149:156823d33999	1180
<>	149:156823d33999	1181	/* Set the DMA error callback */
<>	149:156823d33999	1182	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1183
<>	149:156823d33999	1184	/* Enable the Tx DMA Channel */
<>	149:156823d33999	1185	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<>	149:156823d33999	1186
<>	149:156823d33999	1187	/* Enable Tx DMA Request */
<>	149:156823d33999	1188	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1189
<>	149:156823d33999	1190	/* Process Unlocked */
<>	149:156823d33999	1191	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1192
<>	149:156823d33999	1193	/* Check if the SPI is already enabled */
<>	149:156823d33999	1194	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1195	{
<>	149:156823d33999	1196	/* Enable SPI peripheral */
<>	149:156823d33999	1197	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1198	}
<>	149:156823d33999	1199
<>	149:156823d33999	1200	return HAL_OK;
<>	149:156823d33999	1201	}
<>	149:156823d33999	1202	else
<>	149:156823d33999	1203	{
<>	149:156823d33999	1204	return HAL_BUSY;
<>	149:156823d33999	1205	}
<>	149:156823d33999	1206	}
<>	149:156823d33999	1207
<>	149:156823d33999	1208	/**
<>	149:156823d33999	1209	* @brief Receive an amount of data in no-blocking mode with DMA
<>	149:156823d33999	1210	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1211	* the configuration information for SPI module.
<>	149:156823d33999	1212	* @param pData: pointer to data buffer
<>	149:156823d33999	1213	* @note When the CRC feature is enabled the pData Length must be Size + 1.
<>	149:156823d33999	1214	* @param Size: amount of data to be sent
<>	149:156823d33999	1215	* @retval HAL status
<>	149:156823d33999	1216	*/
<>	149:156823d33999	1217	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	149:156823d33999	1218	{
<>	149:156823d33999	1219	if(hspi->State == HAL_SPI_STATE_READY)
<>	149:156823d33999	1220	{
<>	149:156823d33999	1221	if((pData == NULL) \|\| (Size == 0))
<>	149:156823d33999	1222	{
<>	149:156823d33999	1223	return HAL_ERROR;
<>	149:156823d33999	1224	}
<>	149:156823d33999	1225
<>	149:156823d33999	1226	/* Process Locked */
<>	149:156823d33999	1227	__HAL_LOCK(hspi);
<>	149:156823d33999	1228
<>	149:156823d33999	1229	/* Configure communication */
<>	149:156823d33999	1230	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	149:156823d33999	1231	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1232
<>	149:156823d33999	1233	hspi->pRxBuffPtr = pData;
<>	149:156823d33999	1234	hspi->RxXferSize = Size;
<>	149:156823d33999	1235	hspi->RxXferCount = Size;
<>	149:156823d33999	1236
<>	149:156823d33999	1237	/Init field not used in handle to zero /
<>	149:156823d33999	1238	hspi->RxISR = 0;
<>	149:156823d33999	1239	hspi->TxISR = 0;
<>	149:156823d33999	1240	hspi->pTxBuffPtr = NULL;
<>	149:156823d33999	1241	hspi->TxXferSize = 0;
<>	149:156823d33999	1242	hspi->TxXferCount = 0;
<>	149:156823d33999	1243
<>	149:156823d33999	1244	/* Configure communication direction : 1Line */
<>	149:156823d33999	1245	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	149:156823d33999	1246	{
<>	149:156823d33999	1247	SPI_1LINE_RX(hspi);
<>	149:156823d33999	1248	}
<>	149:156823d33999	1249	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
<>	149:156823d33999	1250	{
<>	149:156823d33999	1251	/* Process Unlocked */
<>	149:156823d33999	1252	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1253
<>	149:156823d33999	1254	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	149:156823d33999	1255	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
<>	149:156823d33999	1256	}
<>	149:156823d33999	1257
<>	149:156823d33999	1258	/* Reset CRC Calculation */
<>	149:156823d33999	1259	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1260	{
<>	149:156823d33999	1261	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1262	}
<>	149:156823d33999	1263
<>	149:156823d33999	1264	/* Set the SPI RxDMA Half transfer complete callback */
<>	149:156823d33999	1265	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<>	149:156823d33999	1266
<>	149:156823d33999	1267	/* Set the SPI Rx DMA transfer complete callback */
<>	149:156823d33999	1268	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<>	149:156823d33999	1269
<>	149:156823d33999	1270	/* Set the DMA error callback */
<>	149:156823d33999	1271	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1272
<>	149:156823d33999	1273	/* Enable the Rx DMA Channel */
<>	149:156823d33999	1274	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<>	149:156823d33999	1275
<>	149:156823d33999	1276	/* Enable Rx DMA Request */
<>	149:156823d33999	1277	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1278
<>	149:156823d33999	1279	/* Process Unlocked */
<>	149:156823d33999	1280	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1281
<>	149:156823d33999	1282	/* Check if the SPI is already enabled */
<>	149:156823d33999	1283	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1284	{
<>	149:156823d33999	1285	/* Enable SPI peripheral */
<>	149:156823d33999	1286	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1287	}
<>	149:156823d33999	1288
<>	149:156823d33999	1289	return HAL_OK;
<>	149:156823d33999	1290	}
<>	149:156823d33999	1291	else
<>	149:156823d33999	1292	{
<>	149:156823d33999	1293	return HAL_BUSY;
<>	149:156823d33999	1294	}
<>	149:156823d33999	1295	}
<>	149:156823d33999	1296
<>	149:156823d33999	1297	/**
<>	149:156823d33999	1298	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
<>	149:156823d33999	1299	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1300	* the configuration information for SPI module.
<>	149:156823d33999	1301	* @param pTxData: pointer to transmission data buffer
<>	149:156823d33999	1302	* @param pRxData: pointer to reception data buffer
<>	149:156823d33999	1303	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
<>	149:156823d33999	1304	* @param Size: amount of data to be sent
<>	149:156823d33999	1305	* @retval HAL status
<>	149:156823d33999	1306	*/
<>	149:156823d33999	1307	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	149:156823d33999	1308	{
<>	149:156823d33999	1309	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
<>	149:156823d33999	1310	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<>	149:156823d33999	1311	{
<>	149:156823d33999	1312	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	149:156823d33999	1313	{
<>	149:156823d33999	1314	return HAL_ERROR;
<>	149:156823d33999	1315	}
<>	149:156823d33999	1316
<>	149:156823d33999	1317	/* Check the parameters */
<>	149:156823d33999	1318	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	149:156823d33999	1319
<>	149:156823d33999	1320	/* Process locked */
<>	149:156823d33999	1321	__HAL_LOCK(hspi);
<>	149:156823d33999	1322
<>	149:156823d33999	1323	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	149:156823d33999	1324	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	149:156823d33999	1325	{
<>	149:156823d33999	1326	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	149:156823d33999	1327	}
<>	149:156823d33999	1328
<>	149:156823d33999	1329	/* Configure communication */
<>	149:156823d33999	1330	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	149:156823d33999	1331
<>	149:156823d33999	1332	hspi->pTxBuffPtr = (uint8_t*)pTxData;
<>	149:156823d33999	1333	hspi->TxXferSize = Size;
<>	149:156823d33999	1334	hspi->TxXferCount = Size;
<>	149:156823d33999	1335
<>	149:156823d33999	1336	hspi->pRxBuffPtr = (uint8_t*)pRxData;
<>	149:156823d33999	1337	hspi->RxXferSize = Size;
<>	149:156823d33999	1338	hspi->RxXferCount = Size;
<>	149:156823d33999	1339
<>	149:156823d33999	1340	/Init field not used in handle to zero /
<>	149:156823d33999	1341	hspi->RxISR = 0;
<>	149:156823d33999	1342	hspi->TxISR = 0;
<>	149:156823d33999	1343
<>	149:156823d33999	1344	/* Reset CRC Calculation */
<>	149:156823d33999	1345	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1346	{
<>	149:156823d33999	1347	SPI_RESET_CRC(hspi);
<>	149:156823d33999	1348	}
<>	149:156823d33999	1349
<>	149:156823d33999	1350	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
<>	149:156823d33999	1351	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<>	149:156823d33999	1352	{
<>	149:156823d33999	1353	/* Set the SPI Rx DMA Half transfer complete callback */
<>	149:156823d33999	1354	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<>	149:156823d33999	1355
<>	149:156823d33999	1356	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<>	149:156823d33999	1357	}
<>	149:156823d33999	1358	else
<>	149:156823d33999	1359	{
<>	149:156823d33999	1360	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
<>	149:156823d33999	1361	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
<>	149:156823d33999	1362
<>	149:156823d33999	1363	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<>	149:156823d33999	1364	}
<>	149:156823d33999	1365
<>	149:156823d33999	1366	/* Set the DMA error callback */
<>	149:156823d33999	1367	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1368
<>	149:156823d33999	1369	/* Enable the Rx DMA Channel */
<>	149:156823d33999	1370	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<>	149:156823d33999	1371
<>	149:156823d33999	1372	/* Enable Rx DMA Request */
<>	149:156823d33999	1373	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1374
<>	149:156823d33999	1375	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
<>	149:156823d33999	1376	is performed in DMA reception complete callback */
<>	149:156823d33999	1377	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
<>	149:156823d33999	1378	{
<>	149:156823d33999	1379	/* Set the DMA error callback */
<>	149:156823d33999	1380	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<>	149:156823d33999	1381	}
<>	149:156823d33999	1382	else
<>	149:156823d33999	1383	{
<>	149:156823d33999	1384	hspi->hdmatx->XferErrorCallback = NULL;
<>	149:156823d33999	1385	}
<>	149:156823d33999	1386
<>	149:156823d33999	1387	/* Enable the Tx DMA Channel */
<>	149:156823d33999	1388	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<>	149:156823d33999	1389
<>	149:156823d33999	1390	/* Check if the SPI is already enabled */
<>	149:156823d33999	1391	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	149:156823d33999	1392	{
<>	149:156823d33999	1393	/* Enable SPI peripheral */
<>	149:156823d33999	1394	__HAL_SPI_ENABLE(hspi);
<>	149:156823d33999	1395	}
<>	149:156823d33999	1396
<>	149:156823d33999	1397	/* Enable Tx DMA Request */
<>	149:156823d33999	1398	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1399
<>	149:156823d33999	1400	/* Process Unlocked */
<>	149:156823d33999	1401	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1402
<>	149:156823d33999	1403	return HAL_OK;
<>	149:156823d33999	1404	}
<>	149:156823d33999	1405	else
<>	149:156823d33999	1406	{
<>	149:156823d33999	1407	return HAL_BUSY;
<>	149:156823d33999	1408	}
<>	149:156823d33999	1409	}
<>	149:156823d33999	1410
<>	149:156823d33999	1411
<>	149:156823d33999	1412	/**
<>	149:156823d33999	1413	* @brief Pauses the DMA Transfer.
<>	149:156823d33999	1414	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1415	* the configuration information for the specified SPI module.
<>	149:156823d33999	1416	* @retval HAL status
<>	149:156823d33999	1417	*/
<>	149:156823d33999	1418	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1419	{
<>	149:156823d33999	1420	/* Process Locked */
<>	149:156823d33999	1421	__HAL_LOCK(hspi);
<>	149:156823d33999	1422
<>	149:156823d33999	1423	/* Disable the SPI DMA Tx & Rx requests */
<>	149:156823d33999	1424	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1425	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1426
<>	149:156823d33999	1427	/* Process Unlocked */
<>	149:156823d33999	1428	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1429
<>	149:156823d33999	1430	return HAL_OK;
<>	149:156823d33999	1431	}
<>	149:156823d33999	1432
<>	149:156823d33999	1433	/**
<>	149:156823d33999	1434	* @brief Resumes the DMA Transfer.
<>	149:156823d33999	1435	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1436	* the configuration information for the specified SPI module.
<>	149:156823d33999	1437	* @retval HAL status
<>	149:156823d33999	1438	*/
<>	149:156823d33999	1439	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1440	{
<>	149:156823d33999	1441	/* Process Locked */
<>	149:156823d33999	1442	__HAL_LOCK(hspi);
<>	149:156823d33999	1443
<>	149:156823d33999	1444	/* Enable the SPI DMA Tx & Rx requests */
<>	149:156823d33999	1445	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1446	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1447
<>	149:156823d33999	1448	/* Process Unlocked */
<>	149:156823d33999	1449	__HAL_UNLOCK(hspi);
<>	149:156823d33999	1450
<>	149:156823d33999	1451	return HAL_OK;
<>	149:156823d33999	1452	}
<>	149:156823d33999	1453
<>	149:156823d33999	1454	/**
<>	149:156823d33999	1455	* @brief Stops the DMA Transfer.
<>	149:156823d33999	1456	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1457	* the configuration information for the specified UART module.
<>	149:156823d33999	1458	* @retval HAL status
<>	149:156823d33999	1459	*/
<>	149:156823d33999	1460	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1461	{
<>	149:156823d33999	1462	/* The Lock is not implemented on this API to allow the user application
<>	149:156823d33999	1463	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<>	149:156823d33999	1464	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<>	149:156823d33999	1465	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<>	149:156823d33999	1466	*/
<>	149:156823d33999	1467
<>	149:156823d33999	1468	/* Abort the SPI DMA tx Channel */
<>	149:156823d33999	1469	if(hspi->hdmatx != NULL)
<>	149:156823d33999	1470	{
<>	149:156823d33999	1471	HAL_DMA_Abort(hspi->hdmatx);
<>	149:156823d33999	1472	}
<>	149:156823d33999	1473	/* Abort the SPI DMA rx Channel */
<>	149:156823d33999	1474	if(hspi->hdmarx != NULL)
<>	149:156823d33999	1475	{
<>	149:156823d33999	1476	HAL_DMA_Abort(hspi->hdmarx);
<>	149:156823d33999	1477	}
<>	149:156823d33999	1478
<>	149:156823d33999	1479	/* Disable the SPI DMA Tx & Rx requests */
<>	149:156823d33999	1480	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	1481	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	1482
<>	149:156823d33999	1483	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1484
<>	149:156823d33999	1485	return HAL_OK;
<>	149:156823d33999	1486	}
<>	149:156823d33999	1487
<>	149:156823d33999	1488	/**
<>	149:156823d33999	1489	* @brief This function handles SPI interrupt request.
<>	149:156823d33999	1490	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1491	* the configuration information for SPI module.
<>	149:156823d33999	1492	* @retval HAL status
<>	149:156823d33999	1493	*/
<>	149:156823d33999	1494	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1495	{
<>	149:156823d33999	1496	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
<>	149:156823d33999	1497	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
<>	149:156823d33999	1498	{
<>	149:156823d33999	1499	hspi->RxISR(hspi);
<>	149:156823d33999	1500	return;
<>	149:156823d33999	1501	}
<>	149:156823d33999	1502
<>	149:156823d33999	1503	/* SPI in mode Tramitter ---------------------------------------------------*/
<>	149:156823d33999	1504	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
<>	149:156823d33999	1505	{
<>	149:156823d33999	1506	hspi->TxISR(hspi);
<>	149:156823d33999	1507	return;
<>	149:156823d33999	1508	}
<>	149:156823d33999	1509
<>	149:156823d33999	1510	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
<>	149:156823d33999	1511	{
<>	149:156823d33999	1512	/* SPI CRC error interrupt occurred ---------------------------------------*/
<>	149:156823d33999	1513	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	149:156823d33999	1514	{
<>	149:156823d33999	1515	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	1516	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	149:156823d33999	1517	}
<>	149:156823d33999	1518	/* SPI Mode Fault error interrupt occurred --------------------------------*/
<>	149:156823d33999	1519	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
<>	149:156823d33999	1520	{
<>	149:156823d33999	1521	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<>	149:156823d33999	1522	__HAL_SPI_CLEAR_MODFFLAG(hspi);
<>	149:156823d33999	1523	}
<>	149:156823d33999	1524
<>	149:156823d33999	1525	/* SPI Overrun error interrupt occurred -----------------------------------*/
<>	149:156823d33999	1526	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
<>	149:156823d33999	1527	{
<>	149:156823d33999	1528	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
<>	149:156823d33999	1529	{
<>	149:156823d33999	1530	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<>	149:156823d33999	1531	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	149:156823d33999	1532	}
<>	149:156823d33999	1533	}
<>	149:156823d33999	1534
<>	149:156823d33999	1535	/* SPI Frame error interrupt occurred -------------------------------------*/
<>	149:156823d33999	1536	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
<>	149:156823d33999	1537	{
<>	149:156823d33999	1538	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
<>	149:156823d33999	1539	__HAL_SPI_CLEAR_FREFLAG(hspi);
<>	149:156823d33999	1540	}
<>	149:156823d33999	1541
<>	149:156823d33999	1542	/* Call the Error call Back in case of Errors */
<>	149:156823d33999	1543	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
<>	149:156823d33999	1544	{
<>	149:156823d33999	1545	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
<>	149:156823d33999	1546	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	1547	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	1548	}
<>	149:156823d33999	1549	}
<>	149:156823d33999	1550	}
<>	149:156823d33999	1551
<>	149:156823d33999	1552	/**
<>	149:156823d33999	1553	* @brief Tx Transfer completed callbacks
<>	149:156823d33999	1554	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1555	* the configuration information for SPI module.
<>	149:156823d33999	1556	* @retval None
<>	149:156823d33999	1557	*/
<>	149:156823d33999	1558	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1559	{
<>	149:156823d33999	1560	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1561	UNUSED(hspi);
<>	149:156823d33999	1562
<>	149:156823d33999	1563	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1564	the HAL_SPI_TxCpltCallback could be implenetd in the user file
<>	149:156823d33999	1565	*/
<>	149:156823d33999	1566	}
<>	149:156823d33999	1567
<>	149:156823d33999	1568	/**
<>	149:156823d33999	1569	* @brief Rx Transfer completed callbacks
<>	149:156823d33999	1570	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1571	* the configuration information for SPI module.
<>	149:156823d33999	1572	* @retval None
<>	149:156823d33999	1573	*/
<>	149:156823d33999	1574	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1575	{
<>	149:156823d33999	1576	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1577	UNUSED(hspi);
<>	149:156823d33999	1578
<>	149:156823d33999	1579	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1580	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1581	*/
<>	149:156823d33999	1582	}
<>	149:156823d33999	1583
<>	149:156823d33999	1584	/**
<>	149:156823d33999	1585	* @brief Tx and Rx Transfer completed callbacks
<>	149:156823d33999	1586	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1587	* the configuration information for SPI module.
<>	149:156823d33999	1588	* @retval None
<>	149:156823d33999	1589	*/
<>	149:156823d33999	1590	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1591	{
<>	149:156823d33999	1592	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1593	UNUSED(hspi);
<>	149:156823d33999	1594
<>	149:156823d33999	1595	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1596	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1597	*/
<>	149:156823d33999	1598	}
<>	149:156823d33999	1599
<>	149:156823d33999	1600	/**
<>	149:156823d33999	1601	* @brief Tx Half Transfer completed callbacks
<>	149:156823d33999	1602	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1603	* the configuration information for SPI module.
<>	149:156823d33999	1604	* @retval None
<>	149:156823d33999	1605	*/
<>	149:156823d33999	1606	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1607	{
<>	149:156823d33999	1608	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1609	UNUSED(hspi);
<>	149:156823d33999	1610
<>	149:156823d33999	1611	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1612	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
<>	149:156823d33999	1613	*/
<>	149:156823d33999	1614	}
<>	149:156823d33999	1615
<>	149:156823d33999	1616	/**
<>	149:156823d33999	1617	* @brief Rx Half Transfer completed callbacks
<>	149:156823d33999	1618	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1619	* the configuration information for SPI module.
<>	149:156823d33999	1620	* @retval None
<>	149:156823d33999	1621	*/
<>	149:156823d33999	1622	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1623	{
<>	149:156823d33999	1624	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1625	UNUSED(hspi);
<>	149:156823d33999	1626
<>	149:156823d33999	1627	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1628	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1629	*/
<>	149:156823d33999	1630	}
<>	149:156823d33999	1631
<>	149:156823d33999	1632	/**
<>	149:156823d33999	1633	* @brief Tx and Rx Transfer completed callbacks
<>	149:156823d33999	1634	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1635	* the configuration information for SPI module.
<>	149:156823d33999	1636	* @retval None
<>	149:156823d33999	1637	*/
<>	149:156823d33999	1638	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1639	{
<>	149:156823d33999	1640	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1641	UNUSED(hspi);
<>	149:156823d33999	1642
<>	149:156823d33999	1643	/* NOTE : This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1644	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
<>	149:156823d33999	1645	*/
<>	149:156823d33999	1646	}
<>	149:156823d33999	1647
<>	149:156823d33999	1648	/**
<>	149:156823d33999	1649	* @brief SPI error callbacks
<>	149:156823d33999	1650	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1651	* the configuration information for SPI module.
<>	149:156823d33999	1652	* @retval None
<>	149:156823d33999	1653	*/
<>	149:156823d33999	1654	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1655	{
<>	149:156823d33999	1656	/* Prevent unused argument(s) compilation warning */
<>	149:156823d33999	1657	UNUSED(hspi);
<>	149:156823d33999	1658
<>	149:156823d33999	1659	/* NOTE : - This function Should not be modified, when the callback is needed,
<>	149:156823d33999	1660	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
<>	149:156823d33999	1661	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
<>	149:156823d33999	1662	and user can use HAL_SPI_GetError() API to check the latest error occurred.
<>	149:156823d33999	1663	*/
<>	149:156823d33999	1664	}
<>	149:156823d33999	1665
<>	149:156823d33999	1666	/**
<>	149:156823d33999	1667	* @}
<>	149:156823d33999	1668	*/
<>	149:156823d33999	1669
<>	149:156823d33999	1670	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
<>	149:156823d33999	1671	* @brief SPI control functions
<>	149:156823d33999	1672	*
<>	149:156823d33999	1673	@verbatim
<>	149:156823d33999	1674	===============================================================================
<>	149:156823d33999	1675	##### Peripheral State and Errors functions #####
<>	149:156823d33999	1676	===============================================================================
<>	149:156823d33999	1677	[..]
<>	149:156823d33999	1678	This subsection provides a set of functions allowing to control the SPI.
<>	149:156823d33999	1679	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<>	149:156823d33999	1680	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<>	149:156823d33999	1681	@endverbatim
<>	149:156823d33999	1682	* @{
<>	149:156823d33999	1683	*/
<>	149:156823d33999	1684
<>	149:156823d33999	1685	/**
<>	149:156823d33999	1686	* @brief Return the SPI state
<>	149:156823d33999	1687	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1688	* the configuration information for SPI module.
<>	149:156823d33999	1689	* @retval HAL state
<>	149:156823d33999	1690	*/
<>	149:156823d33999	1691	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1692	{
<>	149:156823d33999	1693	return hspi->State;
<>	149:156823d33999	1694	}
<>	149:156823d33999	1695
<>	149:156823d33999	1696	/**
<>	149:156823d33999	1697	* @brief Return the SPI error code
<>	149:156823d33999	1698	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	1699	* the configuration information for SPI module.
<>	149:156823d33999	1700	* @retval SPI Error Code
<>	149:156823d33999	1701	*/
<>	149:156823d33999	1702	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1703	{
<>	149:156823d33999	1704	return hspi->ErrorCode;
<>	149:156823d33999	1705	}
<>	149:156823d33999	1706
<>	149:156823d33999	1707	/**
<>	149:156823d33999	1708	* @}
<>	149:156823d33999	1709	*/
<>	149:156823d33999	1710
<>	149:156823d33999	1711	/**
<>	149:156823d33999	1712	* @}
<>	149:156823d33999	1713	*/
<>	149:156823d33999	1714
<>	149:156823d33999	1715
<>	149:156823d33999	1716
<>	149:156823d33999	1717	/** @addtogroup SPI_Private_Functions
<>	149:156823d33999	1718	* @{
<>	149:156823d33999	1719	*/
<>	149:156823d33999	1720
<>	153:fa9ff456f731	1721	/**
<>	153:fa9ff456f731	1722	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<>	149:156823d33999	1723	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1724	* the configuration information for SPI module.
<>	153:fa9ff456f731	1725	* @retval None
<>	149:156823d33999	1726	*/
<>	153:fa9ff456f731	1727	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1728	{
<>	153:fa9ff456f731	1729	/* Receive data in 8bit mode */
<>	153:fa9ff456f731	1730	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
<>	153:fa9ff456f731	1731	hspi->RxXferCount--;
<>	153:fa9ff456f731	1732
<>	153:fa9ff456f731	1733	/* check end of the reception */
<>	153:fa9ff456f731	1734	if(hspi->RxXferCount == 0U)
<>	149:156823d33999	1735	{
<>	153:fa9ff456f731	1736	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1737	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	1738	{
<>	153:fa9ff456f731	1739	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
<>	153:fa9ff456f731	1740	return;
<>	153:fa9ff456f731	1741	}
<>	153:fa9ff456f731	1742	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1743
<>	153:fa9ff456f731	1744	/* Disable RXNE interrupt */
<>	153:fa9ff456f731	1745	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	153:fa9ff456f731	1746
<>	153:fa9ff456f731	1747	if(hspi->TxXferCount == 0U)
<>	153:fa9ff456f731	1748	{
<>	153:fa9ff456f731	1749	SPI_CloseRxTx_ISR(hspi);
<>	153:fa9ff456f731	1750	}
<>	149:156823d33999	1751	}
<>	153:fa9ff456f731	1752	}
<>	149:156823d33999	1753
<>	153:fa9ff456f731	1754	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1755	/**
<>	153:fa9ff456f731	1756	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<>	153:fa9ff456f731	1757	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1758	* the configuration information for SPI module.
<>	153:fa9ff456f731	1759	* @retval None
<>	153:fa9ff456f731	1760	*/
<>	153:fa9ff456f731	1761	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1762	{
<>	153:fa9ff456f731	1763	__IO uint8_t tmpreg = 0U;
<>	149:156823d33999	1764
<>	153:fa9ff456f731	1765	/* Read data register to flush CRC */
<>	153:fa9ff456f731	1766	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
<>	153:fa9ff456f731	1767
<>	153:fa9ff456f731	1768	/* To avoid GCC warning */
<>	153:fa9ff456f731	1769
<>	153:fa9ff456f731	1770	UNUSED(tmpreg);
<>	153:fa9ff456f731	1771
<>	153:fa9ff456f731	1772	/* Disable RXNE interrupt */
<>	153:fa9ff456f731	1773	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	153:fa9ff456f731	1774
<>	153:fa9ff456f731	1775	if(hspi->TxXferCount == 0U)
<>	153:fa9ff456f731	1776	{
<>	153:fa9ff456f731	1777	SPI_CloseRxTx_ISR(hspi);
<>	153:fa9ff456f731	1778	}
<>	153:fa9ff456f731	1779	}
<>	153:fa9ff456f731	1780	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1781
<>	153:fa9ff456f731	1782	/**
<>	153:fa9ff456f731	1783	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
<>	153:fa9ff456f731	1784	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1785	* the configuration information for SPI module.
<>	153:fa9ff456f731	1786	* @retval None
<>	153:fa9ff456f731	1787	*/
<>	153:fa9ff456f731	1788	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1789	{
<>	153:fa9ff456f731	1790	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	153:fa9ff456f731	1791	hspi->TxXferCount--;
<>	153:fa9ff456f731	1792
<>	153:fa9ff456f731	1793	/* check the end of the transmission */
<>	153:fa9ff456f731	1794	if(hspi->TxXferCount == 0U)
<>	153:fa9ff456f731	1795	{
<>	153:fa9ff456f731	1796	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1797	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1798	{
<>	153:fa9ff456f731	1799	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	153:fa9ff456f731	1800	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<>	153:fa9ff456f731	1801	return;
<>	149:156823d33999	1802	}
<>	153:fa9ff456f731	1803	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1804
<>	153:fa9ff456f731	1805	/* Disable TXE interrupt */
<>	153:fa9ff456f731	1806	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<>	153:fa9ff456f731	1807
<>	153:fa9ff456f731	1808	if(hspi->RxXferCount == 0U)
<>	149:156823d33999	1809	{
<>	153:fa9ff456f731	1810	SPI_CloseRxTx_ISR(hspi);
<>	149:156823d33999	1811	}
<>	149:156823d33999	1812	}
<>	149:156823d33999	1813	}
<>	149:156823d33999	1814
<>	149:156823d33999	1815	/**
<>	153:fa9ff456f731	1816	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
<>	149:156823d33999	1817	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1818	* the configuration information for SPI module.
<>	153:fa9ff456f731	1819	* @retval None
<>	149:156823d33999	1820	*/
<>	153:fa9ff456f731	1821	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	1822	{
<>	153:fa9ff456f731	1823	/* Receive data in 16 Bit mode */
<>	153:fa9ff456f731	1824	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	153:fa9ff456f731	1825	hspi->pRxBuffPtr += sizeof(uint16_t);
<>	153:fa9ff456f731	1826	hspi->RxXferCount--;
<>	153:fa9ff456f731	1827
<>	153:fa9ff456f731	1828	if(hspi->RxXferCount == 0U)
<>	149:156823d33999	1829	{
<>	153:fa9ff456f731	1830	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1831	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	1832	{
<>	153:fa9ff456f731	1833	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
<>	153:fa9ff456f731	1834	return;
<>	153:fa9ff456f731	1835	}
<>	153:fa9ff456f731	1836	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1837
<>	153:fa9ff456f731	1838	/* Disable RXNE interrupt */
<>	153:fa9ff456f731	1839	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<>	153:fa9ff456f731	1840
<>	153:fa9ff456f731	1841	if(hspi->TxXferCount == 0U)
<>	153:fa9ff456f731	1842	{
<>	153:fa9ff456f731	1843	SPI_CloseRxTx_ISR(hspi);
<>	153:fa9ff456f731	1844	}
<>	149:156823d33999	1845	}
<>	153:fa9ff456f731	1846	}
<>	153:fa9ff456f731	1847
<>	153:fa9ff456f731	1848	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1849	/**
<>	153:fa9ff456f731	1850	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
<>	153:fa9ff456f731	1851	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1852	* the configuration information for SPI module.
<>	153:fa9ff456f731	1853	* @retval None
<>	153:fa9ff456f731	1854	*/
<>	153:fa9ff456f731	1855	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1856	{
<>	153:fa9ff456f731	1857	/* Receive data in 16 Bit mode */
<>	153:fa9ff456f731	1858	__IO uint16_t tmpreg = 0U;
<>	153:fa9ff456f731	1859
<>	153:fa9ff456f731	1860	/* Read data register to flush CRC */
<>	153:fa9ff456f731	1861	tmpreg = hspi->Instance->DR;
<>	153:fa9ff456f731	1862
<>	153:fa9ff456f731	1863	/* To avoid GCC warning */
<>	153:fa9ff456f731	1864	UNUSED(tmpreg);
<>	153:fa9ff456f731	1865
<>	153:fa9ff456f731	1866	/* Disable RXNE interrupt */
<>	153:fa9ff456f731	1867	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<>	153:fa9ff456f731	1868
<>	153:fa9ff456f731	1869	SPI_CloseRxTx_ISR(hspi);
<>	153:fa9ff456f731	1870	}
<>	153:fa9ff456f731	1871	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1872
<>	153:fa9ff456f731	1873	/**
<>	153:fa9ff456f731	1874	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
<>	153:fa9ff456f731	1875	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1876	* the configuration information for SPI module.
<>	153:fa9ff456f731	1877	* @retval None
<>	153:fa9ff456f731	1878	*/
<>	153:fa9ff456f731	1879	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1880	{
<>	149:156823d33999	1881	/* Transmit data in 16 Bit mode */
<>	153:fa9ff456f731	1882	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
<>	153:fa9ff456f731	1883	hspi->pTxBuffPtr += sizeof(uint16_t);
<>	149:156823d33999	1884	hspi->TxXferCount--;
<>	149:156823d33999	1885
<>	153:fa9ff456f731	1886	/* Enable CRC Transmission */
<>	153:fa9ff456f731	1887	if(hspi->TxXferCount == 0U)
<>	149:156823d33999	1888	{
<>	153:fa9ff456f731	1889	#if (USE_SPI_CRC != 0U)
<>	149:156823d33999	1890	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	1891	{
<>	149:156823d33999	1892	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	153:fa9ff456f731	1893	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<>	153:fa9ff456f731	1894	return;
<>	149:156823d33999	1895	}
<>	153:fa9ff456f731	1896	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1897
<>	153:fa9ff456f731	1898	/* Disable TXE interrupt */
<>	153:fa9ff456f731	1899	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<>	153:fa9ff456f731	1900
<>	153:fa9ff456f731	1901	if(hspi->RxXferCount == 0U)
<>	153:fa9ff456f731	1902	{
<>	153:fa9ff456f731	1903	SPI_CloseRxTx_ISR(hspi);
<>	153:fa9ff456f731	1904	}
<>	153:fa9ff456f731	1905	}
<>	153:fa9ff456f731	1906	}
<>	153:fa9ff456f731	1907
<>	153:fa9ff456f731	1908	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1909	/**
<>	153:fa9ff456f731	1910	* @brief Manage the CRC 8-bit receive in Interrupt context.
<>	153:fa9ff456f731	1911	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1912	* the configuration information for SPI module.
<>	153:fa9ff456f731	1913	* @retval None
<>	153:fa9ff456f731	1914	*/
<>	153:fa9ff456f731	1915	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1916	{
<>	153:fa9ff456f731	1917	__IO uint8_t tmpreg = 0U;
<>	153:fa9ff456f731	1918
<>	153:fa9ff456f731	1919	/* Read data register to flush CRC */
<>	153:fa9ff456f731	1920	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
<>	153:fa9ff456f731	1921
<>	153:fa9ff456f731	1922	/* To avoid GCC warning */
<>	153:fa9ff456f731	1923	UNUSED(tmpreg);
<>	153:fa9ff456f731	1924
<>	153:fa9ff456f731	1925	SPI_CloseRx_ISR(hspi);
<>	153:fa9ff456f731	1926	}
<>	153:fa9ff456f731	1927	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1928
<>	153:fa9ff456f731	1929	/**
<>	153:fa9ff456f731	1930	* @brief Manage the receive 8-bit in Interrupt context.
<>	153:fa9ff456f731	1931	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1932	* the configuration information for SPI module.
<>	153:fa9ff456f731	1933	* @retval None
<>	153:fa9ff456f731	1934	*/
<>	153:fa9ff456f731	1935	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1936	{
<>	153:fa9ff456f731	1937	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
<>	153:fa9ff456f731	1938	hspi->RxXferCount--;
<>	153:fa9ff456f731	1939
<>	153:fa9ff456f731	1940	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1941	/* Enable CRC Transmission */
<>	153:fa9ff456f731	1942	if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	153:fa9ff456f731	1943	{
<>	153:fa9ff456f731	1944	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	153:fa9ff456f731	1945	}
<>	153:fa9ff456f731	1946	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1947
<>	153:fa9ff456f731	1948	if(hspi->RxXferCount == 0U)
<>	153:fa9ff456f731	1949	{
<>	153:fa9ff456f731	1950	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1951	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	1952	{
<>	153:fa9ff456f731	1953	hspi->RxISR = SPI_RxISR_8BITCRC;
<>	153:fa9ff456f731	1954	return;
<>	153:fa9ff456f731	1955	}
<>	153:fa9ff456f731	1956	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1957	SPI_CloseRx_ISR(hspi);
<>	153:fa9ff456f731	1958	}
<>	153:fa9ff456f731	1959	}
<>	153:fa9ff456f731	1960
<>	153:fa9ff456f731	1961	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1962	/**
<>	153:fa9ff456f731	1963	* @brief Manage the CRC 16-bit receive in Interrupt context.
<>	153:fa9ff456f731	1964	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1965	* the configuration information for SPI module.
<>	153:fa9ff456f731	1966	* @retval None
<>	153:fa9ff456f731	1967	*/
<>	153:fa9ff456f731	1968	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1969	{
<>	153:fa9ff456f731	1970	__IO uint16_t tmpreg = 0U;
<>	153:fa9ff456f731	1971
<>	153:fa9ff456f731	1972	/* Read data register to flush CRC */
<>	153:fa9ff456f731	1973	tmpreg = hspi->Instance->DR;
<>	153:fa9ff456f731	1974
<>	153:fa9ff456f731	1975	/* To avoid GCC warning */
<>	153:fa9ff456f731	1976	UNUSED(tmpreg);
<>	153:fa9ff456f731	1977
<>	153:fa9ff456f731	1978	/* Disable RXNE and ERR interrupt */
<>	153:fa9ff456f731	1979	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	153:fa9ff456f731	1980
<>	153:fa9ff456f731	1981	SPI_CloseRx_ISR(hspi);
<>	153:fa9ff456f731	1982	}
<>	153:fa9ff456f731	1983	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	1984
<>	153:fa9ff456f731	1985	/**
<>	153:fa9ff456f731	1986	* @brief Manage the 16-bit receive in Interrupt context.
<>	153:fa9ff456f731	1987	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	1988	* the configuration information for SPI module.
<>	153:fa9ff456f731	1989	* @retval None
<>	153:fa9ff456f731	1990	*/
<>	153:fa9ff456f731	1991	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	1992	{
<>	153:fa9ff456f731	1993	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	153:fa9ff456f731	1994	hspi->pRxBuffPtr += sizeof(uint16_t);
<>	153:fa9ff456f731	1995	hspi->RxXferCount--;
<>	153:fa9ff456f731	1996
<>	153:fa9ff456f731	1997	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	1998	/* Enable CRC Transmission */
<>	153:fa9ff456f731	1999	if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	153:fa9ff456f731	2000	{
<>	153:fa9ff456f731	2001	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	153:fa9ff456f731	2002	}
<>	153:fa9ff456f731	2003	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2004
<>	153:fa9ff456f731	2005	if(hspi->RxXferCount == 0U)
<>	153:fa9ff456f731	2006	{
<>	153:fa9ff456f731	2007	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2008	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	2009	{
<>	153:fa9ff456f731	2010	hspi->RxISR = SPI_RxISR_16BITCRC;
<>	153:fa9ff456f731	2011	return;
<>	153:fa9ff456f731	2012	}
<>	153:fa9ff456f731	2013	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2014	SPI_CloseRx_ISR(hspi);
<>	149:156823d33999	2015	}
<>	149:156823d33999	2016	}
<>	149:156823d33999	2017
<>	149:156823d33999	2018	/**
<>	153:fa9ff456f731	2019	* @brief Handle the data 8-bit transmit in Interrupt mode.
<>	149:156823d33999	2020	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2021	* the configuration information for SPI module.
<>	153:fa9ff456f731	2022	* @retval None
<>	149:156823d33999	2023	*/
<>	153:fa9ff456f731	2024	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	2025	{
<>	153:fa9ff456f731	2026	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	153:fa9ff456f731	2027	hspi->TxXferCount--;
<>	149:156823d33999	2028
<>	153:fa9ff456f731	2029	if(hspi->TxXferCount == 0U)
<>	149:156823d33999	2030	{
<>	153:fa9ff456f731	2031	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2032	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2033	{
<>	153:fa9ff456f731	2034	/* Enable CRC Transmission */
<>	153:fa9ff456f731	2035	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	149:156823d33999	2036	}
<>	153:fa9ff456f731	2037	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2038	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
<>	153:fa9ff456f731	2039	SPI_CloseTx_ISR(hspi);
<>	149:156823d33999	2040	}
<>	149:156823d33999	2041	}
<>	149:156823d33999	2042
<>	149:156823d33999	2043	/**
<>	153:fa9ff456f731	2044	* @brief Handle the data 16-bit transmit in Interrupt mode.
<>	149:156823d33999	2045	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2046	* the configuration information for SPI module.
<>	153:fa9ff456f731	2047	* @retval None
<>	149:156823d33999	2048	*/
<>	153:fa9ff456f731	2049	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	149:156823d33999	2050	{
<>	153:fa9ff456f731	2051	/* Transmit data in 16 Bit mode */
<>	153:fa9ff456f731	2052	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
<>	153:fa9ff456f731	2053	hspi->pTxBuffPtr += sizeof(uint16_t);
<>	153:fa9ff456f731	2054	hspi->TxXferCount--;
<>	153:fa9ff456f731	2055
<>	153:fa9ff456f731	2056	if(hspi->TxXferCount == 0U)
<>	149:156823d33999	2057	{
<>	153:fa9ff456f731	2058	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2059	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	2060	{
<>	153:fa9ff456f731	2061	/* Enable CRC Transmission */
<>	153:fa9ff456f731	2062	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	153:fa9ff456f731	2063	}
<>	153:fa9ff456f731	2064	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2065	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
<>	153:fa9ff456f731	2066	SPI_CloseTx_ISR(hspi);
<>	149:156823d33999	2067	}
<>	149:156823d33999	2068	}
<>	149:156823d33999	2069
<>	149:156823d33999	2070	/**
<>	153:fa9ff456f731	2071	* @brief Handle SPI Communication Timeout.
<>	153:fa9ff456f731	2072	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2073	* the configuration information for SPI module.
<>	153:fa9ff456f731	2074	* @param Flag: SPI flag to check
<>	153:fa9ff456f731	2075	* @param State: flag state to check
<>	153:fa9ff456f731	2076	* @param Timeout: Timeout duration
<>	153:fa9ff456f731	2077	* @param Tickstart: tick start value
<>	153:fa9ff456f731	2078	* @retval HAL status
<>	149:156823d33999	2079	*/
<>	153:fa9ff456f731	2080	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
<>	149:156823d33999	2081	{
<>	153:fa9ff456f731	2082	while((hspi->Instance->SR & Flag) != State)
<>	149:156823d33999	2083	{
<>	153:fa9ff456f731	2084	if(Timeout != HAL_MAX_DELAY)
<>	153:fa9ff456f731	2085	{
<>	153:fa9ff456f731	2086	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) >= Timeout))
<>	153:fa9ff456f731	2087	{
<>	153:fa9ff456f731	2088	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	153:fa9ff456f731	2089	on both master and slave sides in order to resynchronize the master
<>	153:fa9ff456f731	2090	and slave for their respective CRC calculation */
<>	153:fa9ff456f731	2091
<>	153:fa9ff456f731	2092	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	153:fa9ff456f731	2093	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	2094
<>	153:fa9ff456f731	2095	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	153:fa9ff456f731	2096	{
<>	153:fa9ff456f731	2097	/* Disable SPI peripheral */
<>	153:fa9ff456f731	2098	__HAL_SPI_DISABLE(hspi);
<>	153:fa9ff456f731	2099	}
<>	153:fa9ff456f731	2100
<>	153:fa9ff456f731	2101	/* Reset CRC Calculation */
<>	153:fa9ff456f731	2102	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	153:fa9ff456f731	2103	{
<>	153:fa9ff456f731	2104	SPI_RESET_CRC(hspi);
<>	153:fa9ff456f731	2105	}
<>	153:fa9ff456f731	2106
<>	153:fa9ff456f731	2107	hspi->State= HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2108
<>	153:fa9ff456f731	2109	/* Process Unlocked */
<>	153:fa9ff456f731	2110	__HAL_UNLOCK(hspi);
<>	153:fa9ff456f731	2111
<>	153:fa9ff456f731	2112	return HAL_TIMEOUT;
<>	153:fa9ff456f731	2113	}
<>	153:fa9ff456f731	2114	}
<>	149:156823d33999	2115	}
<>	149:156823d33999	2116
<>	153:fa9ff456f731	2117	return HAL_OK;
<>	149:156823d33999	2118	}
<>	149:156823d33999	2119
<>	149:156823d33999	2120	/**
<>	149:156823d33999	2121	* @brief DMA SPI transmit process complete callback
<>	149:156823d33999	2122	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2123	* the configuration information for the specified DMA module.
<>	149:156823d33999	2124	* @retval None
<>	149:156823d33999	2125	*/
<>	149:156823d33999	2126	static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2127	{
<>	149:156823d33999	2128	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2129
<>	149:156823d33999	2130	/* DMA Normal Mode */
<>	149:156823d33999	2131	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	149:156823d33999	2132	{
<>	149:156823d33999	2133	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	2134	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2135	{
<>	149:156823d33999	2136	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2137	}
<>	149:156823d33999	2138
<>	149:156823d33999	2139	/* Disable Tx DMA Request */
<>	149:156823d33999	2140	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	2141
<>	149:156823d33999	2142	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	2143	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2144	{
<>	149:156823d33999	2145	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2146	}
<>	149:156823d33999	2147
<>	149:156823d33999	2148	hspi->TxXferCount = 0;
<>	149:156823d33999	2149	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	2150	}
<>	149:156823d33999	2151
<>	149:156823d33999	2152	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<>	149:156823d33999	2153	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	149:156823d33999	2154	{
<>	149:156823d33999	2155	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	149:156823d33999	2156	}
<>	149:156823d33999	2157
<>	149:156823d33999	2158	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	2159	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	149:156823d33999	2160	{
<>	149:156823d33999	2161	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2162	}
<>	149:156823d33999	2163	else
<>	149:156823d33999	2164	{
<>	149:156823d33999	2165	HAL_SPI_TxCpltCallback(hspi);
<>	149:156823d33999	2166	}
<>	149:156823d33999	2167	}
<>	149:156823d33999	2168
<>	149:156823d33999	2169	/**
<>	149:156823d33999	2170	* @brief DMA SPI receive process complete callback
<>	149:156823d33999	2171	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2172	* the configuration information for the specified DMA module.
<>	149:156823d33999	2173	* @retval None
<>	149:156823d33999	2174	*/
<>	149:156823d33999	2175	static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2176	{
<>	149:156823d33999	2177	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	2178
<>	149:156823d33999	2179	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2180
<>	149:156823d33999	2181	/* DMA Normal mode */
<>	149:156823d33999	2182	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	149:156823d33999	2183	{
<>	149:156823d33999	2184	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	149:156823d33999	2185	{
<>	149:156823d33999	2186	/* Disable SPI peripheral */
<>	149:156823d33999	2187	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	2188	}
<>	149:156823d33999	2189
<>	149:156823d33999	2190	/* Disable Rx DMA Request */
<>	149:156823d33999	2191	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	2192
<>	149:156823d33999	2193	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
<>	149:156823d33999	2194	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	2195
<>	149:156823d33999	2196	/* Reset CRC Calculation */
<>	149:156823d33999	2197	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2198	{
<>	149:156823d33999	2199	/* Wait until RXNE flag is set to send data */
<>	149:156823d33999	2200	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2201	{
<>	149:156823d33999	2202	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2203	}
<>	149:156823d33999	2204
<>	149:156823d33999	2205	/* Read CRC */
<>	149:156823d33999	2206	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	2207	UNUSED(tmpreg);
<>	149:156823d33999	2208
<>	149:156823d33999	2209	/* Wait until RXNE flag is set */
<>	149:156823d33999	2210	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2211	{
<>	149:156823d33999	2212	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2213	}
<>	149:156823d33999	2214
<>	149:156823d33999	2215	/* Check if CRC error occurred */
<>	149:156823d33999	2216	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	149:156823d33999	2217	{
<>	149:156823d33999	2218	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	2219	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	149:156823d33999	2220	}
<>	149:156823d33999	2221	}
<>	149:156823d33999	2222
<>	149:156823d33999	2223	hspi->RxXferCount = 0;
<>	149:156823d33999	2224	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	2225
<>	149:156823d33999	2226	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	2227	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	149:156823d33999	2228	{
<>	149:156823d33999	2229	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2230	}
<>	149:156823d33999	2231	else
<>	149:156823d33999	2232	{
<>	149:156823d33999	2233	HAL_SPI_RxCpltCallback(hspi);
<>	149:156823d33999	2234	}
<>	149:156823d33999	2235	}
<>	149:156823d33999	2236	else
<>	149:156823d33999	2237	{
<>	149:156823d33999	2238	HAL_SPI_RxCpltCallback(hspi);
<>	149:156823d33999	2239	}
<>	149:156823d33999	2240	}
<>	149:156823d33999	2241
<>	149:156823d33999	2242	/**
<>	149:156823d33999	2243	* @brief DMA SPI transmit receive process complete callback
<>	149:156823d33999	2244	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2245	* the configuration information for the specified DMA module.
<>	149:156823d33999	2246	* @retval None
<>	149:156823d33999	2247	*/
<>	149:156823d33999	2248	static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2249	{
<>	149:156823d33999	2250	__IO uint16_t tmpreg = 0;
<>	149:156823d33999	2251
<>	149:156823d33999	2252	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2253
<>	149:156823d33999	2254	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	149:156823d33999	2255	{
<>	149:156823d33999	2256	/* Reset CRC Calculation */
<>	149:156823d33999	2257	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2258	{
<>	149:156823d33999	2259	/* Check if CRC is done on going (RXNE flag set) */
<>	149:156823d33999	2260	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
<>	149:156823d33999	2261	{
<>	149:156823d33999	2262	/* Wait until RXNE flag is set to send data */
<>	149:156823d33999	2263	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2264	{
<>	149:156823d33999	2265	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2266	}
<>	149:156823d33999	2267	}
<>	149:156823d33999	2268	/* Read CRC */
<>	149:156823d33999	2269	tmpreg = hspi->Instance->DR;
<>	149:156823d33999	2270	UNUSED(tmpreg);
<>	149:156823d33999	2271
<>	149:156823d33999	2272	/* Check if CRC error occurred */
<>	149:156823d33999	2273	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	149:156823d33999	2274	{
<>	149:156823d33999	2275	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	149:156823d33999	2276	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	149:156823d33999	2277	}
<>	149:156823d33999	2278	}
<>	149:156823d33999	2279
<>	149:156823d33999	2280	/* Wait until TXE flag is set to send data */
<>	149:156823d33999	2281	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2282	{
<>	149:156823d33999	2283	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2284	}
<>	149:156823d33999	2285
<>	149:156823d33999	2286	/* Disable Tx DMA Request */
<>	149:156823d33999	2287	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	149:156823d33999	2288
<>	149:156823d33999	2289	/* Wait until Busy flag is reset before disabling SPI */
<>	149:156823d33999	2290	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	149:156823d33999	2291	{
<>	149:156823d33999	2292	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	149:156823d33999	2293	}
<>	149:156823d33999	2294
<>	149:156823d33999	2295	/* Disable Rx DMA Request */
<>	149:156823d33999	2296	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	149:156823d33999	2297
<>	149:156823d33999	2298	hspi->TxXferCount = 0;
<>	149:156823d33999	2299	hspi->RxXferCount = 0;
<>	149:156823d33999	2300
<>	149:156823d33999	2301	hspi->State = HAL_SPI_STATE_READY;
<>	149:156823d33999	2302
<>	149:156823d33999	2303	/* Check if Errors has been detected during transfer */
<>	149:156823d33999	2304	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	149:156823d33999	2305	{
<>	149:156823d33999	2306	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2307	}
<>	149:156823d33999	2308	else
<>	149:156823d33999	2309	{
<>	149:156823d33999	2310	HAL_SPI_TxRxCpltCallback(hspi);
<>	149:156823d33999	2311	}
<>	149:156823d33999	2312	}
<>	149:156823d33999	2313	else
<>	149:156823d33999	2314	{
<>	149:156823d33999	2315	HAL_SPI_TxRxCpltCallback(hspi);
<>	149:156823d33999	2316	}
<>	149:156823d33999	2317	}
<>	149:156823d33999	2318
<>	149:156823d33999	2319	/**
<>	149:156823d33999	2320	* @brief DMA SPI half transmit process complete callback
<>	149:156823d33999	2321	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2322	* the configuration information for the specified DMA module.
<>	149:156823d33999	2323	* @retval None
<>	149:156823d33999	2324	*/
<>	149:156823d33999	2325	static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2326	{
<>	149:156823d33999	2327	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2328
<>	149:156823d33999	2329	HAL_SPI_TxHalfCpltCallback(hspi);
<>	149:156823d33999	2330	}
<>	149:156823d33999	2331
<>	149:156823d33999	2332	/**
<>	149:156823d33999	2333	* @brief DMA SPI half receive process complete callback
<>	149:156823d33999	2334	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2335	* the configuration information for the specified DMA module.
<>	149:156823d33999	2336	* @retval None
<>	149:156823d33999	2337	*/
<>	149:156823d33999	2338	static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2339	{
<>	149:156823d33999	2340	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2341
<>	149:156823d33999	2342	HAL_SPI_RxHalfCpltCallback(hspi);
<>	149:156823d33999	2343	}
<>	149:156823d33999	2344
<>	149:156823d33999	2345	/**
<>	149:156823d33999	2346	* @brief DMA SPI Half transmit receive process complete callback
<>	149:156823d33999	2347	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2348	* the configuration information for the specified DMA module.
<>	149:156823d33999	2349	* @retval None
<>	149:156823d33999	2350	*/
<>	149:156823d33999	2351	static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2352	{
<>	149:156823d33999	2353	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2354
<>	149:156823d33999	2355	HAL_SPI_TxRxHalfCpltCallback(hspi);
<>	149:156823d33999	2356	}
<>	149:156823d33999	2357
<>	149:156823d33999	2358	/**
<>	149:156823d33999	2359	* @brief DMA SPI communication error callback
<>	149:156823d33999	2360	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	149:156823d33999	2361	* the configuration information for the specified DMA module.
<>	149:156823d33999	2362	* @retval None
<>	149:156823d33999	2363	*/
<>	149:156823d33999	2364	static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma)
<>	149:156823d33999	2365	{
<>	149:156823d33999	2366	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	149:156823d33999	2367	hspi->TxXferCount = 0;
<>	149:156823d33999	2368	hspi->RxXferCount = 0;
<>	149:156823d33999	2369	hspi->State= HAL_SPI_STATE_READY;
<>	149:156823d33999	2370	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<>	149:156823d33999	2371	HAL_SPI_ErrorCallback(hspi);
<>	149:156823d33999	2372	}
<>	149:156823d33999	2373
<>	149:156823d33999	2374	/**
<>	149:156823d33999	2375	* @brief This function handles SPI Communication Timeout.
<>	149:156823d33999	2376	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	149:156823d33999	2377	* the configuration information for SPI module.
<>	149:156823d33999	2378	* @param Flag: SPI flag to check
<>	149:156823d33999	2379	* @param Status: Flag status to check: RESET or set
<>	149:156823d33999	2380	* @param Timeout: Timeout duration
<>	149:156823d33999	2381	* @retval HAL status
<>	149:156823d33999	2382	*/
<>	149:156823d33999	2383	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
<>	149:156823d33999	2384	{
<>	149:156823d33999	2385	uint32_t tickstart = 0;
<>	149:156823d33999	2386
<>	149:156823d33999	2387	/* Get tick */
<>	149:156823d33999	2388	tickstart = HAL_GetTick();
<>	149:156823d33999	2389
<>	149:156823d33999	2390	/* Wait until flag is set */
<>	149:156823d33999	2391	if(Status == RESET)
<>	149:156823d33999	2392	{
<>	149:156823d33999	2393	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
<>	149:156823d33999	2394	{
<>	149:156823d33999	2395	if(Timeout != HAL_MAX_DELAY)
<>	149:156823d33999	2396	{
<>	149:156823d33999	2397	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
<>	149:156823d33999	2398	{
<>	149:156823d33999	2399	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	149:156823d33999	2400	on both master and slave sides in order to resynchronize the master
<>	149:156823d33999	2401	and slave for their respective CRC calculation */
<>	149:156823d33999	2402
<>	149:156823d33999	2403	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	149:156823d33999	2404	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	2405
<>	149:156823d33999	2406	/* Disable SPI peripheral */
<>	149:156823d33999	2407	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	2408
<>	149:156823d33999	2409	/* Reset CRC Calculation */
<>	149:156823d33999	2410	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2411	{
<>	149:156823d33999	2412	SPI_RESET_CRC(hspi);
<>	149:156823d33999	2413	}
<>	149:156823d33999	2414
<>	149:156823d33999	2415	hspi->State= HAL_SPI_STATE_READY;
<>	149:156823d33999	2416
<>	149:156823d33999	2417	/* Process Unlocked */
<>	149:156823d33999	2418	__HAL_UNLOCK(hspi);
<>	149:156823d33999	2419
<>	149:156823d33999	2420	return HAL_TIMEOUT;
<>	149:156823d33999	2421	}
<>	149:156823d33999	2422	}
<>	149:156823d33999	2423	}
<>	149:156823d33999	2424	}
<>	149:156823d33999	2425	else
<>	149:156823d33999	2426	{
<>	149:156823d33999	2427	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
<>	149:156823d33999	2428	{
<>	149:156823d33999	2429	if(Timeout != HAL_MAX_DELAY)
<>	149:156823d33999	2430	{
<>	149:156823d33999	2431	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
<>	149:156823d33999	2432	{
<>	149:156823d33999	2433	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	149:156823d33999	2434	on both master and slave sides in order to resynchronize the master
<>	149:156823d33999	2435	and slave for their respective CRC calculation */
<>	149:156823d33999	2436
<>	149:156823d33999	2437	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	149:156823d33999	2438	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	149:156823d33999	2439
<>	149:156823d33999	2440	/* Disable SPI peripheral */
<>	149:156823d33999	2441	__HAL_SPI_DISABLE(hspi);
<>	149:156823d33999	2442
<>	149:156823d33999	2443	/* Reset CRC Calculation */
<>	149:156823d33999	2444	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	149:156823d33999	2445	{
<>	149:156823d33999	2446	SPI_RESET_CRC(hspi);
<>	149:156823d33999	2447	}
<>	149:156823d33999	2448
<>	149:156823d33999	2449	hspi->State= HAL_SPI_STATE_READY;
<>	149:156823d33999	2450
<>	149:156823d33999	2451	/* Process Unlocked */
<>	149:156823d33999	2452	__HAL_UNLOCK(hspi);
<>	149:156823d33999	2453
<>	149:156823d33999	2454	return HAL_TIMEOUT;
<>	149:156823d33999	2455	}
<>	149:156823d33999	2456	}
<>	149:156823d33999	2457	}
<>	149:156823d33999	2458	}
<>	149:156823d33999	2459	return HAL_OK;
<>	149:156823d33999	2460	}
<>	149:156823d33999	2461	/**
<>	149:156823d33999	2462	* @}
<>	149:156823d33999	2463	*/
<>	149:156823d33999	2464
<>	153:fa9ff456f731	2465	/**
<>	153:fa9ff456f731	2466	* @brief Handle to check BSY flag before start a new transaction.
<>	153:fa9ff456f731	2467	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2468	* the configuration information for SPI module.
<>	153:fa9ff456f731	2469	* @param Timeout: Timeout duration
<>	153:fa9ff456f731	2470	* @param Tickstart: tick start value
<>	153:fa9ff456f731	2471	* @retval HAL status
<>	153:fa9ff456f731	2472	*/
<>	153:fa9ff456f731	2473	static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<>	153:fa9ff456f731	2474	{
<>	153:fa9ff456f731	2475	/* Control the BSY flag */
<>	153:fa9ff456f731	2476	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<>	153:fa9ff456f731	2477	{
<>	153:fa9ff456f731	2478	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	153:fa9ff456f731	2479	return HAL_TIMEOUT;
<>	153:fa9ff456f731	2480	}
<>	153:fa9ff456f731	2481	return HAL_OK;
<>	153:fa9ff456f731	2482	}
<>	153:fa9ff456f731	2483
<>	153:fa9ff456f731	2484	/**
<>	153:fa9ff456f731	2485	* @brief Handle the end of the RXTX transaction.
<>	153:fa9ff456f731	2486	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2487	* the configuration information for SPI module.
<>	153:fa9ff456f731	2488	* @retval None
<>	153:fa9ff456f731	2489	*/
<>	153:fa9ff456f731	2490	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	2491	{
<>	153:fa9ff456f731	2492	uint32_t tickstart = 0U;
<>	153:fa9ff456f731	2493	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
<>	153:fa9ff456f731	2494	/* Init tickstart for timeout managment*/
<>	153:fa9ff456f731	2495	tickstart = HAL_GetTick();
<>	153:fa9ff456f731	2496
<>	153:fa9ff456f731	2497	/* Disable ERR interrupt */
<>	153:fa9ff456f731	2498	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<>	153:fa9ff456f731	2499
<>	153:fa9ff456f731	2500	/* Wait until TXE flag is set */
<>	153:fa9ff456f731	2501	do
<>	153:fa9ff456f731	2502	{
<>	153:fa9ff456f731	2503	if(count-- == 0)
<>	153:fa9ff456f731	2504	{
<>	153:fa9ff456f731	2505	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	153:fa9ff456f731	2506	break;
<>	153:fa9ff456f731	2507	}
<>	153:fa9ff456f731	2508	}
<>	153:fa9ff456f731	2509	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
<>	153:fa9ff456f731	2510
<>	153:fa9ff456f731	2511	/* Check the end of the transaction */
<>	153:fa9ff456f731	2512	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
<>	153:fa9ff456f731	2513	{
<>	153:fa9ff456f731	2514	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	153:fa9ff456f731	2515	}
<>	153:fa9ff456f731	2516
<>	153:fa9ff456f731	2517	/* Clear overrun flag in 2 Lines communication mode because received is not read */
<>	153:fa9ff456f731	2518	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	153:fa9ff456f731	2519	{
<>	153:fa9ff456f731	2520	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	153:fa9ff456f731	2521	}
<>	153:fa9ff456f731	2522
<>	153:fa9ff456f731	2523	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2524	/* Check if CRC error occurred */
<>	153:fa9ff456f731	2525	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	153:fa9ff456f731	2526	{
<>	153:fa9ff456f731	2527	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2528	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	153:fa9ff456f731	2529	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	153:fa9ff456f731	2530	HAL_SPI_ErrorCallback(hspi);
<>	153:fa9ff456f731	2531	}
<>	153:fa9ff456f731	2532	else
<>	153:fa9ff456f731	2533	{
<>	153:fa9ff456f731	2534	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2535	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<>	153:fa9ff456f731	2536	{
<>	153:fa9ff456f731	2537	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<>	153:fa9ff456f731	2538	{
<>	153:fa9ff456f731	2539	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2540	HAL_SPI_RxCpltCallback(hspi);
<>	153:fa9ff456f731	2541	}
<>	153:fa9ff456f731	2542	else
<>	153:fa9ff456f731	2543	{
<>	153:fa9ff456f731	2544	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2545	HAL_SPI_TxRxCpltCallback(hspi);
<>	153:fa9ff456f731	2546	}
<>	153:fa9ff456f731	2547	}
<>	153:fa9ff456f731	2548	else
<>	153:fa9ff456f731	2549	{
<>	153:fa9ff456f731	2550	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2551	HAL_SPI_ErrorCallback(hspi);
<>	153:fa9ff456f731	2552	}
<>	153:fa9ff456f731	2553	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2554	}
<>	153:fa9ff456f731	2555	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2556	}
<>	153:fa9ff456f731	2557
<>	153:fa9ff456f731	2558	/**
<>	153:fa9ff456f731	2559	* @brief Handle the end of the RX transaction.
<>	153:fa9ff456f731	2560	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2561	* the configuration information for SPI module.
<>	153:fa9ff456f731	2562	* @retval None
<>	153:fa9ff456f731	2563	*/
<>	153:fa9ff456f731	2564	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	2565	{
<>	153:fa9ff456f731	2566	/* Disable RXNE and ERR interrupt */
<>	153:fa9ff456f731	2567	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	153:fa9ff456f731	2568
<>	153:fa9ff456f731	2569	/* Check the end of the transaction */
<>	153:fa9ff456f731	2570	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	153:fa9ff456f731	2571	{
<>	153:fa9ff456f731	2572	/* Disable SPI peripheral */
<>	153:fa9ff456f731	2573	__HAL_SPI_DISABLE(hspi);
<>	153:fa9ff456f731	2574	}
<>	153:fa9ff456f731	2575
<>	153:fa9ff456f731	2576	/* Clear overrun flag in 2 Lines communication mode because received is not read */
<>	153:fa9ff456f731	2577	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	153:fa9ff456f731	2578	{
<>	153:fa9ff456f731	2579	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	153:fa9ff456f731	2580	}
<>	153:fa9ff456f731	2581	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2582
<>	153:fa9ff456f731	2583	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2584	/* Check if CRC error occurred */
<>	153:fa9ff456f731	2585	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	153:fa9ff456f731	2586	{
<>	153:fa9ff456f731	2587	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	153:fa9ff456f731	2588	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	153:fa9ff456f731	2589	HAL_SPI_ErrorCallback(hspi);
<>	153:fa9ff456f731	2590	}
<>	153:fa9ff456f731	2591	else
<>	153:fa9ff456f731	2592	{
<>	153:fa9ff456f731	2593	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2594	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<>	153:fa9ff456f731	2595	{
<>	153:fa9ff456f731	2596	HAL_SPI_RxCpltCallback(hspi);
<>	153:fa9ff456f731	2597	}
<>	153:fa9ff456f731	2598	else
<>	153:fa9ff456f731	2599	{
<>	153:fa9ff456f731	2600	HAL_SPI_ErrorCallback(hspi);
<>	153:fa9ff456f731	2601	}
<>	153:fa9ff456f731	2602	#if (USE_SPI_CRC != 0U)
<>	153:fa9ff456f731	2603	}
<>	153:fa9ff456f731	2604	#endif /* USE_SPI_CRC */
<>	153:fa9ff456f731	2605	}
<>	153:fa9ff456f731	2606
<>	153:fa9ff456f731	2607	/**
<>	153:fa9ff456f731	2608	* @brief Handle the end of the TX transaction.
<>	153:fa9ff456f731	2609	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	153:fa9ff456f731	2610	* the configuration information for SPI module.
<>	153:fa9ff456f731	2611	* @retval None
<>	153:fa9ff456f731	2612	*/
<>	153:fa9ff456f731	2613	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
<>	153:fa9ff456f731	2614	{
<>	153:fa9ff456f731	2615	uint32_t tickstart = 0U;
<>	153:fa9ff456f731	2616	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
<>	153:fa9ff456f731	2617
<>	153:fa9ff456f731	2618	/* Init tickstart for timeout management*/
<>	153:fa9ff456f731	2619	tickstart = HAL_GetTick();
<>	153:fa9ff456f731	2620
<>	153:fa9ff456f731	2621	/* Wait until TXE flag is set */
<>	153:fa9ff456f731	2622	do
<>	153:fa9ff456f731	2623	{
<>	153:fa9ff456f731	2624	if(count-- == 0)
<>	153:fa9ff456f731	2625	{
<>	153:fa9ff456f731	2626	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	153:fa9ff456f731	2627	break;
<>	153:fa9ff456f731	2628	}
<>	153:fa9ff456f731	2629	}
<>	153:fa9ff456f731	2630	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
<>	153:fa9ff456f731	2631
<>	153:fa9ff456f731	2632	/* Disable TXE and ERR interrupt */
<>	153:fa9ff456f731	2633	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
<>	153:fa9ff456f731	2634
<>	153:fa9ff456f731	2635	/* Check Busy flag */
<>	153:fa9ff456f731	2636	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<>	153:fa9ff456f731	2637	{
<>	153:fa9ff456f731	2638	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	153:fa9ff456f731	2639	}
<>	153:fa9ff456f731	2640
<>	153:fa9ff456f731	2641	/* Clear overrun flag in 2 Lines communication mode because received is not read */
<>	153:fa9ff456f731	2642	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	153:fa9ff456f731	2643	{
<>	153:fa9ff456f731	2644	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	153:fa9ff456f731	2645	}
<>	153:fa9ff456f731	2646
<>	153:fa9ff456f731	2647	hspi->State = HAL_SPI_STATE_READY;
<>	153:fa9ff456f731	2648	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	153:fa9ff456f731	2649	{
<>	153:fa9ff456f731	2650	HAL_SPI_ErrorCallback(hspi);
<>	153:fa9ff456f731	2651	}
<>	153:fa9ff456f731	2652	else
<>	153:fa9ff456f731	2653	{
<>	153:fa9ff456f731	2654	HAL_SPI_TxCpltCallback(hspi);
<>	153:fa9ff456f731	2655	}
<>	153:fa9ff456f731	2656	}
<>	153:fa9ff456f731	2657
<>	153:fa9ff456f731	2658	/**
<>	153:fa9ff456f731	2659	* @}
<>	153:fa9ff456f731	2660	*/
<>	153:fa9ff456f731	2661
<>	153:fa9ff456f731	2662
<>	149:156823d33999	2663	#endif /* HAL_SPI_MODULE_ENABLED */
<>	149:156823d33999	2664	/**
<>	149:156823d33999	2665	* @}
<>	149:156823d33999	2666	*/
<>	149:156823d33999	2667
<>	149:156823d33999	2668	/**
<>	149:156823d33999	2669	* @}
<>	149:156823d33999	2670	*/
<>	149:156823d33999	2671
<>	149:156823d33999	2672	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	18 Dec 2017
Imports:	6
Forks:	0
Commits:	181
Dependents:	1
Dependencies:	0
Followers:	4

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.c@180:d79f997829d6, 2017-12-18 (annotated)

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Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.c@180:d79f997829d6, 2017-12-18 (annotated)

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