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targets/TARGET_Maxim/TARGET_MAX32625/device/i2cm_regs.h@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_I2CM_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_I2CM_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 #define MXC_S_I2CM_TRANS_TAG_START 0x000
<> 150:02e0a0aed4ec 58 #define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100
<> 150:02e0a0aed4ec 59 #define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200
<> 150:02e0a0aed4ec 60 #define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400
<> 150:02e0a0aed4ec 61 #define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500
<> 150:02e0a0aed4ec 62 #define MXC_S_I2CM_TRANS_TAG_STOP 0x700
<> 150:02e0a0aed4ec 63 #define MXC_S_I2CM_RSTLS_TAG_DATA 0x100
<> 150:02e0a0aed4ec 64 #define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200
<> 150:02e0a0aed4ec 65
<> 150:02e0a0aed4ec 66 /*
<> 150:02e0a0aed4ec 67 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 68 access to each register in module.
<> 150:02e0a0aed4ec 69 */
<> 150:02e0a0aed4ec 70
<> 150:02e0a0aed4ec 71 /* Offset Register Description
<> 150:02e0a0aed4ec 72 ============= ============================================================================ */
<> 150:02e0a0aed4ec 73 typedef struct {
<> 150:02e0a0aed4ec 74 __IO uint32_t fs_clk_div; /* 0x0000 I2C Master Full Speed SCL Clock Settings */
<> 150:02e0a0aed4ec 75 __I uint32_t rsv004[2]; /* 0x0004-0x0008 */
<> 150:02e0a0aed4ec 76 __IO uint32_t timeout; /* 0x000C I2C Master Timeout and Auto-Stop Settings */
<> 150:02e0a0aed4ec 77 __IO uint32_t ctrl; /* 0x0010 I2C Master Control Register */
<> 150:02e0a0aed4ec 78 __IO uint32_t trans; /* 0x0014 I2C Master Transaction Start and Status Flags */
<> 150:02e0a0aed4ec 79 __IO uint32_t intfl; /* 0x0018 I2C Master Interrupt Flags */
<> 150:02e0a0aed4ec 80 __IO uint32_t inten; /* 0x001C I2C Master Interrupt Enable/Disable Controls */
<> 150:02e0a0aed4ec 81 __I uint32_t rsv020[2]; /* 0x0020-0x0024 */
<> 150:02e0a0aed4ec 82 __IO uint32_t bb; /* 0x0028 I2C Master Bit-Bang Control Register */
<> 150:02e0a0aed4ec 83 } mxc_i2cm_regs_t;
<> 150:02e0a0aed4ec 84
<> 150:02e0a0aed4ec 85
<> 150:02e0a0aed4ec 86 /* Offset Register Description
<> 150:02e0a0aed4ec 87 ============= ============================================================================ */
<> 150:02e0a0aed4ec 88 typedef struct {
<> 150:02e0a0aed4ec 89 union { /* 0x0000-0x07FC FIFO Write Point for Data to Transmit */
<> 150:02e0a0aed4ec 90 __IO uint16_t tx;
<> 150:02e0a0aed4ec 91 __IO uint8_t tx_8[2048];
<> 150:02e0a0aed4ec 92 __IO uint16_t tx_16[1024];
<> 150:02e0a0aed4ec 93 __IO uint32_t tx_32[512];
<> 150:02e0a0aed4ec 94 };
<> 150:02e0a0aed4ec 95 union { /* 0x0800-0x0FFC FIFO Read Point for Received Data */
<> 150:02e0a0aed4ec 96 __IO uint16_t rx;
<> 150:02e0a0aed4ec 97 __IO uint8_t rx_8[2048];
<> 150:02e0a0aed4ec 98 __IO uint16_t rx_16[1024];
<> 150:02e0a0aed4ec 99 __IO uint32_t rx_32[512];
<> 150:02e0a0aed4ec 100 };
<> 150:02e0a0aed4ec 101 } mxc_i2cm_fifo_regs_t;
<> 150:02e0a0aed4ec 102
<> 150:02e0a0aed4ec 103
<> 150:02e0a0aed4ec 104 /*
<> 150:02e0a0aed4ec 105 Register offsets for module I2CM.
<> 150:02e0a0aed4ec 106 */
<> 150:02e0a0aed4ec 107
<> 150:02e0a0aed4ec 108 #define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 109 #define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL)
<> 150:02e0a0aed4ec 110 #define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL)
<> 150:02e0a0aed4ec 111 #define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL)
<> 150:02e0a0aed4ec 112 #define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL)
<> 150:02e0a0aed4ec 113 #define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL)
<> 150:02e0a0aed4ec 114 #define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL)
<> 150:02e0a0aed4ec 115 #define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 116 #define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
<> 150:02e0a0aed4ec 117
<> 150:02e0a0aed4ec 118
<> 150:02e0a0aed4ec 119 /*
<> 150:02e0a0aed4ec 120 Field positions and masks for module I2CM.
<> 150:02e0a0aed4ec 121 */
<> 150:02e0a0aed4ec 122
<> 150:02e0a0aed4ec 123 #define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS 0
<> 150:02e0a0aed4ec 124 #define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS))
<> 150:02e0a0aed4ec 125 #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS 8
<> 150:02e0a0aed4ec 126 #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS))
<> 150:02e0a0aed4ec 127 #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS 20
<> 150:02e0a0aed4ec 128 #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS))
<> 150:02e0a0aed4ec 129
<> 150:02e0a0aed4ec 130 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16
<> 150:02e0a0aed4ec 131 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS))
<> 150:02e0a0aed4ec 132 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24
<> 150:02e0a0aed4ec 133 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS))
<> 150:02e0a0aed4ec 134
<> 150:02e0a0aed4ec 135 #define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2
<> 150:02e0a0aed4ec 136 #define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS))
<> 150:02e0a0aed4ec 137 #define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3
<> 150:02e0a0aed4ec 138 #define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS))
<> 150:02e0a0aed4ec 139 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7
<> 150:02e0a0aed4ec 140 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS))
<> 150:02e0a0aed4ec 141
<> 150:02e0a0aed4ec 142 #define MXC_F_I2CM_TRANS_TX_START_POS 0
<> 150:02e0a0aed4ec 143 #define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS))
<> 150:02e0a0aed4ec 144 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1
<> 150:02e0a0aed4ec 145 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS))
<> 150:02e0a0aed4ec 146 #define MXC_F_I2CM_TRANS_TX_DONE_POS 2
<> 150:02e0a0aed4ec 147 #define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS))
<> 150:02e0a0aed4ec 148 #define MXC_F_I2CM_TRANS_TX_NACKED_POS 3
<> 150:02e0a0aed4ec 149 #define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS))
<> 150:02e0a0aed4ec 150 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4
<> 150:02e0a0aed4ec 151 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS))
<> 150:02e0a0aed4ec 152 #define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5
<> 150:02e0a0aed4ec 153 #define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS))
<> 150:02e0a0aed4ec 154
<> 150:02e0a0aed4ec 155 #define MXC_F_I2CM_INTFL_TX_DONE_POS 0
<> 150:02e0a0aed4ec 156 #define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS))
<> 150:02e0a0aed4ec 157 #define MXC_F_I2CM_INTFL_TX_NACKED_POS 1
<> 150:02e0a0aed4ec 158 #define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS))
<> 150:02e0a0aed4ec 159 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2
<> 150:02e0a0aed4ec 160 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS))
<> 150:02e0a0aed4ec 161 #define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3
<> 150:02e0a0aed4ec 162 #define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS))
<> 150:02e0a0aed4ec 163 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4
<> 150:02e0a0aed4ec 164 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS))
<> 150:02e0a0aed4ec 165 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5
<> 150:02e0a0aed4ec 166 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS))
<> 150:02e0a0aed4ec 167 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6
<> 150:02e0a0aed4ec 168 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS))
<> 150:02e0a0aed4ec 169 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7
<> 150:02e0a0aed4ec 170 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS))
<> 150:02e0a0aed4ec 171 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8
<> 150:02e0a0aed4ec 172 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS))
<> 150:02e0a0aed4ec 173 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9
<> 150:02e0a0aed4ec 174 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS))
<> 150:02e0a0aed4ec 175
<> 150:02e0a0aed4ec 176 #define MXC_F_I2CM_INTEN_TX_DONE_POS 0
<> 150:02e0a0aed4ec 177 #define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS))
<> 150:02e0a0aed4ec 178 #define MXC_F_I2CM_INTEN_TX_NACKED_POS 1
<> 150:02e0a0aed4ec 179 #define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS))
<> 150:02e0a0aed4ec 180 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2
<> 150:02e0a0aed4ec 181 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS))
<> 150:02e0a0aed4ec 182 #define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3
<> 150:02e0a0aed4ec 183 #define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS))
<> 150:02e0a0aed4ec 184 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4
<> 150:02e0a0aed4ec 185 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS))
<> 150:02e0a0aed4ec 186 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5
<> 150:02e0a0aed4ec 187 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS))
<> 150:02e0a0aed4ec 188 #define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS 6
<> 150:02e0a0aed4ec 189 #define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS))
<> 150:02e0a0aed4ec 190 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7
<> 150:02e0a0aed4ec 191 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS))
<> 150:02e0a0aed4ec 192 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8
<> 150:02e0a0aed4ec 193 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS))
<> 150:02e0a0aed4ec 194 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9
<> 150:02e0a0aed4ec 195 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS))
<> 150:02e0a0aed4ec 196
<> 150:02e0a0aed4ec 197 #define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0
<> 150:02e0a0aed4ec 198 #define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS))
<> 150:02e0a0aed4ec 199 #define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1
<> 150:02e0a0aed4ec 200 #define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS))
<> 150:02e0a0aed4ec 201 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2
<> 150:02e0a0aed4ec 202 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS))
<> 150:02e0a0aed4ec 203 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3
<> 150:02e0a0aed4ec 204 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS))
<> 150:02e0a0aed4ec 205 #define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16
<> 150:02e0a0aed4ec 206 #define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS))
<> 150:02e0a0aed4ec 207
<> 150:02e0a0aed4ec 208
<> 150:02e0a0aed4ec 209
<> 150:02e0a0aed4ec 210 #ifdef __cplusplus
<> 150:02e0a0aed4ec 211 }
<> 150:02e0a0aed4ec 212 #endif
<> 150:02e0a0aed4ec 213
<> 150:02e0a0aed4ec 214 #endif /* _MXC_I2CM_REGS_H_ */
<> 150:02e0a0aed4ec 215