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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
Parent:
149:156823d33999 
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 157:ff67d9f36b67 5 * @version V1.4.0
<> 157:ff67d9f36b67 6 * @date 16-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file contains all the functions prototypes for the HAL
<> 144:ef7eb2e8f9f7 8 * module driver.
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @attention
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 15 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 20 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 22 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 23 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 *
<> 144:ef7eb2e8f9f7 36 ******************************************************************************
<> 144:ef7eb2e8f9f7 37 */
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #ifndef __STM32F3xx_HAL_H
<> 144:ef7eb2e8f9f7 41 #define __STM32F3xx_HAL_H
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 44 extern "C" {
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 48 #include "stm32f3xx_hal_conf.h"
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup HAL
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @addtogroup HAL_Private_Macros
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
<> 144:ef7eb2e8f9f7 63 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
<> 144:ef7eb2e8f9f7 64 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
<> 144:ef7eb2e8f9f7 65 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
<> 144:ef7eb2e8f9f7 66 /**
<> 144:ef7eb2e8f9f7 67 * @}
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 71 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 72 /** @defgroup HAL_Exported_Constants HAL Exported Constants
<> 144:ef7eb2e8f9f7 73 * @{
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75 /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
<> 144:ef7eb2e8f9f7 76 * @brief SYSCFG registers bit address in the alias region
<> 144:ef7eb2e8f9f7 77 * @{
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 /* ------------ SYSCFG registers bit address in the alias region -------------*/
<> 144:ef7eb2e8f9f7 80 #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
<> 144:ef7eb2e8f9f7 81 /* --- CFGR2 Register ---*/
<> 144:ef7eb2e8f9f7 82 /* Alias word address of BYP_ADDR_PAR bit */
<> 157:ff67d9f36b67 83 #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)
<> 144:ef7eb2e8f9f7 84 #define BYPADDRPAR_BitNumber 0x04
<> 157:ff67d9f36b67 85 #define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
<> 144:ef7eb2e8f9f7 86 /**
<> 144:ef7eb2e8f9f7 87 * @}
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 #if defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 91 /** @defgroup HAL_DMA_Remapping HAL DMA Remapping
<> 144:ef7eb2e8f9f7 92 * Elements values convention: 0xXXYYYYYY
<> 144:ef7eb2e8f9f7 93 * - YYYYYY : Position in the register
<> 144:ef7eb2e8f9f7 94 * - XX : Register index
<> 144:ef7eb2e8f9f7 95 * - 00: CFGR1 register in SYSCFG
<> 144:ef7eb2e8f9f7 96 * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 157:ff67d9f36b67 99 #define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
<> 157:ff67d9f36b67 100 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4U) */
<> 157:ff67d9f36b67 101 #define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap
<> 157:ff67d9f36b67 102 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6U) */
<> 157:ff67d9f36b67 103 #define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap
<> 157:ff67d9f36b67 104 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7U) */
<> 157:ff67d9f36b67 105 #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
<> 157:ff67d9f36b67 106 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3U) */
<> 157:ff67d9f36b67 107 #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
<> 157:ff67d9f36b67 108 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4U) */
<> 157:ff67d9f36b67 109 #define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 110 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5U) */
<> 157:ff67d9f36b67 111 #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 112 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5U) */
<> 144:ef7eb2e8f9f7 113 #if defined(SYSCFG_CFGR3_DMA_RMP)
<> 144:ef7eb2e8f9f7 114 #if !defined(HAL_REMAP_CFGR3_MASK)
<> 157:ff67d9f36b67 115 #define HAL_REMAP_CFGR3_MASK (0x01000000U)
<> 144:ef7eb2e8f9f7 116 #endif
<> 144:ef7eb2e8f9f7 117
<> 157:ff67d9f36b67 118 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 119 11: Map on DMA1 channel 2U */
<> 157:ff67d9f36b67 120 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 121 01: Map on DMA1 channel 4U */
<> 157:ff67d9f36b67 122 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 123 10: Map on DMA1 channel 6U */
<> 157:ff67d9f36b67 124 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 125 11: Map on DMA1 channel 3U */
<> 157:ff67d9f36b67 126 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 127 01: Map on DMA1 channel 5U */
<> 157:ff67d9f36b67 128 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 129 10: Map on DMA1 channel 7U */
<> 157:ff67d9f36b67 130 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 131 11: Map on DMA1 channel 7U */
<> 157:ff67d9f36b67 132 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 133 01: Map on DMA1 channel 3U */
<> 157:ff67d9f36b67 134 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 135 10: Map on DMA1 channel 5U */
<> 157:ff67d9f36b67 136 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 137 11: Map on DMA1 channel 6U */
<> 157:ff67d9f36b67 138 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 139 01: Map on DMA1 channel 2U */
<> 157:ff67d9f36b67 140 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only)
<> 157:ff67d9f36b67 141 10: Map on DMA1 channel 4U */
<> 157:ff67d9f36b67 142 #define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap
<> 144:ef7eb2e8f9f7 143 x0: No remap (ADC2 on DMA2)
<> 157:ff67d9f36b67 144 10: Map on DMA1 channel 2U */
<> 157:ff67d9f36b67 145 #define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap
<> 157:ff67d9f36b67 146 11: Map on DMA1 channel 4U */
<> 144:ef7eb2e8f9f7 147 #endif /* SYSCFG_CFGR3_DMA_RMP */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 #if defined(SYSCFG_CFGR3_DMA_RMP)
<> 144:ef7eb2e8f9f7 150 #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
<> 144:ef7eb2e8f9f7 151 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
<> 144:ef7eb2e8f9f7 152 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
<> 144:ef7eb2e8f9f7 153 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
<> 144:ef7eb2e8f9f7 154 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
<> 144:ef7eb2e8f9f7 155 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
<> 144:ef7eb2e8f9f7 156 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
<> 144:ef7eb2e8f9f7 157 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
<> 144:ef7eb2e8f9f7 158 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
<> 144:ef7eb2e8f9f7 159 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
<> 144:ef7eb2e8f9f7 160 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
<> 144:ef7eb2e8f9f7 161 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
<> 144:ef7eb2e8f9f7 162 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
<> 144:ef7eb2e8f9f7 163 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
<> 144:ef7eb2e8f9f7 164 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
<> 144:ef7eb2e8f9f7 165 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
<> 144:ef7eb2e8f9f7 166 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
<> 144:ef7eb2e8f9f7 167 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
<> 144:ef7eb2e8f9f7 168 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
<> 144:ef7eb2e8f9f7 169 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
<> 144:ef7eb2e8f9f7 170 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
<> 144:ef7eb2e8f9f7 171 #else
<> 144:ef7eb2e8f9f7 172 #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
<> 144:ef7eb2e8f9f7 173 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
<> 144:ef7eb2e8f9f7 174 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
<> 144:ef7eb2e8f9f7 175 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
<> 144:ef7eb2e8f9f7 176 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
<> 144:ef7eb2e8f9f7 177 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
<> 144:ef7eb2e8f9f7 178 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
<> 144:ef7eb2e8f9f7 179 #endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
<> 144:ef7eb2e8f9f7 180 /**
<> 144:ef7eb2e8f9f7 181 * @}
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 #endif /* SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping
<> 144:ef7eb2e8f9f7 186 * Elements values convention: 0xXXYYYYYY
<> 144:ef7eb2e8f9f7 187 * - YYYYYY : Position in the register
<> 144:ef7eb2e8f9f7 188 * - XX : Register index
<> 144:ef7eb2e8f9f7 189 * - 00: CFGR1 register in SYSCFG
<> 144:ef7eb2e8f9f7 190 * - 01: CFGR3 register in SYSCFG
<> 144:ef7eb2e8f9f7 191 * @{
<> 144:ef7eb2e8f9f7 192 */
<> 157:ff67d9f36b67 193 #define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
<> 144:ef7eb2e8f9f7 194 0: No remap (DAC trigger is TIM8_TRGO)
<> 144:ef7eb2e8f9f7 195 1: Remap (DAC trigger is TIM3_TRGO) */
<> 157:ff67d9f36b67 196 #define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap
<> 144:ef7eb2e8f9f7 197 0: No remap
<> 144:ef7eb2e8f9f7 198 1: Remap (TIM1_TRG3 = TIM17_OC) */
<> 144:ef7eb2e8f9f7 199 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
<> 144:ef7eb2e8f9f7 200 #if !defined(HAL_REMAP_CFGR3_MASK)
<> 157:ff67d9f36b67 201 #define HAL_REMAP_CFGR3_MASK (0x01000000U)
<> 144:ef7eb2e8f9f7 202 #endif
<> 157:ff67d9f36b67 203 #define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
<> 144:ef7eb2e8f9f7 204 0: Remap (DAC trigger is TIM15_TRGO)
<> 144:ef7eb2e8f9f7 205 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
<> 157:ff67d9f36b67 206 #define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
<> 144:ef7eb2e8f9f7 207 0: No remap
<> 144:ef7eb2e8f9f7 208 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
<> 144:ef7eb2e8f9f7 209 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
<> 144:ef7eb2e8f9f7 210 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
<> 144:ef7eb2e8f9f7 211 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
<> 144:ef7eb2e8f9f7 212 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
<> 144:ef7eb2e8f9f7 213 #else
<> 144:ef7eb2e8f9f7 214 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
<> 144:ef7eb2e8f9f7 215 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
<> 144:ef7eb2e8f9f7 216 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @}
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #if defined (STM32F302xE)
<> 144:ef7eb2e8f9f7 222 /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
<> 144:ef7eb2e8f9f7 223 * @{
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225 #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
<> 144:ef7eb2e8f9f7 226 0: No remap (TIM1_CC3)
<> 144:ef7eb2e8f9f7 227 1: Remap (TIM20_TRGO) */
<> 144:ef7eb2e8f9f7 228 #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
<> 144:ef7eb2e8f9f7 229 0: No remap (TIM2_CC2)
<> 144:ef7eb2e8f9f7 230 1: Remap (TIM20_TRGO2) */
<> 144:ef7eb2e8f9f7 231 #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
<> 144:ef7eb2e8f9f7 232 0: No remap (TIM4_CC4)
<> 144:ef7eb2e8f9f7 233 1: Remap (TIM20_CC1) */
<> 144:ef7eb2e8f9f7 234 #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
<> 144:ef7eb2e8f9f7 235 0: No remap (TIM6_TRGO)
<> 144:ef7eb2e8f9f7 236 1: Remap (TIM20_CC2) */
<> 144:ef7eb2e8f9f7 237 #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
<> 144:ef7eb2e8f9f7 238 0: No remap (TIM3_CC4)
<> 144:ef7eb2e8f9f7 239 1: Remap (TIM20_CC3) */
<> 144:ef7eb2e8f9f7 240 #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
<> 144:ef7eb2e8f9f7 241 0: No remap (TIM2_CC1)
<> 144:ef7eb2e8f9f7 242 1: Remap (TIM20_TRGO) */
<> 144:ef7eb2e8f9f7 243 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
<> 157:ff67d9f36b67 244 0: No remap (EXTI line 15U)
<> 144:ef7eb2e8f9f7 245 1: Remap (TIM20_TRGO2) */
<> 144:ef7eb2e8f9f7 246 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
<> 144:ef7eb2e8f9f7 247 0: No remap (TIM3_CC1)
<> 144:ef7eb2e8f9f7 248 1: Remap (TIM20_CC4) */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
<> 144:ef7eb2e8f9f7 251 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
<> 144:ef7eb2e8f9f7 252 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
<> 157:ff67d9f36b67 253 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13U) == HAL_REMAPADCTRIGGER_ADC12_EXT13U) || \
<> 157:ff67d9f36b67 254 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15U) == HAL_REMAPADCTRIGGER_ADC12_EXT15U) || \
<> 144:ef7eb2e8f9f7 255 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
<> 144:ef7eb2e8f9f7 256 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
<> 157:ff67d9f36b67 257 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13U) == HAL_REMAPADCTRIGGER_ADC12_JEXT13U))
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @}
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 #endif /* STM32F302xE */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 #if defined (STM32F303xE) || defined (STM32F398xx)
<> 144:ef7eb2e8f9f7 264 /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
<> 144:ef7eb2e8f9f7 265 * @{
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
<> 144:ef7eb2e8f9f7 268 0: No remap (TIM1_CC3)
<> 144:ef7eb2e8f9f7 269 1: Remap (TIM20_TRGO) */
<> 144:ef7eb2e8f9f7 270 #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
<> 144:ef7eb2e8f9f7 271 0: No remap (TIM2_CC2)
<> 144:ef7eb2e8f9f7 272 1: Remap (TIM20_TRGO2) */
<> 144:ef7eb2e8f9f7 273 #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
<> 144:ef7eb2e8f9f7 274 0: No remap (TIM4_CC4)
<> 144:ef7eb2e8f9f7 275 1: Remap (TIM20_CC1) */
<> 144:ef7eb2e8f9f7 276 #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
<> 144:ef7eb2e8f9f7 277 0: No remap (TIM6_TRGO)
<> 144:ef7eb2e8f9f7 278 1: Remap (TIM20_CC2) */
<> 144:ef7eb2e8f9f7 279 #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
<> 144:ef7eb2e8f9f7 280 0: No remap (TIM3_CC4)
<> 144:ef7eb2e8f9f7 281 1: Remap (TIM20_CC3) */
<> 144:ef7eb2e8f9f7 282 #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
<> 144:ef7eb2e8f9f7 283 0: No remap (TIM2_CC1)
<> 144:ef7eb2e8f9f7 284 1: Remap (TIM20_TRGO) */
<> 144:ef7eb2e8f9f7 285 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
<> 157:ff67d9f36b67 286 0: No remap (EXTI line 15U)
<> 144:ef7eb2e8f9f7 287 1: Remap (TIM20_TRGO2) */
<> 144:ef7eb2e8f9f7 288 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
<> 144:ef7eb2e8f9f7 289 0: No remap (TIM3_CC1)
<> 144:ef7eb2e8f9f7 290 1: Remap (TIM20_CC4) */
<> 144:ef7eb2e8f9f7 291 #define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
<> 157:ff67d9f36b67 292 0: No remap (EXTI line 2U)
<> 144:ef7eb2e8f9f7 293 1: Remap (TIM20_TRGO) */
<> 144:ef7eb2e8f9f7 294 #define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
<> 144:ef7eb2e8f9f7 295 0: No remap (TIM4_CC1)
<> 144:ef7eb2e8f9f7 296 1: Remap (TIM20_TRGO2) */
<> 144:ef7eb2e8f9f7 297 #define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15
<> 144:ef7eb2e8f9f7 298 0: No remap (TIM2_CC1)
<> 144:ef7eb2e8f9f7 299 1: Remap (TIM20_CC1) */
<> 144:ef7eb2e8f9f7 300 #define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5
<> 144:ef7eb2e8f9f7 301 0: No remap (TIM4_CC3)
<> 144:ef7eb2e8f9f7 302 1: Remap (TIM20_TRGO) */
<> 144:ef7eb2e8f9f7 303 #define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
<> 144:ef7eb2e8f9f7 304 0: No remap (TIM1_CC3)
<> 144:ef7eb2e8f9f7 305 1: Remap (TIM20_TRGO2) */
<> 144:ef7eb2e8f9f7 306 #define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
<> 144:ef7eb2e8f9f7 307 0: No remap (TIM7_TRGO)
<> 144:ef7eb2e8f9f7 308 1: Remap (TIM20_CC2) */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
<> 144:ef7eb2e8f9f7 311 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
<> 144:ef7eb2e8f9f7 312 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
<> 157:ff67d9f36b67 313 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13U) == HAL_REMAPADCTRIGGER_ADC12_EXT13U) || \
<> 157:ff67d9f36b67 314 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15U) == HAL_REMAPADCTRIGGER_ADC12_EXT15U) || \
<> 144:ef7eb2e8f9f7 315 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
<> 144:ef7eb2e8f9f7 316 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
<> 157:ff67d9f36b67 317 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13U) == HAL_REMAPADCTRIGGER_ADC12_JEXT13U) || \
<> 144:ef7eb2e8f9f7 318 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
<> 144:ef7eb2e8f9f7 319 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
<> 157:ff67d9f36b67 320 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15U) == HAL_REMAPADCTRIGGER_ADC34_EXT15U) || \
<> 144:ef7eb2e8f9f7 321 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
<> 157:ff67d9f36b67 322 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11U) == HAL_REMAPADCTRIGGER_ADC34_JEXT11U) || \
<> 157:ff67d9f36b67 323 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14U) == HAL_REMAPADCTRIGGER_ADC34_JEXT14U))
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 #endif /* STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
<> 144:ef7eb2e8f9f7 330 * @{
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /** @brief Fast-mode Plus driving capability on a specific GPIO
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335 #if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
<> 144:ef7eb2e8f9f7 336 #define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast-mode Plus on PB6 */
<> 144:ef7eb2e8f9f7 337 #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 #if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
<> 144:ef7eb2e8f9f7 340 #define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast-mode Plus on PB7 */
<> 144:ef7eb2e8f9f7 341 #endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
<> 144:ef7eb2e8f9f7 344 #define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast-mode Plus on PB8 */
<> 144:ef7eb2e8f9f7 345 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
<> 144:ef7eb2e8f9f7 348 #define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast-mode Plus on PB9 */
<> 144:ef7eb2e8f9f7 349 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @}
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 #if defined(SYSCFG_RCR_PAGE0)
<> 144:ef7eb2e8f9f7 355 /* CCM-SRAM defined */
<> 144:ef7eb2e8f9f7 356 /** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection
<> 144:ef7eb2e8f9f7 357 * @{
<> 144:ef7eb2e8f9f7 358 */
<> 157:ff67d9f36b67 359 #define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0U */
<> 157:ff67d9f36b67 360 #define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1U */
<> 157:ff67d9f36b67 361 #define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2U */
<> 157:ff67d9f36b67 362 #define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3U */
<> 144:ef7eb2e8f9f7 363 #if defined(SYSCFG_RCR_PAGE4)
<> 144:ef7eb2e8f9f7 364 /* More than 4KB CCM-SRAM defined */
<> 157:ff67d9f36b67 365 #define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4U */
<> 157:ff67d9f36b67 366 #define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5U */
<> 157:ff67d9f36b67 367 #define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6U */
<> 157:ff67d9f36b67 368 #define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7U */
<> 144:ef7eb2e8f9f7 369 #endif /* SYSCFG_RCR_PAGE4 */
<> 144:ef7eb2e8f9f7 370 #if defined(SYSCFG_RCR_PAGE8)
<> 157:ff67d9f36b67 371 #define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8U */
<> 157:ff67d9f36b67 372 #define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9U */
<> 157:ff67d9f36b67 373 #define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10U) /*!< ICODE SRAM Write protection page 10U */
<> 157:ff67d9f36b67 374 #define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11U) /*!< ICODE SRAM Write protection page 11U */
<> 157:ff67d9f36b67 375 #define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12U) /*!< ICODE SRAM Write protection page 12U */
<> 157:ff67d9f36b67 376 #define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13U) /*!< ICODE SRAM Write protection page 13U */
<> 157:ff67d9f36b67 377 #define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14U) /*!< ICODE SRAM Write protection page 14U */
<> 157:ff67d9f36b67 378 #define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15U) /*!< ICODE SRAM Write protection page 15U */
<> 144:ef7eb2e8f9f7 379 #endif /* SYSCFG_RCR_PAGE8 */
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 #if defined(SYSCFG_RCR_PAGE8)
<> 157:ff67d9f36b67 382 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU))
<> 144:ef7eb2e8f9f7 383 #elif defined(SYSCFG_RCR_PAGE4)
<> 157:ff67d9f36b67 384 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU))
<> 144:ef7eb2e8f9f7 385 #else
<> 157:ff67d9f36b67 386 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU))
<> 144:ef7eb2e8f9f7 387 #endif /* SYSCFG_RCR_PAGE8 */
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @}
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391 #endif /* SYSCFG_RCR_PAGE0 */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts
<> 144:ef7eb2e8f9f7 394 * @{
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 #define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
<> 144:ef7eb2e8f9f7 397 #define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
<> 144:ef7eb2e8f9f7 398 #define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
<> 144:ef7eb2e8f9f7 399 #define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
<> 144:ef7eb2e8f9f7 400 #define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
<> 144:ef7eb2e8f9f7 401 #define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 #define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
<> 144:ef7eb2e8f9f7 404 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
<> 144:ef7eb2e8f9f7 405 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
<> 144:ef7eb2e8f9f7 406 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
<> 144:ef7eb2e8f9f7 407 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
<> 144:ef7eb2e8f9f7 408 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @}
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @}
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 419 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 144:ef7eb2e8f9f7 420 * @{
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 424 * @{
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 427 #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
<> 144:ef7eb2e8f9f7 428 #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
<> 144:ef7eb2e8f9f7 429 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 432 #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
<> 144:ef7eb2e8f9f7 433 #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
<> 144:ef7eb2e8f9f7 434 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
<> 144:ef7eb2e8f9f7 437 #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
<> 144:ef7eb2e8f9f7 438 #define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
<> 144:ef7eb2e8f9f7 439 #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
<> 144:ef7eb2e8f9f7 442 #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
<> 144:ef7eb2e8f9f7 443 #define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
<> 144:ef7eb2e8f9f7 444 #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 447 #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
<> 144:ef7eb2e8f9f7 448 #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
<> 144:ef7eb2e8f9f7 449 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 452 #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
<> 144:ef7eb2e8f9f7 453 #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
<> 144:ef7eb2e8f9f7 454 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
<> 144:ef7eb2e8f9f7 457 #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
<> 144:ef7eb2e8f9f7 458 #define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
<> 144:ef7eb2e8f9f7 459 #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
<> 144:ef7eb2e8f9f7 462 #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
<> 144:ef7eb2e8f9f7 463 #define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
<> 144:ef7eb2e8f9f7 464 #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 467 #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
<> 144:ef7eb2e8f9f7 468 #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
<> 144:ef7eb2e8f9f7 469 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
<> 144:ef7eb2e8f9f7 472 #define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
<> 144:ef7eb2e8f9f7 473 #define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
<> 144:ef7eb2e8f9f7 474 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 144:ef7eb2e8f9f7 477 #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
<> 144:ef7eb2e8f9f7 478 #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
<> 144:ef7eb2e8f9f7 479 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 482 #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
<> 144:ef7eb2e8f9f7 483 #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
<> 144:ef7eb2e8f9f7 484 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 487 #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
<> 144:ef7eb2e8f9f7 488 #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
<> 144:ef7eb2e8f9f7 489 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 492 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 493 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 494 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 497 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 498 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 499 #endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 502 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 503 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 504 #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
<> 144:ef7eb2e8f9f7 507 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
<> 144:ef7eb2e8f9f7 508 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
<> 144:ef7eb2e8f9f7 509 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
<> 144:ef7eb2e8f9f7 510 /**
<> 144:ef7eb2e8f9f7 511 * @}
<> 144:ef7eb2e8f9f7 512 */
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 515 * @{
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 518 #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
<> 144:ef7eb2e8f9f7 519 #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
<> 144:ef7eb2e8f9f7 520 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
<> 144:ef7eb2e8f9f7 523 #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
<> 144:ef7eb2e8f9f7 524 #define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
<> 144:ef7eb2e8f9f7 525 #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 528 #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
<> 144:ef7eb2e8f9f7 529 #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
<> 144:ef7eb2e8f9f7 530 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 533 #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
<> 144:ef7eb2e8f9f7 534 #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
<> 144:ef7eb2e8f9f7 535 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 538 #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
<> 144:ef7eb2e8f9f7 539 #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
<> 144:ef7eb2e8f9f7 540 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
<> 144:ef7eb2e8f9f7 543 #define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
<> 144:ef7eb2e8f9f7 544 #define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
<> 144:ef7eb2e8f9f7 545 #endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
<> 144:ef7eb2e8f9f7 548 #define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP))
<> 144:ef7eb2e8f9f7 549 #define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP))
<> 144:ef7eb2e8f9f7 550 #endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
<> 144:ef7eb2e8f9f7 553 #define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
<> 144:ef7eb2e8f9f7 554 #define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
<> 144:ef7eb2e8f9f7 555 #endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */
<> 144:ef7eb2e8f9f7 556 /**
<> 144:ef7eb2e8f9f7 557 * @}
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
<> 144:ef7eb2e8f9f7 561 * @{
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 #if defined(SYSCFG_CFGR1_MEM_MODE)
<> 144:ef7eb2e8f9f7 564 /** @brief Main Flash memory mapped at 0x00000000
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
<> 144:ef7eb2e8f9f7 567 #endif /* SYSCFG_CFGR1_MEM_MODE */
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
<> 144:ef7eb2e8f9f7 570 /** @brief System Flash memory mapped at 0x00000000
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
<> 144:ef7eb2e8f9f7 573 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
<> 157:ff67d9f36b67 574 }while(0U)
<> 144:ef7eb2e8f9f7 575 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
<> 144:ef7eb2e8f9f7 578 /** @brief Embedded SRAM mapped at 0x00000000
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
<> 144:ef7eb2e8f9f7 581 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
<> 157:ff67d9f36b67 582 }while(0U)
<> 144:ef7eb2e8f9f7 583 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 #if defined(SYSCFG_CFGR1_MEM_MODE_2)
<> 144:ef7eb2e8f9f7 586 #define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
<> 144:ef7eb2e8f9f7 587 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
<> 157:ff67d9f36b67 588 }while(0U)
<> 144:ef7eb2e8f9f7 589 #endif /* SYSCFG_CFGR1_MEM_MODE_2 */
<> 144:ef7eb2e8f9f7 590 /**
<> 144:ef7eb2e8f9f7 591 * @}
<> 144:ef7eb2e8f9f7 592 */
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /** @defgroup Encoder_Mode Encoder Mode
<> 144:ef7eb2e8f9f7 595 * @{
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
<> 144:ef7eb2e8f9f7 598 /** @brief No Encoder mode
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600 #define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
<> 144:ef7eb2e8f9f7 601 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
<> 144:ef7eb2e8f9f7 604 /** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606 #define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
<> 144:ef7eb2e8f9f7 607 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
<> 157:ff67d9f36b67 608 }while(0U)
<> 144:ef7eb2e8f9f7 609 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 #if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
<> 144:ef7eb2e8f9f7 612 /** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614 #define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
<> 144:ef7eb2e8f9f7 615 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
<> 157:ff67d9f36b67 616 }while(0U)
<> 144:ef7eb2e8f9f7 617 #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
<> 144:ef7eb2e8f9f7 620 /** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 #define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
<> 144:ef7eb2e8f9f7 623 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
<> 157:ff67d9f36b67 624 }while(0U)
<> 144:ef7eb2e8f9f7 625 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
<> 144:ef7eb2e8f9f7 626 /**
<> 144:ef7eb2e8f9f7 627 * @}
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /** @defgroup DMA_Remap_Enable DMA Remap Enable
<> 144:ef7eb2e8f9f7 631 * @{
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633 #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 634 /** @brief DMA remapping enable/disable macros
<> 144:ef7eb2e8f9f7 635 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
<> 144:ef7eb2e8f9f7 636 */
<> 144:ef7eb2e8f9f7 637 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
<> 144:ef7eb2e8f9f7 638 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
<> 144:ef7eb2e8f9f7 639 (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
<> 144:ef7eb2e8f9f7 640 (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
<> 157:ff67d9f36b67 641 }while(0U)
<> 144:ef7eb2e8f9f7 642 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
<> 144:ef7eb2e8f9f7 643 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
<> 144:ef7eb2e8f9f7 644 (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
<> 144:ef7eb2e8f9f7 645 (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
<> 157:ff67d9f36b67 646 }while(0U)
<> 144:ef7eb2e8f9f7 647 #elif defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 648 /** @brief DMA remapping enable/disable macros
<> 144:ef7eb2e8f9f7 649 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
<> 144:ef7eb2e8f9f7 652 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
<> 157:ff67d9f36b67 653 }while(0U)
<> 144:ef7eb2e8f9f7 654 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
<> 144:ef7eb2e8f9f7 655 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
<> 157:ff67d9f36b67 656 }while(0U)
<> 144:ef7eb2e8f9f7 657 #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 658 /**
<> 144:ef7eb2e8f9f7 659 * @}
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO
<> 144:ef7eb2e8f9f7 663 * @{
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665 /** @brief Fast-mode Plus driving capability enable/disable macros
<> 144:ef7eb2e8f9f7 666 * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
<> 144:ef7eb2e8f9f7 667 * That you can find above these macros.
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
<> 144:ef7eb2e8f9f7 670 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
<> 157:ff67d9f36b67 671 }while(0U)
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
<> 144:ef7eb2e8f9f7 674 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
<> 157:ff67d9f36b67 675 }while(0U)
<> 144:ef7eb2e8f9f7 676 /**
<> 144:ef7eb2e8f9f7 677 * @}
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable
<> 144:ef7eb2e8f9f7 681 * @{
<> 144:ef7eb2e8f9f7 682 */
<> 144:ef7eb2e8f9f7 683 /** @brief SYSCFG interrupt enable/disable macros
<> 144:ef7eb2e8f9f7 684 * @param __INTERRUPT__: This parameter can be a value of @ref HAL_SYSCFG_Interrupts
<> 144:ef7eb2e8f9f7 685 */
<> 144:ef7eb2e8f9f7 686 #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
<> 144:ef7eb2e8f9f7 687 SYSCFG->CFGR1 |= (__INTERRUPT__); \
<> 157:ff67d9f36b67 688 }while(0U)
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
<> 144:ef7eb2e8f9f7 691 SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
<> 157:ff67d9f36b67 692 }while(0U)
<> 144:ef7eb2e8f9f7 693 /**
<> 144:ef7eb2e8f9f7 694 * @}
<> 144:ef7eb2e8f9f7 695 */
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
<> 144:ef7eb2e8f9f7 698 /** @defgroup USB_Interrupt_Remap USB Interrupt Remap
<> 144:ef7eb2e8f9f7 699 * @{
<> 144:ef7eb2e8f9f7 700 */
<> 144:ef7eb2e8f9f7 701 /** @brief USB interrupt remapping enable/disable macros
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703 #define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
<> 144:ef7eb2e8f9f7 704 #define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
<> 144:ef7eb2e8f9f7 705 /**
<> 144:ef7eb2e8f9f7 706 * @}
<> 144:ef7eb2e8f9f7 707 */
<> 144:ef7eb2e8f9f7 708 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 #if defined(SYSCFG_CFGR1_VBAT)
<> 144:ef7eb2e8f9f7 711 /** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
<> 144:ef7eb2e8f9f7 712 * @{
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714 /** @brief SYSCFG interrupt enable/disable macros
<> 144:ef7eb2e8f9f7 715 */
<> 144:ef7eb2e8f9f7 716 #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
<> 144:ef7eb2e8f9f7 717 #define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
<> 144:ef7eb2e8f9f7 718 /**
<> 144:ef7eb2e8f9f7 719 * @}
<> 144:ef7eb2e8f9f7 720 */
<> 144:ef7eb2e8f9f7 721 #endif /* SYSCFG_CFGR1_VBAT */
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
<> 144:ef7eb2e8f9f7 724 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
<> 144:ef7eb2e8f9f7 725 * @{
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727 /** @brief SYSCFG Break Lockup lock
<> 144:ef7eb2e8f9f7 728 * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
<> 144:ef7eb2e8f9f7 729 * @note The selected configuration is locked and can be unlocked by system reset
<> 144:ef7eb2e8f9f7 730 */
<> 144:ef7eb2e8f9f7 731 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
<> 144:ef7eb2e8f9f7 732 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
<> 157:ff67d9f36b67 733 }while(0U)
<> 144:ef7eb2e8f9f7 734 /**
<> 144:ef7eb2e8f9f7 735 * @}
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 #if defined(SYSCFG_CFGR2_PVD_LOCK)
<> 144:ef7eb2e8f9f7 740 /** @defgroup PVD_Lock_Enable PVD Lock
<> 144:ef7eb2e8f9f7 741 * @{
<> 144:ef7eb2e8f9f7 742 */
<> 144:ef7eb2e8f9f7 743 /** @brief SYSCFG Break PVD lock
<> 144:ef7eb2e8f9f7 744 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
<> 144:ef7eb2e8f9f7 745 * @note The selected configuration is locked and can be unlocked by system reset
<> 144:ef7eb2e8f9f7 746 */
<> 144:ef7eb2e8f9f7 747 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
<> 144:ef7eb2e8f9f7 748 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
<> 157:ff67d9f36b67 749 }while(0U)
<> 144:ef7eb2e8f9f7 750 /**
<> 144:ef7eb2e8f9f7 751 * @}
<> 144:ef7eb2e8f9f7 752 */
<> 144:ef7eb2e8f9f7 753 #endif /* SYSCFG_CFGR2_PVD_LOCK */
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<> 144:ef7eb2e8f9f7 756 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
<> 144:ef7eb2e8f9f7 757 * @{
<> 144:ef7eb2e8f9f7 758 */
<> 144:ef7eb2e8f9f7 759 /** @brief SYSCFG Break SRAM PARITY lock
<> 144:ef7eb2e8f9f7 760 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
<> 144:ef7eb2e8f9f7 761 * @note The selected configuration is locked and can be unlocked by system reset
<> 144:ef7eb2e8f9f7 762 */
<> 144:ef7eb2e8f9f7 763 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
<> 144:ef7eb2e8f9f7 764 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
<> 157:ff67d9f36b67 765 }while(0U)
<> 144:ef7eb2e8f9f7 766 /**
<> 144:ef7eb2e8f9f7 767 * @}
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
<> 144:ef7eb2e8f9f7 772 * @{
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
<> 144:ef7eb2e8f9f7 775 /** @brief Trigger remapping enable/disable macros
<> 144:ef7eb2e8f9f7 776 * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
<> 144:ef7eb2e8f9f7 777 */
<> 144:ef7eb2e8f9f7 778 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
<> 144:ef7eb2e8f9f7 779 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
<> 144:ef7eb2e8f9f7 780 (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
<> 144:ef7eb2e8f9f7 781 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
<> 157:ff67d9f36b67 782 }while(0U)
<> 144:ef7eb2e8f9f7 783 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
<> 144:ef7eb2e8f9f7 784 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
<> 144:ef7eb2e8f9f7 785 (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
<> 144:ef7eb2e8f9f7 786 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
<> 157:ff67d9f36b67 787 }while(0U)
<> 144:ef7eb2e8f9f7 788 #else
<> 144:ef7eb2e8f9f7 789 /** @brief Trigger remapping enable/disable macros
<> 144:ef7eb2e8f9f7 790 * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
<> 144:ef7eb2e8f9f7 791 */
<> 144:ef7eb2e8f9f7 792 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
<> 144:ef7eb2e8f9f7 793 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
<> 157:ff67d9f36b67 794 }while(0U)
<> 144:ef7eb2e8f9f7 795 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
<> 144:ef7eb2e8f9f7 796 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
<> 157:ff67d9f36b67 797 }while(0U)
<> 144:ef7eb2e8f9f7 798 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
<> 144:ef7eb2e8f9f7 799 /**
<> 144:ef7eb2e8f9f7 800 * @}
<> 144:ef7eb2e8f9f7 801 */
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
<> 144:ef7eb2e8f9f7 804 /** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
<> 144:ef7eb2e8f9f7 805 * @{
<> 144:ef7eb2e8f9f7 806 */
<> 144:ef7eb2e8f9f7 807 /** @brief ADC trigger remapping enable/disable macros
<> 144:ef7eb2e8f9f7 808 * @param __ADCTRIGGER_REMAP__: This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
<> 144:ef7eb2e8f9f7 809 */
<> 144:ef7eb2e8f9f7 810 #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
<> 144:ef7eb2e8f9f7 811 (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
<> 157:ff67d9f36b67 812 }while(0U)
<> 144:ef7eb2e8f9f7 813 #define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
<> 144:ef7eb2e8f9f7 814 (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
<> 157:ff67d9f36b67 815 }while(0U)
<> 144:ef7eb2e8f9f7 816 /**
<> 144:ef7eb2e8f9f7 817 * @}
<> 144:ef7eb2e8f9f7 818 */
<> 144:ef7eb2e8f9f7 819 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
<> 144:ef7eb2e8f9f7 822 /** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
<> 144:ef7eb2e8f9f7 823 * @{
<> 144:ef7eb2e8f9f7 824 */
<> 144:ef7eb2e8f9f7 825 /**
<> 144:ef7eb2e8f9f7 826 * @brief Parity check on RAM disable macro
<> 144:ef7eb2e8f9f7 827 * @note Disabling the parity check on RAM locks the configuration bit.
<> 144:ef7eb2e8f9f7 828 * To re-enable the parity check on RAM perform a system reset.
<> 144:ef7eb2e8f9f7 829 */
<> 157:ff67d9f36b67 830 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U)
<> 144:ef7eb2e8f9f7 831 /**
<> 144:ef7eb2e8f9f7 832 * @}
<> 144:ef7eb2e8f9f7 833 */
<> 144:ef7eb2e8f9f7 834 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 #if defined(SYSCFG_RCR_PAGE0)
<> 144:ef7eb2e8f9f7 837 /** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
<> 144:ef7eb2e8f9f7 838 * @{
<> 144:ef7eb2e8f9f7 839 */
<> 144:ef7eb2e8f9f7 840 /** @brief CCM RAM page write protection enable macro
<> 144:ef7eb2e8f9f7 841 * @param __PAGE_WP__: This parameter can be a value of @ref HAL_Page_Write_Protection
<> 144:ef7eb2e8f9f7 842 * @note write protection can only be disabled by a system reset
<> 144:ef7eb2e8f9f7 843 */
<> 144:ef7eb2e8f9f7 844 #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
<> 144:ef7eb2e8f9f7 845 SYSCFG->RCR |= (__PAGE_WP__); \
<> 157:ff67d9f36b67 846 }while(0U)
<> 144:ef7eb2e8f9f7 847 /**
<> 144:ef7eb2e8f9f7 848 * @}
<> 144:ef7eb2e8f9f7 849 */
<> 144:ef7eb2e8f9f7 850 #endif /* SYSCFG_RCR_PAGE0 */
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /**
<> 144:ef7eb2e8f9f7 853 * @}
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 856 /** @addtogroup HAL_Exported_Functions HAL Exported Functions
<> 144:ef7eb2e8f9f7 857 * @{
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
<> 144:ef7eb2e8f9f7 861 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 862 * @{
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 /* Initialization and de-initialization functions ******************************/
<> 144:ef7eb2e8f9f7 865 HAL_StatusTypeDef HAL_Init(void);
<> 144:ef7eb2e8f9f7 866 HAL_StatusTypeDef HAL_DeInit(void);
<> 144:ef7eb2e8f9f7 867 void HAL_MspInit(void);
<> 144:ef7eb2e8f9f7 868 void HAL_MspDeInit(void);
<> 144:ef7eb2e8f9f7 869 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
<> 144:ef7eb2e8f9f7 870 /**
<> 144:ef7eb2e8f9f7 871 * @}
<> 144:ef7eb2e8f9f7 872 */
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
<> 144:ef7eb2e8f9f7 875 * @brief HAL Control functions
<> 144:ef7eb2e8f9f7 876 * @{
<> 144:ef7eb2e8f9f7 877 */
<> 144:ef7eb2e8f9f7 878 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 879 void HAL_IncTick(void);
<> 144:ef7eb2e8f9f7 880 void HAL_Delay(__IO uint32_t Delay);
<> 144:ef7eb2e8f9f7 881 void HAL_SuspendTick(void);
<> 144:ef7eb2e8f9f7 882 void HAL_ResumeTick(void);
<> 144:ef7eb2e8f9f7 883 uint32_t HAL_GetTick(void);
<> 144:ef7eb2e8f9f7 884 uint32_t HAL_GetHalVersion(void);
<> 144:ef7eb2e8f9f7 885 uint32_t HAL_GetREVID(void);
<> 144:ef7eb2e8f9f7 886 uint32_t HAL_GetDEVID(void);
<> 144:ef7eb2e8f9f7 887 void HAL_DBGMCU_EnableDBGSleepMode(void);
<> 144:ef7eb2e8f9f7 888 void HAL_DBGMCU_DisableDBGSleepMode(void);
<> 144:ef7eb2e8f9f7 889 void HAL_DBGMCU_EnableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 890 void HAL_DBGMCU_DisableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 891 void HAL_DBGMCU_EnableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 892 void HAL_DBGMCU_DisableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 893 /**
<> 144:ef7eb2e8f9f7 894 * @}
<> 144:ef7eb2e8f9f7 895 */
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @}
<> 144:ef7eb2e8f9f7 899 */
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /**
<> 144:ef7eb2e8f9f7 902 * @}
<> 144:ef7eb2e8f9f7 903 */
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /**
<> 144:ef7eb2e8f9f7 906 * @}
<> 144:ef7eb2e8f9f7 907 */
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 910 }
<> 144:ef7eb2e8f9f7 911 #endif
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 #endif /* __STM32F3xx_HAL_H */
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/