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targets/TARGET_Maxim/TARGET_MAX32630/device/aes_regs.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-10-10 16:51:05 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24655 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 *************************************************************************** */
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 43 #ifndef _MXC_AES_REGS_H_
<> 157:ff67d9f36b67 44 #define _MXC_AES_REGS_H_
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 #ifdef __cplusplus
<> 157:ff67d9f36b67 47 extern "C" {
<> 157:ff67d9f36b67 48 #endif
<> 157:ff67d9f36b67 49
<> 157:ff67d9f36b67 50 /* **** Includes **** */
<> 157:ff67d9f36b67 51 #include <stdint.h>
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 /// @cond
<> 157:ff67d9f36b67 54 /*
<> 157:ff67d9f36b67 55 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 56 */
<> 157:ff67d9f36b67 57 #ifndef __IO
<> 157:ff67d9f36b67 58 #define __IO volatile
<> 157:ff67d9f36b67 59 #endif
<> 157:ff67d9f36b67 60 #ifndef __I
<> 157:ff67d9f36b67 61 #define __I volatile const
<> 157:ff67d9f36b67 62 #endif
<> 157:ff67d9f36b67 63 #ifndef __O
<> 157:ff67d9f36b67 64 #define __O volatile
<> 157:ff67d9f36b67 65 #endif
<> 157:ff67d9f36b67 66 #ifndef __RO
<> 157:ff67d9f36b67 67 #define __RO volatile const
<> 157:ff67d9f36b67 68 #endif
<> 157:ff67d9f36b67 69 /// @endcond
<> 157:ff67d9f36b67 70
<> 157:ff67d9f36b67 71 /* **** Definitions **** */
<> 157:ff67d9f36b67 72
<> 157:ff67d9f36b67 73 /**
<> 157:ff67d9f36b67 74 * @ingroup aes
<> 157:ff67d9f36b67 75 * @defgroup aes_registers Registers
<> 157:ff67d9f36b67 76 * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
<> 157:ff67d9f36b67 77 * @{
<> 157:ff67d9f36b67 78 */
<> 157:ff67d9f36b67 79
<> 157:ff67d9f36b67 80 /**
<> 157:ff67d9f36b67 81 * Structure type to access the AES Registers.
<> 157:ff67d9f36b67 82 */
<> 157:ff67d9f36b67 83 typedef struct {
<> 157:ff67d9f36b67 84 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> AES_CTRL Register */
<> 157:ff67d9f36b67 85 __RO uint32_t rsv004; /**< <tt>\b 0x0004:</tt> RESERVED */
<> 157:ff67d9f36b67 86 __IO uint32_t erase_all; /**< <tt>\b 0x0008:</tt> AES_ERASE_ALL Register - A write to this register will trigger AES Memory Erase */
<> 157:ff67d9f36b67 87 } mxc_aes_regs_t;
<> 157:ff67d9f36b67 88
<> 157:ff67d9f36b67 89 /**
<> 157:ff67d9f36b67 90 * Structure type to access the AES Memory Registers.
<> 157:ff67d9f36b67 91 */
<> 157:ff67d9f36b67 92 typedef struct {
<> 157:ff67d9f36b67 93 __IO uint32_t inp[4]; /**< <tt>\b 0x0000-0x000C:</tt> AES Input (128 bits) */
<> 157:ff67d9f36b67 94 __IO uint32_t key[8]; /**< <tt>\b 0x0010-0x002C:</tt> AES Symmetric Key (up to 256 bits) */
<> 157:ff67d9f36b67 95 __IO uint32_t out[4]; /**< <tt>\b 0x0030-0x003C:</tt> AES Output Data (128 bits) */
<> 157:ff67d9f36b67 96 __IO uint32_t expkey[8]; /**< <tt>\b 0x0040-0x005C:</tt> AES Expanded Key Data (256 bits) */
<> 157:ff67d9f36b67 97 } mxc_aes_mem_regs_t;
<> 157:ff67d9f36b67 98 /**@} end of group aes_registers */
<> 157:ff67d9f36b67 99
<> 157:ff67d9f36b67 100 /**
<> 157:ff67d9f36b67 101 * @ingroup aes_registers
<> 157:ff67d9f36b67 102 * @defgroup AES_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 103 * @brief AES Register Offsets from the AES Base Peripheral Address.
<> 157:ff67d9f36b67 104 * @{
<> 157:ff67d9f36b67 105 */
<> 157:ff67d9f36b67 106 /**
<> 157:ff67d9f36b67 107 * AES Register offsets from the AES base peripheral address.
<> 157:ff67d9f36b67 108 */
<> 157:ff67d9f36b67 109 #define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 110 #define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0008</tt> */
<> 157:ff67d9f36b67 111 #define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 112 #define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0004</tt> */
<> 157:ff67d9f36b67 113 #define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0008</tt> */
<> 157:ff67d9f36b67 114 #define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x000C</tt> */
<> 157:ff67d9f36b67 115 #define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0010</tt> */
<> 157:ff67d9f36b67 116 #define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0014</tt> */
<> 157:ff67d9f36b67 117 #define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0018</tt> */
<> 157:ff67d9f36b67 118 #define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x001C</tt> */
<> 157:ff67d9f36b67 119 #define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0020</tt> */
<> 157:ff67d9f36b67 120 #define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0024</tt> */
<> 157:ff67d9f36b67 121 #define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0028</tt> */
<> 157:ff67d9f36b67 122 #define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x002C</tt> */
<> 157:ff67d9f36b67 123 #define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0030</tt> */
<> 157:ff67d9f36b67 124 #define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0034</tt> */
<> 157:ff67d9f36b67 125 #define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0038</tt> */
<> 157:ff67d9f36b67 126 #define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x003C</tt> */
<> 157:ff67d9f36b67 127 #define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0040</tt> */
<> 157:ff67d9f36b67 128 #define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0044</tt> */
<> 157:ff67d9f36b67 129 #define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0048</tt> */
<> 157:ff67d9f36b67 130 #define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x004C</tt> */
<> 157:ff67d9f36b67 131 #define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0050</tt> */
<> 157:ff67d9f36b67 132 #define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0054</tt> */
<> 157:ff67d9f36b67 133 #define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0058</tt> */
<> 157:ff67d9f36b67 134 #define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x005C</tt> */
<> 157:ff67d9f36b67 135 /**@} end of group AES_Register_Offsets */
<> 157:ff67d9f36b67 136
<> 157:ff67d9f36b67 137 /**
<> 157:ff67d9f36b67 138 * @ingroup aes_registers
<> 157:ff67d9f36b67 139 * @defgroup AES_CTRL_Register AES_CTRL
<> 157:ff67d9f36b67 140 * @brief Field Positions and Bit Masks for the AES_CTRL register
<> 157:ff67d9f36b67 141 * @{
<> 157:ff67d9f36b67 142 */
<> 157:ff67d9f36b67 143 #define MXC_F_AES_CTRL_START_POS 0 /**< AES_CTRL START Position */
<> 157:ff67d9f36b67 144 #define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) /**< AES_CTRL START Mask */
<> 157:ff67d9f36b67 145 #define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 /**< AES_CTRL CRYPT_MODE Position */
<> 157:ff67d9f36b67 146 #define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL CRYPT_MODE Mask */
<> 157:ff67d9f36b67 147 #define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 /**< AES_CTRL EXP_KEY_MODE Position */
<> 157:ff67d9f36b67 148 #define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL EXP_KEY_MODE Mask */
<> 157:ff67d9f36b67 149 #define MXC_F_AES_CTRL_KEY_SIZE_POS 3 /**< AES_CTRL KEY_SIZE Position */
<> 157:ff67d9f36b67 150 #define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL KEY_SIZE Mask */
<> 157:ff67d9f36b67 151 #define MXC_F_AES_CTRL_INTEN_POS 5 /**< AES_CTRL INTEN Position */
<> 157:ff67d9f36b67 152 #define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) /**< AES_CTRL INTEN Mask */
<> 157:ff67d9f36b67 153 #define MXC_F_AES_CTRL_INTFL_POS 6 /**< AES_CTRL INTFL Position */
<> 157:ff67d9f36b67 154 #define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) /**< AES_CTRL INTFL Mask */
<> 157:ff67d9f36b67 155 #define MXC_F_AES_CTRL_LOAD_HW_KEY_POS 7 /**< AES_CTRL LOAD_HW_KEY Position */
<> 157:ff67d9f36b67 156 #define MXC_F_AES_CTRL_LOAD_HW_KEY ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_LOAD_HW_KEY_POS)) /**< AES_CTRL LOAD_HW_KEY Mask */
<> 157:ff67d9f36b67 157 /**@} end of aes_registers group */
<> 157:ff67d9f36b67 158
<> 157:ff67d9f36b67 159 /*
<> 157:ff67d9f36b67 160 Field values and shifted values for module AES.
<> 157:ff67d9f36b67 161 */
<> 157:ff67d9f36b67 162 ///@cond
<> 157:ff67d9f36b67 163 #define MXC_V_AES_CTRL_ENCRYPT_MODE ((uint32_t)(0x00000000UL)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode value */
<> 157:ff67d9f36b67 164 #define MXC_V_AES_CTRL_DECRYPT_MODE ((uint32_t)(0x00000001UL)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode value */
<> 157:ff67d9f36b67 165
<> 157:ff67d9f36b67 166 #define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode Shifted Value*/
<> 157:ff67d9f36b67 167 #define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode Shifted Value*/
<> 157:ff67d9f36b67 168
<> 157:ff67d9f36b67 169 #define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(0x00000000UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key value */
<> 157:ff67d9f36b67 170 #define MXC_V_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(0x00000001UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key value */
<> 157:ff67d9f36b67 171
<> 157:ff67d9f36b67 172 #define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key Shifted Value*/
<> 157:ff67d9f36b67 173 #define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key Shifted Value*/
<> 157:ff67d9f36b67 174
<> 157:ff67d9f36b67 175 #define MXC_V_AES_CTRL_KEY_SIZE_128 ((uint32_t)(0x00000000UL)) /**< AES_CTRL: KEY_SIZE 128-bit setting value */
<> 157:ff67d9f36b67 176 #define MXC_V_AES_CTRL_KEY_SIZE_192 ((uint32_t)(0x00000001UL)) /**< AES_CTRL: KEY_SIZE 192-bit setting value */
<> 157:ff67d9f36b67 177 #define MXC_V_AES_CTRL_KEY_SIZE_256 ((uint32_t)(0x00000002UL)) /**< AES_CTRL: KEY_SIZE 256-bit setting value */
<> 157:ff67d9f36b67 178
<> 157:ff67d9f36b67 179 #define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 128-bit Shifted Value */
<> 157:ff67d9f36b67 180 #define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 192-bit Shifted Value */
<> 157:ff67d9f36b67 181 #define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 256-bit Shifted Value */
<> 157:ff67d9f36b67 182 ///@endcond
<> 157:ff67d9f36b67 183 #ifdef __cplusplus
<> 157:ff67d9f36b67 184 }
<> 157:ff67d9f36b67 185 #endif
<> 157:ff67d9f36b67 186
<> 157:ff67d9f36b67 187 #endif /* _MXC_AES_REGS_H_ */
<> 157:ff67d9f36b67 188