mbed-dev | Mbed

anyThing Connected Team » Code » mbed-dev

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_tim.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_ll_tim.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.1
<>	144:ef7eb2e8f9f7	6	* @date 31-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of TIM LL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32L4xx_LL_TIM_H
<>	144:ef7eb2e8f9f7	40	#define __STM32L4xx_LL_TIM_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32l4xx.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32L4xx_LL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	#if defined (TIM1) \|\| defined (TIM8) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	/** @defgroup TIM_LL TIM
<>	144:ef7eb2e8f9f7	56	* @{
<>	144:ef7eb2e8f9f7	57	*/
<>	144:ef7eb2e8f9f7	58
<>	144:ef7eb2e8f9f7	59	/* Private types -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	60	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	61	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
<>	144:ef7eb2e8f9f7	62	* @{
<>	144:ef7eb2e8f9f7	63	*/
<>	144:ef7eb2e8f9f7	64	static const uint8_t OFFSET_TAB_CCMRx[] =
<>	144:ef7eb2e8f9f7	65	{
<>	144:ef7eb2e8f9f7	66	0x00U, /* 0: TIMx_CH1 */
<>	144:ef7eb2e8f9f7	67	0x00U, /* 1: TIMx_CH1N */
<>	144:ef7eb2e8f9f7	68	0x00U, /* 2: TIMx_CH2 */
<>	144:ef7eb2e8f9f7	69	0x00U, /* 3: TIMx_CH2N */
<>	144:ef7eb2e8f9f7	70	0x04U, /* 4: TIMx_CH3 */
<>	144:ef7eb2e8f9f7	71	0x04U, /* 5: TIMx_CH3N */
<>	144:ef7eb2e8f9f7	72	0x04U, /* 6: TIMx_CH4 */
<>	144:ef7eb2e8f9f7	73	0x3CU, /* 7: TIMx_CH5 */
<>	144:ef7eb2e8f9f7	74	0x3CU /* 8: TIMx_CH6 */
<>	144:ef7eb2e8f9f7	75	};
<>	144:ef7eb2e8f9f7	76
<>	144:ef7eb2e8f9f7	77	static const uint8_t SHIFT_TAB_OCxx[] =
<>	144:ef7eb2e8f9f7	78	{
<>	144:ef7eb2e8f9f7	79	0U, /* 0: OC1M, OC1FE, OC1PE */
<>	144:ef7eb2e8f9f7	80	0U, /* 1: - NA */
<>	144:ef7eb2e8f9f7	81	8U, /* 2: OC2M, OC2FE, OC2PE */
<>	144:ef7eb2e8f9f7	82	0U, /* 3: - NA */
<>	144:ef7eb2e8f9f7	83	0U, /* 4: OC3M, OC3FE, OC3PE */
<>	144:ef7eb2e8f9f7	84	0U, /* 5: - NA */
<>	144:ef7eb2e8f9f7	85	8U, /* 6: OC4M, OC4FE, OC4PE */
<>	144:ef7eb2e8f9f7	86	0U, /* 7: OC5M, OC5FE, OC5PE */
<>	144:ef7eb2e8f9f7	87	8U /* 8: OC6M, OC6FE, OC6PE */
<>	144:ef7eb2e8f9f7	88	};
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	static const uint8_t SHIFT_TAB_ICxx[] =
<>	144:ef7eb2e8f9f7	91	{
<>	144:ef7eb2e8f9f7	92	0U, /* 0: CC1S, IC1PSC, IC1F */
<>	144:ef7eb2e8f9f7	93	0U, /* 1: - NA */
<>	144:ef7eb2e8f9f7	94	8U, /* 2: CC2S, IC2PSC, IC2F */
<>	144:ef7eb2e8f9f7	95	0U, /* 3: - NA */
<>	144:ef7eb2e8f9f7	96	0U, /* 4: CC3S, IC3PSC, IC3F */
<>	144:ef7eb2e8f9f7	97	0U, /* 5: - NA */
<>	144:ef7eb2e8f9f7	98	8U, /* 6: CC4S, IC4PSC, IC4F */
<>	144:ef7eb2e8f9f7	99	0U, /* 7: - NA */
<>	144:ef7eb2e8f9f7	100	0U /* 8: - NA */
<>	144:ef7eb2e8f9f7	101	};
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	static const uint8_t SHIFT_TAB_CCxP[] =
<>	144:ef7eb2e8f9f7	104	{
<>	144:ef7eb2e8f9f7	105	0U, /* 0: CC1P */
<>	144:ef7eb2e8f9f7	106	2U, /* 1: CC1NP */
<>	144:ef7eb2e8f9f7	107	4U, /* 2: CC2P */
<>	144:ef7eb2e8f9f7	108	6U, /* 3: CC2NP */
<>	144:ef7eb2e8f9f7	109	8U, /* 4: CC3P */
<>	144:ef7eb2e8f9f7	110	10U, /* 5: CC3NP */
<>	144:ef7eb2e8f9f7	111	12U, /* 6: CC4P */
<>	144:ef7eb2e8f9f7	112	16U, /* 7: CC5P */
<>	144:ef7eb2e8f9f7	113	20U /* 8: CC6P */
<>	144:ef7eb2e8f9f7	114	};
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	static const uint8_t SHIFT_TAB_OISx[] =
<>	144:ef7eb2e8f9f7	117	{
<>	144:ef7eb2e8f9f7	118	0U, /* 0: OIS1 */
<>	144:ef7eb2e8f9f7	119	1U, /* 1: OIS1N */
<>	144:ef7eb2e8f9f7	120	2U, /* 2: OIS2 */
<>	144:ef7eb2e8f9f7	121	3U, /* 3: OIS2N */
<>	144:ef7eb2e8f9f7	122	4U, /* 4: OIS3 */
<>	144:ef7eb2e8f9f7	123	5U, /* 5: OIS3N */
<>	144:ef7eb2e8f9f7	124	6U, /* 6: OIS4 */
<>	144:ef7eb2e8f9f7	125	8U, /* 7: OIS5 */
<>	144:ef7eb2e8f9f7	126	10U /* 8: OIS6 */
<>	144:ef7eb2e8f9f7	127	};
<>	144:ef7eb2e8f9f7	128	/**
<>	144:ef7eb2e8f9f7	129	* @}
<>	144:ef7eb2e8f9f7	130	*/
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132
<>	144:ef7eb2e8f9f7	133	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	134	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
<>	144:ef7eb2e8f9f7	135	* @{
<>	144:ef7eb2e8f9f7	136	*/
<>	144:ef7eb2e8f9f7	137	/** @defgroup TIM_LL_POSITION_VAL Bit Position Value
<>	144:ef7eb2e8f9f7	138	* @brief Position of the bit in the register.
<>	144:ef7eb2e8f9f7	139	* @{
<>	144:ef7eb2e8f9f7	140	*/
<>	144:ef7eb2e8f9f7	141	#define TIM_POSITION_ICPSC POSITION_VAL(TIM_CCMR1_IC1PSC)
<>	144:ef7eb2e8f9f7	142	/**
<>	144:ef7eb2e8f9f7	143	* @}
<>	144:ef7eb2e8f9f7	144	*/
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	/* Generic bit definitions for TIMx_OR2 register */
<>	144:ef7eb2e8f9f7	147	#define TIMx_OR2_BKINE TIM1_OR2_BKINE /!< BRK BKIN input enable /
<>	144:ef7eb2e8f9f7	148	#define TIMx_OR2_BKCOMP1E TIM1_OR2_BKCMP1E /!< BRK COMP1 enable /
<>	144:ef7eb2e8f9f7	149	#define TIMx_OR2_BKCOMP2E TIM1_OR2_BKCMP2E /!< BRK COMP2 enable /
<>	144:ef7eb2e8f9f7	150	#if defined(DFSDM1_Channel0)
<>	144:ef7eb2e8f9f7	151	#define TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E /!< BRK DFSDM1_BREAK[0] enable /
<>	144:ef7eb2e8f9f7	152	#endif /* DFSDM1_Channel0 */
<>	144:ef7eb2e8f9f7	153	#define TIMx_OR2_BKINP TIM1_OR2_BKINP /!< BRK BKIN input polarity /
<>	144:ef7eb2e8f9f7	154	#define TIMx_OR2_BKCOMP1P TIM1_OR2_BKCMP1P /!< BRK COMP1 input polarity /
<>	144:ef7eb2e8f9f7	155	#define TIMx_OR2_BKCOMP2P TIM1_OR2_BKCMP2P /!< BRK COMP2 input polarity /
<>	144:ef7eb2e8f9f7	156	#define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /!< TIMx ETR source selection /
<>	144:ef7eb2e8f9f7	157
<>	144:ef7eb2e8f9f7	158	/* Generic bit definitions for TIMx_OR3 register */
<>	144:ef7eb2e8f9f7	159	#define TIMx_OR3_BK2INE TIM1_OR3_BK2INE /!< BRK2 BKIN2 input enable /
<>	144:ef7eb2e8f9f7	160	#define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E /!< BRK2 COMP1 enable /
<>	144:ef7eb2e8f9f7	161	#define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E /!< BRK2 COMP2 enable /
<>	144:ef7eb2e8f9f7	162	#if defined(DFSDM1_Channel0)
<>	144:ef7eb2e8f9f7	163	#define TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E /!< BRK2 DFSDM1_BREAK[1] enable /
<>	144:ef7eb2e8f9f7	164	#endif /* DFSDM1_Channel0 */
<>	144:ef7eb2e8f9f7	165	#define TIMx_OR3_BK2INP TIM1_OR3_BK2INP /!< BRK2 BKIN2 input polarity /
<>	144:ef7eb2e8f9f7	166	#define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P /!< BRK2 COMP1 input polarity /
<>	144:ef7eb2e8f9f7	167	#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /!< BRK2 COMP2 input polarity /
<>	144:ef7eb2e8f9f7	168
<>	144:ef7eb2e8f9f7	169	/* Remap mask definitions */
<>	144:ef7eb2e8f9f7	170	#define TIMx_OR1_RMP_SHIFT ((uint32_t)16U)
<>	144:ef7eb2e8f9f7	171	#define TIMx_OR1_RMP_MASK ((uint32_t)0x0000FFFFU)
<>	144:ef7eb2e8f9f7	172	#if defined(ADC3)
<>	144:ef7eb2e8f9f7	173	#define TIM1_OR1_RMP_MASK ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_ETR_ADC3_RMP \| TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
<>	144:ef7eb2e8f9f7	174	#else
<>	144:ef7eb2e8f9f7	175	#define TIM1_OR1_RMP_MASK ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
<>	144:ef7eb2e8f9f7	176	#endif /* ADC3 */
<>	144:ef7eb2e8f9f7	177	#define TIM2_OR1_RMP_MASK ((uint32_t)((TIM2_OR1_TI4_RMP \| TIM2_OR1_ETR1_RMP \| TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT))
<>	144:ef7eb2e8f9f7	178	#define TIM3_OR1_RMP_MASK ((uint32_t)(TIM3_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
<>	144:ef7eb2e8f9f7	179	#define TIM8_OR1_RMP_MASK ((uint32_t)((TIM8_OR1_ETR_ADC2_RMP \| TIM8_OR1_ETR_ADC3_RMP \| TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
<>	144:ef7eb2e8f9f7	180	#define TIM15_OR1_RMP_MASK ((uint32_t)((TIM15_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
<>	144:ef7eb2e8f9f7	181	#define TIM16_OR1_RMP_MASK ((uint32_t)((TIM16_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
<>	144:ef7eb2e8f9f7	182	#define TIM17_OR1_RMP_MASK ((uint32_t)((TIM17_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
<>	144:ef7eb2e8f9f7	183
<>	144:ef7eb2e8f9f7	184	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
<>	144:ef7eb2e8f9f7	185	#define DT_DELAY_1 ((uint8_t)0x7FU)
<>	144:ef7eb2e8f9f7	186	#define DT_DELAY_2 ((uint8_t)0x3FU)
<>	144:ef7eb2e8f9f7	187	#define DT_DELAY_3 ((uint8_t)0x1FU)
<>	144:ef7eb2e8f9f7	188	#define DT_DELAY_4 ((uint8_t)0x1FU)
<>	144:ef7eb2e8f9f7	189
<>	144:ef7eb2e8f9f7	190	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
<>	144:ef7eb2e8f9f7	191	#define DT_RANGE_1 ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	192	#define DT_RANGE_2 ((uint8_t)0x80U)
<>	144:ef7eb2e8f9f7	193	#define DT_RANGE_3 ((uint8_t)0xC0U)
<>	144:ef7eb2e8f9f7	194	#define DT_RANGE_4 ((uint8_t)0xE0U)
<>	144:ef7eb2e8f9f7	195
<>	144:ef7eb2e8f9f7	196	/** Legacy definitions for compatibility purpose
<>	144:ef7eb2e8f9f7	197	@cond 0
<>	144:ef7eb2e8f9f7	198	*/
<>	144:ef7eb2e8f9f7	199	#if defined(DFSDM1_Channel0)
<>	144:ef7eb2e8f9f7	200	#define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E
<>	144:ef7eb2e8f9f7	201	#define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E
<>	144:ef7eb2e8f9f7	202	#endif /* DFSDM1_Channel0 */
<>	144:ef7eb2e8f9f7	203	/**
<>	144:ef7eb2e8f9f7	204	@endcond
<>	144:ef7eb2e8f9f7	205	*/
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	/**
<>	144:ef7eb2e8f9f7	208	* @}
<>	144:ef7eb2e8f9f7	209	*/
<>	144:ef7eb2e8f9f7	210
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	213	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
<>	144:ef7eb2e8f9f7	214	* @{
<>	144:ef7eb2e8f9f7	215	*/
<>	144:ef7eb2e8f9f7	216	/** @brief Convert channel id into channel index.
<>	144:ef7eb2e8f9f7	217	* @param __CHANNEL__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	218	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	219	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	144:ef7eb2e8f9f7	220	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	221	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	144:ef7eb2e8f9f7	222	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	223	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	144:ef7eb2e8f9f7	224	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	225	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	226	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	227	* @retval none
<>	144:ef7eb2e8f9f7	228	*/
<>	144:ef7eb2e8f9f7	229	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
<>	144:ef7eb2e8f9f7	230	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
<>	144:ef7eb2e8f9f7	231	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
<>	144:ef7eb2e8f9f7	232	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
<>	144:ef7eb2e8f9f7	233	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
<>	144:ef7eb2e8f9f7	234	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
<>	144:ef7eb2e8f9f7	235	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
<>	144:ef7eb2e8f9f7	236	((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
<>	144:ef7eb2e8f9f7	237	((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	/** @brief Calculate the deadtime sampling period(in ps).
<>	144:ef7eb2e8f9f7	240	* @param __TIMCLK__ timer input clock frequency (in Hz).
<>	144:ef7eb2e8f9f7	241	* @param __CKD__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	242	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	144:ef7eb2e8f9f7	243	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	144:ef7eb2e8f9f7	244	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	144:ef7eb2e8f9f7	245	* @retval none
<>	144:ef7eb2e8f9f7	246	*/
<>	144:ef7eb2e8f9f7	247	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
<>	144:ef7eb2e8f9f7	248	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
<>	144:ef7eb2e8f9f7	249	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
<>	144:ef7eb2e8f9f7	250	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
<>	144:ef7eb2e8f9f7	251	/**
<>	144:ef7eb2e8f9f7	252	* @}
<>	144:ef7eb2e8f9f7	253	*/
<>	144:ef7eb2e8f9f7	254
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	257	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	258	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
<>	144:ef7eb2e8f9f7	259	* @{
<>	144:ef7eb2e8f9f7	260	*/
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	/**
<>	144:ef7eb2e8f9f7	263	* @brief TIM Time Base configuration structure definition.
<>	144:ef7eb2e8f9f7	264	*/
<>	144:ef7eb2e8f9f7	265	typedef struct
<>	144:ef7eb2e8f9f7	266	{
<>	144:ef7eb2e8f9f7	267	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	144:ef7eb2e8f9f7	268	This parameter can be a number between 0x0000 and 0xFFFF.
<>	144:ef7eb2e8f9f7	269
<>	144:ef7eb2e8f9f7	270	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	uint32_t CounterMode; /*!< Specifies the counter mode.
<>	144:ef7eb2e8f9f7	273	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
<>	144:ef7eb2e8f9f7	274
<>	144:ef7eb2e8f9f7	275	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
<>	144:ef7eb2e8f9f7	278	Auto-Reload Register at the next update event.
<>	144:ef7eb2e8f9f7	279	This parameter must be a number between 0x0000 and 0xFFFF.
<>	144:ef7eb2e8f9f7	280	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
<>	144:ef7eb2e8f9f7	283
<>	144:ef7eb2e8f9f7	284	uint32_t ClockDivision; /*!< Specifies the clock division.
<>	144:ef7eb2e8f9f7	285	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
<>	144:ef7eb2e8f9f7	286
<>	144:ef7eb2e8f9f7	287	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
<>	144:ef7eb2e8f9f7	290	reaches zero, an update event is generated and counting restarts
<>	144:ef7eb2e8f9f7	291	from the RCR value (N).
<>	144:ef7eb2e8f9f7	292	This means in PWM mode that (N+1) corresponds to:
<>	144:ef7eb2e8f9f7	293	- the number of PWM periods in edge-aligned mode
<>	144:ef7eb2e8f9f7	294	- the number of half PWM period in center-aligned mode
<>	144:ef7eb2e8f9f7	295	This parameter must be a number between 0x00 and 0xFF.
<>	144:ef7eb2e8f9f7	296
<>	144:ef7eb2e8f9f7	297	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
<>	144:ef7eb2e8f9f7	298	} LL_TIM_InitTypeDef;
<>	144:ef7eb2e8f9f7	299
<>	144:ef7eb2e8f9f7	300	/**
<>	144:ef7eb2e8f9f7	301	* @brief TIM Output Compare configuration structure definition.
<>	144:ef7eb2e8f9f7	302	*/
<>	144:ef7eb2e8f9f7	303	typedef struct
<>	144:ef7eb2e8f9f7	304	{
<>	144:ef7eb2e8f9f7	305	uint32_t OCMode; /*!< Specifies the output mode.
<>	144:ef7eb2e8f9f7	306	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
<>	144:ef7eb2e8f9f7	311	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	144:ef7eb2e8f9f7	312
<>	144:ef7eb2e8f9f7	313	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	144:ef7eb2e8f9f7	314
<>	144:ef7eb2e8f9f7	315	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
<>	144:ef7eb2e8f9f7	316	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
<>	144:ef7eb2e8f9f7	321	This parameter can be a number between 0x0000 and 0xFFFF.
<>	144:ef7eb2e8f9f7	322
<>	144:ef7eb2e8f9f7	323	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	326	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	144:ef7eb2e8f9f7	329
<>	144:ef7eb2e8f9f7	330	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	144:ef7eb2e8f9f7	331	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	144:ef7eb2e8f9f7	334
<>	144:ef7eb2e8f9f7	335	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	144:ef7eb2e8f9f7	336	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
<>	144:ef7eb2e8f9f7	337
<>	144:ef7eb2e8f9f7	338	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
<>	144:ef7eb2e8f9f7	339
<>	144:ef7eb2e8f9f7	340	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	144:ef7eb2e8f9f7	341	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
<>	144:ef7eb2e8f9f7	342
<>	144:ef7eb2e8f9f7	343	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
<>	144:ef7eb2e8f9f7	344	} LL_TIM_OC_InitTypeDef;
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/**
<>	144:ef7eb2e8f9f7	347	* @brief TIM Input Capture configuration structure definition.
<>	144:ef7eb2e8f9f7	348	*/
<>	144:ef7eb2e8f9f7	349
<>	144:ef7eb2e8f9f7	350	typedef struct
<>	144:ef7eb2e8f9f7	351	{
<>	144:ef7eb2e8f9f7	352
<>	144:ef7eb2e8f9f7	353	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	354	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	144:ef7eb2e8f9f7	357
<>	144:ef7eb2e8f9f7	358	uint32_t ICActiveInput; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	359	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	144:ef7eb2e8f9f7	360
<>	144:ef7eb2e8f9f7	361	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	144:ef7eb2e8f9f7	362
<>	144:ef7eb2e8f9f7	363	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	364	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	144:ef7eb2e8f9f7	367
<>	144:ef7eb2e8f9f7	368	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	369	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	144:ef7eb2e8f9f7	370
<>	144:ef7eb2e8f9f7	371	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	144:ef7eb2e8f9f7	372	} LL_TIM_IC_InitTypeDef;
<>	144:ef7eb2e8f9f7	373
<>	144:ef7eb2e8f9f7	374
<>	144:ef7eb2e8f9f7	375	/**
<>	144:ef7eb2e8f9f7	376	* @brief TIM Encoder interface configuration structure definition.
<>	144:ef7eb2e8f9f7	377	*/
<>	144:ef7eb2e8f9f7	378	typedef struct
<>	144:ef7eb2e8f9f7	379	{
<>	144:ef7eb2e8f9f7	380	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
<>	144:ef7eb2e8f9f7	381	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
<>	144:ef7eb2e8f9f7	382
<>	144:ef7eb2e8f9f7	383	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	144:ef7eb2e8f9f7	386	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	144:ef7eb2e8f9f7	387
<>	144:ef7eb2e8f9f7	388	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
<>	144:ef7eb2e8f9f7	391	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	144:ef7eb2e8f9f7	392
<>	144:ef7eb2e8f9f7	393	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	144:ef7eb2e8f9f7	396	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	144:ef7eb2e8f9f7	401	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	144:ef7eb2e8f9f7	402
<>	144:ef7eb2e8f9f7	403	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	144:ef7eb2e8f9f7	404
<>	144:ef7eb2e8f9f7	405	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
<>	144:ef7eb2e8f9f7	406	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	144:ef7eb2e8f9f7	407
<>	144:ef7eb2e8f9f7	408	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	144:ef7eb2e8f9f7	409
<>	144:ef7eb2e8f9f7	410	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
<>	144:ef7eb2e8f9f7	411	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	144:ef7eb2e8f9f7	412
<>	144:ef7eb2e8f9f7	413	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	144:ef7eb2e8f9f7	414
<>	144:ef7eb2e8f9f7	415	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
<>	144:ef7eb2e8f9f7	416	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
<>	144:ef7eb2e8f9f7	421	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	144:ef7eb2e8f9f7	422
<>	144:ef7eb2e8f9f7	423	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	144:ef7eb2e8f9f7	424
<>	144:ef7eb2e8f9f7	425	} LL_TIM_ENCODER_InitTypeDef;
<>	144:ef7eb2e8f9f7	426
<>	144:ef7eb2e8f9f7	427	/**
<>	144:ef7eb2e8f9f7	428	* @brief TIM Hall sensor interface configuration structure definition.
<>	144:ef7eb2e8f9f7	429	*/
<>	144:ef7eb2e8f9f7	430	typedef struct
<>	144:ef7eb2e8f9f7	431	{
<>	144:ef7eb2e8f9f7	432
<>	144:ef7eb2e8f9f7	433	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	144:ef7eb2e8f9f7	434	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	144:ef7eb2e8f9f7	435
<>	144:ef7eb2e8f9f7	436	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	144:ef7eb2e8f9f7	439	Prescaler must be set to get a maximum counter period longer than the
<>	144:ef7eb2e8f9f7	440	time interval between 2 consecutive changes on the Hall inputs.
<>	144:ef7eb2e8f9f7	441	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	144:ef7eb2e8f9f7	442
<>	144:ef7eb2e8f9f7	443	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	144:ef7eb2e8f9f7	444
<>	144:ef7eb2e8f9f7	445	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	144:ef7eb2e8f9f7	446	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	144:ef7eb2e8f9f7	447
<>	144:ef7eb2e8f9f7	448	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
<>	144:ef7eb2e8f9f7	451	A positive pulse (TRGO event) is generated with a programmable delay every time
<>	144:ef7eb2e8f9f7	452	a change occurs on the Hall inputs.
<>	144:ef7eb2e8f9f7	453	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
<>	144:ef7eb2e8f9f7	454
<>	144:ef7eb2e8f9f7	455	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
<>	144:ef7eb2e8f9f7	456	} LL_TIM_HALLSENSOR_InitTypeDef;
<>	144:ef7eb2e8f9f7	457
<>	144:ef7eb2e8f9f7	458	/**
<>	144:ef7eb2e8f9f7	459	* @}
<>	144:ef7eb2e8f9f7	460	*/
<>	144:ef7eb2e8f9f7	461	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	462
<>	144:ef7eb2e8f9f7	463	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	464	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
<>	144:ef7eb2e8f9f7	465	* @{
<>	144:ef7eb2e8f9f7	466	*/
<>	144:ef7eb2e8f9f7	467
<>	144:ef7eb2e8f9f7	468	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
<>	144:ef7eb2e8f9f7	469	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
<>	144:ef7eb2e8f9f7	470	* @{
<>	144:ef7eb2e8f9f7	471	*/
<>	144:ef7eb2e8f9f7	472	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
<>	144:ef7eb2e8f9f7	473	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
<>	144:ef7eb2e8f9f7	474	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
<>	144:ef7eb2e8f9f7	475	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
<>	144:ef7eb2e8f9f7	476	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
<>	144:ef7eb2e8f9f7	477	#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /!< Capture/compare 5 interrupt flag /
<>	144:ef7eb2e8f9f7	478	#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /!< Capture/compare 6 interrupt flag /
<>	144:ef7eb2e8f9f7	479	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
<>	144:ef7eb2e8f9f7	480	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
<>	144:ef7eb2e8f9f7	481	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
<>	144:ef7eb2e8f9f7	482	#define LL_TIM_SR_B2IF TIM_SR_B2IF /!< Second break interrupt flag /
<>	144:ef7eb2e8f9f7	483	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
<>	144:ef7eb2e8f9f7	484	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
<>	144:ef7eb2e8f9f7	485	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
<>	144:ef7eb2e8f9f7	486	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
<>	144:ef7eb2e8f9f7	487	#define LL_TIM_SR_SBIF TIM_SR_SBIF /!< System Break interrupt flag /
<>	144:ef7eb2e8f9f7	488	/**
<>	144:ef7eb2e8f9f7	489	* @}
<>	144:ef7eb2e8f9f7	490	*/
<>	144:ef7eb2e8f9f7	491
<>	144:ef7eb2e8f9f7	492	/** @defgroup TIM_LL_EC_IT IT Defines
<>	144:ef7eb2e8f9f7	493	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
<>	144:ef7eb2e8f9f7	494	* @{
<>	144:ef7eb2e8f9f7	495	*/
<>	144:ef7eb2e8f9f7	496	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
<>	144:ef7eb2e8f9f7	497	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
<>	144:ef7eb2e8f9f7	498	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
<>	144:ef7eb2e8f9f7	499	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
<>	144:ef7eb2e8f9f7	500	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
<>	144:ef7eb2e8f9f7	501	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
<>	144:ef7eb2e8f9f7	502	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
<>	144:ef7eb2e8f9f7	503	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
<>	144:ef7eb2e8f9f7	504	/**
<>	144:ef7eb2e8f9f7	505	* @}
<>	144:ef7eb2e8f9f7	506	*/
<>	144:ef7eb2e8f9f7	507
<>	144:ef7eb2e8f9f7	508	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
<>	144:ef7eb2e8f9f7	509	* @{
<>	144:ef7eb2e8f9f7	510	*/
<>	144:ef7eb2e8f9f7	511	#define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
<>	144:ef7eb2e8f9f7	512	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
<>	144:ef7eb2e8f9f7	513	/**
<>	144:ef7eb2e8f9f7	514	* @}
<>	144:ef7eb2e8f9f7	515	*/
<>	144:ef7eb2e8f9f7	516
<>	144:ef7eb2e8f9f7	517	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
<>	144:ef7eb2e8f9f7	518	* @{
<>	144:ef7eb2e8f9f7	519	*/
<>	144:ef7eb2e8f9f7	520	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
<>	144:ef7eb2e8f9f7	521	#define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /!< Counter stops counting at the next update event /
<>	144:ef7eb2e8f9f7	522	/**
<>	144:ef7eb2e8f9f7	523	* @}
<>	144:ef7eb2e8f9f7	524	*/
<>	144:ef7eb2e8f9f7	525
<>	144:ef7eb2e8f9f7	526	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
<>	144:ef7eb2e8f9f7	527	* @{
<>	144:ef7eb2e8f9f7	528	*/
<>	144:ef7eb2e8f9f7	529	#define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /!<Counter used as upcounter /
<>	144:ef7eb2e8f9f7	530	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
<>	144:ef7eb2e8f9f7	531	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
<>	144:ef7eb2e8f9f7	532	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
<>	144:ef7eb2e8f9f7	533	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
<>	144:ef7eb2e8f9f7	534	/**
<>	144:ef7eb2e8f9f7	535	* @}
<>	144:ef7eb2e8f9f7	536	*/
<>	144:ef7eb2e8f9f7	537
<>	144:ef7eb2e8f9f7	538	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
<>	144:ef7eb2e8f9f7	539	* @{
<>	144:ef7eb2e8f9f7	540	*/
<>	144:ef7eb2e8f9f7	541	#define LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U) /!< tDTS=tCK_INT /
<>	144:ef7eb2e8f9f7	542	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
<>	144:ef7eb2e8f9f7	543	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
<>	144:ef7eb2e8f9f7	544	/**
<>	144:ef7eb2e8f9f7	545	* @}
<>	144:ef7eb2e8f9f7	546	*/
<>	144:ef7eb2e8f9f7	547
<>	144:ef7eb2e8f9f7	548	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
<>	144:ef7eb2e8f9f7	549	* @{
<>	144:ef7eb2e8f9f7	550	*/
<>	144:ef7eb2e8f9f7	551	#define LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000U) /!< Timer counter counts up /
<>	144:ef7eb2e8f9f7	552	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
<>	144:ef7eb2e8f9f7	553	/**
<>	144:ef7eb2e8f9f7	554	* @}
<>	144:ef7eb2e8f9f7	555	*/
<>	144:ef7eb2e8f9f7	556
<>	144:ef7eb2e8f9f7	557	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
<>	144:ef7eb2e8f9f7	558	* @{
<>	144:ef7eb2e8f9f7	559	*/
<>	144:ef7eb2e8f9f7	560	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY ((uint32_t)0x00000000U) /!< Capture/compare control bits are updated by setting the COMG bit only /
<>	144:ef7eb2e8f9f7	561	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
<>	144:ef7eb2e8f9f7	562	/**
<>	144:ef7eb2e8f9f7	563	* @}
<>	144:ef7eb2e8f9f7	564	*/
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
<>	144:ef7eb2e8f9f7	567	* @{
<>	144:ef7eb2e8f9f7	568	*/
<>	144:ef7eb2e8f9f7	569	#define LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000U) /!< CCx DMA request sent when CCx event occurs /
<>	144:ef7eb2e8f9f7	570	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
<>	144:ef7eb2e8f9f7	571	/**
<>	144:ef7eb2e8f9f7	572	* @}
<>	144:ef7eb2e8f9f7	573	*/
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
<>	144:ef7eb2e8f9f7	576	* @{
<>	144:ef7eb2e8f9f7	577	*/
<>	144:ef7eb2e8f9f7	578	#define LL_TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U) /!< LOCK OFF - No bit is write protected /
<>	144:ef7eb2e8f9f7	579	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
<>	144:ef7eb2e8f9f7	580	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
<>	144:ef7eb2e8f9f7	581	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
<>	144:ef7eb2e8f9f7	582	/**
<>	144:ef7eb2e8f9f7	583	* @}
<>	144:ef7eb2e8f9f7	584	*/
<>	144:ef7eb2e8f9f7	585
<>	144:ef7eb2e8f9f7	586	/** @defgroup TIM_LL_EC_CHANNEL Channel
<>	144:ef7eb2e8f9f7	587	* @{
<>	144:ef7eb2e8f9f7	588	*/
<>	144:ef7eb2e8f9f7	589	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
<>	144:ef7eb2e8f9f7	590	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
<>	144:ef7eb2e8f9f7	591	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
<>	144:ef7eb2e8f9f7	592	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
<>	144:ef7eb2e8f9f7	593	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
<>	144:ef7eb2e8f9f7	594	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
<>	144:ef7eb2e8f9f7	595	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
<>	144:ef7eb2e8f9f7	596	#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /!< Timer output channel 5 /
<>	144:ef7eb2e8f9f7	597	#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /!< Timer output channel 6 /
<>	144:ef7eb2e8f9f7	598	/**
<>	144:ef7eb2e8f9f7	599	* @}
<>	144:ef7eb2e8f9f7	600	*/
<>	144:ef7eb2e8f9f7	601
<>	144:ef7eb2e8f9f7	602	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	603	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
<>	144:ef7eb2e8f9f7	604	* @{
<>	144:ef7eb2e8f9f7	605	*/
<>	144:ef7eb2e8f9f7	606	#define LL_TIM_OCSTATE_DISABLE ((uint32_t)0x00000000U) /!< OCx is not active /
<>	144:ef7eb2e8f9f7	607	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
<>	144:ef7eb2e8f9f7	608	/**
<>	144:ef7eb2e8f9f7	609	* @}
<>	144:ef7eb2e8f9f7	610	*/
<>	144:ef7eb2e8f9f7	611	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	612
<>	144:ef7eb2e8f9f7	613	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
<>	144:ef7eb2e8f9f7	614	* @{
<>	144:ef7eb2e8f9f7	615	*/
<>	144:ef7eb2e8f9f7	616	#define LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000U) /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
<>	144:ef7eb2e8f9f7	617	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
<>	144:ef7eb2e8f9f7	618	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
<>	144:ef7eb2e8f9f7	619	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
<>	144:ef7eb2e8f9f7	620	#define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /!<OCyREF is forced low/
<>	144:ef7eb2e8f9f7	621	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
<>	144:ef7eb2e8f9f7	622	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
<>	144:ef7eb2e8f9f7	623	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
<>	144:ef7eb2e8f9f7	624	#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /!<Retrigerrable OPM mode 1/
<>	144:ef7eb2e8f9f7	625	#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0) /!<Retrigerrable OPM mode 2/
<>	144:ef7eb2e8f9f7	626	#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 1/
<>	144:ef7eb2e8f9f7	627	#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 2/
<>	144:ef7eb2e8f9f7	628	#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2) /!<Asymmetric PWM mode 1/
<>	144:ef7eb2e8f9f7	629	#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M) /!<Asymmetric PWM mode 2/
<>	144:ef7eb2e8f9f7	630	/**
<>	144:ef7eb2e8f9f7	631	* @}
<>	144:ef7eb2e8f9f7	632	*/
<>	144:ef7eb2e8f9f7	633
<>	144:ef7eb2e8f9f7	634	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
<>	144:ef7eb2e8f9f7	635	* @{
<>	144:ef7eb2e8f9f7	636	*/
<>	144:ef7eb2e8f9f7	637	#define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U) /!< OCxactive high/
<>	144:ef7eb2e8f9f7	638	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
<>	144:ef7eb2e8f9f7	639	/**
<>	144:ef7eb2e8f9f7	640	* @}
<>	144:ef7eb2e8f9f7	641	*/
<>	144:ef7eb2e8f9f7	642
<>	144:ef7eb2e8f9f7	643	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
<>	144:ef7eb2e8f9f7	644	* @{
<>	144:ef7eb2e8f9f7	645	*/
<>	144:ef7eb2e8f9f7	646	#define LL_TIM_OCIDLESTATE_LOW ((uint32_t)0x00000000U) /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
<>	144:ef7eb2e8f9f7	647	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
<>	144:ef7eb2e8f9f7	648	/**
<>	144:ef7eb2e8f9f7	649	* @}
<>	144:ef7eb2e8f9f7	650	*/
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
<>	144:ef7eb2e8f9f7	653	* @{
<>	144:ef7eb2e8f9f7	654	*/
<>	144:ef7eb2e8f9f7	655	#define LL_TIM_GROUPCH5_NONE (uint32_t)0x00000000U /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
<>	144:ef7eb2e8f9f7	656	#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
<>	144:ef7eb2e8f9f7	657	#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
<>	144:ef7eb2e8f9f7	658	#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
<>	144:ef7eb2e8f9f7	659	/**
<>	144:ef7eb2e8f9f7	660	* @}
<>	144:ef7eb2e8f9f7	661	*/
<>	144:ef7eb2e8f9f7	662
<>	144:ef7eb2e8f9f7	663	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
<>	144:ef7eb2e8f9f7	664	* @{
<>	144:ef7eb2e8f9f7	665	*/
<>	144:ef7eb2e8f9f7	666	#define LL_TIM_ACTIVEINPUT_DIRECTTI (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
<>	144:ef7eb2e8f9f7	667	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
<>	144:ef7eb2e8f9f7	668	#define LL_TIM_ACTIVEINPUT_TRC (uint32_t)(TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
<>	144:ef7eb2e8f9f7	669	/**
<>	144:ef7eb2e8f9f7	670	* @}
<>	144:ef7eb2e8f9f7	671	*/
<>	144:ef7eb2e8f9f7	672
<>	144:ef7eb2e8f9f7	673	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
<>	144:ef7eb2e8f9f7	674	* @{
<>	144:ef7eb2e8f9f7	675	*/
<>	144:ef7eb2e8f9f7	676	#define LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000U) /!< No prescaler, capture is done each time an edge is detected on the capture input /
<>	144:ef7eb2e8f9f7	677	#define LL_TIM_ICPSC_DIV2 (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
<>	144:ef7eb2e8f9f7	678	#define LL_TIM_ICPSC_DIV4 (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
<>	144:ef7eb2e8f9f7	679	#define LL_TIM_ICPSC_DIV8 (uint32_t)(TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
<>	144:ef7eb2e8f9f7	680	/**
<>	144:ef7eb2e8f9f7	681	* @}
<>	144:ef7eb2e8f9f7	682	*/
<>	144:ef7eb2e8f9f7	683
<>	144:ef7eb2e8f9f7	684	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
<>	144:ef7eb2e8f9f7	685	* @{
<>	144:ef7eb2e8f9f7	686	*/
<>	144:ef7eb2e8f9f7	687	#define LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000U) /!< No filter, sampling is done at fDTS /
<>	144:ef7eb2e8f9f7	688	#define LL_TIM_IC_FILTER_FDIV1_N2 (uint32_t)(TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
<>	144:ef7eb2e8f9f7	689	#define LL_TIM_IC_FILTER_FDIV1_N4 (uint32_t)(TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
<>	144:ef7eb2e8f9f7	690	#define LL_TIM_IC_FILTER_FDIV1_N8 (uint32_t)((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
<>	144:ef7eb2e8f9f7	691	#define LL_TIM_IC_FILTER_FDIV2_N6 (uint32_t)(TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
<>	144:ef7eb2e8f9f7	692	#define LL_TIM_IC_FILTER_FDIV2_N8 (uint32_t)((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
<>	144:ef7eb2e8f9f7	693	#define LL_TIM_IC_FILTER_FDIV4_N6 (uint32_t)((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
<>	144:ef7eb2e8f9f7	694	#define LL_TIM_IC_FILTER_FDIV4_N8 (uint32_t)((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
<>	144:ef7eb2e8f9f7	695	#define LL_TIM_IC_FILTER_FDIV8_N6 (uint32_t)(TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
<>	144:ef7eb2e8f9f7	696	#define LL_TIM_IC_FILTER_FDIV8_N8 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
<>	144:ef7eb2e8f9f7	697	#define LL_TIM_IC_FILTER_FDIV16_N5 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
<>	144:ef7eb2e8f9f7	698	#define LL_TIM_IC_FILTER_FDIV16_N6 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
<>	144:ef7eb2e8f9f7	699	#define LL_TIM_IC_FILTER_FDIV16_N8 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
<>	144:ef7eb2e8f9f7	700	#define LL_TIM_IC_FILTER_FDIV32_N5 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
<>	144:ef7eb2e8f9f7	701	#define LL_TIM_IC_FILTER_FDIV32_N6 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
<>	144:ef7eb2e8f9f7	702	#define LL_TIM_IC_FILTER_FDIV32_N8 (uint32_t)(TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
<>	144:ef7eb2e8f9f7	703	/**
<>	144:ef7eb2e8f9f7	704	* @}
<>	144:ef7eb2e8f9f7	705	*/
<>	144:ef7eb2e8f9f7	706
<>	144:ef7eb2e8f9f7	707	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
<>	144:ef7eb2e8f9f7	708	* @{
<>	144:ef7eb2e8f9f7	709	*/
<>	144:ef7eb2e8f9f7	710	#define LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000U) /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
<>	144:ef7eb2e8f9f7	711	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
<>	144:ef7eb2e8f9f7	712	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
<>	144:ef7eb2e8f9f7	713	/**
<>	144:ef7eb2e8f9f7	714	* @}
<>	144:ef7eb2e8f9f7	715	*/
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
<>	144:ef7eb2e8f9f7	718	* @{
<>	144:ef7eb2e8f9f7	719	*/
<>	144:ef7eb2e8f9f7	720	#define LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000U) /!< The timer is clocked by the internal clock provided from the RCC /
<>	144:ef7eb2e8f9f7	721	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0 ) /!< Counter counts at each rising or falling edge on a selected inpu t/
<>	144:ef7eb2e8f9f7	722	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
<>	144:ef7eb2e8f9f7	723	/**
<>	144:ef7eb2e8f9f7	724	* @}
<>	144:ef7eb2e8f9f7	725	*/
<>	144:ef7eb2e8f9f7	726
<>	144:ef7eb2e8f9f7	727	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
<>	144:ef7eb2e8f9f7	728	* @{
<>	144:ef7eb2e8f9f7	729	*/
<>	144:ef7eb2e8f9f7	730	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
<>	144:ef7eb2e8f9f7	731	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
<>	144:ef7eb2e8f9f7	732	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
<>	144:ef7eb2e8f9f7	733	/**
<>	144:ef7eb2e8f9f7	734	* @}
<>	144:ef7eb2e8f9f7	735	*/
<>	144:ef7eb2e8f9f7	736
<>	144:ef7eb2e8f9f7	737	/** @defgroup TIM_LL_EC_TRGO Trigger Output
<>	144:ef7eb2e8f9f7	738	* @{
<>	144:ef7eb2e8f9f7	739	*/
<>	144:ef7eb2e8f9f7	740	#define LL_TIM_TRGO_RESET ((uint32_t)0x00000000U) /!< UG bit from the TIMx_EGR register is used as trigger output /
<>	144:ef7eb2e8f9f7	741	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
<>	144:ef7eb2e8f9f7	742	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
<>	144:ef7eb2e8f9f7	743	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
<>	144:ef7eb2e8f9f7	744	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
<>	144:ef7eb2e8f9f7	745	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
<>	144:ef7eb2e8f9f7	746	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
<>	144:ef7eb2e8f9f7	747	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
<>	144:ef7eb2e8f9f7	748	/**
<>	144:ef7eb2e8f9f7	749	* @}
<>	144:ef7eb2e8f9f7	750	*/
<>	144:ef7eb2e8f9f7	751
<>	144:ef7eb2e8f9f7	752	/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
<>	144:ef7eb2e8f9f7	753	* @{
<>	144:ef7eb2e8f9f7	754	*/
<>	144:ef7eb2e8f9f7	755	#define LL_TIM_TRGO2_RESET ((uint32_t)0x00000000U) /!< UG bit from the TIMx_EGR register is used as trigger output 2 /
<>	144:ef7eb2e8f9f7	756	#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /!< Counter Enable signal (CNT_EN) is used as trigger output 2 /
<>	144:ef7eb2e8f9f7	757	#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /!< Update event is used as trigger output 2 /
<>	144:ef7eb2e8f9f7	758	#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< CC1 capture or a compare match is used as trigger output 2 /
<>	144:ef7eb2e8f9f7	759	#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /!< OC1REF signal is used as trigger output 2 /
<>	144:ef7eb2e8f9f7	760	#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC2REF signal is used as trigger output 2 /
<>	144:ef7eb2e8f9f7	761	#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1) /!< OC3REF signal is used as trigger output 2 /
<>	144:ef7eb2e8f9f7	762	#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC4REF signal is used as trigger output 2 /
<>	144:ef7eb2e8f9f7	763	#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /!< OC5REF signal is used as trigger output 2 /
<>	144:ef7eb2e8f9f7	764	#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0) /!< OC6REF signal is used as trigger output 2 /
<>	144:ef7eb2e8f9f7	765	#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1) /!< OC4REF rising or falling edges are used as trigger output 2 /
<>	144:ef7eb2e8f9f7	766	#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC6REF rising or falling edges are used as trigger output 2 /
<>	144:ef7eb2e8f9f7	767	#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2) /!< OC4REF or OC6REF rising edges are used as trigger output 2 /
<>	144:ef7eb2e8f9f7	768	#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC4REF rising or OC6REF falling edges are used as trigger output 2 /
<>	144:ef7eb2e8f9f7	769	#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1) /!< OC5REF or OC6REF rising edges are used as trigger output 2 /
<>	144:ef7eb2e8f9f7	770	#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC5REF rising or OC6REF falling edges are used as trigger output 2 /
<>	144:ef7eb2e8f9f7	771	/**
<>	144:ef7eb2e8f9f7	772	* @}
<>	144:ef7eb2e8f9f7	773	*/
<>	144:ef7eb2e8f9f7	774
<>	144:ef7eb2e8f9f7	775	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
<>	144:ef7eb2e8f9f7	776	* @{
<>	144:ef7eb2e8f9f7	777	*/
<>	144:ef7eb2e8f9f7	778	#define LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000U) /!< Slave mode disabled /
<>	144:ef7eb2e8f9f7	779	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
<>	144:ef7eb2e8f9f7	780	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
<>	144:ef7eb2e8f9f7	781	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
<>	144:ef7eb2e8f9f7	782	#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter /
<>	144:ef7eb2e8f9f7	783	/**
<>	144:ef7eb2e8f9f7	784	* @}
<>	144:ef7eb2e8f9f7	785	*/
<>	144:ef7eb2e8f9f7	786
<>	144:ef7eb2e8f9f7	787	/** @defgroup TIM_LL_EC_TS Trigger Selection
<>	144:ef7eb2e8f9f7	788	* @{
<>	144:ef7eb2e8f9f7	789	*/
<>	144:ef7eb2e8f9f7	790	#define LL_TIM_TS_ITR0 ((uint32_t)0x00000000U) /!< Internal Trigger 0 (ITR0) is used as trigger input /
<>	144:ef7eb2e8f9f7	791	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
<>	144:ef7eb2e8f9f7	792	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
<>	144:ef7eb2e8f9f7	793	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
<>	144:ef7eb2e8f9f7	794	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
<>	144:ef7eb2e8f9f7	795	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
<>	144:ef7eb2e8f9f7	796	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
<>	144:ef7eb2e8f9f7	797	#define LL_TIM_TS_ETRF TIM_SMCR_TS /!< Filtered external Trigger (ETRF) is used as trigger input /
<>	144:ef7eb2e8f9f7	798	/**
<>	144:ef7eb2e8f9f7	799	* @}
<>	144:ef7eb2e8f9f7	800	*/
<>	144:ef7eb2e8f9f7	801
<>	144:ef7eb2e8f9f7	802	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
<>	144:ef7eb2e8f9f7	803	* @{
<>	144:ef7eb2e8f9f7	804	*/
<>	144:ef7eb2e8f9f7	805	#define LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000U) /!< ETR is non-inverted, active at high level or rising edge /
<>	144:ef7eb2e8f9f7	806	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
<>	144:ef7eb2e8f9f7	807	/**
<>	144:ef7eb2e8f9f7	808	* @}
<>	144:ef7eb2e8f9f7	809	*/
<>	144:ef7eb2e8f9f7	810
<>	144:ef7eb2e8f9f7	811	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
<>	144:ef7eb2e8f9f7	812	* @{
<>	144:ef7eb2e8f9f7	813	*/
<>	144:ef7eb2e8f9f7	814	#define LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000U) /!< ETR prescaler OFF /
<>	144:ef7eb2e8f9f7	815	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
<>	144:ef7eb2e8f9f7	816	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
<>	144:ef7eb2e8f9f7	817	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
<>	144:ef7eb2e8f9f7	818	/**
<>	144:ef7eb2e8f9f7	819	* @}
<>	144:ef7eb2e8f9f7	820	*/
<>	144:ef7eb2e8f9f7	821
<>	144:ef7eb2e8f9f7	822	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
<>	144:ef7eb2e8f9f7	823	* @{
<>	144:ef7eb2e8f9f7	824	*/
<>	144:ef7eb2e8f9f7	825	#define LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000U) /!< No filter, sampling is done at fDTS /
<>	144:ef7eb2e8f9f7	826	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
<>	144:ef7eb2e8f9f7	827	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
<>	144:ef7eb2e8f9f7	828	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
<>	144:ef7eb2e8f9f7	829	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
<>	144:ef7eb2e8f9f7	830	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
<>	144:ef7eb2e8f9f7	831	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 ) /!< fSAMPLING=fDTS/4, N=6 /
<>	144:ef7eb2e8f9f7	832	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
<>	144:ef7eb2e8f9f7	833	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
<>	144:ef7eb2e8f9f7	834	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
<>	144:ef7eb2e8f9f7	835	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 ) /!< fSAMPLING=fDTS/16, N=6 /
<>	144:ef7eb2e8f9f7	836	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
<>	144:ef7eb2e8f9f7	837	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 ) /!< fSAMPLING=fDTS/16, N=5 /
<>	144:ef7eb2e8f9f7	838	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
<>	144:ef7eb2e8f9f7	839	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
<>	144:ef7eb2e8f9f7	840	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
<>	144:ef7eb2e8f9f7	841	/**
<>	144:ef7eb2e8f9f7	842	* @}
<>	144:ef7eb2e8f9f7	843	*/
<>	144:ef7eb2e8f9f7	844
<>	144:ef7eb2e8f9f7	845	/** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
<>	144:ef7eb2e8f9f7	846	* @{
<>	144:ef7eb2e8f9f7	847	*/
<>	144:ef7eb2e8f9f7	848	#define LL_TIM_ETRSOURCE_LEGACY ((uint32_t)(0x00000000U)) /!< ETR legacy mode /
<>	144:ef7eb2e8f9f7	849	#define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /!< COMP1 output connected to ETR input /
<>	144:ef7eb2e8f9f7	850	#define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /!< COMP2 output connected to ETR input /
<>	144:ef7eb2e8f9f7	851	/**
<>	144:ef7eb2e8f9f7	852	* @}
<>	144:ef7eb2e8f9f7	853	*/
<>	144:ef7eb2e8f9f7	854
<>	144:ef7eb2e8f9f7	855	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
<>	144:ef7eb2e8f9f7	856	* @{
<>	144:ef7eb2e8f9f7	857	*/
<>	144:ef7eb2e8f9f7	858	#define LL_TIM_BREAK_POLARITY_LOW ((uint32_t)0x00000000U) /!< Break input BRK is active low /
<>	144:ef7eb2e8f9f7	859	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
<>	144:ef7eb2e8f9f7	860	/**
<>	144:ef7eb2e8f9f7	861	* @}
<>	144:ef7eb2e8f9f7	862	*/
<>	144:ef7eb2e8f9f7	863
<>	144:ef7eb2e8f9f7	864	/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
<>	144:ef7eb2e8f9f7	865	* @{
<>	144:ef7eb2e8f9f7	866	*/
<>	144:ef7eb2e8f9f7	867	#define LL_TIM_BREAK_FILTER_FDIV1 ((uint32_t)0x00000000U) /!< No filter, BRK acts asynchronously /
<>	144:ef7eb2e8f9f7	868	#define LL_TIM_BREAK_FILTER_FDIV1_N2 ((uint32_t)0x00010000U) /!< fSAMPLING=fCK_INT, N=2 /
<>	144:ef7eb2e8f9f7	869	#define LL_TIM_BREAK_FILTER_FDIV1_N4 ((uint32_t)0x00020000U) /!< fSAMPLING=fCK_INT, N=4 /
<>	144:ef7eb2e8f9f7	870	#define LL_TIM_BREAK_FILTER_FDIV1_N8 ((uint32_t)0x00030000U) /!< fSAMPLING=fCK_INT, N=8 /
<>	144:ef7eb2e8f9f7	871	#define LL_TIM_BREAK_FILTER_FDIV2_N6 ((uint32_t)0x00040000U) /!< fSAMPLING=fDTS/2, N=6 /
<>	144:ef7eb2e8f9f7	872	#define LL_TIM_BREAK_FILTER_FDIV2_N8 ((uint32_t)0x00050000U) /!< fSAMPLING=fDTS/2, N=8 /
<>	144:ef7eb2e8f9f7	873	#define LL_TIM_BREAK_FILTER_FDIV4_N6 ((uint32_t)0x00060000U) /!< fSAMPLING=fDTS/4, N=6 /
<>	144:ef7eb2e8f9f7	874	#define LL_TIM_BREAK_FILTER_FDIV4_N8 ((uint32_t)0x00070000U) /!< fSAMPLING=fDTS/4, N=8 /
<>	144:ef7eb2e8f9f7	875	#define LL_TIM_BREAK_FILTER_FDIV8_N6 ((uint32_t)0x00080000U) /!< fSAMPLING=fDTS/8, N=6 /
<>	144:ef7eb2e8f9f7	876	#define LL_TIM_BREAK_FILTER_FDIV8_N8 ((uint32_t)0x00090000U) /!< fSAMPLING=fDTS/8, N=8 /
<>	144:ef7eb2e8f9f7	877	#define LL_TIM_BREAK_FILTER_FDIV16_N5 ((uint32_t)0x000A0000U) /!< fSAMPLING=fDTS/16, N=5 /
<>	144:ef7eb2e8f9f7	878	#define LL_TIM_BREAK_FILTER_FDIV16_N6 ((uint32_t)0x000B0000U) /!< fSAMPLING=fDTS/16, N=6 /
<>	144:ef7eb2e8f9f7	879	#define LL_TIM_BREAK_FILTER_FDIV16_N8 ((uint32_t)0x000C0000U) /!< fSAMPLING=fDTS/16, N=8 /
<>	144:ef7eb2e8f9f7	880	#define LL_TIM_BREAK_FILTER_FDIV32_N5 ((uint32_t)0x000D0000U) /!< fSAMPLING=fDTS/32, N=5 /
<>	144:ef7eb2e8f9f7	881	#define LL_TIM_BREAK_FILTER_FDIV32_N6 ((uint32_t)0x000E0000U) /!< fSAMPLING=fDTS/32, N=6 /
<>	144:ef7eb2e8f9f7	882	#define LL_TIM_BREAK_FILTER_FDIV32_N8 ((uint32_t)0x000F0000U) /!< fSAMPLING=fDTS/32, N=8 /
<>	144:ef7eb2e8f9f7	883	/**
<>	144:ef7eb2e8f9f7	884	* @}
<>	144:ef7eb2e8f9f7	885	*/
<>	144:ef7eb2e8f9f7	886
<>	144:ef7eb2e8f9f7	887	/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
<>	144:ef7eb2e8f9f7	888	* @{
<>	144:ef7eb2e8f9f7	889	*/
<>	144:ef7eb2e8f9f7	890	#define LL_TIM_BREAK2_POLARITY_LOW ((uint32_t)0x00000000U) /!< Break input BRK2 is active low /
<>	144:ef7eb2e8f9f7	891	#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /!< Break input BRK2 is active high /
<>	144:ef7eb2e8f9f7	892	/**
<>	144:ef7eb2e8f9f7	893	* @}
<>	144:ef7eb2e8f9f7	894	*/
<>	144:ef7eb2e8f9f7	895
<>	144:ef7eb2e8f9f7	896	/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
<>	144:ef7eb2e8f9f7	897	* @{
<>	144:ef7eb2e8f9f7	898	*/
<>	144:ef7eb2e8f9f7	899	#define LL_TIM_BREAK2_FILTER_FDIV1 ((uint32_t)0x00000000U) /!< No filter, BRK acts asynchronously /
<>	144:ef7eb2e8f9f7	900	#define LL_TIM_BREAK2_FILTER_FDIV1_N2 ((uint32_t)0x00100000U) /!< fSAMPLING=fCK_INT, N=2 /
<>	144:ef7eb2e8f9f7	901	#define LL_TIM_BREAK2_FILTER_FDIV1_N4 ((uint32_t)0x00200000U) /!< fSAMPLING=fCK_INT, N=4 /
<>	144:ef7eb2e8f9f7	902	#define LL_TIM_BREAK2_FILTER_FDIV1_N8 ((uint32_t)0x00300000U) /!< fSAMPLING=fCK_INT, N=8 /
<>	144:ef7eb2e8f9f7	903	#define LL_TIM_BREAK2_FILTER_FDIV2_N6 ((uint32_t)0x00400000U) /!< fSAMPLING=fDTS/2, N=6 /
<>	144:ef7eb2e8f9f7	904	#define LL_TIM_BREAK2_FILTER_FDIV2_N8 ((uint32_t)0x00500000U) /!< fSAMPLING=fDTS/2, N=8 /
<>	144:ef7eb2e8f9f7	905	#define LL_TIM_BREAK2_FILTER_FDIV4_N6 ((uint32_t)0x00600000U) /!< fSAMPLING=fDTS/4, N=6 /
<>	144:ef7eb2e8f9f7	906	#define LL_TIM_BREAK2_FILTER_FDIV4_N8 ((uint32_t)0x00700000U) /!< fSAMPLING=fDTS/4, N=8 /
<>	144:ef7eb2e8f9f7	907	#define LL_TIM_BREAK2_FILTER_FDIV8_N6 ((uint32_t)0x00800000U) /!< fSAMPLING=fDTS/8, N=6 /
<>	144:ef7eb2e8f9f7	908	#define LL_TIM_BREAK2_FILTER_FDIV8_N8 ((uint32_t)0x00900000U) /!< fSAMPLING=fDTS/8, N=8 /
<>	144:ef7eb2e8f9f7	909	#define LL_TIM_BREAK2_FILTER_FDIV16_N5 ((uint32_t)0x00A00000U) /!< fSAMPLING=fDTS/16, N=5 /
<>	144:ef7eb2e8f9f7	910	#define LL_TIM_BREAK2_FILTER_FDIV16_N6 ((uint32_t)0x00B00000U) /!< fSAMPLING=fDTS/16, N=6 /
<>	144:ef7eb2e8f9f7	911	#define LL_TIM_BREAK2_FILTER_FDIV16_N8 ((uint32_t)0x00C00000U) /!< fSAMPLING=fDTS/16, N=8 /
<>	144:ef7eb2e8f9f7	912	#define LL_TIM_BREAK2_FILTER_FDIV32_N5 ((uint32_t)0x00D00000U) /!< fSAMPLING=fDTS/32, N=5 /
<>	144:ef7eb2e8f9f7	913	#define LL_TIM_BREAK2_FILTER_FDIV32_N6 ((uint32_t)0x00E00000U) /!< fSAMPLING=fDTS/32, N=6 /
<>	144:ef7eb2e8f9f7	914	#define LL_TIM_BREAK2_FILTER_FDIV32_N8 ((uint32_t)0x00F00000U) /!< fSAMPLING=fDTS/32, N=8 /
<>	144:ef7eb2e8f9f7	915	/**
<>	144:ef7eb2e8f9f7	916	* @}
<>	144:ef7eb2e8f9f7	917	*/
<>	144:ef7eb2e8f9f7	918
<>	144:ef7eb2e8f9f7	919	/** @defgroup TIM_LL_EC_OSSI OSSI
<>	144:ef7eb2e8f9f7	920	* @{
<>	144:ef7eb2e8f9f7	921	*/
<>	144:ef7eb2e8f9f7	922	#define LL_TIM_OSSI_DISABLE ((uint32_t)0x00000000U) /!< When inactive, OCx/OCxN outputs are disabled /
<>	144:ef7eb2e8f9f7	923	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
<>	144:ef7eb2e8f9f7	924	/**
<>	144:ef7eb2e8f9f7	925	* @}
<>	144:ef7eb2e8f9f7	926	*/
<>	144:ef7eb2e8f9f7	927
<>	144:ef7eb2e8f9f7	928	/** @defgroup TIM_LL_EC_OSSR OSSR
<>	144:ef7eb2e8f9f7	929	* @{
<>	144:ef7eb2e8f9f7	930	*/
<>	144:ef7eb2e8f9f7	931	#define LL_TIM_OSSR_DISABLE ((uint32_t)0x00000000U) /!< When inactive, OCx/OCxN outputs are disabled /
<>	144:ef7eb2e8f9f7	932	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
<>	144:ef7eb2e8f9f7	933	/**
<>	144:ef7eb2e8f9f7	934	* @}
<>	144:ef7eb2e8f9f7	935	*/
<>	144:ef7eb2e8f9f7	936
<>	144:ef7eb2e8f9f7	937	/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
<>	144:ef7eb2e8f9f7	938	* @{
<>	144:ef7eb2e8f9f7	939	*/
<>	144:ef7eb2e8f9f7	940	#define LL_TIM_BREAK_INPUT_BKIN ((uint32_t)0x00000000U) /!< TIMx_BKIN input /
<>	144:ef7eb2e8f9f7	941	#define LL_TIM_BREAK_INPUT_BKIN2 ((uint32_t)0x00000004U) /!< TIMx_BKIN2 input /
<>	144:ef7eb2e8f9f7	942	/**
<>	144:ef7eb2e8f9f7	943	* @}
<>	144:ef7eb2e8f9f7	944	*/
<>	144:ef7eb2e8f9f7	945
<>	144:ef7eb2e8f9f7	946	/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
<>	144:ef7eb2e8f9f7	947	* @{
<>	144:ef7eb2e8f9f7	948	*/
<>	144:ef7eb2e8f9f7	949	#define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /!< BKIN input from AF controller /
<>	144:ef7eb2e8f9f7	950	#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /!< internal signal: COMP1 output /
<>	144:ef7eb2e8f9f7	951	#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /!< internal signal: COMP2 output /
<>	144:ef7eb2e8f9f7	952	#define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /!< internal signal: DFSDM1 break output /
<>	144:ef7eb2e8f9f7	953	/**
<>	144:ef7eb2e8f9f7	954	* @}
<>	144:ef7eb2e8f9f7	955	*/
<>	144:ef7eb2e8f9f7	956
<>	144:ef7eb2e8f9f7	957	/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
<>	144:ef7eb2e8f9f7	958	* @{
<>	144:ef7eb2e8f9f7	959	*/
<>	144:ef7eb2e8f9f7	960	#define LL_TIM_BKIN_POLARITY_LOW ((uint32_t)0x00000000U) /!< BRK BKIN input is active low /
<>	144:ef7eb2e8f9f7	961	#define LL_TIM_BKIN_POLARITY_HIGH TIM1_OR2_BKINP /!< BRK BKIN input is active high /
<>	144:ef7eb2e8f9f7	962	/**
<>	144:ef7eb2e8f9f7	963	* @}
<>	144:ef7eb2e8f9f7	964	*/
<>	144:ef7eb2e8f9f7	965
<>	144:ef7eb2e8f9f7	966	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
<>	144:ef7eb2e8f9f7	967	* @{
<>	144:ef7eb2e8f9f7	968	*/
<>	144:ef7eb2e8f9f7	969	#define LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000U) /!< TIMx_CR1 register is the DMA base address for DMA burst / /!< TIMx_CR1 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	970	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	971	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	972	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	973	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	974	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	975	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	976	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	977	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	978	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	979	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	980	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	981	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	982	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	983	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	984	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	985	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	986	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	987	#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) /!< TIMx_CCMR3 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	988	#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR5 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	989	#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_CCR6 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	990	#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_OR1 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	991	#define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_OR2 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	992	#define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_OR3 register is the DMA base address for DMA burst /
<>	144:ef7eb2e8f9f7	993	/**
<>	144:ef7eb2e8f9f7	994	* @}
<>	144:ef7eb2e8f9f7	995	*/
<>	144:ef7eb2e8f9f7	996
<>	144:ef7eb2e8f9f7	997	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
<>	144:ef7eb2e8f9f7	998	* @{
<>	144:ef7eb2e8f9f7	999	*/
<>	144:ef7eb2e8f9f7	1000	#define LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000U) /!< Transfer is done to 1 register starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1001	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1002	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1003	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1004	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1005	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1006	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1007	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1008	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1009	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1010	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1011	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1012	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1013	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1014	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1015	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1016	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1017	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
<>	144:ef7eb2e8f9f7	1018	/**
<>	144:ef7eb2e8f9f7	1019	* @}
<>	144:ef7eb2e8f9f7	1020	*/
<>	144:ef7eb2e8f9f7	1021
<>	144:ef7eb2e8f9f7	1022	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
<>	144:ef7eb2e8f9f7	1023	* @{
<>	144:ef7eb2e8f9f7	1024	*/
<>	144:ef7eb2e8f9f7	1025	#define LL_TIM_TIM1_ETR_ADC1_RMP_NC ((uint32_t)0x00000000U \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is not connected to ADC1 analog watchdog x /
<>	144:ef7eb2e8f9f7	1026	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 1 /
<>	144:ef7eb2e8f9f7	1027	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 2 /
<>	144:ef7eb2e8f9f7	1028	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 3 /
<>	144:ef7eb2e8f9f7	1029	/**
<>	144:ef7eb2e8f9f7	1030	* @}
<>	144:ef7eb2e8f9f7	1031	*/
<>	144:ef7eb2e8f9f7	1032
<>	144:ef7eb2e8f9f7	1033	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC3 Remap
<>	144:ef7eb2e8f9f7	1034	* @{
<>	144:ef7eb2e8f9f7	1035	*/
<>	144:ef7eb2e8f9f7	1036	#define LL_TIM_TIM1_ETR_ADC3_RMP_NC ((uint32_t)0x00000000U \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is not connected to ADC3 analog watchdog x/
<>	144:ef7eb2e8f9f7	1037	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 1 /
<>	144:ef7eb2e8f9f7	1038	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 2 /
<>	144:ef7eb2e8f9f7	1039	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 3 /
<>	144:ef7eb2e8f9f7	1040	/**
<>	144:ef7eb2e8f9f7	1041	* @}
<>	144:ef7eb2e8f9f7	1042	*/
<>	144:ef7eb2e8f9f7	1043
<>	144:ef7eb2e8f9f7	1044	/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
<>	144:ef7eb2e8f9f7	1045	* @{
<>	144:ef7eb2e8f9f7	1046	*/
<>	144:ef7eb2e8f9f7	1047	#define LL_TIM_TIM1_TI1_RMP_GPIO ((uint32_t)0x00000000U \| TIM1_OR1_RMP_MASK) /!< TIM1 input capture 1 is connected to GPIO /
<>	144:ef7eb2e8f9f7	1048	#define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1 input capture 1 is connected to COMP1 output /
<>	144:ef7eb2e8f9f7	1049	/**
<>	144:ef7eb2e8f9f7	1050	* @}
<>	144:ef7eb2e8f9f7	1051	*/
<>	144:ef7eb2e8f9f7	1052
<>	144:ef7eb2e8f9f7	1053	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
<>	144:ef7eb2e8f9f7	1054	* @{
<>	144:ef7eb2e8f9f7	1055	*/
<>	144:ef7eb2e8f9f7	1056	#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO ((uint32_t)0x00000000U \| TIM2_OR1_RMP_MASK) /!< TIM2_ITR1 is connected to TIM8_TRGO /
<>	144:ef7eb2e8f9f7	1057	#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_FS SOF /
<>	144:ef7eb2e8f9f7	1058	#define LL_TIM_TIM2_ETR_RMP_GPIO ((uint32_t)0x00000000U \| TIM2_OR1_RMP_MASK) /!< TIM2_ETR is connected to GPIO /
<>	144:ef7eb2e8f9f7	1059	#define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2_ETR is connected to LSE /
<>	144:ef7eb2e8f9f7	1060	/**
<>	144:ef7eb2e8f9f7	1061	* @}
<>	144:ef7eb2e8f9f7	1062	*/
<>	144:ef7eb2e8f9f7	1063
<>	144:ef7eb2e8f9f7	1064	/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
<>	144:ef7eb2e8f9f7	1065	* @{
<>	144:ef7eb2e8f9f7	1066	*/
<>	144:ef7eb2e8f9f7	1067	#define LL_TIM_TIM2_TI4_RMP_GPIO ((uint32_t)0x00000000U \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to GPIO /
<>	144:ef7eb2e8f9f7	1068	#define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to COMP1_OUT /
<>	144:ef7eb2e8f9f7	1069	#define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to COMP2_OUT /
<>	144:ef7eb2e8f9f7	1070	#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT /
<>	144:ef7eb2e8f9f7	1071	/**
<>	144:ef7eb2e8f9f7	1072	* @}
<>	144:ef7eb2e8f9f7	1073	*/
<>	144:ef7eb2e8f9f7	1074
<>	144:ef7eb2e8f9f7	1075	/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
<>	144:ef7eb2e8f9f7	1076	* @{
<>	144:ef7eb2e8f9f7	1077	*/
<>	144:ef7eb2e8f9f7	1078	#define LL_TIM_TIM3_TI1_RMP_GPIO ((uint32_t)0x00000000U \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to GPIO /
<>	144:ef7eb2e8f9f7	1079	#define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to COMP1_OUT /
<>	144:ef7eb2e8f9f7	1080	#define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to COMP2_OUT /
<>	144:ef7eb2e8f9f7	1081	#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT /
<>	144:ef7eb2e8f9f7	1082	/**
<>	144:ef7eb2e8f9f7	1083	* @}
<>	144:ef7eb2e8f9f7	1084	*/
<>	144:ef7eb2e8f9f7	1085
<>	144:ef7eb2e8f9f7	1086	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
<>	144:ef7eb2e8f9f7	1087	* @{
<>	144:ef7eb2e8f9f7	1088	*/
<>	144:ef7eb2e8f9f7	1089	#define LL_TIM_TIM8_ETR_ADC2_RMP_NC ((uint32_t)0x00000000U \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is not connected to ADC2 analog watchdog x /
<>	144:ef7eb2e8f9f7	1090	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog /
<>	144:ef7eb2e8f9f7	1091	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 2 /
<>	144:ef7eb2e8f9f7	1092	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 3 /
<>	144:ef7eb2e8f9f7	1093	/**
<>	144:ef7eb2e8f9f7	1094	* @}
<>	144:ef7eb2e8f9f7	1095	*/
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
<>	144:ef7eb2e8f9f7	1098	* @{
<>	144:ef7eb2e8f9f7	1099	*/
<>	144:ef7eb2e8f9f7	1100	#define LL_TIM_TIM8_ETR_ADC3_RMP_NC ((uint32_t)0x00000000U \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is not connected to ADC3 analog watchdog x /
<>	144:ef7eb2e8f9f7	1101	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 1 /
<>	144:ef7eb2e8f9f7	1102	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 2 /
<>	144:ef7eb2e8f9f7	1103	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 3 /
<>	144:ef7eb2e8f9f7	1104	/**
<>	144:ef7eb2e8f9f7	1105	* @}
<>	144:ef7eb2e8f9f7	1106	*/
<>	144:ef7eb2e8f9f7	1107
<>	144:ef7eb2e8f9f7	1108	/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
<>	144:ef7eb2e8f9f7	1109	* @{
<>	144:ef7eb2e8f9f7	1110	*/
<>	144:ef7eb2e8f9f7	1111	#define LL_TIM_TIM8_TI1_RMP_GPIO ((uint32_t)0x00000000U \| TIM8_OR1_RMP_MASK) /!< TIM8 input capture 1 is connected to GPIO /
<>	144:ef7eb2e8f9f7	1112	#define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8 input capture 1 is connected to COMP2 output /
<>	144:ef7eb2e8f9f7	1113	/**
<>	144:ef7eb2e8f9f7	1114	* @}
<>	144:ef7eb2e8f9f7	1115	*/
<>	144:ef7eb2e8f9f7	1116
<>	144:ef7eb2e8f9f7	1117	/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
<>	144:ef7eb2e8f9f7	1118	* @{
<>	144:ef7eb2e8f9f7	1119	*/
<>	144:ef7eb2e8f9f7	1120	#define LL_TIM_TIM15_TI1_RMP_GPIO ((uint32_t)0x00000000U \| TIM15_OR1_RMP_MASK) /!< TIM15 input capture 1 is connected to GPIO /
<>	144:ef7eb2e8f9f7	1121	#define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP \| TIM15_OR1_RMP_MASK) /!< TIM15 input capture 1 is connected to LSE /
<>	144:ef7eb2e8f9f7	1122	/**
<>	144:ef7eb2e8f9f7	1123	* @}
<>	144:ef7eb2e8f9f7	1124	*/
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	/** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE
<>	144:ef7eb2e8f9f7	1127	* @{
<>	144:ef7eb2e8f9f7	1128	*/
<>	144:ef7eb2e8f9f7	1129	#define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION ((uint32_t)0x00000000U \| TIM15_OR1_RMP_MASK) /!< No redirection/
<>	144:ef7eb2e8f9f7	1130	#define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 \| TIM15_OR1_RMP_MASK) /!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
<>	144:ef7eb2e8f9f7	1131	#define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 \| TIM15_OR1_RMP_MASK) /!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y/
<>	144:ef7eb2e8f9f7	1132	#define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE \| TIM15_OR1_RMP_MASK) /!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
<>	144:ef7eb2e8f9f7	1133	/**
<>	144:ef7eb2e8f9f7	1134	* @}
<>	144:ef7eb2e8f9f7	1135	*/
<>	144:ef7eb2e8f9f7	1136
<>	144:ef7eb2e8f9f7	1137	/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
<>	144:ef7eb2e8f9f7	1138	* @{
<>	144:ef7eb2e8f9f7	1139	*/
<>	144:ef7eb2e8f9f7	1140	#define LL_TIM_TIM16_TI1_RMP_GPIO ((uint32_t)0x00000000U \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to GPIO /
<>	144:ef7eb2e8f9f7	1141	#define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to LSI /
<>	144:ef7eb2e8f9f7	1142	#define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to LSE /
<>	144:ef7eb2e8f9f7	1143	#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_TI1_RMP_0 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to RTC wakeup interrupt /
<>	144:ef7eb2e8f9f7	1144	#if defined TIM16_OR1_TI1_RMP_2
<>	144:ef7eb2e8f9f7	1145	#define LL_TIM_TIM16_TI1_RMP_MSI (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to MSI /
<>	144:ef7eb2e8f9f7	1146	#define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_TI1_RMP_0 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to HSE/32 /
<>	144:ef7eb2e8f9f7	1147	#define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to MCO /
<>	144:ef7eb2e8f9f7	1148	#endif
<>	144:ef7eb2e8f9f7	1149	/**
<>	144:ef7eb2e8f9f7	1150	* @}
<>	144:ef7eb2e8f9f7	1151	*/
<>	144:ef7eb2e8f9f7	1152
<>	144:ef7eb2e8f9f7	1153	/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
<>	144:ef7eb2e8f9f7	1154	* @{
<>	144:ef7eb2e8f9f7	1155	*/
<>	144:ef7eb2e8f9f7	1156	#define LL_TIM_TIM17_TI1_RMP_GPIO ((uint32_t)0x00000000U \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to GPIO /
<>	144:ef7eb2e8f9f7	1157	#define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to MSI /
<>	144:ef7eb2e8f9f7	1158	#define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to HSE/32 /
<>	144:ef7eb2e8f9f7	1159	#define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to MCO /
<>	144:ef7eb2e8f9f7	1160	/**
<>	144:ef7eb2e8f9f7	1161	* @}
<>	144:ef7eb2e8f9f7	1162	*/
<>	144:ef7eb2e8f9f7	1163
<>	144:ef7eb2e8f9f7	1164	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
<>	144:ef7eb2e8f9f7	1165	* @{
<>	144:ef7eb2e8f9f7	1166	*/
<>	144:ef7eb2e8f9f7	1167	#define LL_TIM_OCREF_CLR_INT_NC ((uint32_t)0x00000000U ) /!< OCREF_CLR_INT is not connected /
<>	144:ef7eb2e8f9f7	1168	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
<>	144:ef7eb2e8f9f7	1169	/**
<>	144:ef7eb2e8f9f7	1170	* @}
<>	144:ef7eb2e8f9f7	1171	*/
<>	144:ef7eb2e8f9f7	1172
<>	144:ef7eb2e8f9f7	1173	/** Legacy definitions for compatibility purpose
<>	144:ef7eb2e8f9f7	1174	@cond 0
<>	144:ef7eb2e8f9f7	1175	*/
<>	144:ef7eb2e8f9f7	1176	#define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
<>	144:ef7eb2e8f9f7	1177	/**
<>	144:ef7eb2e8f9f7	1178	@endcond
<>	144:ef7eb2e8f9f7	1179	*/
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	/**
<>	144:ef7eb2e8f9f7	1182	* @}
<>	144:ef7eb2e8f9f7	1183	*/
<>	144:ef7eb2e8f9f7	1184
<>	144:ef7eb2e8f9f7	1185	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1186	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
<>	144:ef7eb2e8f9f7	1187	* @{
<>	144:ef7eb2e8f9f7	1188	*/
<>	144:ef7eb2e8f9f7	1189
<>	144:ef7eb2e8f9f7	1190	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
<>	144:ef7eb2e8f9f7	1191	* @{
<>	144:ef7eb2e8f9f7	1192	*/
<>	144:ef7eb2e8f9f7	1193	/**
<>	144:ef7eb2e8f9f7	1194	* @brief Write a value in TIM register.
<>	144:ef7eb2e8f9f7	1195	* @param __INSTANCE__ TIM Instance
<>	144:ef7eb2e8f9f7	1196	* @param __REG__ Register to be written
<>	144:ef7eb2e8f9f7	1197	* @param __VALUE__ Value to be written in the register
<>	144:ef7eb2e8f9f7	1198	* @retval None
<>	144:ef7eb2e8f9f7	1199	*/
<>	144:ef7eb2e8f9f7	1200	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	144:ef7eb2e8f9f7	1201
<>	144:ef7eb2e8f9f7	1202	/**
<>	144:ef7eb2e8f9f7	1203	* @brief Read a value in TIM register.
<>	144:ef7eb2e8f9f7	1204	* @param __INSTANCE__ TIM Instance
<>	144:ef7eb2e8f9f7	1205	* @param __REG__ Register to be read
<>	144:ef7eb2e8f9f7	1206	* @retval Register value
<>	144:ef7eb2e8f9f7	1207	*/
<>	144:ef7eb2e8f9f7	1208	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	144:ef7eb2e8f9f7	1209	/**
<>	144:ef7eb2e8f9f7	1210	* @}
<>	144:ef7eb2e8f9f7	1211	*/
<>	144:ef7eb2e8f9f7	1212
<>	144:ef7eb2e8f9f7	1213	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
<>	144:ef7eb2e8f9f7	1214	* @{
<>	144:ef7eb2e8f9f7	1215	*/
<>	144:ef7eb2e8f9f7	1216	/**
<>	144:ef7eb2e8f9f7	1217	* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
<>	144:ef7eb2e8f9f7	1218	* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
<>	144:ef7eb2e8f9f7	1219	* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
<>	144:ef7eb2e8f9f7	1220	* to TIMx_CNT register bit 31)
<>	144:ef7eb2e8f9f7	1221	* @param __CNT__ Counter value
<>	144:ef7eb2e8f9f7	1222	* @retval UIF status bit
<>	144:ef7eb2e8f9f7	1223	*/
<>	144:ef7eb2e8f9f7	1224	#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
<>	144:ef7eb2e8f9f7	1225	(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> POSITION_VAL(TIM_CNT_UIFCPY))
<>	144:ef7eb2e8f9f7	1226
<>	144:ef7eb2e8f9f7	1227	/**
<>	144:ef7eb2e8f9f7	1228	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
<>	144:ef7eb2e8f9f7	1229	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
<>	144:ef7eb2e8f9f7	1230	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1231	* @param __CKD__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1232	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	144:ef7eb2e8f9f7	1233	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	144:ef7eb2e8f9f7	1234	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	144:ef7eb2e8f9f7	1235	* @param __DT__ deadtime duration (in ns)
<>	144:ef7eb2e8f9f7	1236	* @retval DTG[0:7]
<>	144:ef7eb2e8f9f7	1237	*/
<>	144:ef7eb2e8f9f7	1238	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
<>	144:ef7eb2e8f9f7	1239	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
<>	144:ef7eb2e8f9f7	1240	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
<>	144:ef7eb2e8f9f7	1241	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
<>	144:ef7eb2e8f9f7	1242	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
<>	144:ef7eb2e8f9f7	1243	0U)
<>	144:ef7eb2e8f9f7	1244
<>	144:ef7eb2e8f9f7	1245	/**
<>	144:ef7eb2e8f9f7	1246	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
<>	144:ef7eb2e8f9f7	1247	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
<>	144:ef7eb2e8f9f7	1248	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1249	* @param __CNTCLK__ counter clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1250	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	1251	*/
<>	144:ef7eb2e8f9f7	1252	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
<>	144:ef7eb2e8f9f7	1253	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
<>	144:ef7eb2e8f9f7	1254
<>	144:ef7eb2e8f9f7	1255	/**
<>	144:ef7eb2e8f9f7	1256	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
<>	144:ef7eb2e8f9f7	1257	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
<>	144:ef7eb2e8f9f7	1258	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1259	* @param __PSC__ prescaler
<>	144:ef7eb2e8f9f7	1260	* @param __FREQ__ output signal frequency (in Hz)
<>	144:ef7eb2e8f9f7	1261	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	1262	*/
<>	144:ef7eb2e8f9f7	1263	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
<>	144:ef7eb2e8f9f7	1264	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
<>	144:ef7eb2e8f9f7	1265
<>	144:ef7eb2e8f9f7	1266	/**
<>	144:ef7eb2e8f9f7	1267	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
<>	144:ef7eb2e8f9f7	1268	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
<>	144:ef7eb2e8f9f7	1269	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1270	* @param __PSC__ prescaler
<>	144:ef7eb2e8f9f7	1271	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	144:ef7eb2e8f9f7	1272	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	1273	*/
<>	144:ef7eb2e8f9f7	1274	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
<>	144:ef7eb2e8f9f7	1275	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
<>	144:ef7eb2e8f9f7	1276	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
<>	144:ef7eb2e8f9f7	1277
<>	144:ef7eb2e8f9f7	1278	/**
<>	144:ef7eb2e8f9f7	1279	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
<>	144:ef7eb2e8f9f7	1280	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
<>	144:ef7eb2e8f9f7	1281	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	144:ef7eb2e8f9f7	1282	* @param __PSC__ prescaler
<>	144:ef7eb2e8f9f7	1283	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	144:ef7eb2e8f9f7	1284	* @param __PULSE__ pulse duration (in us)
<>	144:ef7eb2e8f9f7	1285	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	1286	*/
<>	144:ef7eb2e8f9f7	1287	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
<>	144:ef7eb2e8f9f7	1288	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
<>	144:ef7eb2e8f9f7	1289	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
<>	144:ef7eb2e8f9f7	1290
<>	144:ef7eb2e8f9f7	1291	/**
<>	144:ef7eb2e8f9f7	1292	* @brief HELPER macro retrieving the ratio of the input capture prescaler
<>	144:ef7eb2e8f9f7	1293	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
<>	144:ef7eb2e8f9f7	1294	* @param __ICPSC__ This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1295	* @arg @ref LL_TIM_ICPSC_DIV1
<>	144:ef7eb2e8f9f7	1296	* @arg @ref LL_TIM_ICPSC_DIV2
<>	144:ef7eb2e8f9f7	1297	* @arg @ref LL_TIM_ICPSC_DIV4
<>	144:ef7eb2e8f9f7	1298	* @arg @ref LL_TIM_ICPSC_DIV8
<>	144:ef7eb2e8f9f7	1299	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
<>	144:ef7eb2e8f9f7	1300	*/
<>	144:ef7eb2e8f9f7	1301	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
<>	144:ef7eb2e8f9f7	1302	((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_POSITION_ICPSC)))
<>	144:ef7eb2e8f9f7	1303
<>	144:ef7eb2e8f9f7	1304
<>	144:ef7eb2e8f9f7	1305	/**
<>	144:ef7eb2e8f9f7	1306	* @}
<>	144:ef7eb2e8f9f7	1307	*/
<>	144:ef7eb2e8f9f7	1308
<>	144:ef7eb2e8f9f7	1309
<>	144:ef7eb2e8f9f7	1310	/**
<>	144:ef7eb2e8f9f7	1311	* @}
<>	144:ef7eb2e8f9f7	1312	*/
<>	144:ef7eb2e8f9f7	1313
<>	144:ef7eb2e8f9f7	1314	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1315	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
<>	144:ef7eb2e8f9f7	1316	* @{
<>	144:ef7eb2e8f9f7	1317	*/
<>	144:ef7eb2e8f9f7	1318
<>	144:ef7eb2e8f9f7	1319	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
<>	144:ef7eb2e8f9f7	1320	* @{
<>	144:ef7eb2e8f9f7	1321	*/
<>	144:ef7eb2e8f9f7	1322	/**
<>	144:ef7eb2e8f9f7	1323	* @brief Enable timer counter.
<>	144:ef7eb2e8f9f7	1324	* @rmtoll CR1 CEN LL_TIM_EnableCounter
<>	144:ef7eb2e8f9f7	1325	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1326	* @retval None
<>	144:ef7eb2e8f9f7	1327	*/
<>	144:ef7eb2e8f9f7	1328	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1329	{
<>	144:ef7eb2e8f9f7	1330	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	144:ef7eb2e8f9f7	1331	}
<>	144:ef7eb2e8f9f7	1332
<>	144:ef7eb2e8f9f7	1333	/**
<>	144:ef7eb2e8f9f7	1334	* @brief Disable timer counter.
<>	144:ef7eb2e8f9f7	1335	* @rmtoll CR1 CEN LL_TIM_DisableCounter
<>	144:ef7eb2e8f9f7	1336	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1337	* @retval None
<>	144:ef7eb2e8f9f7	1338	*/
<>	144:ef7eb2e8f9f7	1339	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1340	{
<>	144:ef7eb2e8f9f7	1341	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	144:ef7eb2e8f9f7	1342	}
<>	144:ef7eb2e8f9f7	1343
<>	144:ef7eb2e8f9f7	1344	/**
<>	144:ef7eb2e8f9f7	1345	* @brief Indicates whether the timer counter is enabled.
<>	144:ef7eb2e8f9f7	1346	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
<>	144:ef7eb2e8f9f7	1347	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1348	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1349	*/
<>	144:ef7eb2e8f9f7	1350	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1351	{
<>	144:ef7eb2e8f9f7	1352	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
<>	144:ef7eb2e8f9f7	1353	}
<>	144:ef7eb2e8f9f7	1354
<>	144:ef7eb2e8f9f7	1355	/**
<>	144:ef7eb2e8f9f7	1356	* @brief Enable update event generation.
<>	144:ef7eb2e8f9f7	1357	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
<>	144:ef7eb2e8f9f7	1358	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1359	* @retval None
<>	144:ef7eb2e8f9f7	1360	*/
<>	144:ef7eb2e8f9f7	1361	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1362	{
<>	144:ef7eb2e8f9f7	1363	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	144:ef7eb2e8f9f7	1364	}
<>	144:ef7eb2e8f9f7	1365
<>	144:ef7eb2e8f9f7	1366	/**
<>	144:ef7eb2e8f9f7	1367	* @brief Disable update event generation.
<>	144:ef7eb2e8f9f7	1368	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
<>	144:ef7eb2e8f9f7	1369	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1370	* @retval None
<>	144:ef7eb2e8f9f7	1371	*/
<>	144:ef7eb2e8f9f7	1372	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1373	{
<>	144:ef7eb2e8f9f7	1374	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	144:ef7eb2e8f9f7	1375	}
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	/**
<>	144:ef7eb2e8f9f7	1378	* @brief Indicates whether update event generation is enabled.
<>	144:ef7eb2e8f9f7	1379	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
<>	144:ef7eb2e8f9f7	1380	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1381	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1382	*/
<>	144:ef7eb2e8f9f7	1383	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1384	{
<>	144:ef7eb2e8f9f7	1385	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
<>	144:ef7eb2e8f9f7	1386	}
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	/**
<>	144:ef7eb2e8f9f7	1389	* @brief Set update event source
<>	144:ef7eb2e8f9f7	1390	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
<>	144:ef7eb2e8f9f7	1391	* generate an update interrupt or DMA request if enabled:
<>	144:ef7eb2e8f9f7	1392	* - Counter overflow/underflow
<>	144:ef7eb2e8f9f7	1393	* - Setting the UG bit
<>	144:ef7eb2e8f9f7	1394	* - Update generation through the slave mode controller
<>	144:ef7eb2e8f9f7	1395	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
<>	144:ef7eb2e8f9f7	1396	* overflow/underflow generates an update interrupt or DMA request if enabled.
<>	144:ef7eb2e8f9f7	1397	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
<>	144:ef7eb2e8f9f7	1398	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1399	* @param UpdateSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1400	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	144:ef7eb2e8f9f7	1401	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	144:ef7eb2e8f9f7	1402	* @retval None
<>	144:ef7eb2e8f9f7	1403	*/
<>	144:ef7eb2e8f9f7	1404	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx, uint32_t UpdateSource)
<>	144:ef7eb2e8f9f7	1405	{
<>	144:ef7eb2e8f9f7	1406	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
<>	144:ef7eb2e8f9f7	1407	}
<>	144:ef7eb2e8f9f7	1408
<>	144:ef7eb2e8f9f7	1409	/**
<>	144:ef7eb2e8f9f7	1410	* @brief Get actual event update source
<>	144:ef7eb2e8f9f7	1411	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
<>	144:ef7eb2e8f9f7	1412	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1413	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1414	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	144:ef7eb2e8f9f7	1415	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	144:ef7eb2e8f9f7	1416	*/
<>	144:ef7eb2e8f9f7	1417	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1418	{
<>	144:ef7eb2e8f9f7	1419	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
<>	144:ef7eb2e8f9f7	1420	}
<>	144:ef7eb2e8f9f7	1421
<>	144:ef7eb2e8f9f7	1422	/**
<>	144:ef7eb2e8f9f7	1423	* @brief Set one pulse mode (one shot v.s. repetitive).
<>	144:ef7eb2e8f9f7	1424	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
<>	144:ef7eb2e8f9f7	1425	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1426	* @param OnePulseMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1427	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	144:ef7eb2e8f9f7	1428	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	144:ef7eb2e8f9f7	1429	* @retval None
<>	144:ef7eb2e8f9f7	1430	*/
<>	144:ef7eb2e8f9f7	1431	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx, uint32_t OnePulseMode)
<>	144:ef7eb2e8f9f7	1432	{
<>	144:ef7eb2e8f9f7	1433	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
<>	144:ef7eb2e8f9f7	1434	}
<>	144:ef7eb2e8f9f7	1435
<>	144:ef7eb2e8f9f7	1436	/**
<>	144:ef7eb2e8f9f7	1437	* @brief Get actual one pulse mode.
<>	144:ef7eb2e8f9f7	1438	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
<>	144:ef7eb2e8f9f7	1439	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1440	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1441	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	144:ef7eb2e8f9f7	1442	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	144:ef7eb2e8f9f7	1443	*/
<>	144:ef7eb2e8f9f7	1444	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1445	{
<>	144:ef7eb2e8f9f7	1446	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
<>	144:ef7eb2e8f9f7	1447	}
<>	144:ef7eb2e8f9f7	1448
<>	144:ef7eb2e8f9f7	1449	/**
<>	144:ef7eb2e8f9f7	1450	* @brief Set the timer counter counting mode.
<>	144:ef7eb2e8f9f7	1451	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	144:ef7eb2e8f9f7	1452	* check whether or not the counter mode selection feature is supported
<>	144:ef7eb2e8f9f7	1453	* by a timer instance.
<>	144:ef7eb2e8f9f7	1454	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
<>	144:ef7eb2e8f9f7	1455	* CR1 CMS LL_TIM_SetCounterMode
<>	144:ef7eb2e8f9f7	1456	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1457	* @param CounterMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1458	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	144:ef7eb2e8f9f7	1459	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	144:ef7eb2e8f9f7	1460	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	144:ef7eb2e8f9f7	1461	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	144:ef7eb2e8f9f7	1462	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	144:ef7eb2e8f9f7	1463	* @retval None
<>	144:ef7eb2e8f9f7	1464	*/
<>	144:ef7eb2e8f9f7	1465	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef * TIMx, uint32_t CounterMode)
<>	144:ef7eb2e8f9f7	1466	{
<>	144:ef7eb2e8f9f7	1467	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
<>	144:ef7eb2e8f9f7	1468	}
<>	144:ef7eb2e8f9f7	1469
<>	144:ef7eb2e8f9f7	1470	/**
<>	144:ef7eb2e8f9f7	1471	* @brief Get actual counter mode.
<>	144:ef7eb2e8f9f7	1472	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	144:ef7eb2e8f9f7	1473	* check whether or not the counter mode selection feature is supported
<>	144:ef7eb2e8f9f7	1474	* by a timer instance.
<>	144:ef7eb2e8f9f7	1475	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
<>	144:ef7eb2e8f9f7	1476	* CR1 CMS LL_TIM_GetCounterMode
<>	144:ef7eb2e8f9f7	1477	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1478	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1479	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	144:ef7eb2e8f9f7	1480	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	144:ef7eb2e8f9f7	1481	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	144:ef7eb2e8f9f7	1482	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	144:ef7eb2e8f9f7	1483	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	144:ef7eb2e8f9f7	1484	*/
<>	144:ef7eb2e8f9f7	1485	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1486	{
<>	144:ef7eb2e8f9f7	1487	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
<>	144:ef7eb2e8f9f7	1488	}
<>	144:ef7eb2e8f9f7	1489
<>	144:ef7eb2e8f9f7	1490	/**
<>	144:ef7eb2e8f9f7	1491	* @brief Enable auto-reload (ARR) preload.
<>	144:ef7eb2e8f9f7	1492	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
<>	144:ef7eb2e8f9f7	1493	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1494	* @retval None
<>	144:ef7eb2e8f9f7	1495	*/
<>	144:ef7eb2e8f9f7	1496	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1497	{
<>	144:ef7eb2e8f9f7	1498	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	144:ef7eb2e8f9f7	1499	}
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	/**
<>	144:ef7eb2e8f9f7	1502	* @brief Disable auto-reload (ARR) preload.
<>	144:ef7eb2e8f9f7	1503	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
<>	144:ef7eb2e8f9f7	1504	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1505	* @retval None
<>	144:ef7eb2e8f9f7	1506	*/
<>	144:ef7eb2e8f9f7	1507	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1508	{
<>	144:ef7eb2e8f9f7	1509	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	144:ef7eb2e8f9f7	1510	}
<>	144:ef7eb2e8f9f7	1511
<>	144:ef7eb2e8f9f7	1512	/**
<>	144:ef7eb2e8f9f7	1513	* @brief Indicates whether auto-reload (ARR) preload is enabled.
<>	144:ef7eb2e8f9f7	1514	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
<>	144:ef7eb2e8f9f7	1515	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1516	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1517	*/
<>	144:ef7eb2e8f9f7	1518	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1519	{
<>	144:ef7eb2e8f9f7	1520	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
<>	144:ef7eb2e8f9f7	1521	}
<>	144:ef7eb2e8f9f7	1522
<>	144:ef7eb2e8f9f7	1523	/**
<>	144:ef7eb2e8f9f7	1524	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	144:ef7eb2e8f9f7	1525	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1526	* whether or not the clock division feature is supported by the timer
<>	144:ef7eb2e8f9f7	1527	* instance.
<>	144:ef7eb2e8f9f7	1528	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
<>	144:ef7eb2e8f9f7	1529	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1530	* @param ClockDivision This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1531	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	144:ef7eb2e8f9f7	1532	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	144:ef7eb2e8f9f7	1533	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	144:ef7eb2e8f9f7	1534	* @retval None
<>	144:ef7eb2e8f9f7	1535	*/
<>	144:ef7eb2e8f9f7	1536	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef * TIMx, uint32_t ClockDivision)
<>	144:ef7eb2e8f9f7	1537	{
<>	144:ef7eb2e8f9f7	1538	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
<>	144:ef7eb2e8f9f7	1539	}
<>	144:ef7eb2e8f9f7	1540
<>	144:ef7eb2e8f9f7	1541	/**
<>	144:ef7eb2e8f9f7	1542	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	144:ef7eb2e8f9f7	1543	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1544	* whether or not the clock division feature is supported by the timer
<>	144:ef7eb2e8f9f7	1545	* instance.
<>	144:ef7eb2e8f9f7	1546	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
<>	144:ef7eb2e8f9f7	1547	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1548	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1549	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	144:ef7eb2e8f9f7	1550	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	144:ef7eb2e8f9f7	1551	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	144:ef7eb2e8f9f7	1552	*/
<>	144:ef7eb2e8f9f7	1553	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1554	{
<>	144:ef7eb2e8f9f7	1555	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
<>	144:ef7eb2e8f9f7	1556	}
<>	144:ef7eb2e8f9f7	1557
<>	144:ef7eb2e8f9f7	1558	/**
<>	144:ef7eb2e8f9f7	1559	* @brief Set the counter value.
<>	144:ef7eb2e8f9f7	1560	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1561	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	1562	* @rmtoll CNT CNT LL_TIM_SetCounter
<>	144:ef7eb2e8f9f7	1563	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1564	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	144:ef7eb2e8f9f7	1565	* @retval None
<>	144:ef7eb2e8f9f7	1566	*/
<>	144:ef7eb2e8f9f7	1567	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef * TIMx, uint32_t Counter)
<>	144:ef7eb2e8f9f7	1568	{
<>	144:ef7eb2e8f9f7	1569	WRITE_REG(TIMx->CNT, Counter);
<>	144:ef7eb2e8f9f7	1570	}
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	/**
<>	144:ef7eb2e8f9f7	1573	* @brief Get the counter value.
<>	144:ef7eb2e8f9f7	1574	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1575	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	1576	* @rmtoll CNT CNT LL_TIM_GetCounter
<>	144:ef7eb2e8f9f7	1577	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1578	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	144:ef7eb2e8f9f7	1579	*/
<>	144:ef7eb2e8f9f7	1580	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1581	{
<>	144:ef7eb2e8f9f7	1582	return (uint32_t)(READ_REG(TIMx->CNT));
<>	144:ef7eb2e8f9f7	1583	}
<>	144:ef7eb2e8f9f7	1584
<>	144:ef7eb2e8f9f7	1585	/**
<>	144:ef7eb2e8f9f7	1586	* @brief Get the current direction of the counter
<>	144:ef7eb2e8f9f7	1587	* @rmtoll CR1 DIR LL_TIM_GetDirection
<>	144:ef7eb2e8f9f7	1588	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1589	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1590	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
<>	144:ef7eb2e8f9f7	1591	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
<>	144:ef7eb2e8f9f7	1592	*/
<>	144:ef7eb2e8f9f7	1593	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1594	{
<>	144:ef7eb2e8f9f7	1595	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
<>	144:ef7eb2e8f9f7	1596	}
<>	144:ef7eb2e8f9f7	1597
<>	144:ef7eb2e8f9f7	1598	/**
<>	144:ef7eb2e8f9f7	1599	* @brief Set the prescaler value.
<>	144:ef7eb2e8f9f7	1600	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
<>	144:ef7eb2e8f9f7	1601	* @note The prescaler can be changed on the fly as this control register is buffered. The new
<>	144:ef7eb2e8f9f7	1602	* prescaler ratio is taken into account at the next update event.
<>	144:ef7eb2e8f9f7	1603	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
<>	144:ef7eb2e8f9f7	1604	* @rmtoll PSC PSC LL_TIM_SetPrescaler
<>	144:ef7eb2e8f9f7	1605	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1606	* @param Prescaler between Min_Data=0 and Max_Data=65535
<>	144:ef7eb2e8f9f7	1607	* @retval None
<>	144:ef7eb2e8f9f7	1608	*/
<>	144:ef7eb2e8f9f7	1609	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Prescaler)
<>	144:ef7eb2e8f9f7	1610	{
<>	144:ef7eb2e8f9f7	1611	WRITE_REG(TIMx->PSC, Prescaler);
<>	144:ef7eb2e8f9f7	1612	}
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	/**
<>	144:ef7eb2e8f9f7	1615	* @brief Get the prescaler value.
<>	144:ef7eb2e8f9f7	1616	* @rmtoll PSC PSC LL_TIM_GetPrescaler
<>	144:ef7eb2e8f9f7	1617	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1618	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
<>	144:ef7eb2e8f9f7	1619	*/
<>	144:ef7eb2e8f9f7	1620	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1621	{
<>	144:ef7eb2e8f9f7	1622	return (uint32_t)(READ_REG(TIMx->PSC));
<>	144:ef7eb2e8f9f7	1623	}
<>	144:ef7eb2e8f9f7	1624
<>	144:ef7eb2e8f9f7	1625	/**
<>	144:ef7eb2e8f9f7	1626	* @brief Set the auto-reload value.
<>	144:ef7eb2e8f9f7	1627	* @note The counter is blocked while the auto-reload value is null.
<>	144:ef7eb2e8f9f7	1628	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1629	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	1630	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
<>	144:ef7eb2e8f9f7	1631	* @rmtoll ARR ARR LL_TIM_SetAutoReload
<>	144:ef7eb2e8f9f7	1632	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1633	* @param AutoReload between Min_Data=0 and Max_Data=65535
<>	144:ef7eb2e8f9f7	1634	* @retval None
<>	144:ef7eb2e8f9f7	1635	*/
<>	144:ef7eb2e8f9f7	1636	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef * TIMx, uint32_t AutoReload)
<>	144:ef7eb2e8f9f7	1637	{
<>	144:ef7eb2e8f9f7	1638	WRITE_REG(TIMx->ARR, AutoReload);
<>	144:ef7eb2e8f9f7	1639	}
<>	144:ef7eb2e8f9f7	1640
<>	144:ef7eb2e8f9f7	1641	/**
<>	144:ef7eb2e8f9f7	1642	* @brief Get the auto-reload value.
<>	144:ef7eb2e8f9f7	1643	* @rmtoll ARR ARR LL_TIM_GetAutoReload
<>	144:ef7eb2e8f9f7	1644	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1645	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	1646	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1647	* @retval Auto-reload value
<>	144:ef7eb2e8f9f7	1648	*/
<>	144:ef7eb2e8f9f7	1649	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1650	{
<>	144:ef7eb2e8f9f7	1651	return (uint32_t)(READ_REG(TIMx->ARR));
<>	144:ef7eb2e8f9f7	1652	}
<>	144:ef7eb2e8f9f7	1653
<>	144:ef7eb2e8f9f7	1654	/**
<>	144:ef7eb2e8f9f7	1655	* @brief Set the repetition counter value.
<>	144:ef7eb2e8f9f7	1656	* @note For advanced timer instances RepetitionCounter can be up to 65535.
<>	144:ef7eb2e8f9f7	1657	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1658	* whether or not a timer instance supports a repetition counter.
<>	144:ef7eb2e8f9f7	1659	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
<>	144:ef7eb2e8f9f7	1660	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1661	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
<>	144:ef7eb2e8f9f7	1662	* @retval None
<>	144:ef7eb2e8f9f7	1663	*/
<>	144:ef7eb2e8f9f7	1664	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx, uint32_t RepetitionCounter)
<>	144:ef7eb2e8f9f7	1665	{
<>	144:ef7eb2e8f9f7	1666	WRITE_REG(TIMx->RCR, RepetitionCounter);
<>	144:ef7eb2e8f9f7	1667	}
<>	144:ef7eb2e8f9f7	1668
<>	144:ef7eb2e8f9f7	1669	/**
<>	144:ef7eb2e8f9f7	1670	* @brief Get the repetition counter value.
<>	144:ef7eb2e8f9f7	1671	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1672	* whether or not a timer instance supports a repetition counter.
<>	144:ef7eb2e8f9f7	1673	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
<>	144:ef7eb2e8f9f7	1674	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1675	* @retval Repetition counter value
<>	144:ef7eb2e8f9f7	1676	*/
<>	144:ef7eb2e8f9f7	1677	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1678	{
<>	144:ef7eb2e8f9f7	1679	return (uint32_t)(READ_REG(TIMx->RCR));
<>	144:ef7eb2e8f9f7	1680	}
<>	144:ef7eb2e8f9f7	1681
<>	144:ef7eb2e8f9f7	1682	/**
<>	144:ef7eb2e8f9f7	1683	* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
<>	144:ef7eb2e8f9f7	1684	* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
<>	144:ef7eb2e8f9f7	1685	* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
<>	144:ef7eb2e8f9f7	1686	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1687	* @retval None
<>	144:ef7eb2e8f9f7	1688	*/
<>	144:ef7eb2e8f9f7	1689	__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1690	{
<>	144:ef7eb2e8f9f7	1691	SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
<>	144:ef7eb2e8f9f7	1692	}
<>	144:ef7eb2e8f9f7	1693
<>	144:ef7eb2e8f9f7	1694	/**
<>	144:ef7eb2e8f9f7	1695	* @brief Disable update interrupt flag (UIF) remapping.
<>	144:ef7eb2e8f9f7	1696	* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
<>	144:ef7eb2e8f9f7	1697	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1698	* @retval None
<>	144:ef7eb2e8f9f7	1699	*/
<>	144:ef7eb2e8f9f7	1700	__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1701	{
<>	144:ef7eb2e8f9f7	1702	CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
<>	144:ef7eb2e8f9f7	1703	}
<>	144:ef7eb2e8f9f7	1704
<>	144:ef7eb2e8f9f7	1705	/**
<>	144:ef7eb2e8f9f7	1706	* @}
<>	144:ef7eb2e8f9f7	1707	*/
<>	144:ef7eb2e8f9f7	1708
<>	144:ef7eb2e8f9f7	1709	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
<>	144:ef7eb2e8f9f7	1710	* @{
<>	144:ef7eb2e8f9f7	1711	*/
<>	144:ef7eb2e8f9f7	1712	/**
<>	144:ef7eb2e8f9f7	1713	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
<>	144:ef7eb2e8f9f7	1714	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
<>	144:ef7eb2e8f9f7	1715	* they are updated only when a commutation event (COM) occurs.
<>	144:ef7eb2e8f9f7	1716	* @note Only on channels that have a complementary output.
<>	144:ef7eb2e8f9f7	1717	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1718	* whether or not a timer instance is able to generate a commutation event.
<>	144:ef7eb2e8f9f7	1719	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
<>	144:ef7eb2e8f9f7	1720	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1721	* @retval None
<>	144:ef7eb2e8f9f7	1722	*/
<>	144:ef7eb2e8f9f7	1723	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1724	{
<>	144:ef7eb2e8f9f7	1725	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
<>	144:ef7eb2e8f9f7	1726	}
<>	144:ef7eb2e8f9f7	1727
<>	144:ef7eb2e8f9f7	1728	/**
<>	144:ef7eb2e8f9f7	1729	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
<>	144:ef7eb2e8f9f7	1730	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1731	* whether or not a timer instance is able to generate a commutation event.
<>	144:ef7eb2e8f9f7	1732	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
<>	144:ef7eb2e8f9f7	1733	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1734	* @retval None
<>	144:ef7eb2e8f9f7	1735	*/
<>	144:ef7eb2e8f9f7	1736	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1737	{
<>	144:ef7eb2e8f9f7	1738	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
<>	144:ef7eb2e8f9f7	1739	}
<>	144:ef7eb2e8f9f7	1740
<>	144:ef7eb2e8f9f7	1741	/**
<>	144:ef7eb2e8f9f7	1742	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
<>	144:ef7eb2e8f9f7	1743	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	1744	* whether or not a timer instance is able to generate a commutation event.
<>	144:ef7eb2e8f9f7	1745	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
<>	144:ef7eb2e8f9f7	1746	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1747	* @param CCUpdateSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1748	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
<>	144:ef7eb2e8f9f7	1749	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
<>	144:ef7eb2e8f9f7	1750	* @retval None
<>	144:ef7eb2e8f9f7	1751	*/
<>	144:ef7eb2e8f9f7	1752	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx, uint32_t CCUpdateSource)
<>	144:ef7eb2e8f9f7	1753	{
<>	144:ef7eb2e8f9f7	1754	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
<>	144:ef7eb2e8f9f7	1755	}
<>	144:ef7eb2e8f9f7	1756
<>	144:ef7eb2e8f9f7	1757	/**
<>	144:ef7eb2e8f9f7	1758	* @brief Set the trigger of the capture/compare DMA request.
<>	144:ef7eb2e8f9f7	1759	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
<>	144:ef7eb2e8f9f7	1760	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1761	* @param DMAReqTrigger This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1762	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	144:ef7eb2e8f9f7	1763	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	144:ef7eb2e8f9f7	1764	* @retval None
<>	144:ef7eb2e8f9f7	1765	*/
<>	144:ef7eb2e8f9f7	1766	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx, uint32_t DMAReqTrigger)
<>	144:ef7eb2e8f9f7	1767	{
<>	144:ef7eb2e8f9f7	1768	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
<>	144:ef7eb2e8f9f7	1769	}
<>	144:ef7eb2e8f9f7	1770
<>	144:ef7eb2e8f9f7	1771	/**
<>	144:ef7eb2e8f9f7	1772	* @brief Get actual trigger of the capture/compare DMA request.
<>	144:ef7eb2e8f9f7	1773	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
<>	144:ef7eb2e8f9f7	1774	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1775	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1776	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	144:ef7eb2e8f9f7	1777	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	144:ef7eb2e8f9f7	1778	*/
<>	144:ef7eb2e8f9f7	1779	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	1780	{
<>	144:ef7eb2e8f9f7	1781	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
<>	144:ef7eb2e8f9f7	1782	}
<>	144:ef7eb2e8f9f7	1783
<>	144:ef7eb2e8f9f7	1784	/**
<>	144:ef7eb2e8f9f7	1785	* @brief Set the lock level to freeze the
<>	144:ef7eb2e8f9f7	1786	* configuration of several capture/compare parameters.
<>	144:ef7eb2e8f9f7	1787	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	1788	* the lock mechanism is supported by a timer instance.
<>	144:ef7eb2e8f9f7	1789	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
<>	144:ef7eb2e8f9f7	1790	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1791	* @param LockLevel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1792	* @arg @ref LL_TIM_LOCKLEVEL_OFF
<>	144:ef7eb2e8f9f7	1793	* @arg @ref LL_TIM_LOCKLEVEL_1
<>	144:ef7eb2e8f9f7	1794	* @arg @ref LL_TIM_LOCKLEVEL_2
<>	144:ef7eb2e8f9f7	1795	* @arg @ref LL_TIM_LOCKLEVEL_3
<>	144:ef7eb2e8f9f7	1796	* @retval None
<>	144:ef7eb2e8f9f7	1797	*/
<>	144:ef7eb2e8f9f7	1798	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx, uint32_t LockLevel)
<>	144:ef7eb2e8f9f7	1799	{
<>	144:ef7eb2e8f9f7	1800	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
<>	144:ef7eb2e8f9f7	1801	}
<>	144:ef7eb2e8f9f7	1802
<>	144:ef7eb2e8f9f7	1803	/**
<>	144:ef7eb2e8f9f7	1804	* @brief Enable capture/compare channels.
<>	144:ef7eb2e8f9f7	1805	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
<>	144:ef7eb2e8f9f7	1806	* CCER CC1NE LL_TIM_CC_EnableChannel\n
<>	144:ef7eb2e8f9f7	1807	* CCER CC2E LL_TIM_CC_EnableChannel\n
<>	144:ef7eb2e8f9f7	1808	* CCER CC2NE LL_TIM_CC_EnableChannel\n
<>	144:ef7eb2e8f9f7	1809	* CCER CC3E LL_TIM_CC_EnableChannel\n
<>	144:ef7eb2e8f9f7	1810	* CCER CC3NE LL_TIM_CC_EnableChannel\n
<>	144:ef7eb2e8f9f7	1811	* CCER CC4E LL_TIM_CC_EnableChannel\n
<>	144:ef7eb2e8f9f7	1812	* CCER CC5E LL_TIM_CC_EnableChannel\n
<>	144:ef7eb2e8f9f7	1813	* CCER CC6E LL_TIM_CC_EnableChannel
<>	144:ef7eb2e8f9f7	1814	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1815	* @param Channels This parameter can be a combination of the following values:
<>	144:ef7eb2e8f9f7	1816	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	1817	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	144:ef7eb2e8f9f7	1818	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	1819	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	144:ef7eb2e8f9f7	1820	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	1821	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	144:ef7eb2e8f9f7	1822	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	1823	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	1824	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	1825	* @retval None
<>	144:ef7eb2e8f9f7	1826	*/
<>	144:ef7eb2e8f9f7	1827	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx, uint32_t Channels)
<>	144:ef7eb2e8f9f7	1828	{
<>	144:ef7eb2e8f9f7	1829	SET_BIT(TIMx->CCER, Channels);
<>	144:ef7eb2e8f9f7	1830	}
<>	144:ef7eb2e8f9f7	1831
<>	144:ef7eb2e8f9f7	1832	/**
<>	144:ef7eb2e8f9f7	1833	* @brief Disable capture/compare channels.
<>	144:ef7eb2e8f9f7	1834	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
<>	144:ef7eb2e8f9f7	1835	* CCER CC1NE LL_TIM_CC_DisableChannel\n
<>	144:ef7eb2e8f9f7	1836	* CCER CC2E LL_TIM_CC_DisableChannel\n
<>	144:ef7eb2e8f9f7	1837	* CCER CC2NE LL_TIM_CC_DisableChannel\n
<>	144:ef7eb2e8f9f7	1838	* CCER CC3E LL_TIM_CC_DisableChannel\n
<>	144:ef7eb2e8f9f7	1839	* CCER CC3NE LL_TIM_CC_DisableChannel\n
<>	144:ef7eb2e8f9f7	1840	* CCER CC4E LL_TIM_CC_DisableChannel\n
<>	144:ef7eb2e8f9f7	1841	* CCER CC5E LL_TIM_CC_DisableChannel\n
<>	144:ef7eb2e8f9f7	1842	* CCER CC6E LL_TIM_CC_DisableChannel
<>	144:ef7eb2e8f9f7	1843	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1844	* @param Channels This parameter can be a combination of the following values:
<>	144:ef7eb2e8f9f7	1845	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	1846	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	144:ef7eb2e8f9f7	1847	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	1848	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	144:ef7eb2e8f9f7	1849	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	1850	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	144:ef7eb2e8f9f7	1851	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	1852	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	1853	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	1854	* @retval None
<>	144:ef7eb2e8f9f7	1855	*/
<>	144:ef7eb2e8f9f7	1856	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx, uint32_t Channels)
<>	144:ef7eb2e8f9f7	1857	{
<>	144:ef7eb2e8f9f7	1858	CLEAR_BIT(TIMx->CCER, Channels);
<>	144:ef7eb2e8f9f7	1859	}
<>	144:ef7eb2e8f9f7	1860
<>	144:ef7eb2e8f9f7	1861	/**
<>	144:ef7eb2e8f9f7	1862	* @brief Indicate whether channel(s) is(are) enabled.
<>	144:ef7eb2e8f9f7	1863	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
<>	144:ef7eb2e8f9f7	1864	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
<>	144:ef7eb2e8f9f7	1865	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
<>	144:ef7eb2e8f9f7	1866	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
<>	144:ef7eb2e8f9f7	1867	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
<>	144:ef7eb2e8f9f7	1868	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
<>	144:ef7eb2e8f9f7	1869	* CCER CC4E LL_TIM_CC_IsEnabledChannel\n
<>	144:ef7eb2e8f9f7	1870	* CCER CC5E LL_TIM_CC_IsEnabledChannel\n
<>	144:ef7eb2e8f9f7	1871	* CCER CC6E LL_TIM_CC_IsEnabledChannel
<>	144:ef7eb2e8f9f7	1872	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1873	* @param Channels This parameter can be a combination of the following values:
<>	144:ef7eb2e8f9f7	1874	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	1875	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	144:ef7eb2e8f9f7	1876	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	1877	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	144:ef7eb2e8f9f7	1878	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	1879	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	144:ef7eb2e8f9f7	1880	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	1881	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	1882	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	1883	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	1884	*/
<>	144:ef7eb2e8f9f7	1885	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx, uint32_t Channels)
<>	144:ef7eb2e8f9f7	1886	{
<>	144:ef7eb2e8f9f7	1887	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
<>	144:ef7eb2e8f9f7	1888	}
<>	144:ef7eb2e8f9f7	1889
<>	144:ef7eb2e8f9f7	1890	/**
<>	144:ef7eb2e8f9f7	1891	* @}
<>	144:ef7eb2e8f9f7	1892	*/
<>	144:ef7eb2e8f9f7	1893
<>	144:ef7eb2e8f9f7	1894	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
<>	144:ef7eb2e8f9f7	1895	* @{
<>	144:ef7eb2e8f9f7	1896	*/
<>	144:ef7eb2e8f9f7	1897	/**
<>	144:ef7eb2e8f9f7	1898	* @brief Configure an output channel.
<>	144:ef7eb2e8f9f7	1899	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1900	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1901	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1902	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1903	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1904	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1905	* CCER CC1P LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1906	* CCER CC2P LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1907	* CCER CC3P LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1908	* CCER CC4P LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1909	* CCER CC5P LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1910	* CCER CC6P LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1911	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1912	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1913	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1914	* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1915	* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
<>	144:ef7eb2e8f9f7	1916	* CR2 OIS6 LL_TIM_OC_ConfigOutput
<>	144:ef7eb2e8f9f7	1917	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1918	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1919	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	1920	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	1921	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	1922	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	1923	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	1924	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	1925	* @param Configuration This parameter must be a combination of all the following values:
<>	144:ef7eb2e8f9f7	1926	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
<>	144:ef7eb2e8f9f7	1927	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
<>	144:ef7eb2e8f9f7	1928	* @retval None
<>	144:ef7eb2e8f9f7	1929	*/
<>	144:ef7eb2e8f9f7	1930	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration)
<>	144:ef7eb2e8f9f7	1931	{
<>	144:ef7eb2e8f9f7	1932	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	1933	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	1934	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
<>	144:ef7eb2e8f9f7	1935	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
<>	144:ef7eb2e8f9f7	1936	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
<>	144:ef7eb2e8f9f7	1937	}
<>	144:ef7eb2e8f9f7	1938
<>	144:ef7eb2e8f9f7	1939	/**
<>	144:ef7eb2e8f9f7	1940	* @brief Define the behavior of the output reference signal OCxREF from which
<>	144:ef7eb2e8f9f7	1941	* OCx and OCxN (when relevant) are derived.
<>	144:ef7eb2e8f9f7	1942	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
<>	144:ef7eb2e8f9f7	1943	* CCMR1 OC2M LL_TIM_OC_SetMode\n
<>	144:ef7eb2e8f9f7	1944	* CCMR2 OC3M LL_TIM_OC_SetMode\n
<>	144:ef7eb2e8f9f7	1945	* CCMR2 OC4M LL_TIM_OC_SetMode\n
<>	144:ef7eb2e8f9f7	1946	* CCMR3 OC5M LL_TIM_OC_SetMode\n
<>	144:ef7eb2e8f9f7	1947	* CCMR3 OC6M LL_TIM_OC_SetMode
<>	144:ef7eb2e8f9f7	1948	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1949	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1950	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	1951	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	1952	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	1953	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	1954	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	1955	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	1956	* @param Mode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1957	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	144:ef7eb2e8f9f7	1958	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	144:ef7eb2e8f9f7	1959	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	144:ef7eb2e8f9f7	1960	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	144:ef7eb2e8f9f7	1961	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	144:ef7eb2e8f9f7	1962	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	144:ef7eb2e8f9f7	1963	* @arg @ref LL_TIM_OCMODE_PWM1
<>	144:ef7eb2e8f9f7	1964	* @arg @ref LL_TIM_OCMODE_PWM2
<>	144:ef7eb2e8f9f7	1965	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
<>	144:ef7eb2e8f9f7	1966	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
<>	144:ef7eb2e8f9f7	1967	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
<>	144:ef7eb2e8f9f7	1968	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
<>	144:ef7eb2e8f9f7	1969	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
<>	144:ef7eb2e8f9f7	1970	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
<>	144:ef7eb2e8f9f7	1971	* @retval None
<>	144:ef7eb2e8f9f7	1972	*/
<>	144:ef7eb2e8f9f7	1973	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Mode)
<>	144:ef7eb2e8f9f7	1974	{
<>	144:ef7eb2e8f9f7	1975	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	1976	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	1977	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
<>	144:ef7eb2e8f9f7	1978	}
<>	144:ef7eb2e8f9f7	1979
<>	144:ef7eb2e8f9f7	1980	/**
<>	144:ef7eb2e8f9f7	1981	* @brief Get the output compare mode of an output channel.
<>	144:ef7eb2e8f9f7	1982	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
<>	144:ef7eb2e8f9f7	1983	* CCMR1 OC2M LL_TIM_OC_GetMode\n
<>	144:ef7eb2e8f9f7	1984	* CCMR2 OC3M LL_TIM_OC_GetMode\n
<>	144:ef7eb2e8f9f7	1985	* CCMR2 OC4M LL_TIM_OC_GetMode\n
<>	144:ef7eb2e8f9f7	1986	* CCMR3 OC5M LL_TIM_OC_GetMode\n
<>	144:ef7eb2e8f9f7	1987	* CCMR3 OC6M LL_TIM_OC_GetMode
<>	144:ef7eb2e8f9f7	1988	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	1989	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1990	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	1991	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	1992	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	1993	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	1994	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	1995	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	1996	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1997	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	144:ef7eb2e8f9f7	1998	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	144:ef7eb2e8f9f7	1999	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	144:ef7eb2e8f9f7	2000	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	144:ef7eb2e8f9f7	2001	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	144:ef7eb2e8f9f7	2002	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	144:ef7eb2e8f9f7	2003	* @arg @ref LL_TIM_OCMODE_PWM1
<>	144:ef7eb2e8f9f7	2004	* @arg @ref LL_TIM_OCMODE_PWM2
<>	144:ef7eb2e8f9f7	2005	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
<>	144:ef7eb2e8f9f7	2006	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
<>	144:ef7eb2e8f9f7	2007	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
<>	144:ef7eb2e8f9f7	2008	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
<>	144:ef7eb2e8f9f7	2009	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
<>	144:ef7eb2e8f9f7	2010	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
<>	144:ef7eb2e8f9f7	2011	*/
<>	144:ef7eb2e8f9f7	2012	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2013	{
<>	144:ef7eb2e8f9f7	2014	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2015	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2016	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
<>	144:ef7eb2e8f9f7	2017	}
<>	144:ef7eb2e8f9f7	2018
<>	144:ef7eb2e8f9f7	2019	/**
<>	144:ef7eb2e8f9f7	2020	* @brief Set the polarity of an output channel.
<>	144:ef7eb2e8f9f7	2021	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2022	* CCER CC1NP LL_TIM_OC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2023	* CCER CC2P LL_TIM_OC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2024	* CCER CC2NP LL_TIM_OC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2025	* CCER CC3P LL_TIM_OC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2026	* CCER CC3NP LL_TIM_OC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2027	* CCER CC4P LL_TIM_OC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2028	* CCER CC5P LL_TIM_OC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2029	* CCER CC6P LL_TIM_OC_SetPolarity
<>	144:ef7eb2e8f9f7	2030	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2031	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2032	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2033	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	144:ef7eb2e8f9f7	2034	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2035	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	144:ef7eb2e8f9f7	2036	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2037	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	144:ef7eb2e8f9f7	2038	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2039	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2040	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2041	* @param Polarity This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2042	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	144:ef7eb2e8f9f7	2043	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	144:ef7eb2e8f9f7	2044	* @retval None
<>	144:ef7eb2e8f9f7	2045	*/
<>	144:ef7eb2e8f9f7	2046	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Polarity)
<>	144:ef7eb2e8f9f7	2047	{
<>	144:ef7eb2e8f9f7	2048	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2049	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
<>	144:ef7eb2e8f9f7	2050	}
<>	144:ef7eb2e8f9f7	2051
<>	144:ef7eb2e8f9f7	2052	/**
<>	144:ef7eb2e8f9f7	2053	* @brief Get the polarity of an output channel.
<>	144:ef7eb2e8f9f7	2054	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2055	* CCER CC1NP LL_TIM_OC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2056	* CCER CC2P LL_TIM_OC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2057	* CCER CC2NP LL_TIM_OC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2058	* CCER CC3P LL_TIM_OC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2059	* CCER CC3NP LL_TIM_OC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2060	* CCER CC4P LL_TIM_OC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2061	* CCER CC5P LL_TIM_OC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2062	* CCER CC6P LL_TIM_OC_GetPolarity
<>	144:ef7eb2e8f9f7	2063	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2064	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2065	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2066	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	144:ef7eb2e8f9f7	2067	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2068	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	144:ef7eb2e8f9f7	2069	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2070	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	144:ef7eb2e8f9f7	2071	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2072	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2073	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2074	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2075	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	144:ef7eb2e8f9f7	2076	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	144:ef7eb2e8f9f7	2077	*/
<>	144:ef7eb2e8f9f7	2078	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2079	{
<>	144:ef7eb2e8f9f7	2080	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2081	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
<>	144:ef7eb2e8f9f7	2082	}
<>	144:ef7eb2e8f9f7	2083
<>	144:ef7eb2e8f9f7	2084	/**
<>	144:ef7eb2e8f9f7	2085	* @brief Set the IDLE state of an output channel
<>	144:ef7eb2e8f9f7	2086	* @note This function is significant only for the timer instances
<>	144:ef7eb2e8f9f7	2087	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
<>	144:ef7eb2e8f9f7	2088	* can be used to check whether or not a timer instance provides
<>	144:ef7eb2e8f9f7	2089	* a break input.
<>	144:ef7eb2e8f9f7	2090	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
<>	144:ef7eb2e8f9f7	2091	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
<>	144:ef7eb2e8f9f7	2092	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
<>	144:ef7eb2e8f9f7	2093	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
<>	144:ef7eb2e8f9f7	2094	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
<>	144:ef7eb2e8f9f7	2095	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
<>	144:ef7eb2e8f9f7	2096	* CR2 OIS4 LL_TIM_OC_SetIdleState\n
<>	144:ef7eb2e8f9f7	2097	* CR2 OIS5 LL_TIM_OC_SetIdleState\n
<>	144:ef7eb2e8f9f7	2098	* CR2 OIS6 LL_TIM_OC_SetIdleState
<>	144:ef7eb2e8f9f7	2099	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2100	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2101	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2102	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	144:ef7eb2e8f9f7	2103	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2104	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	144:ef7eb2e8f9f7	2105	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2106	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	144:ef7eb2e8f9f7	2107	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2108	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2109	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2110	* @param IdleState This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2111	* @arg @ref LL_TIM_OCIDLESTATE_LOW
<>	144:ef7eb2e8f9f7	2112	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
<>	144:ef7eb2e8f9f7	2113	* @retval None
<>	144:ef7eb2e8f9f7	2114	*/
<>	144:ef7eb2e8f9f7	2115	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t IdleState)
<>	144:ef7eb2e8f9f7	2116	{
<>	144:ef7eb2e8f9f7	2117	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2118	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
<>	144:ef7eb2e8f9f7	2119	}
<>	144:ef7eb2e8f9f7	2120
<>	144:ef7eb2e8f9f7	2121	/**
<>	144:ef7eb2e8f9f7	2122	* @brief Get the IDLE state of an output channel
<>	144:ef7eb2e8f9f7	2123	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
<>	144:ef7eb2e8f9f7	2124	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
<>	144:ef7eb2e8f9f7	2125	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
<>	144:ef7eb2e8f9f7	2126	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
<>	144:ef7eb2e8f9f7	2127	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
<>	144:ef7eb2e8f9f7	2128	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
<>	144:ef7eb2e8f9f7	2129	* CR2 OIS4 LL_TIM_OC_GetIdleState\n
<>	144:ef7eb2e8f9f7	2130	* CR2 OIS5 LL_TIM_OC_GetIdleState\n
<>	144:ef7eb2e8f9f7	2131	* CR2 OIS6 LL_TIM_OC_GetIdleState
<>	144:ef7eb2e8f9f7	2132	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2133	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2134	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2135	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	144:ef7eb2e8f9f7	2136	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2137	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	144:ef7eb2e8f9f7	2138	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2139	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	144:ef7eb2e8f9f7	2140	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2141	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2142	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2143	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2144	* @arg @ref LL_TIM_OCIDLESTATE_LOW
<>	144:ef7eb2e8f9f7	2145	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
<>	144:ef7eb2e8f9f7	2146	*/
<>	144:ef7eb2e8f9f7	2147	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2148	{
<>	144:ef7eb2e8f9f7	2149	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2150	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
<>	144:ef7eb2e8f9f7	2151	}
<>	144:ef7eb2e8f9f7	2152
<>	144:ef7eb2e8f9f7	2153	/**
<>	144:ef7eb2e8f9f7	2154	* @brief Enable fast mode for the output channel.
<>	144:ef7eb2e8f9f7	2155	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
<>	144:ef7eb2e8f9f7	2156	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
<>	144:ef7eb2e8f9f7	2157	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
<>	144:ef7eb2e8f9f7	2158	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
<>	144:ef7eb2e8f9f7	2159	* CCMR2 OC4FE LL_TIM_OC_EnableFast\n
<>	144:ef7eb2e8f9f7	2160	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
<>	144:ef7eb2e8f9f7	2161	* CCMR3 OC6FE LL_TIM_OC_EnableFast
<>	144:ef7eb2e8f9f7	2162	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2163	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2164	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2165	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2166	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2167	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2168	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2169	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2170	* @retval None
<>	144:ef7eb2e8f9f7	2171	*/
<>	144:ef7eb2e8f9f7	2172	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2173	{
<>	144:ef7eb2e8f9f7	2174	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2175	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2176	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	144:ef7eb2e8f9f7	2177
<>	144:ef7eb2e8f9f7	2178	}
<>	144:ef7eb2e8f9f7	2179
<>	144:ef7eb2e8f9f7	2180	/**
<>	144:ef7eb2e8f9f7	2181	* @brief Disable fast mode for the output channel.
<>	144:ef7eb2e8f9f7	2182	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
<>	144:ef7eb2e8f9f7	2183	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
<>	144:ef7eb2e8f9f7	2184	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
<>	144:ef7eb2e8f9f7	2185	* CCMR2 OC4FE LL_TIM_OC_DisableFast\n
<>	144:ef7eb2e8f9f7	2186	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
<>	144:ef7eb2e8f9f7	2187	* CCMR3 OC6FE LL_TIM_OC_DisableFast
<>	144:ef7eb2e8f9f7	2188	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2189	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2190	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2191	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2192	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2193	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2194	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2195	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2196	* @retval None
<>	144:ef7eb2e8f9f7	2197	*/
<>	144:ef7eb2e8f9f7	2198	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2199	{
<>	144:ef7eb2e8f9f7	2200	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2201	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2202	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	144:ef7eb2e8f9f7	2203
<>	144:ef7eb2e8f9f7	2204	}
<>	144:ef7eb2e8f9f7	2205
<>	144:ef7eb2e8f9f7	2206	/**
<>	144:ef7eb2e8f9f7	2207	* @brief Indicates whether fast mode is enabled for the output channel.
<>	144:ef7eb2e8f9f7	2208	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
<>	144:ef7eb2e8f9f7	2209	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
<>	144:ef7eb2e8f9f7	2210	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
<>	144:ef7eb2e8f9f7	2211	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
<>	144:ef7eb2e8f9f7	2212	* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
<>	144:ef7eb2e8f9f7	2213	* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
<>	144:ef7eb2e8f9f7	2214	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2215	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2216	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2217	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2218	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2219	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2220	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2221	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2222	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2223	*/
<>	144:ef7eb2e8f9f7	2224	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2225	{
<>	144:ef7eb2e8f9f7	2226	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2227	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2228	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
<>	144:ef7eb2e8f9f7	2229	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	144:ef7eb2e8f9f7	2230	}
<>	144:ef7eb2e8f9f7	2231
<>	144:ef7eb2e8f9f7	2232	/**
<>	144:ef7eb2e8f9f7	2233	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
<>	144:ef7eb2e8f9f7	2234	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
<>	144:ef7eb2e8f9f7	2235	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
<>	144:ef7eb2e8f9f7	2236	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
<>	144:ef7eb2e8f9f7	2237	* CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
<>	144:ef7eb2e8f9f7	2238	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
<>	144:ef7eb2e8f9f7	2239	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
<>	144:ef7eb2e8f9f7	2240	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2241	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2242	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2243	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2244	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2245	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2246	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2247	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2248	* @retval None
<>	144:ef7eb2e8f9f7	2249	*/
<>	144:ef7eb2e8f9f7	2250	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2251	{
<>	144:ef7eb2e8f9f7	2252	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2253	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2254	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	144:ef7eb2e8f9f7	2255	}
<>	144:ef7eb2e8f9f7	2256
<>	144:ef7eb2e8f9f7	2257	/**
<>	144:ef7eb2e8f9f7	2258	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
<>	144:ef7eb2e8f9f7	2259	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
<>	144:ef7eb2e8f9f7	2260	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
<>	144:ef7eb2e8f9f7	2261	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
<>	144:ef7eb2e8f9f7	2262	* CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
<>	144:ef7eb2e8f9f7	2263	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
<>	144:ef7eb2e8f9f7	2264	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
<>	144:ef7eb2e8f9f7	2265	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2266	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2267	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2268	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2269	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2270	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2271	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2272	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2273	* @retval None
<>	144:ef7eb2e8f9f7	2274	*/
<>	144:ef7eb2e8f9f7	2275	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2276	{
<>	144:ef7eb2e8f9f7	2277	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2278	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2279	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	144:ef7eb2e8f9f7	2280	}
<>	144:ef7eb2e8f9f7	2281
<>	144:ef7eb2e8f9f7	2282	/**
<>	144:ef7eb2e8f9f7	2283	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
<>	144:ef7eb2e8f9f7	2284	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
<>	144:ef7eb2e8f9f7	2285	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
<>	144:ef7eb2e8f9f7	2286	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
<>	144:ef7eb2e8f9f7	2287	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
<>	144:ef7eb2e8f9f7	2288	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
<>	144:ef7eb2e8f9f7	2289	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
<>	144:ef7eb2e8f9f7	2290	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2291	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2292	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2293	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2294	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2295	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2296	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2297	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2298	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2299	*/
<>	144:ef7eb2e8f9f7	2300	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2301	{
<>	144:ef7eb2e8f9f7	2302	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2303	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2304	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
<>	144:ef7eb2e8f9f7	2305	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	144:ef7eb2e8f9f7	2306	}
<>	144:ef7eb2e8f9f7	2307
<>	144:ef7eb2e8f9f7	2308	/**
<>	144:ef7eb2e8f9f7	2309	* @brief Enable clearing the output channel on an external event.
<>	144:ef7eb2e8f9f7	2310	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	144:ef7eb2e8f9f7	2311	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	144:ef7eb2e8f9f7	2312	* or not a timer instance can clear the OCxREF signal on an external event.
<>	144:ef7eb2e8f9f7	2313	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
<>	144:ef7eb2e8f9f7	2314	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
<>	144:ef7eb2e8f9f7	2315	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
<>	144:ef7eb2e8f9f7	2316	* CCMR2 OC4CE LL_TIM_OC_EnableClear\n
<>	144:ef7eb2e8f9f7	2317	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
<>	144:ef7eb2e8f9f7	2318	* CCMR3 OC6CE LL_TIM_OC_EnableClear
<>	144:ef7eb2e8f9f7	2319	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2320	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2321	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2322	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2323	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2324	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2325	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2326	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2327	* @retval None
<>	144:ef7eb2e8f9f7	2328	*/
<>	144:ef7eb2e8f9f7	2329	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2330	{
<>	144:ef7eb2e8f9f7	2331	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2332	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2333	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	144:ef7eb2e8f9f7	2334	}
<>	144:ef7eb2e8f9f7	2335
<>	144:ef7eb2e8f9f7	2336	/**
<>	144:ef7eb2e8f9f7	2337	* @brief Disable clearing the output channel on an external event.
<>	144:ef7eb2e8f9f7	2338	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	144:ef7eb2e8f9f7	2339	* or not a timer instance can clear the OCxREF signal on an external event.
<>	144:ef7eb2e8f9f7	2340	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
<>	144:ef7eb2e8f9f7	2341	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
<>	144:ef7eb2e8f9f7	2342	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
<>	144:ef7eb2e8f9f7	2343	* CCMR2 OC4CE LL_TIM_OC_DisableClear\n
<>	144:ef7eb2e8f9f7	2344	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
<>	144:ef7eb2e8f9f7	2345	* CCMR3 OC6CE LL_TIM_OC_DisableClear
<>	144:ef7eb2e8f9f7	2346	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2347	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2348	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2349	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2350	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2351	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2352	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2353	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2354	* @retval None
<>	144:ef7eb2e8f9f7	2355	*/
<>	144:ef7eb2e8f9f7	2356	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2357	{
<>	144:ef7eb2e8f9f7	2358	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2359	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2360	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	144:ef7eb2e8f9f7	2361	}
<>	144:ef7eb2e8f9f7	2362
<>	144:ef7eb2e8f9f7	2363	/**
<>	144:ef7eb2e8f9f7	2364	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
<>	144:ef7eb2e8f9f7	2365	* @note This function enables clearing the output channel on an external event.
<>	144:ef7eb2e8f9f7	2366	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	144:ef7eb2e8f9f7	2367	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	144:ef7eb2e8f9f7	2368	* or not a timer instance can clear the OCxREF signal on an external event.
<>	144:ef7eb2e8f9f7	2369	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
<>	144:ef7eb2e8f9f7	2370	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
<>	144:ef7eb2e8f9f7	2371	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
<>	144:ef7eb2e8f9f7	2372	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
<>	144:ef7eb2e8f9f7	2373	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
<>	144:ef7eb2e8f9f7	2374	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
<>	144:ef7eb2e8f9f7	2375	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2376	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2377	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2378	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2379	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2380	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2381	* @arg @ref LL_TIM_CHANNEL_CH5
<>	144:ef7eb2e8f9f7	2382	* @arg @ref LL_TIM_CHANNEL_CH6
<>	144:ef7eb2e8f9f7	2383	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2384	*/
<>	144:ef7eb2e8f9f7	2385	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2386	{
<>	144:ef7eb2e8f9f7	2387	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2388	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2389	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
<>	144:ef7eb2e8f9f7	2390	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	144:ef7eb2e8f9f7	2391	}
<>	144:ef7eb2e8f9f7	2392
<>	144:ef7eb2e8f9f7	2393	/**
<>	144:ef7eb2e8f9f7	2394	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
<>	144:ef7eb2e8f9f7	2395	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2396	* dead-time insertion feature is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2397	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
<>	144:ef7eb2e8f9f7	2398	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
<>	144:ef7eb2e8f9f7	2399	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2400	* @param DeadTime between Min_Data=0 and Max_Data=255
<>	144:ef7eb2e8f9f7	2401	* @retval None
<>	144:ef7eb2e8f9f7	2402	*/
<>	144:ef7eb2e8f9f7	2403	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx, uint32_t DeadTime)
<>	144:ef7eb2e8f9f7	2404	{
<>	144:ef7eb2e8f9f7	2405	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
<>	144:ef7eb2e8f9f7	2406	}
<>	144:ef7eb2e8f9f7	2407
<>	144:ef7eb2e8f9f7	2408	/**
<>	144:ef7eb2e8f9f7	2409	* @brief Set compare value for output channel 1 (TIMx_CCR1).
<>	144:ef7eb2e8f9f7	2410	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2411	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2412	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2413	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2414	* output channel 1 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2415	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
<>	144:ef7eb2e8f9f7	2416	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2417	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	144:ef7eb2e8f9f7	2418	* @retval None
<>	144:ef7eb2e8f9f7	2419	*/
<>	144:ef7eb2e8f9f7	2420	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx, uint32_t CompareValue)
<>	144:ef7eb2e8f9f7	2421	{
<>	144:ef7eb2e8f9f7	2422	WRITE_REG(TIMx->CCR1, CompareValue);
<>	144:ef7eb2e8f9f7	2423	}
<>	144:ef7eb2e8f9f7	2424
<>	144:ef7eb2e8f9f7	2425	/**
<>	144:ef7eb2e8f9f7	2426	* @brief Set compare value for output channel 2 (TIMx_CCR2).
<>	144:ef7eb2e8f9f7	2427	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2428	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2429	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2430	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2431	* output channel 2 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2432	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
<>	144:ef7eb2e8f9f7	2433	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2434	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	144:ef7eb2e8f9f7	2435	* @retval None
<>	144:ef7eb2e8f9f7	2436	*/
<>	144:ef7eb2e8f9f7	2437	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx, uint32_t CompareValue)
<>	144:ef7eb2e8f9f7	2438	{
<>	144:ef7eb2e8f9f7	2439	WRITE_REG(TIMx->CCR2, CompareValue);
<>	144:ef7eb2e8f9f7	2440	}
<>	144:ef7eb2e8f9f7	2441
<>	144:ef7eb2e8f9f7	2442	/**
<>	144:ef7eb2e8f9f7	2443	* @brief Set compare value for output channel 3 (TIMx_CCR3).
<>	144:ef7eb2e8f9f7	2444	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2445	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2446	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2447	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2448	* output channel is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2449	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
<>	144:ef7eb2e8f9f7	2450	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2451	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	144:ef7eb2e8f9f7	2452	* @retval None
<>	144:ef7eb2e8f9f7	2453	*/
<>	144:ef7eb2e8f9f7	2454	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx, uint32_t CompareValue)
<>	144:ef7eb2e8f9f7	2455	{
<>	144:ef7eb2e8f9f7	2456	WRITE_REG(TIMx->CCR3, CompareValue);
<>	144:ef7eb2e8f9f7	2457	}
<>	144:ef7eb2e8f9f7	2458
<>	144:ef7eb2e8f9f7	2459	/**
<>	144:ef7eb2e8f9f7	2460	* @brief Set compare value for output channel 4 (TIMx_CCR4).
<>	144:ef7eb2e8f9f7	2461	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2462	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2463	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2464	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2465	* output channel 4 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2466	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
<>	144:ef7eb2e8f9f7	2467	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2468	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	144:ef7eb2e8f9f7	2469	* @retval None
<>	144:ef7eb2e8f9f7	2470	*/
<>	144:ef7eb2e8f9f7	2471	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx, uint32_t CompareValue)
<>	144:ef7eb2e8f9f7	2472	{
<>	144:ef7eb2e8f9f7	2473	WRITE_REG(TIMx->CCR4, CompareValue);
<>	144:ef7eb2e8f9f7	2474	}
<>	144:ef7eb2e8f9f7	2475
<>	144:ef7eb2e8f9f7	2476	/**
<>	144:ef7eb2e8f9f7	2477	* @brief Set compare value for output channel 5 (TIMx_CCR5).
<>	144:ef7eb2e8f9f7	2478	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2479	* output channel 5 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2480	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
<>	144:ef7eb2e8f9f7	2481	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2482	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	144:ef7eb2e8f9f7	2483	* @retval None
<>	144:ef7eb2e8f9f7	2484	*/
<>	144:ef7eb2e8f9f7	2485	__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx, uint32_t CompareValue)
<>	144:ef7eb2e8f9f7	2486	{
<>	144:ef7eb2e8f9f7	2487	WRITE_REG(TIMx->CCR5, CompareValue);
<>	144:ef7eb2e8f9f7	2488	}
<>	144:ef7eb2e8f9f7	2489
<>	144:ef7eb2e8f9f7	2490	/**
<>	144:ef7eb2e8f9f7	2491	* @brief Set compare value for output channel 6 (TIMx_CCR6).
<>	144:ef7eb2e8f9f7	2492	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2493	* output channel 6 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2494	* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
<>	144:ef7eb2e8f9f7	2495	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2496	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	144:ef7eb2e8f9f7	2497	* @retval None
<>	144:ef7eb2e8f9f7	2498	*/
<>	144:ef7eb2e8f9f7	2499	__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx, uint32_t CompareValue)
<>	144:ef7eb2e8f9f7	2500	{
<>	144:ef7eb2e8f9f7	2501	WRITE_REG(TIMx->CCR6, CompareValue);
<>	144:ef7eb2e8f9f7	2502	}
<>	144:ef7eb2e8f9f7	2503
<>	144:ef7eb2e8f9f7	2504	/**
<>	144:ef7eb2e8f9f7	2505	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
<>	144:ef7eb2e8f9f7	2506	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2507	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2508	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2509	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2510	* output channel 1 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2511	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
<>	144:ef7eb2e8f9f7	2512	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2513	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	2514	*/
<>	144:ef7eb2e8f9f7	2515	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2516	{
<>	144:ef7eb2e8f9f7	2517	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	144:ef7eb2e8f9f7	2518	}
<>	144:ef7eb2e8f9f7	2519
<>	144:ef7eb2e8f9f7	2520	/**
<>	144:ef7eb2e8f9f7	2521	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
<>	144:ef7eb2e8f9f7	2522	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2523	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2524	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2525	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2526	* output channel 2 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2527	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
<>	144:ef7eb2e8f9f7	2528	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2529	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	2530	*/
<>	144:ef7eb2e8f9f7	2531	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2532	{
<>	144:ef7eb2e8f9f7	2533	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	144:ef7eb2e8f9f7	2534	}
<>	144:ef7eb2e8f9f7	2535
<>	144:ef7eb2e8f9f7	2536	/**
<>	144:ef7eb2e8f9f7	2537	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
<>	144:ef7eb2e8f9f7	2538	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2539	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2540	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2541	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2542	* output channel 3 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2543	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
<>	144:ef7eb2e8f9f7	2544	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2545	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	2546	*/
<>	144:ef7eb2e8f9f7	2547	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2548	{
<>	144:ef7eb2e8f9f7	2549	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	144:ef7eb2e8f9f7	2550	}
<>	144:ef7eb2e8f9f7	2551
<>	144:ef7eb2e8f9f7	2552	/**
<>	144:ef7eb2e8f9f7	2553	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
<>	144:ef7eb2e8f9f7	2554	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2555	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2556	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2557	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2558	* output channel 4 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2559	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
<>	144:ef7eb2e8f9f7	2560	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2561	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	2562	*/
<>	144:ef7eb2e8f9f7	2563	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2564	{
<>	144:ef7eb2e8f9f7	2565	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	144:ef7eb2e8f9f7	2566	}
<>	144:ef7eb2e8f9f7	2567
<>	144:ef7eb2e8f9f7	2568	/**
<>	144:ef7eb2e8f9f7	2569	* @brief Get compare value (TIMx_CCR5) set for output channel 5.
<>	144:ef7eb2e8f9f7	2570	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2571	* output channel 5 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2572	* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
<>	144:ef7eb2e8f9f7	2573	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2574	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	2575	*/
<>	144:ef7eb2e8f9f7	2576	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2577	{
<>	144:ef7eb2e8f9f7	2578	return (uint32_t)(READ_REG(TIMx->CCR5));
<>	144:ef7eb2e8f9f7	2579	}
<>	144:ef7eb2e8f9f7	2580
<>	144:ef7eb2e8f9f7	2581	/**
<>	144:ef7eb2e8f9f7	2582	* @brief Get compare value (TIMx_CCR6) set for output channel 6.
<>	144:ef7eb2e8f9f7	2583	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2584	* output channel 6 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2585	* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
<>	144:ef7eb2e8f9f7	2586	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2587	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	2588	*/
<>	144:ef7eb2e8f9f7	2589	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2590	{
<>	144:ef7eb2e8f9f7	2591	return (uint32_t)(READ_REG(TIMx->CCR6));
<>	144:ef7eb2e8f9f7	2592	}
<>	144:ef7eb2e8f9f7	2593
<>	144:ef7eb2e8f9f7	2594	/**
<>	144:ef7eb2e8f9f7	2595	* @brief Select on which reference signal the OC5REF is combined to.
<>	144:ef7eb2e8f9f7	2596	* @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2597	* whether or not a timer instance supports the combined 3-phase PWM mode.
<>	144:ef7eb2e8f9f7	2598	* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
<>	144:ef7eb2e8f9f7	2599	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
<>	144:ef7eb2e8f9f7	2600	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
<>	144:ef7eb2e8f9f7	2601	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2602	* @param GroupCH5 This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2603	* @arg @ref LL_TIM_GROUPCH5_NONE
<>	144:ef7eb2e8f9f7	2604	* @arg @ref LL_TIM_GROUPCH5_OC1REFC
<>	144:ef7eb2e8f9f7	2605	* @arg @ref LL_TIM_GROUPCH5_OC2REFC
<>	144:ef7eb2e8f9f7	2606	* @arg @ref LL_TIM_GROUPCH5_OC3REFC
<>	144:ef7eb2e8f9f7	2607	* @retval None
<>	144:ef7eb2e8f9f7	2608	*/
<>	144:ef7eb2e8f9f7	2609	__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx, uint32_t GroupCH5)
<>	144:ef7eb2e8f9f7	2610	{
<>	144:ef7eb2e8f9f7	2611	MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
<>	144:ef7eb2e8f9f7	2612	}
<>	144:ef7eb2e8f9f7	2613
<>	144:ef7eb2e8f9f7	2614	/**
<>	144:ef7eb2e8f9f7	2615	* @}
<>	144:ef7eb2e8f9f7	2616	*/
<>	144:ef7eb2e8f9f7	2617
<>	144:ef7eb2e8f9f7	2618	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
<>	144:ef7eb2e8f9f7	2619	* @{
<>	144:ef7eb2e8f9f7	2620	*/
<>	144:ef7eb2e8f9f7	2621	/**
<>	144:ef7eb2e8f9f7	2622	* @brief Configure input channel.
<>	144:ef7eb2e8f9f7	2623	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2624	* CCMR1 IC1PSC LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2625	* CCMR1 IC1F LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2626	* CCMR1 CC2S LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2627	* CCMR1 IC2PSC LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2628	* CCMR1 IC2F LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2629	* CCMR2 CC3S LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2630	* CCMR2 IC3PSC LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2631	* CCMR2 IC3F LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2632	* CCMR2 CC4S LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2633	* CCMR2 IC4PSC LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2634	* CCMR2 IC4F LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2635	* CCER CC1P LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2636	* CCER CC1NP LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2637	* CCER CC2P LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2638	* CCER CC2NP LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2639	* CCER CC3P LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2640	* CCER CC3NP LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2641	* CCER CC4P LL_TIM_IC_Config\n
<>	144:ef7eb2e8f9f7	2642	* CCER CC4NP LL_TIM_IC_Config
<>	144:ef7eb2e8f9f7	2643	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2644	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2645	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2646	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2647	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2648	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2649	* @param Configuration This parameter must be a combination of all the following values:
<>	144:ef7eb2e8f9f7	2650	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
<>	144:ef7eb2e8f9f7	2651	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
<>	144:ef7eb2e8f9f7	2652	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	144:ef7eb2e8f9f7	2653	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	2654	* @retval None
<>	144:ef7eb2e8f9f7	2655	*/
<>	144:ef7eb2e8f9f7	2656	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration)
<>	144:ef7eb2e8f9f7	2657	{
<>	144:ef7eb2e8f9f7	2658	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2659	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2660	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
<>	144:ef7eb2e8f9f7	2661	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), (Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
<>	144:ef7eb2e8f9f7	2662	}
<>	144:ef7eb2e8f9f7	2663
<>	144:ef7eb2e8f9f7	2664	/**
<>	144:ef7eb2e8f9f7	2665	* @brief Set the active input.
<>	144:ef7eb2e8f9f7	2666	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
<>	144:ef7eb2e8f9f7	2667	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
<>	144:ef7eb2e8f9f7	2668	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
<>	144:ef7eb2e8f9f7	2669	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
<>	144:ef7eb2e8f9f7	2670	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2671	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2672	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2673	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2674	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2675	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2676	* @param ICActiveInput This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2677	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	144:ef7eb2e8f9f7	2678	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	144:ef7eb2e8f9f7	2679	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	144:ef7eb2e8f9f7	2680	* @retval None
<>	144:ef7eb2e8f9f7	2681	*/
<>	144:ef7eb2e8f9f7	2682	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICActiveInput)
<>	144:ef7eb2e8f9f7	2683	{
<>	144:ef7eb2e8f9f7	2684	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2685	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2686	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	144:ef7eb2e8f9f7	2687	}
<>	144:ef7eb2e8f9f7	2688
<>	144:ef7eb2e8f9f7	2689	/**
<>	144:ef7eb2e8f9f7	2690	* @brief Get the current active input.
<>	144:ef7eb2e8f9f7	2691	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
<>	144:ef7eb2e8f9f7	2692	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
<>	144:ef7eb2e8f9f7	2693	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
<>	144:ef7eb2e8f9f7	2694	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
<>	144:ef7eb2e8f9f7	2695	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2696	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2697	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2698	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2699	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2700	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2701	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2702	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	144:ef7eb2e8f9f7	2703	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	144:ef7eb2e8f9f7	2704	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	144:ef7eb2e8f9f7	2705	*/
<>	144:ef7eb2e8f9f7	2706	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2707	{
<>	144:ef7eb2e8f9f7	2708	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2709	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2710	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	144:ef7eb2e8f9f7	2711	}
<>	144:ef7eb2e8f9f7	2712
<>	144:ef7eb2e8f9f7	2713	/**
<>	144:ef7eb2e8f9f7	2714	* @brief Set the prescaler of input channel.
<>	144:ef7eb2e8f9f7	2715	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
<>	144:ef7eb2e8f9f7	2716	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
<>	144:ef7eb2e8f9f7	2717	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
<>	144:ef7eb2e8f9f7	2718	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
<>	144:ef7eb2e8f9f7	2719	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2720	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2721	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2722	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2723	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2724	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2725	* @param ICPrescaler This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2726	* @arg @ref LL_TIM_ICPSC_DIV1
<>	144:ef7eb2e8f9f7	2727	* @arg @ref LL_TIM_ICPSC_DIV2
<>	144:ef7eb2e8f9f7	2728	* @arg @ref LL_TIM_ICPSC_DIV4
<>	144:ef7eb2e8f9f7	2729	* @arg @ref LL_TIM_ICPSC_DIV8
<>	144:ef7eb2e8f9f7	2730	* @retval None
<>	144:ef7eb2e8f9f7	2731	*/
<>	144:ef7eb2e8f9f7	2732	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPrescaler)
<>	144:ef7eb2e8f9f7	2733	{
<>	144:ef7eb2e8f9f7	2734	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2735	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2736	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	144:ef7eb2e8f9f7	2737	}
<>	144:ef7eb2e8f9f7	2738
<>	144:ef7eb2e8f9f7	2739	/**
<>	144:ef7eb2e8f9f7	2740	* @brief Get the current prescaler value acting on an input channel.
<>	144:ef7eb2e8f9f7	2741	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
<>	144:ef7eb2e8f9f7	2742	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
<>	144:ef7eb2e8f9f7	2743	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
<>	144:ef7eb2e8f9f7	2744	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
<>	144:ef7eb2e8f9f7	2745	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2746	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2747	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2748	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2749	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2750	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2751	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2752	* @arg @ref LL_TIM_ICPSC_DIV1
<>	144:ef7eb2e8f9f7	2753	* @arg @ref LL_TIM_ICPSC_DIV2
<>	144:ef7eb2e8f9f7	2754	* @arg @ref LL_TIM_ICPSC_DIV4
<>	144:ef7eb2e8f9f7	2755	* @arg @ref LL_TIM_ICPSC_DIV8
<>	144:ef7eb2e8f9f7	2756	*/
<>	144:ef7eb2e8f9f7	2757	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2758	{
<>	144:ef7eb2e8f9f7	2759	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2760	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2761	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	144:ef7eb2e8f9f7	2762	}
<>	144:ef7eb2e8f9f7	2763
<>	144:ef7eb2e8f9f7	2764	/**
<>	144:ef7eb2e8f9f7	2765	* @brief Set the input filter duration.
<>	144:ef7eb2e8f9f7	2766	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
<>	144:ef7eb2e8f9f7	2767	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
<>	144:ef7eb2e8f9f7	2768	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
<>	144:ef7eb2e8f9f7	2769	* CCMR2 IC4F LL_TIM_IC_SetFilter
<>	144:ef7eb2e8f9f7	2770	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2771	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2772	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2773	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2774	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2775	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2776	* @param ICFilter This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2777	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	144:ef7eb2e8f9f7	2778	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	144:ef7eb2e8f9f7	2779	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	144:ef7eb2e8f9f7	2780	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	144:ef7eb2e8f9f7	2781	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	144:ef7eb2e8f9f7	2782	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	144:ef7eb2e8f9f7	2783	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	144:ef7eb2e8f9f7	2784	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	144:ef7eb2e8f9f7	2785	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	144:ef7eb2e8f9f7	2786	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	144:ef7eb2e8f9f7	2787	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	144:ef7eb2e8f9f7	2788	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	144:ef7eb2e8f9f7	2789	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	144:ef7eb2e8f9f7	2790	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	144:ef7eb2e8f9f7	2791	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	144:ef7eb2e8f9f7	2792	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	144:ef7eb2e8f9f7	2793	* @retval None
<>	144:ef7eb2e8f9f7	2794	*/
<>	144:ef7eb2e8f9f7	2795	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICFilter)
<>	144:ef7eb2e8f9f7	2796	{
<>	144:ef7eb2e8f9f7	2797	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2798	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2799	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	144:ef7eb2e8f9f7	2800	}
<>	144:ef7eb2e8f9f7	2801
<>	144:ef7eb2e8f9f7	2802	/**
<>	144:ef7eb2e8f9f7	2803	* @brief Get the input filter duration.
<>	144:ef7eb2e8f9f7	2804	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
<>	144:ef7eb2e8f9f7	2805	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
<>	144:ef7eb2e8f9f7	2806	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
<>	144:ef7eb2e8f9f7	2807	* CCMR2 IC4F LL_TIM_IC_GetFilter
<>	144:ef7eb2e8f9f7	2808	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2809	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2810	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2811	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2812	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2813	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2814	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2815	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	144:ef7eb2e8f9f7	2816	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	144:ef7eb2e8f9f7	2817	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	144:ef7eb2e8f9f7	2818	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	144:ef7eb2e8f9f7	2819	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	144:ef7eb2e8f9f7	2820	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	144:ef7eb2e8f9f7	2821	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	144:ef7eb2e8f9f7	2822	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	144:ef7eb2e8f9f7	2823	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	144:ef7eb2e8f9f7	2824	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	144:ef7eb2e8f9f7	2825	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	144:ef7eb2e8f9f7	2826	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	144:ef7eb2e8f9f7	2827	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	144:ef7eb2e8f9f7	2828	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	144:ef7eb2e8f9f7	2829	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	144:ef7eb2e8f9f7	2830	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	144:ef7eb2e8f9f7	2831	*/
<>	144:ef7eb2e8f9f7	2832	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2833	{
<>	144:ef7eb2e8f9f7	2834	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2835	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
<>	144:ef7eb2e8f9f7	2836	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U );
<>	144:ef7eb2e8f9f7	2837	}
<>	144:ef7eb2e8f9f7	2838
<>	144:ef7eb2e8f9f7	2839	/**
<>	144:ef7eb2e8f9f7	2840	* @brief Set the input channel polarity.
<>	144:ef7eb2e8f9f7	2841	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2842	* CCER CC1NP LL_TIM_IC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2843	* CCER CC2P LL_TIM_IC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2844	* CCER CC2NP LL_TIM_IC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2845	* CCER CC3P LL_TIM_IC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2846	* CCER CC3NP LL_TIM_IC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2847	* CCER CC4P LL_TIM_IC_SetPolarity\n
<>	144:ef7eb2e8f9f7	2848	* CCER CC4NP LL_TIM_IC_SetPolarity
<>	144:ef7eb2e8f9f7	2849	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2850	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2851	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2852	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2853	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2854	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2855	* @param ICPolarity This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2856	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	144:ef7eb2e8f9f7	2857	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	144:ef7eb2e8f9f7	2858	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	2859	* @retval None
<>	144:ef7eb2e8f9f7	2860	*/
<>	144:ef7eb2e8f9f7	2861	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPolarity)
<>	144:ef7eb2e8f9f7	2862	{
<>	144:ef7eb2e8f9f7	2863	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2864	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]);
<>	144:ef7eb2e8f9f7	2865	}
<>	144:ef7eb2e8f9f7	2866
<>	144:ef7eb2e8f9f7	2867	/**
<>	144:ef7eb2e8f9f7	2868	* @brief Get the current input channel polarity.
<>	144:ef7eb2e8f9f7	2869	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2870	* CCER CC1NP LL_TIM_IC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2871	* CCER CC2P LL_TIM_IC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2872	* CCER CC2NP LL_TIM_IC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2873	* CCER CC3P LL_TIM_IC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2874	* CCER CC3NP LL_TIM_IC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2875	* CCER CC4P LL_TIM_IC_GetPolarity\n
<>	144:ef7eb2e8f9f7	2876	* CCER CC4NP LL_TIM_IC_GetPolarity
<>	144:ef7eb2e8f9f7	2877	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2878	* @param Channel This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2879	* @arg @ref LL_TIM_CHANNEL_CH1
<>	144:ef7eb2e8f9f7	2880	* @arg @ref LL_TIM_CHANNEL_CH2
<>	144:ef7eb2e8f9f7	2881	* @arg @ref LL_TIM_CHANNEL_CH3
<>	144:ef7eb2e8f9f7	2882	* @arg @ref LL_TIM_CHANNEL_CH4
<>	144:ef7eb2e8f9f7	2883	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	2884	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	144:ef7eb2e8f9f7	2885	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	144:ef7eb2e8f9f7	2886	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	2887	*/
<>	144:ef7eb2e8f9f7	2888	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2889	{
<>	144:ef7eb2e8f9f7	2890	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	144:ef7eb2e8f9f7	2891	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
<>	144:ef7eb2e8f9f7	2892	}
<>	144:ef7eb2e8f9f7	2893
<>	144:ef7eb2e8f9f7	2894	/**
<>	144:ef7eb2e8f9f7	2895	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
<>	144:ef7eb2e8f9f7	2896	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2897	* a timer instance provides an XOR input.
<>	144:ef7eb2e8f9f7	2898	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
<>	144:ef7eb2e8f9f7	2899	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2900	* @retval None
<>	144:ef7eb2e8f9f7	2901	*/
<>	144:ef7eb2e8f9f7	2902	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2903	{
<>	144:ef7eb2e8f9f7	2904	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	144:ef7eb2e8f9f7	2905	}
<>	144:ef7eb2e8f9f7	2906
<>	144:ef7eb2e8f9f7	2907	/**
<>	144:ef7eb2e8f9f7	2908	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
<>	144:ef7eb2e8f9f7	2909	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2910	* a timer instance provides an XOR input.
<>	144:ef7eb2e8f9f7	2911	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
<>	144:ef7eb2e8f9f7	2912	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2913	* @retval None
<>	144:ef7eb2e8f9f7	2914	*/
<>	144:ef7eb2e8f9f7	2915	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2916	{
<>	144:ef7eb2e8f9f7	2917	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	144:ef7eb2e8f9f7	2918	}
<>	144:ef7eb2e8f9f7	2919
<>	144:ef7eb2e8f9f7	2920	/**
<>	144:ef7eb2e8f9f7	2921	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
<>	144:ef7eb2e8f9f7	2922	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2923	* a timer instance provides an XOR input.
<>	144:ef7eb2e8f9f7	2924	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
<>	144:ef7eb2e8f9f7	2925	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2926	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	2927	*/
<>	144:ef7eb2e8f9f7	2928	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2929	{
<>	144:ef7eb2e8f9f7	2930	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
<>	144:ef7eb2e8f9f7	2931	}
<>	144:ef7eb2e8f9f7	2932
<>	144:ef7eb2e8f9f7	2933	/**
<>	144:ef7eb2e8f9f7	2934	* @brief Get captured value for input channel 1.
<>	144:ef7eb2e8f9f7	2935	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2936	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2937	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2938	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2939	* input channel 1 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2940	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
<>	144:ef7eb2e8f9f7	2941	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2942	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	2943	*/
<>	144:ef7eb2e8f9f7	2944	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2945	{
<>	144:ef7eb2e8f9f7	2946	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	144:ef7eb2e8f9f7	2947	}
<>	144:ef7eb2e8f9f7	2948
<>	144:ef7eb2e8f9f7	2949	/**
<>	144:ef7eb2e8f9f7	2950	* @brief Get captured value for input channel 2.
<>	144:ef7eb2e8f9f7	2951	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2952	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2953	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2954	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2955	* input channel 2 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2956	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
<>	144:ef7eb2e8f9f7	2957	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2958	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	2959	*/
<>	144:ef7eb2e8f9f7	2960	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2961	{
<>	144:ef7eb2e8f9f7	2962	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	144:ef7eb2e8f9f7	2963	}
<>	144:ef7eb2e8f9f7	2964
<>	144:ef7eb2e8f9f7	2965	/**
<>	144:ef7eb2e8f9f7	2966	* @brief Get captured value for input channel 3.
<>	144:ef7eb2e8f9f7	2967	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2968	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2969	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2970	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2971	* input channel 3 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2972	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
<>	144:ef7eb2e8f9f7	2973	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2974	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	2975	*/
<>	144:ef7eb2e8f9f7	2976	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2977	{
<>	144:ef7eb2e8f9f7	2978	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	144:ef7eb2e8f9f7	2979	}
<>	144:ef7eb2e8f9f7	2980
<>	144:ef7eb2e8f9f7	2981	/**
<>	144:ef7eb2e8f9f7	2982	* @brief Get captured value for input channel 4.
<>	144:ef7eb2e8f9f7	2983	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	144:ef7eb2e8f9f7	2984	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	2985	* whether or not a timer instance supports a 32 bits counter.
<>	144:ef7eb2e8f9f7	2986	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	2987	* input channel 4 is supported by a timer instance.
<>	144:ef7eb2e8f9f7	2988	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
<>	144:ef7eb2e8f9f7	2989	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	2990	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	144:ef7eb2e8f9f7	2991	*/
<>	144:ef7eb2e8f9f7	2992	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	2993	{
<>	144:ef7eb2e8f9f7	2994	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	144:ef7eb2e8f9f7	2995	}
<>	144:ef7eb2e8f9f7	2996
<>	144:ef7eb2e8f9f7	2997	/**
<>	144:ef7eb2e8f9f7	2998	* @}
<>	144:ef7eb2e8f9f7	2999	*/
<>	144:ef7eb2e8f9f7	3000
<>	144:ef7eb2e8f9f7	3001	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
<>	144:ef7eb2e8f9f7	3002	* @{
<>	144:ef7eb2e8f9f7	3003	*/
<>	144:ef7eb2e8f9f7	3004	/**
<>	144:ef7eb2e8f9f7	3005	* @brief Enable external clock mode 2.
<>	144:ef7eb2e8f9f7	3006	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
<>	144:ef7eb2e8f9f7	3007	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	3008	* whether or not a timer instance supports external clock mode2.
<>	144:ef7eb2e8f9f7	3009	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
<>	144:ef7eb2e8f9f7	3010	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3011	* @retval None
<>	144:ef7eb2e8f9f7	3012	*/
<>	144:ef7eb2e8f9f7	3013	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3014	{
<>	144:ef7eb2e8f9f7	3015	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	144:ef7eb2e8f9f7	3016	}
<>	144:ef7eb2e8f9f7	3017
<>	144:ef7eb2e8f9f7	3018	/**
<>	144:ef7eb2e8f9f7	3019	* @brief Disable external clock mode 2.
<>	144:ef7eb2e8f9f7	3020	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	3021	* whether or not a timer instance supports external clock mode2.
<>	144:ef7eb2e8f9f7	3022	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
<>	144:ef7eb2e8f9f7	3023	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3024	* @retval None
<>	144:ef7eb2e8f9f7	3025	*/
<>	144:ef7eb2e8f9f7	3026	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3027	{
<>	144:ef7eb2e8f9f7	3028	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	144:ef7eb2e8f9f7	3029	}
<>	144:ef7eb2e8f9f7	3030
<>	144:ef7eb2e8f9f7	3031	/**
<>	144:ef7eb2e8f9f7	3032	* @brief Indicate whether external clock mode 2 is enabled.
<>	144:ef7eb2e8f9f7	3033	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	3034	* whether or not a timer instance supports external clock mode2.
<>	144:ef7eb2e8f9f7	3035	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
<>	144:ef7eb2e8f9f7	3036	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3037	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3038	*/
<>	144:ef7eb2e8f9f7	3039	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3040	{
<>	144:ef7eb2e8f9f7	3041	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
<>	144:ef7eb2e8f9f7	3042	}
<>	144:ef7eb2e8f9f7	3043
<>	144:ef7eb2e8f9f7	3044	/**
<>	144:ef7eb2e8f9f7	3045	* @brief Set the clock source of the counter clock.
<>	144:ef7eb2e8f9f7	3046	* @note when selected clock source is external clock mode 1, the timer input
<>	144:ef7eb2e8f9f7	3047	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
<>	144:ef7eb2e8f9f7	3048	* function. This timer input must be configured by calling
<>	144:ef7eb2e8f9f7	3049	* the @ref LL_TIM_IC_Config() function.
<>	144:ef7eb2e8f9f7	3050	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	3051	* whether or not a timer instance supports external clock mode1.
<>	144:ef7eb2e8f9f7	3052	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	3053	* whether or not a timer instance supports external clock mode2.
<>	144:ef7eb2e8f9f7	3054	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
<>	144:ef7eb2e8f9f7	3055	* SMCR ECE LL_TIM_SetClockSource
<>	144:ef7eb2e8f9f7	3056	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3057	* @param ClockSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3058	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
<>	144:ef7eb2e8f9f7	3059	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
<>	144:ef7eb2e8f9f7	3060	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
<>	144:ef7eb2e8f9f7	3061	* @retval None
<>	144:ef7eb2e8f9f7	3062	*/
<>	144:ef7eb2e8f9f7	3063	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef * TIMx, uint32_t ClockSource)
<>	144:ef7eb2e8f9f7	3064	{
<>	144:ef7eb2e8f9f7	3065	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
<>	144:ef7eb2e8f9f7	3066	}
<>	144:ef7eb2e8f9f7	3067
<>	144:ef7eb2e8f9f7	3068	/**
<>	144:ef7eb2e8f9f7	3069	* @brief Set the encoder interface mode.
<>	144:ef7eb2e8f9f7	3070	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	3071	* whether or not a timer instance supports the encoder mode.
<>	144:ef7eb2e8f9f7	3072	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
<>	144:ef7eb2e8f9f7	3073	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3074	* @param EncoderMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3075	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
<>	144:ef7eb2e8f9f7	3076	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
<>	144:ef7eb2e8f9f7	3077	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
<>	144:ef7eb2e8f9f7	3078	* @retval None
<>	144:ef7eb2e8f9f7	3079	*/
<>	144:ef7eb2e8f9f7	3080	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx, uint32_t EncoderMode)
<>	144:ef7eb2e8f9f7	3081	{
<>	144:ef7eb2e8f9f7	3082	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
<>	144:ef7eb2e8f9f7	3083	}
<>	144:ef7eb2e8f9f7	3084
<>	144:ef7eb2e8f9f7	3085	/**
<>	144:ef7eb2e8f9f7	3086	* @}
<>	144:ef7eb2e8f9f7	3087	*/
<>	144:ef7eb2e8f9f7	3088
<>	144:ef7eb2e8f9f7	3089	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
<>	144:ef7eb2e8f9f7	3090	* @{
<>	144:ef7eb2e8f9f7	3091	*/
<>	144:ef7eb2e8f9f7	3092	/**
<>	144:ef7eb2e8f9f7	3093	* @brief Set the trigger output (TRGO) used for timer synchronization .
<>	144:ef7eb2e8f9f7	3094	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	3095	* whether or not a timer instance can operate as a master timer.
<>	144:ef7eb2e8f9f7	3096	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
<>	144:ef7eb2e8f9f7	3097	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3098	* @param TimerSynchronization This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3099	* @arg @ref LL_TIM_TRGO_RESET
<>	144:ef7eb2e8f9f7	3100	* @arg @ref LL_TIM_TRGO_ENABLE
<>	144:ef7eb2e8f9f7	3101	* @arg @ref LL_TIM_TRGO_UPDATE
<>	144:ef7eb2e8f9f7	3102	* @arg @ref LL_TIM_TRGO_CC1IF
<>	144:ef7eb2e8f9f7	3103	* @arg @ref LL_TIM_TRGO_OC1REF
<>	144:ef7eb2e8f9f7	3104	* @arg @ref LL_TIM_TRGO_OC2REF
<>	144:ef7eb2e8f9f7	3105	* @arg @ref LL_TIM_TRGO_OC3REF
<>	144:ef7eb2e8f9f7	3106	* @arg @ref LL_TIM_TRGO_OC4REF
<>	144:ef7eb2e8f9f7	3107	* @retval None
<>	144:ef7eb2e8f9f7	3108	*/
<>	144:ef7eb2e8f9f7	3109	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx, uint32_t TimerSynchronization)
<>	144:ef7eb2e8f9f7	3110	{
<>	144:ef7eb2e8f9f7	3111	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
<>	144:ef7eb2e8f9f7	3112	}
<>	144:ef7eb2e8f9f7	3113
<>	144:ef7eb2e8f9f7	3114	/**
<>	144:ef7eb2e8f9f7	3115	* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
<>	144:ef7eb2e8f9f7	3116	* @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
<>	144:ef7eb2e8f9f7	3117	* whether or not a timer instance can be used for ADC synchronization.
<>	144:ef7eb2e8f9f7	3118	* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
<>	144:ef7eb2e8f9f7	3119	* @param TIMx Timer Instance
<>	144:ef7eb2e8f9f7	3120	* @param ADCSynchronization This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3121	* @arg @ref LL_TIM_TRGO2_RESET
<>	144:ef7eb2e8f9f7	3122	* @arg @ref LL_TIM_TRGO2_ENABLE
<>	144:ef7eb2e8f9f7	3123	* @arg @ref LL_TIM_TRGO2_UPDATE
<>	144:ef7eb2e8f9f7	3124	* @arg @ref LL_TIM_TRGO2_CC1F
<>	144:ef7eb2e8f9f7	3125	* @arg @ref LL_TIM_TRGO2_OC1
<>	144:ef7eb2e8f9f7	3126	* @arg @ref LL_TIM_TRGO2_OC2
<>	144:ef7eb2e8f9f7	3127	* @arg @ref LL_TIM_TRGO2_OC3
<>	144:ef7eb2e8f9f7	3128	* @arg @ref LL_TIM_TRGO2_OC4
<>	144:ef7eb2e8f9f7	3129	* @arg @ref LL_TIM_TRGO2_OC5
<>	144:ef7eb2e8f9f7	3130	* @arg @ref LL_TIM_TRGO2_OC6
<>	144:ef7eb2e8f9f7	3131	* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
<>	144:ef7eb2e8f9f7	3132	* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
<>	144:ef7eb2e8f9f7	3133	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
<>	144:ef7eb2e8f9f7	3134	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
<>	144:ef7eb2e8f9f7	3135	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
<>	144:ef7eb2e8f9f7	3136	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
<>	144:ef7eb2e8f9f7	3137	* @retval None
<>	144:ef7eb2e8f9f7	3138	*/
<>	144:ef7eb2e8f9f7	3139	__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx, uint32_t ADCSynchronization)
<>	144:ef7eb2e8f9f7	3140	{
<>	144:ef7eb2e8f9f7	3141	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
<>	144:ef7eb2e8f9f7	3142	}
<>	144:ef7eb2e8f9f7	3143
<>	144:ef7eb2e8f9f7	3144	/**
<>	144:ef7eb2e8f9f7	3145	* @brief Set the synchronization mode of a slave timer.
<>	144:ef7eb2e8f9f7	3146	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3147	* a timer instance can operate as a slave timer.
<>	144:ef7eb2e8f9f7	3148	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
<>	144:ef7eb2e8f9f7	3149	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3150	* @param SlaveMode This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3151	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
<>	144:ef7eb2e8f9f7	3152	* @arg @ref LL_TIM_SLAVEMODE_RESET
<>	144:ef7eb2e8f9f7	3153	* @arg @ref LL_TIM_SLAVEMODE_GATED
<>	144:ef7eb2e8f9f7	3154	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
<>	144:ef7eb2e8f9f7	3155	* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
<>	144:ef7eb2e8f9f7	3156	* @retval None
<>	144:ef7eb2e8f9f7	3157	*/
<>	144:ef7eb2e8f9f7	3158	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx, uint32_t SlaveMode)
<>	144:ef7eb2e8f9f7	3159	{
<>	144:ef7eb2e8f9f7	3160	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
<>	144:ef7eb2e8f9f7	3161	}
<>	144:ef7eb2e8f9f7	3162
<>	144:ef7eb2e8f9f7	3163	/**
<>	144:ef7eb2e8f9f7	3164	* @brief Set the selects the trigger input to be used to synchronize the counter.
<>	144:ef7eb2e8f9f7	3165	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3166	* a timer instance can operate as a slave timer.
<>	144:ef7eb2e8f9f7	3167	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
<>	144:ef7eb2e8f9f7	3168	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3169	* @param TriggerInput This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3170	* @arg @ref LL_TIM_TS_ITR0
<>	144:ef7eb2e8f9f7	3171	* @arg @ref LL_TIM_TS_ITR1
<>	144:ef7eb2e8f9f7	3172	* @arg @ref LL_TIM_TS_ITR2
<>	144:ef7eb2e8f9f7	3173	* @arg @ref LL_TIM_TS_ITR3
<>	144:ef7eb2e8f9f7	3174	* @arg @ref LL_TIM_TS_TI1F_ED
<>	144:ef7eb2e8f9f7	3175	* @arg @ref LL_TIM_TS_TI1FP1
<>	144:ef7eb2e8f9f7	3176	* @arg @ref LL_TIM_TS_TI2FP2
<>	144:ef7eb2e8f9f7	3177	* @arg @ref LL_TIM_TS_ETRF
<>	144:ef7eb2e8f9f7	3178	* @retval None
<>	144:ef7eb2e8f9f7	3179	*/
<>	144:ef7eb2e8f9f7	3180	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx, uint32_t TriggerInput)
<>	144:ef7eb2e8f9f7	3181	{
<>	144:ef7eb2e8f9f7	3182	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
<>	144:ef7eb2e8f9f7	3183	}
<>	144:ef7eb2e8f9f7	3184
<>	144:ef7eb2e8f9f7	3185	/**
<>	144:ef7eb2e8f9f7	3186	* @brief Enable the Master/Slave mode.
<>	144:ef7eb2e8f9f7	3187	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3188	* a timer instance can operate as a slave timer.
<>	144:ef7eb2e8f9f7	3189	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
<>	144:ef7eb2e8f9f7	3190	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3191	* @retval None
<>	144:ef7eb2e8f9f7	3192	*/
<>	144:ef7eb2e8f9f7	3193	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3194	{
<>	144:ef7eb2e8f9f7	3195	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	144:ef7eb2e8f9f7	3196	}
<>	144:ef7eb2e8f9f7	3197
<>	144:ef7eb2e8f9f7	3198	/**
<>	144:ef7eb2e8f9f7	3199	* @brief Disable the Master/Slave mode.
<>	144:ef7eb2e8f9f7	3200	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3201	* a timer instance can operate as a slave timer.
<>	144:ef7eb2e8f9f7	3202	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
<>	144:ef7eb2e8f9f7	3203	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3204	* @retval None
<>	144:ef7eb2e8f9f7	3205	*/
<>	144:ef7eb2e8f9f7	3206	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3207	{
<>	144:ef7eb2e8f9f7	3208	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	144:ef7eb2e8f9f7	3209	}
<>	144:ef7eb2e8f9f7	3210
<>	144:ef7eb2e8f9f7	3211	/**
<>	144:ef7eb2e8f9f7	3212	* @brief Indicates whether the Master/Slave mode is enabled.
<>	144:ef7eb2e8f9f7	3213	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3214	* a timer instance can operate as a slave timer.
<>	144:ef7eb2e8f9f7	3215	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
<>	144:ef7eb2e8f9f7	3216	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3217	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3218	*/
<>	144:ef7eb2e8f9f7	3219	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3220	{
<>	144:ef7eb2e8f9f7	3221	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
<>	144:ef7eb2e8f9f7	3222	}
<>	144:ef7eb2e8f9f7	3223
<>	144:ef7eb2e8f9f7	3224	/**
<>	144:ef7eb2e8f9f7	3225	* @brief Configure the external trigger (ETR) input.
<>	144:ef7eb2e8f9f7	3226	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3227	* a timer instance provides an external trigger input.
<>	144:ef7eb2e8f9f7	3228	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
<>	144:ef7eb2e8f9f7	3229	* SMCR ETPS LL_TIM_ConfigETR\n
<>	144:ef7eb2e8f9f7	3230	* SMCR ETF LL_TIM_ConfigETR
<>	144:ef7eb2e8f9f7	3231	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3232	* @param ETRPolarity This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3233	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
<>	144:ef7eb2e8f9f7	3234	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
<>	144:ef7eb2e8f9f7	3235	* @param ETRPrescaler This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3236	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
<>	144:ef7eb2e8f9f7	3237	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
<>	144:ef7eb2e8f9f7	3238	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
<>	144:ef7eb2e8f9f7	3239	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
<>	144:ef7eb2e8f9f7	3240	* @param ETRFilter This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3241	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
<>	144:ef7eb2e8f9f7	3242	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
<>	144:ef7eb2e8f9f7	3243	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
<>	144:ef7eb2e8f9f7	3244	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
<>	144:ef7eb2e8f9f7	3245	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
<>	144:ef7eb2e8f9f7	3246	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
<>	144:ef7eb2e8f9f7	3247	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
<>	144:ef7eb2e8f9f7	3248	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
<>	144:ef7eb2e8f9f7	3249	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
<>	144:ef7eb2e8f9f7	3250	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
<>	144:ef7eb2e8f9f7	3251	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
<>	144:ef7eb2e8f9f7	3252	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
<>	144:ef7eb2e8f9f7	3253	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
<>	144:ef7eb2e8f9f7	3254	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
<>	144:ef7eb2e8f9f7	3255	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
<>	144:ef7eb2e8f9f7	3256	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
<>	144:ef7eb2e8f9f7	3257	* @retval None
<>	144:ef7eb2e8f9f7	3258	*/
<>	144:ef7eb2e8f9f7	3259	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef * TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
<>	144:ef7eb2e8f9f7	3260	{
<>	144:ef7eb2e8f9f7	3261	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
<>	144:ef7eb2e8f9f7	3262	}
<>	144:ef7eb2e8f9f7	3263
<>	144:ef7eb2e8f9f7	3264	/**
<>	144:ef7eb2e8f9f7	3265	* @brief Select the external trigger (ETR) input source.
<>	144:ef7eb2e8f9f7	3266	* @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
<>	144:ef7eb2e8f9f7	3267	* not a timer instance supports ETR source selection.
<>	144:ef7eb2e8f9f7	3268	* @rmtoll OR2 ETRSEL LL_TIM_SetETRSource
<>	144:ef7eb2e8f9f7	3269	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3270	* @param ETRSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3271	* @arg @ref LL_TIM_ETRSOURCE_LEGACY
<>	144:ef7eb2e8f9f7	3272	* @arg @ref LL_TIM_ETRSOURCE_COMP1
<>	144:ef7eb2e8f9f7	3273	* @arg @ref LL_TIM_ETRSOURCE_COMP2
<>	144:ef7eb2e8f9f7	3274	* @retval None
<>	144:ef7eb2e8f9f7	3275	*/
<>	144:ef7eb2e8f9f7	3276	__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef * TIMx, uint32_t ETRSource)
<>	144:ef7eb2e8f9f7	3277	{
<>	144:ef7eb2e8f9f7	3278
<>	144:ef7eb2e8f9f7	3279	MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
<>	144:ef7eb2e8f9f7	3280	}
<>	144:ef7eb2e8f9f7	3281
<>	144:ef7eb2e8f9f7	3282	/**
<>	144:ef7eb2e8f9f7	3283	* @}
<>	144:ef7eb2e8f9f7	3284	*/
<>	144:ef7eb2e8f9f7	3285
<>	144:ef7eb2e8f9f7	3286	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
<>	144:ef7eb2e8f9f7	3287	* @{
<>	144:ef7eb2e8f9f7	3288	*/
<>	144:ef7eb2e8f9f7	3289	/**
<>	144:ef7eb2e8f9f7	3290	* @brief Enable the break function.
<>	144:ef7eb2e8f9f7	3291	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3292	* a timer instance provides a break input.
<>	144:ef7eb2e8f9f7	3293	* @rmtoll BDTR BKE LL_TIM_EnableBRK
<>	144:ef7eb2e8f9f7	3294	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3295	* @retval None
<>	144:ef7eb2e8f9f7	3296	*/
<>	144:ef7eb2e8f9f7	3297	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3298	{
<>	144:ef7eb2e8f9f7	3299	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
<>	144:ef7eb2e8f9f7	3300	}
<>	144:ef7eb2e8f9f7	3301
<>	144:ef7eb2e8f9f7	3302	/**
<>	144:ef7eb2e8f9f7	3303	* @brief Disable the break function.
<>	144:ef7eb2e8f9f7	3304	* @rmtoll BDTR BKE LL_TIM_DisableBRK
<>	144:ef7eb2e8f9f7	3305	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3306	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3307	* a timer instance provides a break input.
<>	144:ef7eb2e8f9f7	3308	* @retval None
<>	144:ef7eb2e8f9f7	3309	*/
<>	144:ef7eb2e8f9f7	3310	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3311	{
<>	144:ef7eb2e8f9f7	3312	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
<>	144:ef7eb2e8f9f7	3313	}
<>	144:ef7eb2e8f9f7	3314
<>	144:ef7eb2e8f9f7	3315	/**
<>	144:ef7eb2e8f9f7	3316	* @brief Configure the break input.
<>	144:ef7eb2e8f9f7	3317	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3318	* a timer instance provides a break input.
<>	144:ef7eb2e8f9f7	3319	* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
<>	144:ef7eb2e8f9f7	3320	* BDTR BKF LL_TIM_ConfigBRK
<>	144:ef7eb2e8f9f7	3321	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3322	* @param BreakPolarity This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3323	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
<>	144:ef7eb2e8f9f7	3324	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
<>	144:ef7eb2e8f9f7	3325	* @param BreakFilter This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3326	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
<>	144:ef7eb2e8f9f7	3327	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
<>	144:ef7eb2e8f9f7	3328	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
<>	144:ef7eb2e8f9f7	3329	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
<>	144:ef7eb2e8f9f7	3330	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
<>	144:ef7eb2e8f9f7	3331	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
<>	144:ef7eb2e8f9f7	3332	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
<>	144:ef7eb2e8f9f7	3333	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
<>	144:ef7eb2e8f9f7	3334	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
<>	144:ef7eb2e8f9f7	3335	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
<>	144:ef7eb2e8f9f7	3336	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
<>	144:ef7eb2e8f9f7	3337	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
<>	144:ef7eb2e8f9f7	3338	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
<>	144:ef7eb2e8f9f7	3339	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
<>	144:ef7eb2e8f9f7	3340	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
<>	144:ef7eb2e8f9f7	3341	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
<>	144:ef7eb2e8f9f7	3342	* @retval None
<>	144:ef7eb2e8f9f7	3343	*/
<>	144:ef7eb2e8f9f7	3344	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef * TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
<>	144:ef7eb2e8f9f7	3345	{
<>	144:ef7eb2e8f9f7	3346	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP \| TIM_BDTR_BKF, BreakPolarity \| BreakFilter);
<>	144:ef7eb2e8f9f7	3347	}
<>	144:ef7eb2e8f9f7	3348
<>	144:ef7eb2e8f9f7	3349	/**
<>	144:ef7eb2e8f9f7	3350	* @brief Enable the break 2 function.
<>	144:ef7eb2e8f9f7	3351	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3352	* a timer instance provides a second break input.
<>	144:ef7eb2e8f9f7	3353	* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
<>	144:ef7eb2e8f9f7	3354	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3355	* @retval None
<>	144:ef7eb2e8f9f7	3356	*/
<>	144:ef7eb2e8f9f7	3357	__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3358	{
<>	144:ef7eb2e8f9f7	3359	SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
<>	144:ef7eb2e8f9f7	3360	}
<>	144:ef7eb2e8f9f7	3361
<>	144:ef7eb2e8f9f7	3362	/**
<>	144:ef7eb2e8f9f7	3363	* @brief Disable the break 2 function.
<>	144:ef7eb2e8f9f7	3364	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3365	* a timer instance provides a second break input.
<>	144:ef7eb2e8f9f7	3366	* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
<>	144:ef7eb2e8f9f7	3367	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3368	* @retval None
<>	144:ef7eb2e8f9f7	3369	*/
<>	144:ef7eb2e8f9f7	3370	__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3371	{
<>	144:ef7eb2e8f9f7	3372	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
<>	144:ef7eb2e8f9f7	3373	}
<>	144:ef7eb2e8f9f7	3374
<>	144:ef7eb2e8f9f7	3375	/**
<>	144:ef7eb2e8f9f7	3376	* @brief Configure the break 2 input.
<>	144:ef7eb2e8f9f7	3377	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3378	* a timer instance provides a second break input.
<>	144:ef7eb2e8f9f7	3379	* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
<>	144:ef7eb2e8f9f7	3380	* BDTR BK2F LL_TIM_ConfigBRK2
<>	144:ef7eb2e8f9f7	3381	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3382	* @param Break2Polarity This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3383	* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
<>	144:ef7eb2e8f9f7	3384	* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
<>	144:ef7eb2e8f9f7	3385	* @param Break2Filter This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3386	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
<>	144:ef7eb2e8f9f7	3387	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
<>	144:ef7eb2e8f9f7	3388	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
<>	144:ef7eb2e8f9f7	3389	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
<>	144:ef7eb2e8f9f7	3390	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
<>	144:ef7eb2e8f9f7	3391	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
<>	144:ef7eb2e8f9f7	3392	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
<>	144:ef7eb2e8f9f7	3393	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
<>	144:ef7eb2e8f9f7	3394	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
<>	144:ef7eb2e8f9f7	3395	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
<>	144:ef7eb2e8f9f7	3396	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
<>	144:ef7eb2e8f9f7	3397	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
<>	144:ef7eb2e8f9f7	3398	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
<>	144:ef7eb2e8f9f7	3399	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
<>	144:ef7eb2e8f9f7	3400	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
<>	144:ef7eb2e8f9f7	3401	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
<>	144:ef7eb2e8f9f7	3402	* @retval None
<>	144:ef7eb2e8f9f7	3403	*/
<>	144:ef7eb2e8f9f7	3404	__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
<>	144:ef7eb2e8f9f7	3405	{
<>	144:ef7eb2e8f9f7	3406	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P \| TIM_BDTR_BK2F, Break2Polarity \| Break2Filter);
<>	144:ef7eb2e8f9f7	3407	}
<>	144:ef7eb2e8f9f7	3408
<>	144:ef7eb2e8f9f7	3409	/**
<>	144:ef7eb2e8f9f7	3410	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
<>	144:ef7eb2e8f9f7	3411	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3412	* a timer instance provides a break input.
<>	144:ef7eb2e8f9f7	3413	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
<>	144:ef7eb2e8f9f7	3414	* BDTR OSSR LL_TIM_SetOffStates
<>	144:ef7eb2e8f9f7	3415	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3416	* @param OffStateIdle This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3417	* @arg @ref LL_TIM_OSSI_DISABLE
<>	144:ef7eb2e8f9f7	3418	* @arg @ref LL_TIM_OSSI_ENABLE
<>	144:ef7eb2e8f9f7	3419	* @param OffStateRun This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3420	* @arg @ref LL_TIM_OSSR_DISABLE
<>	144:ef7eb2e8f9f7	3421	* @arg @ref LL_TIM_OSSR_ENABLE
<>	144:ef7eb2e8f9f7	3422	* @retval None
<>	144:ef7eb2e8f9f7	3423	*/
<>	144:ef7eb2e8f9f7	3424	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef * TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
<>	144:ef7eb2e8f9f7	3425	{
<>	144:ef7eb2e8f9f7	3426	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
<>	144:ef7eb2e8f9f7	3427	}
<>	144:ef7eb2e8f9f7	3428
<>	144:ef7eb2e8f9f7	3429	/**
<>	144:ef7eb2e8f9f7	3430	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
<>	144:ef7eb2e8f9f7	3431	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3432	* a timer instance provides a break input.
<>	144:ef7eb2e8f9f7	3433	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
<>	144:ef7eb2e8f9f7	3434	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3435	* @retval None
<>	144:ef7eb2e8f9f7	3436	*/
<>	144:ef7eb2e8f9f7	3437	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3438	{
<>	144:ef7eb2e8f9f7	3439	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
<>	144:ef7eb2e8f9f7	3440	}
<>	144:ef7eb2e8f9f7	3441
<>	144:ef7eb2e8f9f7	3442	/**
<>	144:ef7eb2e8f9f7	3443	* @brief Disable automatic output (MOE can be set only by software).
<>	144:ef7eb2e8f9f7	3444	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3445	* a timer instance provides a break input.
<>	144:ef7eb2e8f9f7	3446	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
<>	144:ef7eb2e8f9f7	3447	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3448	* @retval None
<>	144:ef7eb2e8f9f7	3449	*/
<>	144:ef7eb2e8f9f7	3450	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3451	{
<>	144:ef7eb2e8f9f7	3452	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
<>	144:ef7eb2e8f9f7	3453	}
<>	144:ef7eb2e8f9f7	3454
<>	144:ef7eb2e8f9f7	3455	/**
<>	144:ef7eb2e8f9f7	3456	* @brief Indicate whether automatic output is enabled.
<>	144:ef7eb2e8f9f7	3457	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3458	* a timer instance provides a break input.
<>	144:ef7eb2e8f9f7	3459	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
<>	144:ef7eb2e8f9f7	3460	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3461	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3462	*/
<>	144:ef7eb2e8f9f7	3463	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3464	{
<>	144:ef7eb2e8f9f7	3465	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
<>	144:ef7eb2e8f9f7	3466	}
<>	144:ef7eb2e8f9f7	3467
<>	144:ef7eb2e8f9f7	3468	/**
<>	144:ef7eb2e8f9f7	3469	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
<>	144:ef7eb2e8f9f7	3470	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
<>	144:ef7eb2e8f9f7	3471	* software and is reset in case of break or break2 event
<>	144:ef7eb2e8f9f7	3472	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3473	* a timer instance provides a break input.
<>	144:ef7eb2e8f9f7	3474	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
<>	144:ef7eb2e8f9f7	3475	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3476	* @retval None
<>	144:ef7eb2e8f9f7	3477	*/
<>	144:ef7eb2e8f9f7	3478	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3479	{
<>	144:ef7eb2e8f9f7	3480	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
<>	144:ef7eb2e8f9f7	3481	}
<>	144:ef7eb2e8f9f7	3482
<>	144:ef7eb2e8f9f7	3483	/**
<>	144:ef7eb2e8f9f7	3484	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
<>	144:ef7eb2e8f9f7	3485	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
<>	144:ef7eb2e8f9f7	3486	* software and is reset in case of break or break2 event.
<>	144:ef7eb2e8f9f7	3487	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3488	* a timer instance provides a break input.
<>	144:ef7eb2e8f9f7	3489	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
<>	144:ef7eb2e8f9f7	3490	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3491	* @retval None
<>	144:ef7eb2e8f9f7	3492	*/
<>	144:ef7eb2e8f9f7	3493	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3494	{
<>	144:ef7eb2e8f9f7	3495	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
<>	144:ef7eb2e8f9f7	3496	}
<>	144:ef7eb2e8f9f7	3497
<>	144:ef7eb2e8f9f7	3498	/**
<>	144:ef7eb2e8f9f7	3499	* @brief Indicates whether outputs are enabled.
<>	144:ef7eb2e8f9f7	3500	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3501	* a timer instance provides a break input.
<>	144:ef7eb2e8f9f7	3502	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
<>	144:ef7eb2e8f9f7	3503	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3504	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3505	*/
<>	144:ef7eb2e8f9f7	3506	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3507	{
<>	144:ef7eb2e8f9f7	3508	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
<>	144:ef7eb2e8f9f7	3509	}
<>	144:ef7eb2e8f9f7	3510
<>	144:ef7eb2e8f9f7	3511	/**
<>	144:ef7eb2e8f9f7	3512	* @brief Enable the signals connected to the designated timer break input.
<>	144:ef7eb2e8f9f7	3513	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
<>	144:ef7eb2e8f9f7	3514	* or not a timer instance allows for break input selection.
<>	144:ef7eb2e8f9f7	3515	* @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3516	* OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3517	* OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3518	* OR2 BKDFBK0E LL_TIM_EnableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3519	* OR3 BKINE LL_TIM_EnableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3520	* OR3 BKCMP1E LL_TIM_EnableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3521	* OR3 BKCMP2E LL_TIM_EnableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3522	* OR3 BKDFBK0E LL_TIM_EnableBreakInputSource
<>	144:ef7eb2e8f9f7	3523	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3524	* @param BreakInput This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3525	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
<>	144:ef7eb2e8f9f7	3526	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
<>	144:ef7eb2e8f9f7	3527	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3528	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
<>	144:ef7eb2e8f9f7	3529	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
<>	144:ef7eb2e8f9f7	3530	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
<>	144:ef7eb2e8f9f7	3531	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
<>	144:ef7eb2e8f9f7	3532	* @retval None
<>	144:ef7eb2e8f9f7	3533	*/
<>	144:ef7eb2e8f9f7	3534	__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source)
<>	144:ef7eb2e8f9f7	3535	{
<>	144:ef7eb2e8f9f7	3536	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
<>	144:ef7eb2e8f9f7	3537	SET_BIT(*pReg , Source);
<>	144:ef7eb2e8f9f7	3538	}
<>	144:ef7eb2e8f9f7	3539
<>	144:ef7eb2e8f9f7	3540	/**
<>	144:ef7eb2e8f9f7	3541	* @brief Disable the signals connected to the designated timer break input.
<>	144:ef7eb2e8f9f7	3542	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
<>	144:ef7eb2e8f9f7	3543	* or not a timer instance allows for break input selection.
<>	144:ef7eb2e8f9f7	3544	* @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3545	* OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3546	* OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3547	* OR2 BKDFBK0E LL_TIM_DisableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3548	* OR3 BKINE LL_TIM_DisableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3549	* OR3 BKCMP1E LL_TIM_DisableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3550	* OR3 BKCMP2E LL_TIM_DisableBreakInputSource\n
<>	144:ef7eb2e8f9f7	3551	* OR3 BKDFBK0E LL_TIM_DisableBreakInputSource
<>	144:ef7eb2e8f9f7	3552	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3553	* @param BreakInput This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3554	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
<>	144:ef7eb2e8f9f7	3555	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
<>	144:ef7eb2e8f9f7	3556	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3557	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
<>	144:ef7eb2e8f9f7	3558	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
<>	144:ef7eb2e8f9f7	3559	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
<>	144:ef7eb2e8f9f7	3560	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
<>	144:ef7eb2e8f9f7	3561	* @retval None
<>	144:ef7eb2e8f9f7	3562	*/
<>	144:ef7eb2e8f9f7	3563	__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source)
<>	144:ef7eb2e8f9f7	3564	{
<>	144:ef7eb2e8f9f7	3565	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
<>	144:ef7eb2e8f9f7	3566	CLEAR_BIT(*pReg, Source);
<>	144:ef7eb2e8f9f7	3567	}
<>	144:ef7eb2e8f9f7	3568
<>	144:ef7eb2e8f9f7	3569	/**
<>	144:ef7eb2e8f9f7	3570	* @brief Set the polarity of the break signal for the timer break input.
<>	144:ef7eb2e8f9f7	3571	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
<>	144:ef7eb2e8f9f7	3572	* or not a timer instance allows for break input selection.
<>	144:ef7eb2e8f9f7	3573	* @rmtoll OR2 BKINE LL_TIM_SetBreakInputSourcePolarity\n
<>	144:ef7eb2e8f9f7	3574	* OR2 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n
<>	144:ef7eb2e8f9f7	3575	* OR2 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n
<>	144:ef7eb2e8f9f7	3576	* OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
<>	144:ef7eb2e8f9f7	3577	* OR3 BKINE LL_TIM_SetBreakInputSourcePolarity\n
<>	144:ef7eb2e8f9f7	3578	* OR3 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n
<>	144:ef7eb2e8f9f7	3579	* OR3 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n
<>	144:ef7eb2e8f9f7	3580	* OR3 BKINP LL_TIM_SetBreakInputSourcePolarity
<>	144:ef7eb2e8f9f7	3581	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3582	* @param BreakInput This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3583	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
<>	144:ef7eb2e8f9f7	3584	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
<>	144:ef7eb2e8f9f7	3585	* @param Source This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3586	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
<>	144:ef7eb2e8f9f7	3587	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
<>	144:ef7eb2e8f9f7	3588	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
<>	144:ef7eb2e8f9f7	3589	* @param Polarity This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3590	* @arg @ref LL_TIM_BKIN_POLARITY_LOW
<>	144:ef7eb2e8f9f7	3591	* @arg @ref LL_TIM_BKIN_POLARITY_HIGH
<>	144:ef7eb2e8f9f7	3592	* @retval None
<>	144:ef7eb2e8f9f7	3593	*/
<>	144:ef7eb2e8f9f7	3594	__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
<>	144:ef7eb2e8f9f7	3595	{
<>	144:ef7eb2e8f9f7	3596	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
<>	144:ef7eb2e8f9f7	3597	MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (POSITION_VAL(Source))) , (Polarity << (POSITION_VAL(Source))));
<>	144:ef7eb2e8f9f7	3598	}
<>	144:ef7eb2e8f9f7	3599
<>	144:ef7eb2e8f9f7	3600	/**
<>	144:ef7eb2e8f9f7	3601	* @}
<>	144:ef7eb2e8f9f7	3602	*/
<>	144:ef7eb2e8f9f7	3603
<>	144:ef7eb2e8f9f7	3604	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
<>	144:ef7eb2e8f9f7	3605	* @{
<>	144:ef7eb2e8f9f7	3606	*/
<>	144:ef7eb2e8f9f7	3607	/**
<>	144:ef7eb2e8f9f7	3608	* @brief Configures the timer DMA burst feature.
<>	144:ef7eb2e8f9f7	3609	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
<>	144:ef7eb2e8f9f7	3610	* not a timer instance supports the DMA burst mode.
<>	144:ef7eb2e8f9f7	3611	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
<>	144:ef7eb2e8f9f7	3612	* DCR DBA LL_TIM_ConfigDMABurst
<>	144:ef7eb2e8f9f7	3613	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3614	* @param DMABurstBaseAddress This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3615	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
<>	144:ef7eb2e8f9f7	3616	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
<>	144:ef7eb2e8f9f7	3617	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
<>	144:ef7eb2e8f9f7	3618	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
<>	144:ef7eb2e8f9f7	3619	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
<>	144:ef7eb2e8f9f7	3620	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
<>	144:ef7eb2e8f9f7	3621	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
<>	144:ef7eb2e8f9f7	3622	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
<>	144:ef7eb2e8f9f7	3623	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
<>	144:ef7eb2e8f9f7	3624	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
<>	144:ef7eb2e8f9f7	3625	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
<>	144:ef7eb2e8f9f7	3626	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
<>	144:ef7eb2e8f9f7	3627	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
<>	144:ef7eb2e8f9f7	3628	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
<>	144:ef7eb2e8f9f7	3629	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
<>	144:ef7eb2e8f9f7	3630	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
<>	144:ef7eb2e8f9f7	3631	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
<>	144:ef7eb2e8f9f7	3632	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
<>	144:ef7eb2e8f9f7	3633	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
<>	144:ef7eb2e8f9f7	3634	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
<>	144:ef7eb2e8f9f7	3635	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
<>	144:ef7eb2e8f9f7	3636	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
<>	144:ef7eb2e8f9f7	3637	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
<>	144:ef7eb2e8f9f7	3638	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
<>	144:ef7eb2e8f9f7	3639	* @param DMABurstLength This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3640	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
<>	144:ef7eb2e8f9f7	3641	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
<>	144:ef7eb2e8f9f7	3642	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
<>	144:ef7eb2e8f9f7	3643	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
<>	144:ef7eb2e8f9f7	3644	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
<>	144:ef7eb2e8f9f7	3645	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
<>	144:ef7eb2e8f9f7	3646	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
<>	144:ef7eb2e8f9f7	3647	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
<>	144:ef7eb2e8f9f7	3648	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
<>	144:ef7eb2e8f9f7	3649	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
<>	144:ef7eb2e8f9f7	3650	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
<>	144:ef7eb2e8f9f7	3651	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
<>	144:ef7eb2e8f9f7	3652	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
<>	144:ef7eb2e8f9f7	3653	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
<>	144:ef7eb2e8f9f7	3654	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
<>	144:ef7eb2e8f9f7	3655	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
<>	144:ef7eb2e8f9f7	3656	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
<>	144:ef7eb2e8f9f7	3657	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
<>	144:ef7eb2e8f9f7	3658	* @retval None
<>	144:ef7eb2e8f9f7	3659	*/
<>	144:ef7eb2e8f9f7	3660	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
<>	144:ef7eb2e8f9f7	3661	{
<>	144:ef7eb2e8f9f7	3662	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
<>	144:ef7eb2e8f9f7	3663	}
<>	144:ef7eb2e8f9f7	3664
<>	144:ef7eb2e8f9f7	3665	/**
<>	144:ef7eb2e8f9f7	3666	* @}
<>	144:ef7eb2e8f9f7	3667	*/
<>	144:ef7eb2e8f9f7	3668
<>	144:ef7eb2e8f9f7	3669	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
<>	144:ef7eb2e8f9f7	3670	* @{
<>	144:ef7eb2e8f9f7	3671	*/
<>	144:ef7eb2e8f9f7	3672	/**
<>	144:ef7eb2e8f9f7	3673	* @brief Remap TIM inputs (input channel, internal/external triggers).
<>	144:ef7eb2e8f9f7	3674	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
<>	144:ef7eb2e8f9f7	3675	* a some timer inputs can be remapped.
<>	144:ef7eb2e8f9f7	3676	* @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3677	* TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3678	* TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3679	* TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3680	* TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3681	* TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3682	* TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3683	* TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3684	* TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3685	* TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3686	* TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3687	* TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3688	* TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
<>	144:ef7eb2e8f9f7	3689	* TIM17_OR1 TI1_RMP LL_TIM_SetRemap
<>	144:ef7eb2e8f9f7	3690	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3691	* @param Remap Remap param depends on the TIMx. Description available only
<>	144:ef7eb2e8f9f7	3692	* in CHM version of the User Manual (not in .pdf).
<>	144:ef7eb2e8f9f7	3693	* Otherwise see Reference Manual description of OR registers.
<>	144:ef7eb2e8f9f7	3694	*
<>	144:ef7eb2e8f9f7	3695	* Below description summarizes "Timer Instance" and "Remap" param combinations:
<>	144:ef7eb2e8f9f7	3696	*
<>	144:ef7eb2e8f9f7	3697	* TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
<>	144:ef7eb2e8f9f7	3698	*
<>	144:ef7eb2e8f9f7	3699	* . . ADC1_RMP can be one of the following values
<>	144:ef7eb2e8f9f7	3700	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
<>	144:ef7eb2e8f9f7	3701	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
<>	144:ef7eb2e8f9f7	3702	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
<>	144:ef7eb2e8f9f7	3703	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
<>	144:ef7eb2e8f9f7	3704	*
<>	144:ef7eb2e8f9f7	3705	* . . ADC3_RMP can be one of the following values
<>	144:ef7eb2e8f9f7	3706	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
<>	144:ef7eb2e8f9f7	3707	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
<>	144:ef7eb2e8f9f7	3708	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
<>	144:ef7eb2e8f9f7	3709	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
<>	144:ef7eb2e8f9f7	3710	*
<>	144:ef7eb2e8f9f7	3711	* . . TI1_RMP can be one of the following values
<>	144:ef7eb2e8f9f7	3712	* @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
<>	144:ef7eb2e8f9f7	3713	* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
<>	144:ef7eb2e8f9f7	3714	*
<>	144:ef7eb2e8f9f7	3715	* TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
<>	144:ef7eb2e8f9f7	3716	*
<>	144:ef7eb2e8f9f7	3717	* ITR1_RMP can be one of the following values
<>	144:ef7eb2e8f9f7	3718	* @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
<>	144:ef7eb2e8f9f7	3719	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
<>	144:ef7eb2e8f9f7	3720	*
<>	144:ef7eb2e8f9f7	3721	* . . ETR1_RMP can be one of the following values
<>	144:ef7eb2e8f9f7	3722	* @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
<>	144:ef7eb2e8f9f7	3723	* @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
<>	144:ef7eb2e8f9f7	3724	*
<>	144:ef7eb2e8f9f7	3725	* . . TI4_RMP can be one of the following values
<>	144:ef7eb2e8f9f7	3726	* @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
<>	144:ef7eb2e8f9f7	3727	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
<>	144:ef7eb2e8f9f7	3728	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
<>	144:ef7eb2e8f9f7	3729	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
<>	144:ef7eb2e8f9f7	3730	*
<>	144:ef7eb2e8f9f7	3731	* TIM3: one of the following values
<>	144:ef7eb2e8f9f7	3732	*
<>	144:ef7eb2e8f9f7	3733	* @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
<>	144:ef7eb2e8f9f7	3734	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
<>	144:ef7eb2e8f9f7	3735	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
<>	144:ef7eb2e8f9f7	3736	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
<>	144:ef7eb2e8f9f7	3737	*
<>	144:ef7eb2e8f9f7	3738	* TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
<>	144:ef7eb2e8f9f7	3739	*
<>	144:ef7eb2e8f9f7	3740	* . . ADC1_RMP can be one of the following values
<>	144:ef7eb2e8f9f7	3741	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
<>	144:ef7eb2e8f9f7	3742	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
<>	144:ef7eb2e8f9f7	3743	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
<>	144:ef7eb2e8f9f7	3744	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
<>	144:ef7eb2e8f9f7	3745	*
<>	144:ef7eb2e8f9f7	3746	* . . ADC3_RMP can be one of the following values
<>	144:ef7eb2e8f9f7	3747	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
<>	144:ef7eb2e8f9f7	3748	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
<>	144:ef7eb2e8f9f7	3749	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
<>	144:ef7eb2e8f9f7	3750	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
<>	144:ef7eb2e8f9f7	3751	*
<>	144:ef7eb2e8f9f7	3752	* . . TI1_RMP can be one of the following values
<>	144:ef7eb2e8f9f7	3753	* @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
<>	144:ef7eb2e8f9f7	3754	* @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
<>	144:ef7eb2e8f9f7	3755	*
<>	144:ef7eb2e8f9f7	3756	* TIM15: any combination of TI1_RMP, ENCODER_MODE where
<>	144:ef7eb2e8f9f7	3757	*
<>	144:ef7eb2e8f9f7	3758	* . . TI1_RMP can be one of the following values
<>	144:ef7eb2e8f9f7	3759	* @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
<>	144:ef7eb2e8f9f7	3760	* @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
<>	144:ef7eb2e8f9f7	3761	*
<>	144:ef7eb2e8f9f7	3762	* . . ENCODER_MODE can be one of the following values
<>	144:ef7eb2e8f9f7	3763	* @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
<>	144:ef7eb2e8f9f7	3764	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
<>	144:ef7eb2e8f9f7	3765	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
<>	144:ef7eb2e8f9f7	3766	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
<>	144:ef7eb2e8f9f7	3767	*
<>	144:ef7eb2e8f9f7	3768	* TIM16: one of the following values
<>	144:ef7eb2e8f9f7	3769	*
<>	144:ef7eb2e8f9f7	3770	* @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
<>	144:ef7eb2e8f9f7	3771	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
<>	144:ef7eb2e8f9f7	3772	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
<>	144:ef7eb2e8f9f7	3773	* @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
<>	144:ef7eb2e8f9f7	3774	* @arg @ref LL_TIM_TIM16_TI1_RMP_MSI (*)
<>	144:ef7eb2e8f9f7	3775	* @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 (*)
<>	144:ef7eb2e8f9f7	3776	* @arg @ref LL_TIM_TIM16_TI1_RMP_MCO (*)
<>	144:ef7eb2e8f9f7	3777	*
<>	144:ef7eb2e8f9f7	3778	* TIM17: one of the following values
<>	144:ef7eb2e8f9f7	3779	*
<>	144:ef7eb2e8f9f7	3780	* @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
<>	144:ef7eb2e8f9f7	3781	* @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
<>	144:ef7eb2e8f9f7	3782	* @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
<>	144:ef7eb2e8f9f7	3783	* @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
<>	144:ef7eb2e8f9f7	3784	*
<>	144:ef7eb2e8f9f7	3785	* (*) Value not defined in all devices. \n
<>	144:ef7eb2e8f9f7	3786	* @retval None
<>	144:ef7eb2e8f9f7	3787	*/
<>	144:ef7eb2e8f9f7	3788	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef * TIMx, uint32_t Remap)
<>	144:ef7eb2e8f9f7	3789	{
<>	144:ef7eb2e8f9f7	3790	MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
<>	144:ef7eb2e8f9f7	3791	}
<>	144:ef7eb2e8f9f7	3792
<>	144:ef7eb2e8f9f7	3793	/**
<>	144:ef7eb2e8f9f7	3794	* @}
<>	144:ef7eb2e8f9f7	3795	*/
<>	144:ef7eb2e8f9f7	3796
<>	144:ef7eb2e8f9f7	3797	#if defined(TIM_SMCR_OCCS)
<>	144:ef7eb2e8f9f7	3798	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
<>	144:ef7eb2e8f9f7	3799	* @{
<>	144:ef7eb2e8f9f7	3800	*/
<>	144:ef7eb2e8f9f7	3801	/**
<>	144:ef7eb2e8f9f7	3802	* @brief Set the OCREF clear source
<>	144:ef7eb2e8f9f7	3803	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
<>	144:ef7eb2e8f9f7	3804	* @note This function can only be used in Output compare and PWM modes.
<>	144:ef7eb2e8f9f7	3805	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
<>	144:ef7eb2e8f9f7	3806	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3807	* @param OCRefClearInputSource This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3808	* @arg @ref LL_TIM_OCREF_CLR_INT_NC
<>	144:ef7eb2e8f9f7	3809	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
<>	144:ef7eb2e8f9f7	3810	* @retval None
<>	144:ef7eb2e8f9f7	3811	*/
<>	144:ef7eb2e8f9f7	3812
<>	144:ef7eb2e8f9f7	3813	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx, uint32_t OCRefClearInputSource)
<>	144:ef7eb2e8f9f7	3814	{
<>	144:ef7eb2e8f9f7	3815	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
<>	144:ef7eb2e8f9f7	3816	}
<>	144:ef7eb2e8f9f7	3817	/**
<>	144:ef7eb2e8f9f7	3818	* @}
<>	144:ef7eb2e8f9f7	3819	*/
<>	144:ef7eb2e8f9f7	3820
<>	144:ef7eb2e8f9f7	3821	#endif /* TIM_SMCR_OCCS */
<>	144:ef7eb2e8f9f7	3822	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
<>	144:ef7eb2e8f9f7	3823	* @{
<>	144:ef7eb2e8f9f7	3824	*/
<>	144:ef7eb2e8f9f7	3825	/**
<>	144:ef7eb2e8f9f7	3826	* @brief Clear the update interrupt flag (UIF).
<>	144:ef7eb2e8f9f7	3827	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
<>	144:ef7eb2e8f9f7	3828	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3829	* @retval None
<>	144:ef7eb2e8f9f7	3830	*/
<>	144:ef7eb2e8f9f7	3831	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3832	{
<>	144:ef7eb2e8f9f7	3833	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
<>	144:ef7eb2e8f9f7	3834	}
<>	144:ef7eb2e8f9f7	3835
<>	144:ef7eb2e8f9f7	3836	/**
<>	144:ef7eb2e8f9f7	3837	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
<>	144:ef7eb2e8f9f7	3838	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
<>	144:ef7eb2e8f9f7	3839	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3840	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3841	*/
<>	144:ef7eb2e8f9f7	3842	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3843	{
<>	144:ef7eb2e8f9f7	3844	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
<>	144:ef7eb2e8f9f7	3845	}
<>	144:ef7eb2e8f9f7	3846
<>	144:ef7eb2e8f9f7	3847	/**
<>	144:ef7eb2e8f9f7	3848	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
<>	144:ef7eb2e8f9f7	3849	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
<>	144:ef7eb2e8f9f7	3850	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3851	* @retval None
<>	144:ef7eb2e8f9f7	3852	*/
<>	144:ef7eb2e8f9f7	3853	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3854	{
<>	144:ef7eb2e8f9f7	3855	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
<>	144:ef7eb2e8f9f7	3856	}
<>	144:ef7eb2e8f9f7	3857
<>	144:ef7eb2e8f9f7	3858	/**
<>	144:ef7eb2e8f9f7	3859	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
<>	144:ef7eb2e8f9f7	3860	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
<>	144:ef7eb2e8f9f7	3861	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3862	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3863	*/
<>	144:ef7eb2e8f9f7	3864	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3865	{
<>	144:ef7eb2e8f9f7	3866	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
<>	144:ef7eb2e8f9f7	3867	}
<>	144:ef7eb2e8f9f7	3868
<>	144:ef7eb2e8f9f7	3869	/**
<>	144:ef7eb2e8f9f7	3870	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
<>	144:ef7eb2e8f9f7	3871	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
<>	144:ef7eb2e8f9f7	3872	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3873	* @retval None
<>	144:ef7eb2e8f9f7	3874	*/
<>	144:ef7eb2e8f9f7	3875	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3876	{
<>	144:ef7eb2e8f9f7	3877	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
<>	144:ef7eb2e8f9f7	3878	}
<>	144:ef7eb2e8f9f7	3879
<>	144:ef7eb2e8f9f7	3880	/**
<>	144:ef7eb2e8f9f7	3881	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
<>	144:ef7eb2e8f9f7	3882	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
<>	144:ef7eb2e8f9f7	3883	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3884	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3885	*/
<>	144:ef7eb2e8f9f7	3886	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3887	{
<>	144:ef7eb2e8f9f7	3888	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
<>	144:ef7eb2e8f9f7	3889	}
<>	144:ef7eb2e8f9f7	3890
<>	144:ef7eb2e8f9f7	3891	/**
<>	144:ef7eb2e8f9f7	3892	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
<>	144:ef7eb2e8f9f7	3893	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
<>	144:ef7eb2e8f9f7	3894	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3895	* @retval None
<>	144:ef7eb2e8f9f7	3896	*/
<>	144:ef7eb2e8f9f7	3897	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3898	{
<>	144:ef7eb2e8f9f7	3899	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
<>	144:ef7eb2e8f9f7	3900	}
<>	144:ef7eb2e8f9f7	3901
<>	144:ef7eb2e8f9f7	3902	/**
<>	144:ef7eb2e8f9f7	3903	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
<>	144:ef7eb2e8f9f7	3904	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
<>	144:ef7eb2e8f9f7	3905	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3906	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3907	*/
<>	144:ef7eb2e8f9f7	3908	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3909	{
<>	144:ef7eb2e8f9f7	3910	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
<>	144:ef7eb2e8f9f7	3911	}
<>	144:ef7eb2e8f9f7	3912
<>	144:ef7eb2e8f9f7	3913	/**
<>	144:ef7eb2e8f9f7	3914	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
<>	144:ef7eb2e8f9f7	3915	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
<>	144:ef7eb2e8f9f7	3916	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3917	* @retval None
<>	144:ef7eb2e8f9f7	3918	*/
<>	144:ef7eb2e8f9f7	3919	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3920	{
<>	144:ef7eb2e8f9f7	3921	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
<>	144:ef7eb2e8f9f7	3922	}
<>	144:ef7eb2e8f9f7	3923
<>	144:ef7eb2e8f9f7	3924	/**
<>	144:ef7eb2e8f9f7	3925	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
<>	144:ef7eb2e8f9f7	3926	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
<>	144:ef7eb2e8f9f7	3927	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3928	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3929	*/
<>	144:ef7eb2e8f9f7	3930	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3931	{
<>	144:ef7eb2e8f9f7	3932	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
<>	144:ef7eb2e8f9f7	3933	}
<>	144:ef7eb2e8f9f7	3934
<>	144:ef7eb2e8f9f7	3935	/**
<>	144:ef7eb2e8f9f7	3936	* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
<>	144:ef7eb2e8f9f7	3937	* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
<>	144:ef7eb2e8f9f7	3938	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3939	* @retval None
<>	144:ef7eb2e8f9f7	3940	*/
<>	144:ef7eb2e8f9f7	3941	__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3942	{
<>	144:ef7eb2e8f9f7	3943	WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
<>	144:ef7eb2e8f9f7	3944	}
<>	144:ef7eb2e8f9f7	3945
<>	144:ef7eb2e8f9f7	3946	/**
<>	144:ef7eb2e8f9f7	3947	* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
<>	144:ef7eb2e8f9f7	3948	* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
<>	144:ef7eb2e8f9f7	3949	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3950	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3951	*/
<>	144:ef7eb2e8f9f7	3952	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3953	{
<>	144:ef7eb2e8f9f7	3954	return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
<>	144:ef7eb2e8f9f7	3955	}
<>	144:ef7eb2e8f9f7	3956
<>	144:ef7eb2e8f9f7	3957	/**
<>	144:ef7eb2e8f9f7	3958	* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
<>	144:ef7eb2e8f9f7	3959	* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
<>	144:ef7eb2e8f9f7	3960	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3961	* @retval None
<>	144:ef7eb2e8f9f7	3962	*/
<>	144:ef7eb2e8f9f7	3963	__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3964	{
<>	144:ef7eb2e8f9f7	3965	WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
<>	144:ef7eb2e8f9f7	3966	}
<>	144:ef7eb2e8f9f7	3967
<>	144:ef7eb2e8f9f7	3968	/**
<>	144:ef7eb2e8f9f7	3969	* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
<>	144:ef7eb2e8f9f7	3970	* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
<>	144:ef7eb2e8f9f7	3971	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3972	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3973	*/
<>	144:ef7eb2e8f9f7	3974	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3975	{
<>	144:ef7eb2e8f9f7	3976	return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
<>	144:ef7eb2e8f9f7	3977	}
<>	144:ef7eb2e8f9f7	3978
<>	144:ef7eb2e8f9f7	3979	/**
<>	144:ef7eb2e8f9f7	3980	* @brief Clear the commutation interrupt flag (COMIF).
<>	144:ef7eb2e8f9f7	3981	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
<>	144:ef7eb2e8f9f7	3982	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3983	* @retval None
<>	144:ef7eb2e8f9f7	3984	*/
<>	144:ef7eb2e8f9f7	3985	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3986	{
<>	144:ef7eb2e8f9f7	3987	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
<>	144:ef7eb2e8f9f7	3988	}
<>	144:ef7eb2e8f9f7	3989
<>	144:ef7eb2e8f9f7	3990	/**
<>	144:ef7eb2e8f9f7	3991	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
<>	144:ef7eb2e8f9f7	3992	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
<>	144:ef7eb2e8f9f7	3993	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	3994	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	3995	*/
<>	144:ef7eb2e8f9f7	3996	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	3997	{
<>	144:ef7eb2e8f9f7	3998	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
<>	144:ef7eb2e8f9f7	3999	}
<>	144:ef7eb2e8f9f7	4000
<>	144:ef7eb2e8f9f7	4001	/**
<>	144:ef7eb2e8f9f7	4002	* @brief Clear the trigger interrupt flag (TIF).
<>	144:ef7eb2e8f9f7	4003	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
<>	144:ef7eb2e8f9f7	4004	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4005	* @retval None
<>	144:ef7eb2e8f9f7	4006	*/
<>	144:ef7eb2e8f9f7	4007	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4008	{
<>	144:ef7eb2e8f9f7	4009	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
<>	144:ef7eb2e8f9f7	4010	}
<>	144:ef7eb2e8f9f7	4011
<>	144:ef7eb2e8f9f7	4012	/**
<>	144:ef7eb2e8f9f7	4013	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
<>	144:ef7eb2e8f9f7	4014	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
<>	144:ef7eb2e8f9f7	4015	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4016	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4017	*/
<>	144:ef7eb2e8f9f7	4018	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4019	{
<>	144:ef7eb2e8f9f7	4020	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
<>	144:ef7eb2e8f9f7	4021	}
<>	144:ef7eb2e8f9f7	4022
<>	144:ef7eb2e8f9f7	4023	/**
<>	144:ef7eb2e8f9f7	4024	* @brief Clear the break interrupt flag (BIF).
<>	144:ef7eb2e8f9f7	4025	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
<>	144:ef7eb2e8f9f7	4026	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4027	* @retval None
<>	144:ef7eb2e8f9f7	4028	*/
<>	144:ef7eb2e8f9f7	4029	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4030	{
<>	144:ef7eb2e8f9f7	4031	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
<>	144:ef7eb2e8f9f7	4032	}
<>	144:ef7eb2e8f9f7	4033
<>	144:ef7eb2e8f9f7	4034	/**
<>	144:ef7eb2e8f9f7	4035	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
<>	144:ef7eb2e8f9f7	4036	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
<>	144:ef7eb2e8f9f7	4037	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4038	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4039	*/
<>	144:ef7eb2e8f9f7	4040	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4041	{
<>	144:ef7eb2e8f9f7	4042	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
<>	144:ef7eb2e8f9f7	4043	}
<>	144:ef7eb2e8f9f7	4044
<>	144:ef7eb2e8f9f7	4045	/**
<>	144:ef7eb2e8f9f7	4046	* @brief Clear the break 2 interrupt flag (B2IF).
<>	144:ef7eb2e8f9f7	4047	* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
<>	144:ef7eb2e8f9f7	4048	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4049	* @retval None
<>	144:ef7eb2e8f9f7	4050	*/
<>	144:ef7eb2e8f9f7	4051	__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4052	{
<>	144:ef7eb2e8f9f7	4053	WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
<>	144:ef7eb2e8f9f7	4054	}
<>	144:ef7eb2e8f9f7	4055
<>	144:ef7eb2e8f9f7	4056	/**
<>	144:ef7eb2e8f9f7	4057	* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
<>	144:ef7eb2e8f9f7	4058	* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
<>	144:ef7eb2e8f9f7	4059	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4060	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4061	*/
<>	144:ef7eb2e8f9f7	4062	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4063	{
<>	144:ef7eb2e8f9f7	4064	return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
<>	144:ef7eb2e8f9f7	4065	}
<>	144:ef7eb2e8f9f7	4066
<>	144:ef7eb2e8f9f7	4067	/**
<>	144:ef7eb2e8f9f7	4068	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
<>	144:ef7eb2e8f9f7	4069	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
<>	144:ef7eb2e8f9f7	4070	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4071	* @retval None
<>	144:ef7eb2e8f9f7	4072	*/
<>	144:ef7eb2e8f9f7	4073	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4074	{
<>	144:ef7eb2e8f9f7	4075	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
<>	144:ef7eb2e8f9f7	4076	}
<>	144:ef7eb2e8f9f7	4077
<>	144:ef7eb2e8f9f7	4078	/**
<>	144:ef7eb2e8f9f7	4079	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
<>	144:ef7eb2e8f9f7	4080	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
<>	144:ef7eb2e8f9f7	4081	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4082	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4083	*/
<>	144:ef7eb2e8f9f7	4084	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4085	{
<>	144:ef7eb2e8f9f7	4086	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
<>	144:ef7eb2e8f9f7	4087	}
<>	144:ef7eb2e8f9f7	4088
<>	144:ef7eb2e8f9f7	4089	/**
<>	144:ef7eb2e8f9f7	4090	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
<>	144:ef7eb2e8f9f7	4091	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
<>	144:ef7eb2e8f9f7	4092	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4093	* @retval None
<>	144:ef7eb2e8f9f7	4094	*/
<>	144:ef7eb2e8f9f7	4095	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4096	{
<>	144:ef7eb2e8f9f7	4097	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
<>	144:ef7eb2e8f9f7	4098	}
<>	144:ef7eb2e8f9f7	4099
<>	144:ef7eb2e8f9f7	4100	/**
<>	144:ef7eb2e8f9f7	4101	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
<>	144:ef7eb2e8f9f7	4102	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
<>	144:ef7eb2e8f9f7	4103	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4104	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4105	*/
<>	144:ef7eb2e8f9f7	4106	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4107	{
<>	144:ef7eb2e8f9f7	4108	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
<>	144:ef7eb2e8f9f7	4109	}
<>	144:ef7eb2e8f9f7	4110
<>	144:ef7eb2e8f9f7	4111	/**
<>	144:ef7eb2e8f9f7	4112	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
<>	144:ef7eb2e8f9f7	4113	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
<>	144:ef7eb2e8f9f7	4114	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4115	* @retval None
<>	144:ef7eb2e8f9f7	4116	*/
<>	144:ef7eb2e8f9f7	4117	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4118	{
<>	144:ef7eb2e8f9f7	4119	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
<>	144:ef7eb2e8f9f7	4120	}
<>	144:ef7eb2e8f9f7	4121
<>	144:ef7eb2e8f9f7	4122	/**
<>	144:ef7eb2e8f9f7	4123	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
<>	144:ef7eb2e8f9f7	4124	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
<>	144:ef7eb2e8f9f7	4125	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4126	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4127	*/
<>	144:ef7eb2e8f9f7	4128	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4129	{
<>	144:ef7eb2e8f9f7	4130	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
<>	144:ef7eb2e8f9f7	4131	}
<>	144:ef7eb2e8f9f7	4132
<>	144:ef7eb2e8f9f7	4133	/**
<>	144:ef7eb2e8f9f7	4134	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
<>	144:ef7eb2e8f9f7	4135	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
<>	144:ef7eb2e8f9f7	4136	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4137	* @retval None
<>	144:ef7eb2e8f9f7	4138	*/
<>	144:ef7eb2e8f9f7	4139	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4140	{
<>	144:ef7eb2e8f9f7	4141	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
<>	144:ef7eb2e8f9f7	4142	}
<>	144:ef7eb2e8f9f7	4143
<>	144:ef7eb2e8f9f7	4144	/**
<>	144:ef7eb2e8f9f7	4145	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
<>	144:ef7eb2e8f9f7	4146	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
<>	144:ef7eb2e8f9f7	4147	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4148	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4149	*/
<>	144:ef7eb2e8f9f7	4150	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4151	{
<>	144:ef7eb2e8f9f7	4152	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
<>	144:ef7eb2e8f9f7	4153	}
<>	144:ef7eb2e8f9f7	4154
<>	144:ef7eb2e8f9f7	4155	/**
<>	144:ef7eb2e8f9f7	4156	* @brief Clear the system break interrupt flag (SBIF).
<>	144:ef7eb2e8f9f7	4157	* @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
<>	144:ef7eb2e8f9f7	4158	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4159	* @retval None
<>	144:ef7eb2e8f9f7	4160	*/
<>	144:ef7eb2e8f9f7	4161	__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4162	{
<>	144:ef7eb2e8f9f7	4163	WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
<>	144:ef7eb2e8f9f7	4164	}
<>	144:ef7eb2e8f9f7	4165
<>	144:ef7eb2e8f9f7	4166	/**
<>	144:ef7eb2e8f9f7	4167	* @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
<>	144:ef7eb2e8f9f7	4168	* @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
<>	144:ef7eb2e8f9f7	4169	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4170	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4171	*/
<>	144:ef7eb2e8f9f7	4172	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4173	{
<>	144:ef7eb2e8f9f7	4174	return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF));
<>	144:ef7eb2e8f9f7	4175	}
<>	144:ef7eb2e8f9f7	4176
<>	144:ef7eb2e8f9f7	4177	/**
<>	144:ef7eb2e8f9f7	4178	* @}
<>	144:ef7eb2e8f9f7	4179	*/
<>	144:ef7eb2e8f9f7	4180
<>	144:ef7eb2e8f9f7	4181	/** @defgroup TIM_LL_EF_IT_Management IT-Management
<>	144:ef7eb2e8f9f7	4182	* @{
<>	144:ef7eb2e8f9f7	4183	*/
<>	144:ef7eb2e8f9f7	4184	/**
<>	144:ef7eb2e8f9f7	4185	* @brief Enable update interrupt (UIE).
<>	144:ef7eb2e8f9f7	4186	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
<>	144:ef7eb2e8f9f7	4187	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4188	* @retval None
<>	144:ef7eb2e8f9f7	4189	*/
<>	144:ef7eb2e8f9f7	4190	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4191	{
<>	144:ef7eb2e8f9f7	4192	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	144:ef7eb2e8f9f7	4193	}
<>	144:ef7eb2e8f9f7	4194
<>	144:ef7eb2e8f9f7	4195	/**
<>	144:ef7eb2e8f9f7	4196	* @brief Disable update interrupt (UIE).
<>	144:ef7eb2e8f9f7	4197	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
<>	144:ef7eb2e8f9f7	4198	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4199	* @retval None
<>	144:ef7eb2e8f9f7	4200	*/
<>	144:ef7eb2e8f9f7	4201	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4202	{
<>	144:ef7eb2e8f9f7	4203	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	144:ef7eb2e8f9f7	4204	}
<>	144:ef7eb2e8f9f7	4205
<>	144:ef7eb2e8f9f7	4206	/**
<>	144:ef7eb2e8f9f7	4207	* @brief Indicates whether the update interrupt (UIE) is enabled.
<>	144:ef7eb2e8f9f7	4208	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
<>	144:ef7eb2e8f9f7	4209	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4210	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4211	*/
<>	144:ef7eb2e8f9f7	4212	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4213	{
<>	144:ef7eb2e8f9f7	4214	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
<>	144:ef7eb2e8f9f7	4215	}
<>	144:ef7eb2e8f9f7	4216
<>	144:ef7eb2e8f9f7	4217	/**
<>	144:ef7eb2e8f9f7	4218	* @brief Enable capture/compare 1 interrupt (CC1IE).
<>	144:ef7eb2e8f9f7	4219	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
<>	144:ef7eb2e8f9f7	4220	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4221	* @retval None
<>	144:ef7eb2e8f9f7	4222	*/
<>	144:ef7eb2e8f9f7	4223	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4224	{
<>	144:ef7eb2e8f9f7	4225	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	144:ef7eb2e8f9f7	4226	}
<>	144:ef7eb2e8f9f7	4227
<>	144:ef7eb2e8f9f7	4228	/**
<>	144:ef7eb2e8f9f7	4229	* @brief Disable capture/compare 1 interrupt (CC1IE).
<>	144:ef7eb2e8f9f7	4230	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
<>	144:ef7eb2e8f9f7	4231	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4232	* @retval None
<>	144:ef7eb2e8f9f7	4233	*/
<>	144:ef7eb2e8f9f7	4234	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4235	{
<>	144:ef7eb2e8f9f7	4236	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	144:ef7eb2e8f9f7	4237	}
<>	144:ef7eb2e8f9f7	4238
<>	144:ef7eb2e8f9f7	4239	/**
<>	144:ef7eb2e8f9f7	4240	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
<>	144:ef7eb2e8f9f7	4241	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
<>	144:ef7eb2e8f9f7	4242	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4243	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4244	*/
<>	144:ef7eb2e8f9f7	4245	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4246	{
<>	144:ef7eb2e8f9f7	4247	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
<>	144:ef7eb2e8f9f7	4248	}
<>	144:ef7eb2e8f9f7	4249
<>	144:ef7eb2e8f9f7	4250	/**
<>	144:ef7eb2e8f9f7	4251	* @brief Enable capture/compare 2 interrupt (CC2IE).
<>	144:ef7eb2e8f9f7	4252	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
<>	144:ef7eb2e8f9f7	4253	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4254	* @retval None
<>	144:ef7eb2e8f9f7	4255	*/
<>	144:ef7eb2e8f9f7	4256	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4257	{
<>	144:ef7eb2e8f9f7	4258	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	144:ef7eb2e8f9f7	4259	}
<>	144:ef7eb2e8f9f7	4260
<>	144:ef7eb2e8f9f7	4261	/**
<>	144:ef7eb2e8f9f7	4262	* @brief Disable capture/compare 2 interrupt (CC2IE).
<>	144:ef7eb2e8f9f7	4263	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
<>	144:ef7eb2e8f9f7	4264	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4265	* @retval None
<>	144:ef7eb2e8f9f7	4266	*/
<>	144:ef7eb2e8f9f7	4267	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4268	{
<>	144:ef7eb2e8f9f7	4269	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	144:ef7eb2e8f9f7	4270	}
<>	144:ef7eb2e8f9f7	4271
<>	144:ef7eb2e8f9f7	4272	/**
<>	144:ef7eb2e8f9f7	4273	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
<>	144:ef7eb2e8f9f7	4274	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
<>	144:ef7eb2e8f9f7	4275	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4276	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4277	*/
<>	144:ef7eb2e8f9f7	4278	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4279	{
<>	144:ef7eb2e8f9f7	4280	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
<>	144:ef7eb2e8f9f7	4281	}
<>	144:ef7eb2e8f9f7	4282
<>	144:ef7eb2e8f9f7	4283	/**
<>	144:ef7eb2e8f9f7	4284	* @brief Enable capture/compare 3 interrupt (CC3IE).
<>	144:ef7eb2e8f9f7	4285	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
<>	144:ef7eb2e8f9f7	4286	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4287	* @retval None
<>	144:ef7eb2e8f9f7	4288	*/
<>	144:ef7eb2e8f9f7	4289	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4290	{
<>	144:ef7eb2e8f9f7	4291	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	144:ef7eb2e8f9f7	4292	}
<>	144:ef7eb2e8f9f7	4293
<>	144:ef7eb2e8f9f7	4294	/**
<>	144:ef7eb2e8f9f7	4295	* @brief Disable capture/compare 3 interrupt (CC3IE).
<>	144:ef7eb2e8f9f7	4296	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
<>	144:ef7eb2e8f9f7	4297	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4298	* @retval None
<>	144:ef7eb2e8f9f7	4299	*/
<>	144:ef7eb2e8f9f7	4300	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4301	{
<>	144:ef7eb2e8f9f7	4302	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	144:ef7eb2e8f9f7	4303	}
<>	144:ef7eb2e8f9f7	4304
<>	144:ef7eb2e8f9f7	4305	/**
<>	144:ef7eb2e8f9f7	4306	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
<>	144:ef7eb2e8f9f7	4307	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
<>	144:ef7eb2e8f9f7	4308	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4309	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4310	*/
<>	144:ef7eb2e8f9f7	4311	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4312	{
<>	144:ef7eb2e8f9f7	4313	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
<>	144:ef7eb2e8f9f7	4314	}
<>	144:ef7eb2e8f9f7	4315
<>	144:ef7eb2e8f9f7	4316	/**
<>	144:ef7eb2e8f9f7	4317	* @brief Enable capture/compare 4 interrupt (CC4IE).
<>	144:ef7eb2e8f9f7	4318	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
<>	144:ef7eb2e8f9f7	4319	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4320	* @retval None
<>	144:ef7eb2e8f9f7	4321	*/
<>	144:ef7eb2e8f9f7	4322	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4323	{
<>	144:ef7eb2e8f9f7	4324	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	144:ef7eb2e8f9f7	4325	}
<>	144:ef7eb2e8f9f7	4326
<>	144:ef7eb2e8f9f7	4327	/**
<>	144:ef7eb2e8f9f7	4328	* @brief Disable capture/compare 4 interrupt (CC4IE).
<>	144:ef7eb2e8f9f7	4329	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
<>	144:ef7eb2e8f9f7	4330	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4331	* @retval None
<>	144:ef7eb2e8f9f7	4332	*/
<>	144:ef7eb2e8f9f7	4333	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4334	{
<>	144:ef7eb2e8f9f7	4335	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	144:ef7eb2e8f9f7	4336	}
<>	144:ef7eb2e8f9f7	4337
<>	144:ef7eb2e8f9f7	4338	/**
<>	144:ef7eb2e8f9f7	4339	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
<>	144:ef7eb2e8f9f7	4340	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
<>	144:ef7eb2e8f9f7	4341	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4342	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4343	*/
<>	144:ef7eb2e8f9f7	4344	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4345	{
<>	144:ef7eb2e8f9f7	4346	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
<>	144:ef7eb2e8f9f7	4347	}
<>	144:ef7eb2e8f9f7	4348
<>	144:ef7eb2e8f9f7	4349	/**
<>	144:ef7eb2e8f9f7	4350	* @brief Enable commutation interrupt (COMIE).
<>	144:ef7eb2e8f9f7	4351	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
<>	144:ef7eb2e8f9f7	4352	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4353	* @retval None
<>	144:ef7eb2e8f9f7	4354	*/
<>	144:ef7eb2e8f9f7	4355	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4356	{
<>	144:ef7eb2e8f9f7	4357	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
<>	144:ef7eb2e8f9f7	4358	}
<>	144:ef7eb2e8f9f7	4359
<>	144:ef7eb2e8f9f7	4360	/**
<>	144:ef7eb2e8f9f7	4361	* @brief Disable commutation interrupt (COMIE).
<>	144:ef7eb2e8f9f7	4362	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
<>	144:ef7eb2e8f9f7	4363	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4364	* @retval None
<>	144:ef7eb2e8f9f7	4365	*/
<>	144:ef7eb2e8f9f7	4366	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4367	{
<>	144:ef7eb2e8f9f7	4368	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
<>	144:ef7eb2e8f9f7	4369	}
<>	144:ef7eb2e8f9f7	4370
<>	144:ef7eb2e8f9f7	4371	/**
<>	144:ef7eb2e8f9f7	4372	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
<>	144:ef7eb2e8f9f7	4373	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
<>	144:ef7eb2e8f9f7	4374	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4375	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4376	*/
<>	144:ef7eb2e8f9f7	4377	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4378	{
<>	144:ef7eb2e8f9f7	4379	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
<>	144:ef7eb2e8f9f7	4380	}
<>	144:ef7eb2e8f9f7	4381
<>	144:ef7eb2e8f9f7	4382	/**
<>	144:ef7eb2e8f9f7	4383	* @brief Enable trigger interrupt (TIE).
<>	144:ef7eb2e8f9f7	4384	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
<>	144:ef7eb2e8f9f7	4385	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4386	* @retval None
<>	144:ef7eb2e8f9f7	4387	*/
<>	144:ef7eb2e8f9f7	4388	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4389	{
<>	144:ef7eb2e8f9f7	4390	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	144:ef7eb2e8f9f7	4391	}
<>	144:ef7eb2e8f9f7	4392
<>	144:ef7eb2e8f9f7	4393	/**
<>	144:ef7eb2e8f9f7	4394	* @brief Disable trigger interrupt (TIE).
<>	144:ef7eb2e8f9f7	4395	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
<>	144:ef7eb2e8f9f7	4396	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4397	* @retval None
<>	144:ef7eb2e8f9f7	4398	*/
<>	144:ef7eb2e8f9f7	4399	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4400	{
<>	144:ef7eb2e8f9f7	4401	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	144:ef7eb2e8f9f7	4402	}
<>	144:ef7eb2e8f9f7	4403
<>	144:ef7eb2e8f9f7	4404	/**
<>	144:ef7eb2e8f9f7	4405	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
<>	144:ef7eb2e8f9f7	4406	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
<>	144:ef7eb2e8f9f7	4407	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4408	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4409	*/
<>	144:ef7eb2e8f9f7	4410	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4411	{
<>	144:ef7eb2e8f9f7	4412	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
<>	144:ef7eb2e8f9f7	4413	}
<>	144:ef7eb2e8f9f7	4414
<>	144:ef7eb2e8f9f7	4415	/**
<>	144:ef7eb2e8f9f7	4416	* @brief Enable break interrupt (BIE).
<>	144:ef7eb2e8f9f7	4417	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
<>	144:ef7eb2e8f9f7	4418	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4419	* @retval None
<>	144:ef7eb2e8f9f7	4420	*/
<>	144:ef7eb2e8f9f7	4421	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4422	{
<>	144:ef7eb2e8f9f7	4423	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
<>	144:ef7eb2e8f9f7	4424	}
<>	144:ef7eb2e8f9f7	4425
<>	144:ef7eb2e8f9f7	4426	/**
<>	144:ef7eb2e8f9f7	4427	* @brief Disable break interrupt (BIE).
<>	144:ef7eb2e8f9f7	4428	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
<>	144:ef7eb2e8f9f7	4429	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4430	* @retval None
<>	144:ef7eb2e8f9f7	4431	*/
<>	144:ef7eb2e8f9f7	4432	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4433	{
<>	144:ef7eb2e8f9f7	4434	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
<>	144:ef7eb2e8f9f7	4435	}
<>	144:ef7eb2e8f9f7	4436
<>	144:ef7eb2e8f9f7	4437	/**
<>	144:ef7eb2e8f9f7	4438	* @brief Indicates whether the break interrupt (BIE) is enabled.
<>	144:ef7eb2e8f9f7	4439	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
<>	144:ef7eb2e8f9f7	4440	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4441	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4442	*/
<>	144:ef7eb2e8f9f7	4443	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4444	{
<>	144:ef7eb2e8f9f7	4445	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
<>	144:ef7eb2e8f9f7	4446	}
<>	144:ef7eb2e8f9f7	4447
<>	144:ef7eb2e8f9f7	4448	/**
<>	144:ef7eb2e8f9f7	4449	* @}
<>	144:ef7eb2e8f9f7	4450	*/
<>	144:ef7eb2e8f9f7	4451
<>	144:ef7eb2e8f9f7	4452	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
<>	144:ef7eb2e8f9f7	4453	* @{
<>	144:ef7eb2e8f9f7	4454	*/
<>	144:ef7eb2e8f9f7	4455	/**
<>	144:ef7eb2e8f9f7	4456	* @brief Enable update DMA request (UDE).
<>	144:ef7eb2e8f9f7	4457	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
<>	144:ef7eb2e8f9f7	4458	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4459	* @retval None
<>	144:ef7eb2e8f9f7	4460	*/
<>	144:ef7eb2e8f9f7	4461	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4462	{
<>	144:ef7eb2e8f9f7	4463	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	144:ef7eb2e8f9f7	4464	}
<>	144:ef7eb2e8f9f7	4465
<>	144:ef7eb2e8f9f7	4466	/**
<>	144:ef7eb2e8f9f7	4467	* @brief Disable update DMA request (UDE).
<>	144:ef7eb2e8f9f7	4468	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
<>	144:ef7eb2e8f9f7	4469	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4470	* @retval None
<>	144:ef7eb2e8f9f7	4471	*/
<>	144:ef7eb2e8f9f7	4472	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4473	{
<>	144:ef7eb2e8f9f7	4474	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	144:ef7eb2e8f9f7	4475	}
<>	144:ef7eb2e8f9f7	4476
<>	144:ef7eb2e8f9f7	4477	/**
<>	144:ef7eb2e8f9f7	4478	* @brief Indicates whether the update DMA request (UDE) is enabled.
<>	144:ef7eb2e8f9f7	4479	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
<>	144:ef7eb2e8f9f7	4480	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4481	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4482	*/
<>	144:ef7eb2e8f9f7	4483	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4484	{
<>	144:ef7eb2e8f9f7	4485	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
<>	144:ef7eb2e8f9f7	4486	}
<>	144:ef7eb2e8f9f7	4487
<>	144:ef7eb2e8f9f7	4488	/**
<>	144:ef7eb2e8f9f7	4489	* @brief Enable capture/compare 1 DMA request (CC1DE).
<>	144:ef7eb2e8f9f7	4490	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
<>	144:ef7eb2e8f9f7	4491	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4492	* @retval None
<>	144:ef7eb2e8f9f7	4493	*/
<>	144:ef7eb2e8f9f7	4494	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4495	{
<>	144:ef7eb2e8f9f7	4496	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	144:ef7eb2e8f9f7	4497	}
<>	144:ef7eb2e8f9f7	4498
<>	144:ef7eb2e8f9f7	4499	/**
<>	144:ef7eb2e8f9f7	4500	* @brief Disable capture/compare 1 DMA request (CC1DE).
<>	144:ef7eb2e8f9f7	4501	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
<>	144:ef7eb2e8f9f7	4502	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4503	* @retval None
<>	144:ef7eb2e8f9f7	4504	*/
<>	144:ef7eb2e8f9f7	4505	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4506	{
<>	144:ef7eb2e8f9f7	4507	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	144:ef7eb2e8f9f7	4508	}
<>	144:ef7eb2e8f9f7	4509
<>	144:ef7eb2e8f9f7	4510	/**
<>	144:ef7eb2e8f9f7	4511	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
<>	144:ef7eb2e8f9f7	4512	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
<>	144:ef7eb2e8f9f7	4513	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4514	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4515	*/
<>	144:ef7eb2e8f9f7	4516	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4517	{
<>	144:ef7eb2e8f9f7	4518	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
<>	144:ef7eb2e8f9f7	4519	}
<>	144:ef7eb2e8f9f7	4520
<>	144:ef7eb2e8f9f7	4521	/**
<>	144:ef7eb2e8f9f7	4522	* @brief Enable capture/compare 2 DMA request (CC2DE).
<>	144:ef7eb2e8f9f7	4523	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
<>	144:ef7eb2e8f9f7	4524	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4525	* @retval None
<>	144:ef7eb2e8f9f7	4526	*/
<>	144:ef7eb2e8f9f7	4527	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4528	{
<>	144:ef7eb2e8f9f7	4529	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	144:ef7eb2e8f9f7	4530	}
<>	144:ef7eb2e8f9f7	4531
<>	144:ef7eb2e8f9f7	4532	/**
<>	144:ef7eb2e8f9f7	4533	* @brief Disable capture/compare 2 DMA request (CC2DE).
<>	144:ef7eb2e8f9f7	4534	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
<>	144:ef7eb2e8f9f7	4535	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4536	* @retval None
<>	144:ef7eb2e8f9f7	4537	*/
<>	144:ef7eb2e8f9f7	4538	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4539	{
<>	144:ef7eb2e8f9f7	4540	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	144:ef7eb2e8f9f7	4541	}
<>	144:ef7eb2e8f9f7	4542
<>	144:ef7eb2e8f9f7	4543	/**
<>	144:ef7eb2e8f9f7	4544	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
<>	144:ef7eb2e8f9f7	4545	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
<>	144:ef7eb2e8f9f7	4546	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4547	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4548	*/
<>	144:ef7eb2e8f9f7	4549	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4550	{
<>	144:ef7eb2e8f9f7	4551	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
<>	144:ef7eb2e8f9f7	4552	}
<>	144:ef7eb2e8f9f7	4553
<>	144:ef7eb2e8f9f7	4554	/**
<>	144:ef7eb2e8f9f7	4555	* @brief Enable capture/compare 3 DMA request (CC3DE).
<>	144:ef7eb2e8f9f7	4556	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
<>	144:ef7eb2e8f9f7	4557	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4558	* @retval None
<>	144:ef7eb2e8f9f7	4559	*/
<>	144:ef7eb2e8f9f7	4560	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4561	{
<>	144:ef7eb2e8f9f7	4562	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	144:ef7eb2e8f9f7	4563	}
<>	144:ef7eb2e8f9f7	4564
<>	144:ef7eb2e8f9f7	4565	/**
<>	144:ef7eb2e8f9f7	4566	* @brief Disable capture/compare 3 DMA request (CC3DE).
<>	144:ef7eb2e8f9f7	4567	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
<>	144:ef7eb2e8f9f7	4568	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4569	* @retval None
<>	144:ef7eb2e8f9f7	4570	*/
<>	144:ef7eb2e8f9f7	4571	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4572	{
<>	144:ef7eb2e8f9f7	4573	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	144:ef7eb2e8f9f7	4574	}
<>	144:ef7eb2e8f9f7	4575
<>	144:ef7eb2e8f9f7	4576	/**
<>	144:ef7eb2e8f9f7	4577	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
<>	144:ef7eb2e8f9f7	4578	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
<>	144:ef7eb2e8f9f7	4579	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4580	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4581	*/
<>	144:ef7eb2e8f9f7	4582	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4583	{
<>	144:ef7eb2e8f9f7	4584	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
<>	144:ef7eb2e8f9f7	4585	}
<>	144:ef7eb2e8f9f7	4586
<>	144:ef7eb2e8f9f7	4587	/**
<>	144:ef7eb2e8f9f7	4588	* @brief Enable capture/compare 4 DMA request (CC4DE).
<>	144:ef7eb2e8f9f7	4589	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
<>	144:ef7eb2e8f9f7	4590	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4591	* @retval None
<>	144:ef7eb2e8f9f7	4592	*/
<>	144:ef7eb2e8f9f7	4593	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4594	{
<>	144:ef7eb2e8f9f7	4595	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	144:ef7eb2e8f9f7	4596	}
<>	144:ef7eb2e8f9f7	4597
<>	144:ef7eb2e8f9f7	4598	/**
<>	144:ef7eb2e8f9f7	4599	* @brief Disable capture/compare 4 DMA request (CC4DE).
<>	144:ef7eb2e8f9f7	4600	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
<>	144:ef7eb2e8f9f7	4601	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4602	* @retval None
<>	144:ef7eb2e8f9f7	4603	*/
<>	144:ef7eb2e8f9f7	4604	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4605	{
<>	144:ef7eb2e8f9f7	4606	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	144:ef7eb2e8f9f7	4607	}
<>	144:ef7eb2e8f9f7	4608
<>	144:ef7eb2e8f9f7	4609	/**
<>	144:ef7eb2e8f9f7	4610	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
<>	144:ef7eb2e8f9f7	4611	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
<>	144:ef7eb2e8f9f7	4612	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4613	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4614	*/
<>	144:ef7eb2e8f9f7	4615	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4616	{
<>	144:ef7eb2e8f9f7	4617	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
<>	144:ef7eb2e8f9f7	4618	}
<>	144:ef7eb2e8f9f7	4619
<>	144:ef7eb2e8f9f7	4620	/**
<>	144:ef7eb2e8f9f7	4621	* @brief Enable commutation DMA request (COMDE).
<>	144:ef7eb2e8f9f7	4622	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
<>	144:ef7eb2e8f9f7	4623	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4624	* @retval None
<>	144:ef7eb2e8f9f7	4625	*/
<>	144:ef7eb2e8f9f7	4626	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4627	{
<>	144:ef7eb2e8f9f7	4628	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
<>	144:ef7eb2e8f9f7	4629	}
<>	144:ef7eb2e8f9f7	4630
<>	144:ef7eb2e8f9f7	4631	/**
<>	144:ef7eb2e8f9f7	4632	* @brief Disable commutation DMA request (COMDE).
<>	144:ef7eb2e8f9f7	4633	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
<>	144:ef7eb2e8f9f7	4634	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4635	* @retval None
<>	144:ef7eb2e8f9f7	4636	*/
<>	144:ef7eb2e8f9f7	4637	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4638	{
<>	144:ef7eb2e8f9f7	4639	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
<>	144:ef7eb2e8f9f7	4640	}
<>	144:ef7eb2e8f9f7	4641
<>	144:ef7eb2e8f9f7	4642	/**
<>	144:ef7eb2e8f9f7	4643	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
<>	144:ef7eb2e8f9f7	4644	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
<>	144:ef7eb2e8f9f7	4645	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4646	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4647	*/
<>	144:ef7eb2e8f9f7	4648	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4649	{
<>	144:ef7eb2e8f9f7	4650	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
<>	144:ef7eb2e8f9f7	4651	}
<>	144:ef7eb2e8f9f7	4652
<>	144:ef7eb2e8f9f7	4653	/**
<>	144:ef7eb2e8f9f7	4654	* @brief Enable trigger interrupt (TDE).
<>	144:ef7eb2e8f9f7	4655	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
<>	144:ef7eb2e8f9f7	4656	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4657	* @retval None
<>	144:ef7eb2e8f9f7	4658	*/
<>	144:ef7eb2e8f9f7	4659	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4660	{
<>	144:ef7eb2e8f9f7	4661	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	144:ef7eb2e8f9f7	4662	}
<>	144:ef7eb2e8f9f7	4663
<>	144:ef7eb2e8f9f7	4664	/**
<>	144:ef7eb2e8f9f7	4665	* @brief Disable trigger interrupt (TDE).
<>	144:ef7eb2e8f9f7	4666	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
<>	144:ef7eb2e8f9f7	4667	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4668	* @retval None
<>	144:ef7eb2e8f9f7	4669	*/
<>	144:ef7eb2e8f9f7	4670	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4671	{
<>	144:ef7eb2e8f9f7	4672	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	144:ef7eb2e8f9f7	4673	}
<>	144:ef7eb2e8f9f7	4674
<>	144:ef7eb2e8f9f7	4675	/**
<>	144:ef7eb2e8f9f7	4676	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
<>	144:ef7eb2e8f9f7	4677	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
<>	144:ef7eb2e8f9f7	4678	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4679	* @retval State of bit (1 or 0).
<>	144:ef7eb2e8f9f7	4680	*/
<>	144:ef7eb2e8f9f7	4681	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4682	{
<>	144:ef7eb2e8f9f7	4683	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
<>	144:ef7eb2e8f9f7	4684	}
<>	144:ef7eb2e8f9f7	4685
<>	144:ef7eb2e8f9f7	4686	/**
<>	144:ef7eb2e8f9f7	4687	* @}
<>	144:ef7eb2e8f9f7	4688	*/
<>	144:ef7eb2e8f9f7	4689
<>	144:ef7eb2e8f9f7	4690	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
<>	144:ef7eb2e8f9f7	4691	* @{
<>	144:ef7eb2e8f9f7	4692	*/
<>	144:ef7eb2e8f9f7	4693	/**
<>	144:ef7eb2e8f9f7	4694	* @brief Generate an update event.
<>	144:ef7eb2e8f9f7	4695	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
<>	144:ef7eb2e8f9f7	4696	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4697	* @retval None
<>	144:ef7eb2e8f9f7	4698	*/
<>	144:ef7eb2e8f9f7	4699	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4700	{
<>	144:ef7eb2e8f9f7	4701	SET_BIT(TIMx->EGR, TIM_EGR_UG);
<>	144:ef7eb2e8f9f7	4702	}
<>	144:ef7eb2e8f9f7	4703
<>	144:ef7eb2e8f9f7	4704	/**
<>	144:ef7eb2e8f9f7	4705	* @brief Generate Capture/Compare 1 event.
<>	144:ef7eb2e8f9f7	4706	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
<>	144:ef7eb2e8f9f7	4707	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4708	* @retval None
<>	144:ef7eb2e8f9f7	4709	*/
<>	144:ef7eb2e8f9f7	4710	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4711	{
<>	144:ef7eb2e8f9f7	4712	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
<>	144:ef7eb2e8f9f7	4713	}
<>	144:ef7eb2e8f9f7	4714
<>	144:ef7eb2e8f9f7	4715	/**
<>	144:ef7eb2e8f9f7	4716	* @brief Generate Capture/Compare 2 event.
<>	144:ef7eb2e8f9f7	4717	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
<>	144:ef7eb2e8f9f7	4718	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4719	* @retval None
<>	144:ef7eb2e8f9f7	4720	*/
<>	144:ef7eb2e8f9f7	4721	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4722	{
<>	144:ef7eb2e8f9f7	4723	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
<>	144:ef7eb2e8f9f7	4724	}
<>	144:ef7eb2e8f9f7	4725
<>	144:ef7eb2e8f9f7	4726	/**
<>	144:ef7eb2e8f9f7	4727	* @brief Generate Capture/Compare 3 event.
<>	144:ef7eb2e8f9f7	4728	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
<>	144:ef7eb2e8f9f7	4729	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4730	* @retval None
<>	144:ef7eb2e8f9f7	4731	*/
<>	144:ef7eb2e8f9f7	4732	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4733	{
<>	144:ef7eb2e8f9f7	4734	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
<>	144:ef7eb2e8f9f7	4735	}
<>	144:ef7eb2e8f9f7	4736
<>	144:ef7eb2e8f9f7	4737	/**
<>	144:ef7eb2e8f9f7	4738	* @brief Generate Capture/Compare 4 event.
<>	144:ef7eb2e8f9f7	4739	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
<>	144:ef7eb2e8f9f7	4740	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4741	* @retval None
<>	144:ef7eb2e8f9f7	4742	*/
<>	144:ef7eb2e8f9f7	4743	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4744	{
<>	144:ef7eb2e8f9f7	4745	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
<>	144:ef7eb2e8f9f7	4746	}
<>	144:ef7eb2e8f9f7	4747
<>	144:ef7eb2e8f9f7	4748	/**
<>	144:ef7eb2e8f9f7	4749	* @brief Generate commutation event.
<>	144:ef7eb2e8f9f7	4750	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
<>	144:ef7eb2e8f9f7	4751	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4752	* @retval None
<>	144:ef7eb2e8f9f7	4753	*/
<>	144:ef7eb2e8f9f7	4754	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4755	{
<>	144:ef7eb2e8f9f7	4756	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
<>	144:ef7eb2e8f9f7	4757	}
<>	144:ef7eb2e8f9f7	4758
<>	144:ef7eb2e8f9f7	4759	/**
<>	144:ef7eb2e8f9f7	4760	* @brief Generate trigger event.
<>	144:ef7eb2e8f9f7	4761	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
<>	144:ef7eb2e8f9f7	4762	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4763	* @retval None
<>	144:ef7eb2e8f9f7	4764	*/
<>	144:ef7eb2e8f9f7	4765	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4766	{
<>	144:ef7eb2e8f9f7	4767	SET_BIT(TIMx->EGR, TIM_EGR_TG);
<>	144:ef7eb2e8f9f7	4768	}
<>	144:ef7eb2e8f9f7	4769
<>	144:ef7eb2e8f9f7	4770	/**
<>	144:ef7eb2e8f9f7	4771	* @brief Generate break event.
<>	144:ef7eb2e8f9f7	4772	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
<>	144:ef7eb2e8f9f7	4773	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4774	* @retval None
<>	144:ef7eb2e8f9f7	4775	*/
<>	144:ef7eb2e8f9f7	4776	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4777	{
<>	144:ef7eb2e8f9f7	4778	SET_BIT(TIMx->EGR, TIM_EGR_BG);
<>	144:ef7eb2e8f9f7	4779	}
<>	144:ef7eb2e8f9f7	4780
<>	144:ef7eb2e8f9f7	4781	/**
<>	144:ef7eb2e8f9f7	4782	* @brief Generate break 2 event.
<>	144:ef7eb2e8f9f7	4783	* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
<>	144:ef7eb2e8f9f7	4784	* @param TIMx Timer instance
<>	144:ef7eb2e8f9f7	4785	* @retval None
<>	144:ef7eb2e8f9f7	4786	*/
<>	144:ef7eb2e8f9f7	4787	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)
<>	144:ef7eb2e8f9f7	4788	{
<>	144:ef7eb2e8f9f7	4789	SET_BIT(TIMx->EGR, TIM_EGR_B2G);
<>	144:ef7eb2e8f9f7	4790	}
<>	144:ef7eb2e8f9f7	4791
<>	144:ef7eb2e8f9f7	4792	/**
<>	144:ef7eb2e8f9f7	4793	* @}
<>	144:ef7eb2e8f9f7	4794	*/
<>	144:ef7eb2e8f9f7	4795
<>	144:ef7eb2e8f9f7	4796	#if defined(USE_FULL_LL_DRIVER)
<>	144:ef7eb2e8f9f7	4797	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
<>	144:ef7eb2e8f9f7	4798	* @{
<>	144:ef7eb2e8f9f7	4799	*/
<>	144:ef7eb2e8f9f7	4800
<>	144:ef7eb2e8f9f7	4801	ErrorStatus LL_TIM_DeInit(TIM_TypeDef* TIMx);
<>	144:ef7eb2e8f9f7	4802	void LL_TIM_StructInit(LL_TIM_InitTypeDef* TIM_InitStruct);
<>	144:ef7eb2e8f9f7	4803	ErrorStatus LL_TIM_Init(TIM_TypeDef* TIMx, LL_TIM_InitTypeDef* TIM_InitStruct);
<>	144:ef7eb2e8f9f7	4804	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct);
<>	144:ef7eb2e8f9f7	4805	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct);
<>	144:ef7eb2e8f9f7	4806	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef* TIM_ICInitStruct);
<>	144:ef7eb2e8f9f7	4807	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef* TIM_IC_InitStruct);
<>	144:ef7eb2e8f9f7	4808	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct);
<>	144:ef7eb2e8f9f7	4809	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef* TIMx, LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct);
<>	144:ef7eb2e8f9f7	4810	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct);
<>	144:ef7eb2e8f9f7	4811	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef* TIMx, LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct);
<>	144:ef7eb2e8f9f7	4812	/**
<>	144:ef7eb2e8f9f7	4813	* @}
<>	144:ef7eb2e8f9f7	4814	*/
<>	144:ef7eb2e8f9f7	4815	#endif /* USE_FULL_LL_DRIVER */
<>	144:ef7eb2e8f9f7	4816
<>	144:ef7eb2e8f9f7	4817	/**
<>	144:ef7eb2e8f9f7	4818	* @}
<>	144:ef7eb2e8f9f7	4819	*/
<>	144:ef7eb2e8f9f7	4820
<>	144:ef7eb2e8f9f7	4821	/**
<>	144:ef7eb2e8f9f7	4822	* @}
<>	144:ef7eb2e8f9f7	4823	*/
<>	144:ef7eb2e8f9f7	4824
<>	144:ef7eb2e8f9f7	4825	#endif /* TIM1 \|\| TIM8 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
<>	144:ef7eb2e8f9f7	4826
<>	144:ef7eb2e8f9f7	4827	/**
<>	144:ef7eb2e8f9f7	4828	* @}
<>	144:ef7eb2e8f9f7	4829	*/
<>	144:ef7eb2e8f9f7	4830
<>	144:ef7eb2e8f9f7	4831	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	4832	}
<>	144:ef7eb2e8f9f7	4833	#endif
<>	144:ef7eb2e8f9f7	4834
<>	144:ef7eb2e8f9f7	4835	#endif /* __STM32L4xx_LL_TIM_H */
<>	144:ef7eb2e8f9f7	4836
<>	144:ef7eb2e8f9f7	4837	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Repository details

Type:	Library
Created:	18 Dec 2017
Imports:	6
Forks:	0
Commits:	181
Dependents:	1
Dependencies:	0
Followers:	4

Important changes to repositories hosted on mbed.com

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_tim.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Important changes to repositories hosted on mbed.com

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_tim.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning