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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 113:b3775bf36a83

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l0xx_hal_i2c.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.0
<>	144:ef7eb2e8f9f7	6	* @date 8-January-2016
<>	144:ef7eb2e8f9f7	7	* @brief I2C HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Inter Integrated Circuit (I2C) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + IO operation functions
<>	144:ef7eb2e8f9f7	12	* + Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	13	*
<>	144:ef7eb2e8f9f7	14	@verbatim
<>	144:ef7eb2e8f9f7	15	==============================================================================
<>	144:ef7eb2e8f9f7	16	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	17	==============================================================================
<>	144:ef7eb2e8f9f7	18	[..]
<>	144:ef7eb2e8f9f7	19	The I2C HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	20
<>	144:ef7eb2e8f9f7	21	(#) Declare a I2C_HandleTypeDef handle structure, for example:
<>	144:ef7eb2e8f9f7	22	I2C_HandleTypeDef hi2c;
<>	144:ef7eb2e8f9f7	23
<>	144:ef7eb2e8f9f7	24	(#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API:
<>	144:ef7eb2e8f9f7	25	(##) Enable the I2Cx interface clock
<>	144:ef7eb2e8f9f7	26	(##) I2C pins configuration
<>	144:ef7eb2e8f9f7	27	(+++) Enable the clock for the I2C GPIOs
<>	144:ef7eb2e8f9f7	28	(+++) Configure I2C pins as alternate function open-drain
<>	144:ef7eb2e8f9f7	29	(##) NVIC configuration if you need to use interrupt process
<>	144:ef7eb2e8f9f7	30	(+++) Configure the I2Cx interrupt priority
<>	144:ef7eb2e8f9f7	31	(+++) Enable the NVIC I2C IRQ Channel
<>	144:ef7eb2e8f9f7	32	(##) DMA Configuration if you need to use DMA process
<>	144:ef7eb2e8f9f7	33	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
<>	144:ef7eb2e8f9f7	34	(+++) Enable the DMAx interface clock using
<>	144:ef7eb2e8f9f7	35	(+++) Configure the DMA handle parameters
<>	144:ef7eb2e8f9f7	36	(+++) Configure the DMA Tx or Rx channel
<>	144:ef7eb2e8f9f7	37	(+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
<>	144:ef7eb2e8f9f7	38	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
<>	144:ef7eb2e8f9f7	39	the DMA Tx or Rx channel
<>	144:ef7eb2e8f9f7	40
<>	144:ef7eb2e8f9f7	41	(#) Configure the Communication Clock Timing, Own Address1, Master Adressing Mode, Dual Addressing mode,
<>	144:ef7eb2e8f9f7	42	Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
<>	144:ef7eb2e8f9f7	45	(GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	52	=================================
<>	144:ef7eb2e8f9f7	53	[..]
<>	144:ef7eb2e8f9f7	54	(+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	55	(+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	56	(+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	57	(+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	58
<>	144:ef7eb2e8f9f7	59	* Polling mode IO MEM operation *
<>	144:ef7eb2e8f9f7	60	=====================================
<>	144:ef7eb2e8f9f7	61	[..]
<>	144:ef7eb2e8f9f7	62	(+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	63	(+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	64
<>	144:ef7eb2e8f9f7	65
<>	144:ef7eb2e8f9f7	66	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	67	===================================
<>	144:ef7eb2e8f9f7	68	[..]
<>	144:ef7eb2e8f9f7	69	(+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	70	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	71	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
<>	144:ef7eb2e8f9f7	72	(+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	73	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	74	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
<>	144:ef7eb2e8f9f7	75	(+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	76	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	77	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
<>	144:ef7eb2e8f9f7	78	(+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
<>	144:ef7eb2e8f9f7	79	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	80	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
<>	144:ef7eb2e8f9f7	81	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	82	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84	* Interrupt mode IO MEM operation *
<>	144:ef7eb2e8f9f7	85	=======================================
<>	144:ef7eb2e8f9f7	86	[..]
<>	144:ef7eb2e8f9f7	87	(+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
<>	144:ef7eb2e8f9f7	88	HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	89	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	90	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
<>	144:ef7eb2e8f9f7	91	(+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
<>	144:ef7eb2e8f9f7	92	HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	93	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	94	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
<>	144:ef7eb2e8f9f7	95	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	96	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	99	==============================
<>	144:ef7eb2e8f9f7	100	[..]
<>	144:ef7eb2e8f9f7	101	(+) Transmit in master mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	102	HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	103	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	104	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
<>	144:ef7eb2e8f9f7	105	(+) Receive in master mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	106	HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	107	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	108	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
<>	144:ef7eb2e8f9f7	109	(+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	110	HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	111	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	112	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
<>	144:ef7eb2e8f9f7	113	(+) Receive in slave mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	114	HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	115	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	116	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
<>	144:ef7eb2e8f9f7	117	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	118	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	119
<>	144:ef7eb2e8f9f7	120	* DMA mode IO MEM operation *
<>	144:ef7eb2e8f9f7	121	=================================
<>	144:ef7eb2e8f9f7	122	[..]
<>	144:ef7eb2e8f9f7	123	(+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
<>	144:ef7eb2e8f9f7	124	HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	125	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	126	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
<>	144:ef7eb2e8f9f7	127	(+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
<>	144:ef7eb2e8f9f7	128	HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	129	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	130	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
<>	144:ef7eb2e8f9f7	131	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	132	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	133
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	* I2C HAL driver macros list *
<>	144:ef7eb2e8f9f7	136	==================================
<>	144:ef7eb2e8f9f7	137	[..]
<>	144:ef7eb2e8f9f7	138	Below the list of most used macros in I2C HAL driver.
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
<>	144:ef7eb2e8f9f7	141	(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
<>	144:ef7eb2e8f9f7	142	(+) __HAL_I2C_GET_FLAG : Check whether the specified I2C flag is set or not
<>	144:ef7eb2e8f9f7	143	(+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
<>	144:ef7eb2e8f9f7	144	(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	145	(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	[..]
<>	144:ef7eb2e8f9f7	148	(@) You can refer to the I2C HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150	@endverbatim
<>	144:ef7eb2e8f9f7	151	******************************************************************************
<>	144:ef7eb2e8f9f7	152	* @attention
<>	144:ef7eb2e8f9f7	153	*
<>	144:ef7eb2e8f9f7	154	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	155	*
<>	144:ef7eb2e8f9f7	156	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	157	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	158	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	159	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	160	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	161	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	162	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	163	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	164	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	165	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	166	*
<>	144:ef7eb2e8f9f7	167	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	168	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	169	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	170	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	171	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	172	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	173	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	174	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	175	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	176	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	177	*
<>	144:ef7eb2e8f9f7	178	******************************************************************************
<>	144:ef7eb2e8f9f7	179	*/
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	182	#include "stm32l0xx_hal.h"
<>	144:ef7eb2e8f9f7	183
<>	144:ef7eb2e8f9f7	184	/** @addtogroup STM32L0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	185	* @{
<>	144:ef7eb2e8f9f7	186	*/
<>	144:ef7eb2e8f9f7	187
<>	144:ef7eb2e8f9f7	188	#ifdef HAL_I2C_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	189
<>	144:ef7eb2e8f9f7	190	/** @addtogroup I2C I2C
<>	144:ef7eb2e8f9f7	191	* @brief I2C HAL module driver
<>	144:ef7eb2e8f9f7	192	* @{
<>	144:ef7eb2e8f9f7	193	*/
<>	144:ef7eb2e8f9f7	194
<>	144:ef7eb2e8f9f7	195	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	196	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	197	/** @addtogroup I2C_Private
<>	144:ef7eb2e8f9f7	198	* @{
<>	144:ef7eb2e8f9f7	199	*/
<>	144:ef7eb2e8f9f7	200	#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /<! I2C TIMING clear register Mask /
<>	144:ef7eb2e8f9f7	201	#define I2C_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
<>	144:ef7eb2e8f9f7	202	#define I2C_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
<>	144:ef7eb2e8f9f7	203	#define I2C_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
<>	144:ef7eb2e8f9f7	204	#define I2C_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
<>	144:ef7eb2e8f9f7	205	#define I2C_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
<>	144:ef7eb2e8f9f7	206	#define I2C_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
<>	144:ef7eb2e8f9f7	207	#define I2C_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
<>	144:ef7eb2e8f9f7	208	#define I2C_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
<>	144:ef7eb2e8f9f7	209	#define I2C_TIMEOUT_FLAG ((uint32_t)25) /* 25 ms */
<>	144:ef7eb2e8f9f7	210	/**
<>	144:ef7eb2e8f9f7	211	* @}
<>	144:ef7eb2e8f9f7	212	*/
<>	144:ef7eb2e8f9f7	213
<>	144:ef7eb2e8f9f7	214	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	215	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	216	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	217	/** @addtogroup I2C_Private
<>	144:ef7eb2e8f9f7	218	* @{
<>	144:ef7eb2e8f9f7	219	*/
<>	144:ef7eb2e8f9f7	220	static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	221	static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	222	static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	223	static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	224	static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	225	static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	226	static void I2C_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	227
<>	144:ef7eb2e8f9f7	228	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	229	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	230	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	231	static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	232	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	233	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	234	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236	static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	237	static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	240	static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	241
<>	144:ef7eb2e8f9f7	242	static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
<>	144:ef7eb2e8f9f7	243	/**
<>	144:ef7eb2e8f9f7	244	* @}
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	/** @addtogroup I2C_Exported_Functions
<>	144:ef7eb2e8f9f7	250	* @{
<>	144:ef7eb2e8f9f7	251	*/
<>	144:ef7eb2e8f9f7	252
<>	144:ef7eb2e8f9f7	253	/** @addtogroup I2C_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	254	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	255	*
<>	144:ef7eb2e8f9f7	256	@verbatim
<>	144:ef7eb2e8f9f7	257	===============================================================================
<>	144:ef7eb2e8f9f7	258	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	259	===============================================================================
<>	144:ef7eb2e8f9f7	260	[..] This subsection provides a set of functions allowing to initialize and
<>	144:ef7eb2e8f9f7	261	de-initialiaze the I2Cx peripheral:
<>	144:ef7eb2e8f9f7	262
<>	144:ef7eb2e8f9f7	263	(+) User must Implement HAL_I2C_MspInit() function in which he configures
<>	144:ef7eb2e8f9f7	264	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<>	144:ef7eb2e8f9f7	265
<>	144:ef7eb2e8f9f7	266	(+) Call the function HAL_I2C_Init() to configure the selected device with
<>	144:ef7eb2e8f9f7	267	the selected configuration:
<>	144:ef7eb2e8f9f7	268	(++) Clock Timing
<>	144:ef7eb2e8f9f7	269	(++) Own Address 1
<>	144:ef7eb2e8f9f7	270	(++) Addressing mode (Master, Slave)
<>	144:ef7eb2e8f9f7	271	(++) Dual Addressing mode
<>	144:ef7eb2e8f9f7	272	(++) Own Address 2
<>	144:ef7eb2e8f9f7	273	(++) Own Address 2 Mask
<>	144:ef7eb2e8f9f7	274	(++) General call mode
<>	144:ef7eb2e8f9f7	275	(++) Nostretch mode
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	(+) Call the function HAL_I2C_DeInit() to restore the default configuration
<>	144:ef7eb2e8f9f7	278	of the selected I2Cx periperal.
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	@endverbatim
<>	144:ef7eb2e8f9f7	281	* @{
<>	144:ef7eb2e8f9f7	282	*/
<>	144:ef7eb2e8f9f7	283
<>	144:ef7eb2e8f9f7	284	/**
<>	144:ef7eb2e8f9f7	285	* @brief Initializes the I2C according to the specified parameters
<>	144:ef7eb2e8f9f7	286	* in the I2C_InitTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	287	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	288	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	289	* @retval HAL status
<>	144:ef7eb2e8f9f7	290	*/
<>	144:ef7eb2e8f9f7	291	HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	292	{
<>	144:ef7eb2e8f9f7	293	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	294	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	295	{
<>	144:ef7eb2e8f9f7	296	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	297	}
<>	144:ef7eb2e8f9f7	298
<>	144:ef7eb2e8f9f7	299	/* Check the parameters */
<>	144:ef7eb2e8f9f7	300	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	301	assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
<>	144:ef7eb2e8f9f7	302	assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
<>	144:ef7eb2e8f9f7	303	assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
<>	144:ef7eb2e8f9f7	304	assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
<>	144:ef7eb2e8f9f7	305	assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
<>	144:ef7eb2e8f9f7	306	assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
<>	144:ef7eb2e8f9f7	307	assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
<>	144:ef7eb2e8f9f7	308
<>	144:ef7eb2e8f9f7	309	if(hi2c->State == HAL_I2C_STATE_RESET)
<>	144:ef7eb2e8f9f7	310	{
<>	144:ef7eb2e8f9f7	311	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	312	hi2c->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
<>	144:ef7eb2e8f9f7	315	HAL_I2C_MspInit(hi2c);
<>	144:ef7eb2e8f9f7	316	}
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	/* Disable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	321	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	322
<>	144:ef7eb2e8f9f7	323	/---------------------------- I2Cx TIMINGR Configuration ------------------/
<>	144:ef7eb2e8f9f7	324	/* Configure I2Cx: Frequency range */
<>	144:ef7eb2e8f9f7	325	hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
<>	144:ef7eb2e8f9f7	326
<>	144:ef7eb2e8f9f7	327	/---------------------------- I2Cx OAR1 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	328	/* Configure I2Cx: Own Address1 and ack own address1 mode */
<>	144:ef7eb2e8f9f7	329	hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
<>	144:ef7eb2e8f9f7	330	if(hi2c->Init.OwnAddress1 != 0)
<>	144:ef7eb2e8f9f7	331	{
<>	144:ef7eb2e8f9f7	332	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	333	{
<>	144:ef7eb2e8f9f7	334	hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN \| hi2c->Init.OwnAddress1);
<>	144:ef7eb2e8f9f7	335	}
<>	144:ef7eb2e8f9f7	336	else /* I2C_ADDRESSINGMODE_10BIT */
<>	144:ef7eb2e8f9f7	337	{
<>	144:ef7eb2e8f9f7	338	hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN \| I2C_OAR1_OA1MODE \| hi2c->Init.OwnAddress1);
<>	144:ef7eb2e8f9f7	339	}
<>	144:ef7eb2e8f9f7	340	}
<>	144:ef7eb2e8f9f7	341
<>	144:ef7eb2e8f9f7	342	/---------------------------- I2Cx CR2 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	343	/* Configure I2Cx: Addressing Master mode */
<>	144:ef7eb2e8f9f7	344	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<>	144:ef7eb2e8f9f7	345	{
<>	144:ef7eb2e8f9f7	346	hi2c->Instance->CR2 = (I2C_CR2_ADD10);
<>	144:ef7eb2e8f9f7	347	}
<>	144:ef7eb2e8f9f7	348	/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
<>	144:ef7eb2e8f9f7	349	hi2c->Instance->CR2 \|= (I2C_CR2_AUTOEND \| I2C_CR2_NACK);
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/---------------------------- I2Cx OAR2 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	352	/* Configure I2Cx: Dual mode and Own Address2 */
<>	144:ef7eb2e8f9f7	353	hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode \| hi2c->Init.OwnAddress2 \| (hi2c->Init.OwnAddress2Masks << 8));
<>	144:ef7eb2e8f9f7	354
<>	144:ef7eb2e8f9f7	355	/---------------------------- I2Cx CR1 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	356	/* Configure I2Cx: Generalcall and NoStretch mode */
<>	144:ef7eb2e8f9f7	357	hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode \| hi2c->Init.NoStretchMode);
<>	144:ef7eb2e8f9f7	358
<>	144:ef7eb2e8f9f7	359	/* Enable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	360	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	361
<>	144:ef7eb2e8f9f7	362	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	363	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	364
<>	144:ef7eb2e8f9f7	365	return HAL_OK;
<>	144:ef7eb2e8f9f7	366	}
<>	144:ef7eb2e8f9f7	367
<>	144:ef7eb2e8f9f7	368	/**
<>	144:ef7eb2e8f9f7	369	* @brief DeInitializes the I2C peripheral.
<>	144:ef7eb2e8f9f7	370	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	371	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	372	* @retval HAL status
<>	144:ef7eb2e8f9f7	373	*/
<>	144:ef7eb2e8f9f7	374	HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	375	{
<>	144:ef7eb2e8f9f7	376	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	377	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	378	{
<>	144:ef7eb2e8f9f7	379	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	380	}
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	/* Check the parameters */
<>	144:ef7eb2e8f9f7	383	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	386
<>	144:ef7eb2e8f9f7	387	/* Disable the I2C Peripheral Clock */
<>	144:ef7eb2e8f9f7	388	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	391	HAL_I2C_MspDeInit(hi2c);
<>	144:ef7eb2e8f9f7	392
<>	144:ef7eb2e8f9f7	393	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	hi2c->State = HAL_I2C_STATE_RESET;
<>	144:ef7eb2e8f9f7	396
<>	144:ef7eb2e8f9f7	397	/* Release Lock */
<>	144:ef7eb2e8f9f7	398	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	return HAL_OK;
<>	144:ef7eb2e8f9f7	401	}
<>	144:ef7eb2e8f9f7	402
<>	144:ef7eb2e8f9f7	403	/**
<>	144:ef7eb2e8f9f7	404	* @brief I2C MSP Init.
<>	144:ef7eb2e8f9f7	405	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	406	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	407	* @retval None
<>	144:ef7eb2e8f9f7	408	*/
<>	144:ef7eb2e8f9f7	409	__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	410	{
<>	144:ef7eb2e8f9f7	411	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	412	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	413
<>	144:ef7eb2e8f9f7	414	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	415	the HAL_I2C_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	416	*/
<>	144:ef7eb2e8f9f7	417	}
<>	144:ef7eb2e8f9f7	418
<>	144:ef7eb2e8f9f7	419	/**
<>	144:ef7eb2e8f9f7	420	* @brief I2C MSP DeInit
<>	144:ef7eb2e8f9f7	421	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	422	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	423	* @retval None
<>	144:ef7eb2e8f9f7	424	*/
<>	144:ef7eb2e8f9f7	425	__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	426	{
<>	144:ef7eb2e8f9f7	427	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	428	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	429
<>	144:ef7eb2e8f9f7	430	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	431	the HAL_I2C_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	432	*/
<>	144:ef7eb2e8f9f7	433	}
<>	144:ef7eb2e8f9f7	434
<>	144:ef7eb2e8f9f7	435	/**
<>	144:ef7eb2e8f9f7	436	* @}
<>	144:ef7eb2e8f9f7	437	*/
<>	144:ef7eb2e8f9f7	438
<>	144:ef7eb2e8f9f7	439	/** @addtogroup I2C_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	440	* @brief Data transfers functions
<>	144:ef7eb2e8f9f7	441	*
<>	144:ef7eb2e8f9f7	442	@verbatim
<>	144:ef7eb2e8f9f7	443	===============================================================================
<>	144:ef7eb2e8f9f7	444	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	445	===============================================================================
<>	144:ef7eb2e8f9f7	446	[..]
<>	144:ef7eb2e8f9f7	447	This subsection provides a set of functions allowing to manage the I2C data
<>	144:ef7eb2e8f9f7	448	transfers.
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	451	(++) Blocking mode : The communication is performed in the polling mode.
<>	144:ef7eb2e8f9f7	452	The status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	453	after finishing transfer.
<>	144:ef7eb2e8f9f7	454	(++) No-Blocking mode : The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	455	or DMA. These functions return the status of the transfer startup.
<>	144:ef7eb2e8f9f7	456	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	457	dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	458	using DMA mode.
<>	144:ef7eb2e8f9f7	459
<>	144:ef7eb2e8f9f7	460	(#) Blocking mode functions are :
<>	144:ef7eb2e8f9f7	461	(++) HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	462	(++) HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	463	(++) HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	464	(++) HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	465	(++) HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	466	(++) HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	467	(++) HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	468
<>	144:ef7eb2e8f9f7	469	(#) No-Blocking mode functions with Interrupt are :
<>	144:ef7eb2e8f9f7	470	(++) HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	471	(++) HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	472	(++) HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	473	(++) HAL_I2C_Slave_Receive_IT()
<>	144:ef7eb2e8f9f7	474	(++) HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	475	(++) HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	476
<>	144:ef7eb2e8f9f7	477	(#) No-Blocking mode functions with DMA are :
<>	144:ef7eb2e8f9f7	478	(++) HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	479	(++) HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	480	(++) HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	481	(++) HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	482	(++) HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	483	(++) HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	484
<>	144:ef7eb2e8f9f7	485	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<>	144:ef7eb2e8f9f7	486	(++) HAL_I2C_MemTxCpltCallback()
<>	144:ef7eb2e8f9f7	487	(++) HAL_I2C_MemRxCpltCallback()
<>	144:ef7eb2e8f9f7	488	(++) HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	489	(++) HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	490	(++) HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	491	(++) HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	492	(++) HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	493
<>	144:ef7eb2e8f9f7	494	@endverbatim
<>	144:ef7eb2e8f9f7	495	* @{
<>	144:ef7eb2e8f9f7	496	*/
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	/**
<>	144:ef7eb2e8f9f7	499	* @brief Transmits in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	500	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	501	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	502	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	503	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	504	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	505	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	506	* @retval HAL status
<>	144:ef7eb2e8f9f7	507	*/
<>	144:ef7eb2e8f9f7	508	HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	509	{
<>	144:ef7eb2e8f9f7	510	uint32_t sizetmp = 0;
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	513	{
<>	144:ef7eb2e8f9f7	514	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	515	{
<>	144:ef7eb2e8f9f7	516	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	517	}
<>	144:ef7eb2e8f9f7	518
<>	144:ef7eb2e8f9f7	519	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	520	{
<>	144:ef7eb2e8f9f7	521	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	522	}
<>	144:ef7eb2e8f9f7	523
<>	144:ef7eb2e8f9f7	524	/* Process Locked */
<>	144:ef7eb2e8f9f7	525	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	526
<>	144:ef7eb2e8f9f7	527	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
<>	144:ef7eb2e8f9f7	528	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	531	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
<>	144:ef7eb2e8f9f7	532	/* Size > 255, need to set RELOAD bit */
<>	144:ef7eb2e8f9f7	533	if(Size > 255)
<>	144:ef7eb2e8f9f7	534	{
<>	144:ef7eb2e8f9f7	535	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	536	sizetmp = 255;
<>	144:ef7eb2e8f9f7	537	}
<>	144:ef7eb2e8f9f7	538	else
<>	144:ef7eb2e8f9f7	539	{
<>	144:ef7eb2e8f9f7	540	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	541	sizetmp = Size;
<>	144:ef7eb2e8f9f7	542	}
<>	144:ef7eb2e8f9f7	543
<>	144:ef7eb2e8f9f7	544	do
<>	144:ef7eb2e8f9f7	545	{
<>	144:ef7eb2e8f9f7	546	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	547	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	548	{
<>	144:ef7eb2e8f9f7	549	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	550	{
<>	144:ef7eb2e8f9f7	551	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	552	}
<>	144:ef7eb2e8f9f7	553	else
<>	144:ef7eb2e8f9f7	554	{
<>	144:ef7eb2e8f9f7	555	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	556	}
<>	144:ef7eb2e8f9f7	557	}
<>	144:ef7eb2e8f9f7	558	/* Write data to TXDR */
<>	144:ef7eb2e8f9f7	559	hi2c->Instance->TXDR = (*pData++);
<>	144:ef7eb2e8f9f7	560	sizetmp--;
<>	144:ef7eb2e8f9f7	561	Size--;
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	if((sizetmp == 0)&&(Size!=0))
<>	144:ef7eb2e8f9f7	564	{
<>	144:ef7eb2e8f9f7	565	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	566	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	567	{
<>	144:ef7eb2e8f9f7	568	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	569	}
<>	144:ef7eb2e8f9f7	570
<>	144:ef7eb2e8f9f7	571	if(Size > 255)
<>	144:ef7eb2e8f9f7	572	{
<>	144:ef7eb2e8f9f7	573	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	574	sizetmp = 255;
<>	144:ef7eb2e8f9f7	575	}
<>	144:ef7eb2e8f9f7	576	else
<>	144:ef7eb2e8f9f7	577	{
<>	144:ef7eb2e8f9f7	578	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	579	sizetmp = Size;
<>	144:ef7eb2e8f9f7	580	}
<>	144:ef7eb2e8f9f7	581	}
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	}while(Size > 0);
<>	144:ef7eb2e8f9f7	584
<>	144:ef7eb2e8f9f7	585	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	586	/* Wait until STOPF flag is set */
<>	144:ef7eb2e8f9f7	587	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	588	{
<>	144:ef7eb2e8f9f7	589	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	590	{
<>	144:ef7eb2e8f9f7	591	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	592	}
<>	144:ef7eb2e8f9f7	593	else
<>	144:ef7eb2e8f9f7	594	{
<>	144:ef7eb2e8f9f7	595	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	596	}
<>	144:ef7eb2e8f9f7	597	}
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	600	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	601
<>	144:ef7eb2e8f9f7	602	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	603	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	606
<>	144:ef7eb2e8f9f7	607	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	608	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	609
<>	144:ef7eb2e8f9f7	610	return HAL_OK;
<>	144:ef7eb2e8f9f7	611	}
<>	144:ef7eb2e8f9f7	612	else
<>	144:ef7eb2e8f9f7	613	{
<>	144:ef7eb2e8f9f7	614	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	615	}
<>	144:ef7eb2e8f9f7	616	}
<>	144:ef7eb2e8f9f7	617
<>	144:ef7eb2e8f9f7	618	/**
<>	144:ef7eb2e8f9f7	619	* @brief Receives in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	620	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	621	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	622	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	623	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	624	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	625	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	626	* @retval HAL status
<>	144:ef7eb2e8f9f7	627	*/
<>	144:ef7eb2e8f9f7	628	HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	629	{
<>	144:ef7eb2e8f9f7	630	uint32_t sizetmp = 0;
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	633	{
<>	144:ef7eb2e8f9f7	634	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	635	{
<>	144:ef7eb2e8f9f7	636	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	637	}
<>	144:ef7eb2e8f9f7	638
<>	144:ef7eb2e8f9f7	639	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	640	{
<>	144:ef7eb2e8f9f7	641	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	642	}
<>	144:ef7eb2e8f9f7	643
<>	144:ef7eb2e8f9f7	644	/* Process Locked */
<>	144:ef7eb2e8f9f7	645	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	646
<>	144:ef7eb2e8f9f7	647	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
<>	144:ef7eb2e8f9f7	648	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	649
<>	144:ef7eb2e8f9f7	650	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	651	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
<>	144:ef7eb2e8f9f7	652	/* Size > 255, need to set RELOAD bit */
<>	144:ef7eb2e8f9f7	653	if(Size > 255)
<>	144:ef7eb2e8f9f7	654	{
<>	144:ef7eb2e8f9f7	655	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	656	sizetmp = 255;
<>	144:ef7eb2e8f9f7	657	}
<>	144:ef7eb2e8f9f7	658	else
<>	144:ef7eb2e8f9f7	659	{
<>	144:ef7eb2e8f9f7	660	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	661	sizetmp = Size;
<>	144:ef7eb2e8f9f7	662	}
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	do
<>	144:ef7eb2e8f9f7	665	{
<>	144:ef7eb2e8f9f7	666	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	667	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)
<>	144:ef7eb2e8f9f7	668	{
<>	144:ef7eb2e8f9f7	669	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	670	{
<>	144:ef7eb2e8f9f7	671	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	672	}
<>	144:ef7eb2e8f9f7	673	else
<>	144:ef7eb2e8f9f7	674	{
<>	144:ef7eb2e8f9f7	675	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	676	}
<>	144:ef7eb2e8f9f7	677	}
<>	144:ef7eb2e8f9f7	678
<>	144:ef7eb2e8f9f7	679	/* Write data to RXDR */
<>	144:ef7eb2e8f9f7	680	(*pData++) =hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	681	sizetmp--;
<>	144:ef7eb2e8f9f7	682	Size--;
<>	144:ef7eb2e8f9f7	683
<>	144:ef7eb2e8f9f7	684	if((sizetmp == 0)&&(Size!=0))
<>	144:ef7eb2e8f9f7	685	{
<>	144:ef7eb2e8f9f7	686	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	687	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	688	{
<>	144:ef7eb2e8f9f7	689	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	690	}
<>	144:ef7eb2e8f9f7	691
<>	144:ef7eb2e8f9f7	692	if(Size > 255)
<>	144:ef7eb2e8f9f7	693	{
<>	144:ef7eb2e8f9f7	694	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	695	sizetmp = 255;
<>	144:ef7eb2e8f9f7	696	}
<>	144:ef7eb2e8f9f7	697	else
<>	144:ef7eb2e8f9f7	698	{
<>	144:ef7eb2e8f9f7	699	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	700	sizetmp = Size;
<>	144:ef7eb2e8f9f7	701	}
<>	144:ef7eb2e8f9f7	702	}
<>	144:ef7eb2e8f9f7	703
<>	144:ef7eb2e8f9f7	704	}while(Size > 0);
<>	144:ef7eb2e8f9f7	705
<>	144:ef7eb2e8f9f7	706	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	707	/* Wait until STOPF flag is set */
<>	144:ef7eb2e8f9f7	708	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	709	{
<>	144:ef7eb2e8f9f7	710	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	711	{
<>	144:ef7eb2e8f9f7	712	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	713	}
<>	144:ef7eb2e8f9f7	714	else
<>	144:ef7eb2e8f9f7	715	{
<>	144:ef7eb2e8f9f7	716	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	717	}
<>	144:ef7eb2e8f9f7	718	}
<>	144:ef7eb2e8f9f7	719
<>	144:ef7eb2e8f9f7	720	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	721	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	724	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	725
<>	144:ef7eb2e8f9f7	726	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	727
<>	144:ef7eb2e8f9f7	728	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	729	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	730
<>	144:ef7eb2e8f9f7	731	return HAL_OK;
<>	144:ef7eb2e8f9f7	732	}
<>	144:ef7eb2e8f9f7	733	else
<>	144:ef7eb2e8f9f7	734	{
<>	144:ef7eb2e8f9f7	735	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	736	}
<>	144:ef7eb2e8f9f7	737	}
<>	144:ef7eb2e8f9f7	738
<>	144:ef7eb2e8f9f7	739	/**
<>	144:ef7eb2e8f9f7	740	* @brief Transmits in slave mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	741	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	742	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	743	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	744	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	745	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	746	* @retval HAL status
<>	144:ef7eb2e8f9f7	747	*/
<>	144:ef7eb2e8f9f7	748	HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	749	{
<>	144:ef7eb2e8f9f7	750	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	751	{
<>	144:ef7eb2e8f9f7	752	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	753	{
<>	144:ef7eb2e8f9f7	754	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	755	}
<>	144:ef7eb2e8f9f7	756
<>	144:ef7eb2e8f9f7	757	/* Process Locked */
<>	144:ef7eb2e8f9f7	758	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	759
<>	144:ef7eb2e8f9f7	760	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
<>	144:ef7eb2e8f9f7	761	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	762
<>	144:ef7eb2e8f9f7	763	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	764	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	767	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	768	{
<>	144:ef7eb2e8f9f7	769	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	770	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	771	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	772	}
<>	144:ef7eb2e8f9f7	773
<>	144:ef7eb2e8f9f7	774	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	775	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	776
<>	144:ef7eb2e8f9f7	777	/* If 10bit addressing mode is selected */
<>	144:ef7eb2e8f9f7	778	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<>	144:ef7eb2e8f9f7	779	{
<>	144:ef7eb2e8f9f7	780	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	781	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	782	{
<>	144:ef7eb2e8f9f7	783	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	784	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	785	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	786	}
<>	144:ef7eb2e8f9f7	787
<>	144:ef7eb2e8f9f7	788	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	789	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	790	}
<>	144:ef7eb2e8f9f7	791
<>	144:ef7eb2e8f9f7	792	/* Wait until DIR flag is set Transmitter mode */
<>	144:ef7eb2e8f9f7	793	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	794	{
<>	144:ef7eb2e8f9f7	795	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	796	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	797	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	798	}
<>	144:ef7eb2e8f9f7	799
<>	144:ef7eb2e8f9f7	800	do
<>	144:ef7eb2e8f9f7	801	{
<>	144:ef7eb2e8f9f7	802	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	803	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	804	{
<>	144:ef7eb2e8f9f7	805	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	806	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	807
<>	144:ef7eb2e8f9f7	808	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	809	{
<>	144:ef7eb2e8f9f7	810	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	811	}
<>	144:ef7eb2e8f9f7	812	else
<>	144:ef7eb2e8f9f7	813	{
<>	144:ef7eb2e8f9f7	814	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	815	}
<>	144:ef7eb2e8f9f7	816	}
<>	144:ef7eb2e8f9f7	817
<>	144:ef7eb2e8f9f7	818	/* Read data from TXDR */
<>	144:ef7eb2e8f9f7	819	hi2c->Instance->TXDR = (*pData++);
<>	144:ef7eb2e8f9f7	820	Size--;
<>	144:ef7eb2e8f9f7	821	}while(Size > 0);
<>	144:ef7eb2e8f9f7	822
<>	144:ef7eb2e8f9f7	823	/* Wait until STOP flag is set */
<>	144:ef7eb2e8f9f7	824	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	825	{
<>	144:ef7eb2e8f9f7	826	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	827	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	830	{
<>	144:ef7eb2e8f9f7	831	/* Normal use case for Transmitter mode */
<>	144:ef7eb2e8f9f7	832	/* A NACK is generated to confirm the end of transfer */
<>	144:ef7eb2e8f9f7	833	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	834	}
<>	144:ef7eb2e8f9f7	835	else
<>	144:ef7eb2e8f9f7	836	{
<>	144:ef7eb2e8f9f7	837	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	838	}
<>	144:ef7eb2e8f9f7	839	}
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	/* Clear STOP flag */
<>	144:ef7eb2e8f9f7	842	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	843
<>	144:ef7eb2e8f9f7	844	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	845	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	846	{
<>	144:ef7eb2e8f9f7	847	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	848	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	849	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	850	}
<>	144:ef7eb2e8f9f7	851
<>	144:ef7eb2e8f9f7	852	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	853	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	854
<>	144:ef7eb2e8f9f7	855	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	858	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	return HAL_OK;
<>	144:ef7eb2e8f9f7	861	}
<>	144:ef7eb2e8f9f7	862	else
<>	144:ef7eb2e8f9f7	863	{
<>	144:ef7eb2e8f9f7	864	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	865	}
<>	144:ef7eb2e8f9f7	866	}
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	/**
<>	144:ef7eb2e8f9f7	869	* @brief Receive in slave mode an amount of data in blocking mode
<>	144:ef7eb2e8f9f7	870	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	871	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	872	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	873	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	874	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	875	* @retval HAL status
<>	144:ef7eb2e8f9f7	876	*/
<>	144:ef7eb2e8f9f7	877	HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	878	{
<>	144:ef7eb2e8f9f7	879	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	880	{
<>	144:ef7eb2e8f9f7	881	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	882	{
<>	144:ef7eb2e8f9f7	883	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	884	}
<>	144:ef7eb2e8f9f7	885
<>	144:ef7eb2e8f9f7	886	/* Process Locked */
<>	144:ef7eb2e8f9f7	887	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	888
<>	144:ef7eb2e8f9f7	889	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
<>	144:ef7eb2e8f9f7	890	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	891
<>	144:ef7eb2e8f9f7	892	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	893	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	894
<>	144:ef7eb2e8f9f7	895	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	896	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	897	{
<>	144:ef7eb2e8f9f7	898	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	899	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	900	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	901	}
<>	144:ef7eb2e8f9f7	902
<>	144:ef7eb2e8f9f7	903	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	904	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	905
<>	144:ef7eb2e8f9f7	906	/* Wait until DIR flag is reset Receiver mode */
<>	144:ef7eb2e8f9f7	907	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	908	{
<>	144:ef7eb2e8f9f7	909	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	910	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	911	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	912	}
<>	144:ef7eb2e8f9f7	913
<>	144:ef7eb2e8f9f7	914	while(Size > 0)
<>	144:ef7eb2e8f9f7	915	{
<>	144:ef7eb2e8f9f7	916	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	917	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	918	{
<>	144:ef7eb2e8f9f7	919	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	920	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	921
<>	144:ef7eb2e8f9f7	922	/* Store Last receive data if any */
<>	144:ef7eb2e8f9f7	923	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	144:ef7eb2e8f9f7	924	{
<>	144:ef7eb2e8f9f7	925	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	926	(*pData++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	927	}
<>	144:ef7eb2e8f9f7	928
<>	144:ef7eb2e8f9f7	929	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	930	{
<>	144:ef7eb2e8f9f7	931	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	932	}
<>	144:ef7eb2e8f9f7	933	else
<>	144:ef7eb2e8f9f7	934	{
<>	144:ef7eb2e8f9f7	935	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	936	}
<>	144:ef7eb2e8f9f7	937	}
<>	144:ef7eb2e8f9f7	938
<>	144:ef7eb2e8f9f7	939	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	940	(*pData++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	941	Size--;
<>	144:ef7eb2e8f9f7	942	}
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/* Wait until STOP flag is set */
<>	144:ef7eb2e8f9f7	945	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	946	{
<>	144:ef7eb2e8f9f7	947	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	948	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	951	{
<>	144:ef7eb2e8f9f7	952	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	953	}
<>	144:ef7eb2e8f9f7	954	else
<>	144:ef7eb2e8f9f7	955	{
<>	144:ef7eb2e8f9f7	956	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	957	}
<>	144:ef7eb2e8f9f7	958	}
<>	144:ef7eb2e8f9f7	959
<>	144:ef7eb2e8f9f7	960	/* Clear STOP flag */
<>	144:ef7eb2e8f9f7	961	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	962
<>	144:ef7eb2e8f9f7	963	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	964	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	965	{
<>	144:ef7eb2e8f9f7	966	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	967	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	968	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	969	}
<>	144:ef7eb2e8f9f7	970
<>	144:ef7eb2e8f9f7	971
<>	144:ef7eb2e8f9f7	972	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	973	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	974
<>	144:ef7eb2e8f9f7	975	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	976
<>	144:ef7eb2e8f9f7	977	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	978	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	979
<>	144:ef7eb2e8f9f7	980	return HAL_OK;
<>	144:ef7eb2e8f9f7	981	}
<>	144:ef7eb2e8f9f7	982	else
<>	144:ef7eb2e8f9f7	983	{
<>	144:ef7eb2e8f9f7	984	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	985	}
<>	144:ef7eb2e8f9f7	986	}
<>	144:ef7eb2e8f9f7	987
<>	144:ef7eb2e8f9f7	988	/**
<>	144:ef7eb2e8f9f7	989	* @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	990	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	991	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	992	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	993	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	994	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	995	* @retval HAL status
<>	144:ef7eb2e8f9f7	996	*/
<>	144:ef7eb2e8f9f7	997	HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	998	{
<>	144:ef7eb2e8f9f7	999	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1000	{
<>	144:ef7eb2e8f9f7	1001	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1002	{
<>	144:ef7eb2e8f9f7	1003	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1004	}
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1007	{
<>	144:ef7eb2e8f9f7	1008	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1009	}
<>	144:ef7eb2e8f9f7	1010
<>	144:ef7eb2e8f9f7	1011	/* Process Locked */
<>	144:ef7eb2e8f9f7	1012	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1013
<>	144:ef7eb2e8f9f7	1014	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
<>	144:ef7eb2e8f9f7	1015	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1016
<>	144:ef7eb2e8f9f7	1017	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1018	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1019	if(Size > 255)
<>	144:ef7eb2e8f9f7	1020	{
<>	144:ef7eb2e8f9f7	1021	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	1022	}
<>	144:ef7eb2e8f9f7	1023	else
<>	144:ef7eb2e8f9f7	1024	{
<>	144:ef7eb2e8f9f7	1025	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1026	}
<>	144:ef7eb2e8f9f7	1027
<>	144:ef7eb2e8f9f7	1028	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1029	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
<>	144:ef7eb2e8f9f7	1030	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	1031	{
<>	144:ef7eb2e8f9f7	1032	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	1033	}
<>	144:ef7eb2e8f9f7	1034	else
<>	144:ef7eb2e8f9f7	1035	{
<>	144:ef7eb2e8f9f7	1036	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	1037	}
<>	144:ef7eb2e8f9f7	1038
<>	144:ef7eb2e8f9f7	1039	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1040	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1041
<>	144:ef7eb2e8f9f7	1042	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1043	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1044	process unlock */
<>	144:ef7eb2e8f9f7	1045
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
<>	144:ef7eb2e8f9f7	1048	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1049	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1050	__HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_TXI );
<>	144:ef7eb2e8f9f7	1051
<>	144:ef7eb2e8f9f7	1052	return HAL_OK;
<>	144:ef7eb2e8f9f7	1053	}
<>	144:ef7eb2e8f9f7	1054	else
<>	144:ef7eb2e8f9f7	1055	{
<>	144:ef7eb2e8f9f7	1056	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1057	}
<>	144:ef7eb2e8f9f7	1058	}
<>	144:ef7eb2e8f9f7	1059
<>	144:ef7eb2e8f9f7	1060	/**
<>	144:ef7eb2e8f9f7	1061	* @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1062	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1063	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1064	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	1065	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1066	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1067	* @retval HAL status
<>	144:ef7eb2e8f9f7	1068	*/
<>	144:ef7eb2e8f9f7	1069	HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1070	{
<>	144:ef7eb2e8f9f7	1071	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1072	{
<>	144:ef7eb2e8f9f7	1073	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1074	{
<>	144:ef7eb2e8f9f7	1075	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1076	}
<>	144:ef7eb2e8f9f7	1077
<>	144:ef7eb2e8f9f7	1078	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1079	{
<>	144:ef7eb2e8f9f7	1080	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1081	}
<>	144:ef7eb2e8f9f7	1082
<>	144:ef7eb2e8f9f7	1083	/* Process Locked */
<>	144:ef7eb2e8f9f7	1084	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1085
<>	144:ef7eb2e8f9f7	1086	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
<>	144:ef7eb2e8f9f7	1087	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1088
<>	144:ef7eb2e8f9f7	1089	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1090	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1091	if(Size > 255)
<>	144:ef7eb2e8f9f7	1092	{
<>	144:ef7eb2e8f9f7	1093	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	1094	}
<>	144:ef7eb2e8f9f7	1095	else
<>	144:ef7eb2e8f9f7	1096	{
<>	144:ef7eb2e8f9f7	1097	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1098	}
<>	144:ef7eb2e8f9f7	1099
<>	144:ef7eb2e8f9f7	1100	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1101	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
<>	144:ef7eb2e8f9f7	1102	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	1103	{
<>	144:ef7eb2e8f9f7	1104	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1105	}
<>	144:ef7eb2e8f9f7	1106	else
<>	144:ef7eb2e8f9f7	1107	{
<>	144:ef7eb2e8f9f7	1108	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1109	}
<>	144:ef7eb2e8f9f7	1110
<>	144:ef7eb2e8f9f7	1111	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1112	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1113
<>	144:ef7eb2e8f9f7	1114	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1115	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1116	process unlock */
<>	144:ef7eb2e8f9f7	1117
<>	144:ef7eb2e8f9f7	1118	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
<>	144:ef7eb2e8f9f7	1119	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1120	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1121	__HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_RXI );
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	return HAL_OK;
<>	144:ef7eb2e8f9f7	1124	}
<>	144:ef7eb2e8f9f7	1125	else
<>	144:ef7eb2e8f9f7	1126	{
<>	144:ef7eb2e8f9f7	1127	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1128	}
<>	144:ef7eb2e8f9f7	1129	}
<>	144:ef7eb2e8f9f7	1130
<>	144:ef7eb2e8f9f7	1131	/**
<>	144:ef7eb2e8f9f7	1132	* @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1133	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1134	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1135	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1136	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1137	* @retval HAL status
<>	144:ef7eb2e8f9f7	1138	*/
<>	144:ef7eb2e8f9f7	1139	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1140	{
<>	144:ef7eb2e8f9f7	1141	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1142	{
<>	144:ef7eb2e8f9f7	1143	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1144	{
<>	144:ef7eb2e8f9f7	1145	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1146	}
<>	144:ef7eb2e8f9f7	1147
<>	144:ef7eb2e8f9f7	1148	/* Process Locked */
<>	144:ef7eb2e8f9f7	1149	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1150
<>	144:ef7eb2e8f9f7	1151	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1152	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1153
<>	144:ef7eb2e8f9f7	1154	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1155	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1158	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1159	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1160
<>	144:ef7eb2e8f9f7	1161	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1162	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1163
<>	144:ef7eb2e8f9f7	1164	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1165	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1166	process unlock */
<>	144:ef7eb2e8f9f7	1167
<>	144:ef7eb2e8f9f7	1168	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
<>	144:ef7eb2e8f9f7	1169	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1170	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1171	__HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_TXI );
<>	144:ef7eb2e8f9f7	1172
<>	144:ef7eb2e8f9f7	1173	return HAL_OK;
<>	144:ef7eb2e8f9f7	1174	}
<>	144:ef7eb2e8f9f7	1175	else
<>	144:ef7eb2e8f9f7	1176	{
<>	144:ef7eb2e8f9f7	1177	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1178	}
<>	144:ef7eb2e8f9f7	1179	}
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	/**
<>	144:ef7eb2e8f9f7	1182	* @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1183	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1184	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1185	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1186	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1187	* @retval HAL status
<>	144:ef7eb2e8f9f7	1188	*/
<>	144:ef7eb2e8f9f7	1189	HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1190	{
<>	144:ef7eb2e8f9f7	1191	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1192	{
<>	144:ef7eb2e8f9f7	1193	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1194	{
<>	144:ef7eb2e8f9f7	1195	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1196	}
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	/* Process Locked */
<>	144:ef7eb2e8f9f7	1199	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1202	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1203
<>	144:ef7eb2e8f9f7	1204	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1205	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1206
<>	144:ef7eb2e8f9f7	1207	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1208	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1209	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1210
<>	144:ef7eb2e8f9f7	1211	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1212	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1213
<>	144:ef7eb2e8f9f7	1214	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1215	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1216	process unlock */
<>	144:ef7eb2e8f9f7	1217
<>	144:ef7eb2e8f9f7	1218	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
<>	144:ef7eb2e8f9f7	1219	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1220	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1221	__HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI);
<>	144:ef7eb2e8f9f7	1222
<>	144:ef7eb2e8f9f7	1223	return HAL_OK;
<>	144:ef7eb2e8f9f7	1224	}
<>	144:ef7eb2e8f9f7	1225	else
<>	144:ef7eb2e8f9f7	1226	{
<>	144:ef7eb2e8f9f7	1227	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1228	}
<>	144:ef7eb2e8f9f7	1229	}
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	/**
<>	144:ef7eb2e8f9f7	1232	* @brief Transmit in master mode an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1233	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1234	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1235	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	1236	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1237	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1238	* @retval HAL status
<>	144:ef7eb2e8f9f7	1239	*/
<>	144:ef7eb2e8f9f7	1240	HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1241	{
<>	144:ef7eb2e8f9f7	1242	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1243	{
<>	144:ef7eb2e8f9f7	1244	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1245	{
<>	144:ef7eb2e8f9f7	1246	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1247	}
<>	144:ef7eb2e8f9f7	1248
<>	144:ef7eb2e8f9f7	1249	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1250	{
<>	144:ef7eb2e8f9f7	1251	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1252	}
<>	144:ef7eb2e8f9f7	1253
<>	144:ef7eb2e8f9f7	1254	/* Process Locked */
<>	144:ef7eb2e8f9f7	1255	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1256
<>	144:ef7eb2e8f9f7	1257	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
<>	144:ef7eb2e8f9f7	1258	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1259
<>	144:ef7eb2e8f9f7	1260	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1261	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1262	if(Size > 255)
<>	144:ef7eb2e8f9f7	1263	{
<>	144:ef7eb2e8f9f7	1264	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	1265	}
<>	144:ef7eb2e8f9f7	1266	else
<>	144:ef7eb2e8f9f7	1267	{
<>	144:ef7eb2e8f9f7	1268	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1269	}
<>	144:ef7eb2e8f9f7	1270
<>	144:ef7eb2e8f9f7	1271	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1272	hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
<>	144:ef7eb2e8f9f7	1273
<>	144:ef7eb2e8f9f7	1274	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1275	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1276
<>	144:ef7eb2e8f9f7	1277	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1278	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	1279
<>	144:ef7eb2e8f9f7	1280	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1281	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
<>	144:ef7eb2e8f9f7	1282	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	1283	{
<>	144:ef7eb2e8f9f7	1284	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	1285	}
<>	144:ef7eb2e8f9f7	1286	else
<>	144:ef7eb2e8f9f7	1287	{
<>	144:ef7eb2e8f9f7	1288	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	1289	}
<>	144:ef7eb2e8f9f7	1290
<>	144:ef7eb2e8f9f7	1291	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	1292	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
<>	144:ef7eb2e8f9f7	1293	{
<>	144:ef7eb2e8f9f7	1294	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1295	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1296
<>	144:ef7eb2e8f9f7	1297	/* Abort DMA */
<>	144:ef7eb2e8f9f7	1298	HAL_DMA_Abort(hi2c->hdmatx);
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1301	{
<>	144:ef7eb2e8f9f7	1302	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1303	}
<>	144:ef7eb2e8f9f7	1304	else
<>	144:ef7eb2e8f9f7	1305	{
<>	144:ef7eb2e8f9f7	1306	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1307	}
<>	144:ef7eb2e8f9f7	1308	}
<>	144:ef7eb2e8f9f7	1309
<>	144:ef7eb2e8f9f7	1310
<>	144:ef7eb2e8f9f7	1311	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	1312	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	1313
<>	144:ef7eb2e8f9f7	1314	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1315	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1316
<>	144:ef7eb2e8f9f7	1317	return HAL_OK;
<>	144:ef7eb2e8f9f7	1318	}
<>	144:ef7eb2e8f9f7	1319	else
<>	144:ef7eb2e8f9f7	1320	{
<>	144:ef7eb2e8f9f7	1321	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1322	}
<>	144:ef7eb2e8f9f7	1323	}
<>	144:ef7eb2e8f9f7	1324
<>	144:ef7eb2e8f9f7	1325	/**
<>	144:ef7eb2e8f9f7	1326	* @brief Receive in master mode an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1327	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1328	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1329	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	1330	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1331	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1332	* @retval HAL status
<>	144:ef7eb2e8f9f7	1333	*/
<>	144:ef7eb2e8f9f7	1334	HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1335	{
<>	144:ef7eb2e8f9f7	1336	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1337	{
<>	144:ef7eb2e8f9f7	1338	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1339	{
<>	144:ef7eb2e8f9f7	1340	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1341	}
<>	144:ef7eb2e8f9f7	1342
<>	144:ef7eb2e8f9f7	1343	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1344	{
<>	144:ef7eb2e8f9f7	1345	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1346	}
<>	144:ef7eb2e8f9f7	1347
<>	144:ef7eb2e8f9f7	1348	/* Process Locked */
<>	144:ef7eb2e8f9f7	1349	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1350
<>	144:ef7eb2e8f9f7	1351	hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
<>	144:ef7eb2e8f9f7	1352	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1353
<>	144:ef7eb2e8f9f7	1354	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1355	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1356	if(Size > 255)
<>	144:ef7eb2e8f9f7	1357	{
<>	144:ef7eb2e8f9f7	1358	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	1359	}
<>	144:ef7eb2e8f9f7	1360	else
<>	144:ef7eb2e8f9f7	1361	{
<>	144:ef7eb2e8f9f7	1362	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1363	}
<>	144:ef7eb2e8f9f7	1364
<>	144:ef7eb2e8f9f7	1365	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1366	hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
<>	144:ef7eb2e8f9f7	1367
<>	144:ef7eb2e8f9f7	1368	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1369	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1370
<>	144:ef7eb2e8f9f7	1371	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1372	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	1373
<>	144:ef7eb2e8f9f7	1374	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1375	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
<>	144:ef7eb2e8f9f7	1376	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	1377	{
<>	144:ef7eb2e8f9f7	1378	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1379	}
<>	144:ef7eb2e8f9f7	1380	else
<>	144:ef7eb2e8f9f7	1381	{
<>	144:ef7eb2e8f9f7	1382	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1383	}
<>	144:ef7eb2e8f9f7	1384
<>	144:ef7eb2e8f9f7	1385	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	1386	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)
<>	144:ef7eb2e8f9f7	1387	{
<>	144:ef7eb2e8f9f7	1388	/* Abort DMA */
<>	144:ef7eb2e8f9f7	1389	HAL_DMA_Abort(hi2c->hdmarx);
<>	144:ef7eb2e8f9f7	1390
<>	144:ef7eb2e8f9f7	1391	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1392	{
<>	144:ef7eb2e8f9f7	1393	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1394	}
<>	144:ef7eb2e8f9f7	1395	else
<>	144:ef7eb2e8f9f7	1396	{
<>	144:ef7eb2e8f9f7	1397	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1398	}
<>	144:ef7eb2e8f9f7	1399	}
<>	144:ef7eb2e8f9f7	1400
<>	144:ef7eb2e8f9f7	1401	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	1402	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	1403
<>	144:ef7eb2e8f9f7	1404	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1405	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1406
<>	144:ef7eb2e8f9f7	1407	return HAL_OK;
<>	144:ef7eb2e8f9f7	1408	}
<>	144:ef7eb2e8f9f7	1409	else
<>	144:ef7eb2e8f9f7	1410	{
<>	144:ef7eb2e8f9f7	1411	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1412	}
<>	144:ef7eb2e8f9f7	1413	}
<>	144:ef7eb2e8f9f7	1414
<>	144:ef7eb2e8f9f7	1415	/**
<>	144:ef7eb2e8f9f7	1416	* @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1417	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1418	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1419	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1420	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1421	* @retval HAL status
<>	144:ef7eb2e8f9f7	1422	*/
<>	144:ef7eb2e8f9f7	1423	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1424	{
<>	144:ef7eb2e8f9f7	1425	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1426	{
<>	144:ef7eb2e8f9f7	1427	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1428	{
<>	144:ef7eb2e8f9f7	1429	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1430	}
<>	144:ef7eb2e8f9f7	1431	/* Process Locked */
<>	144:ef7eb2e8f9f7	1432	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1433
<>	144:ef7eb2e8f9f7	1434	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1435	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1436
<>	144:ef7eb2e8f9f7	1437	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1438	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1439	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1442	hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
<>	144:ef7eb2e8f9f7	1443
<>	144:ef7eb2e8f9f7	1444	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1445	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1448	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	1449
<>	144:ef7eb2e8f9f7	1450	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1451	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1452
<>	144:ef7eb2e8f9f7	1453	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	1454	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
<>	144:ef7eb2e8f9f7	1455	{
<>	144:ef7eb2e8f9f7	1456	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1457	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1458	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1459	}
<>	144:ef7eb2e8f9f7	1460
<>	144:ef7eb2e8f9f7	1461	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1462	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	1463
<>	144:ef7eb2e8f9f7	1464	/* If 10bits addressing mode is selected */
<>	144:ef7eb2e8f9f7	1465	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<>	144:ef7eb2e8f9f7	1466	{
<>	144:ef7eb2e8f9f7	1467	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	1468	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
<>	144:ef7eb2e8f9f7	1469	{
<>	144:ef7eb2e8f9f7	1470	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1471	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1472	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1473	}
<>	144:ef7eb2e8f9f7	1474
<>	144:ef7eb2e8f9f7	1475	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1476	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	1477	}
<>	144:ef7eb2e8f9f7	1478
<>	144:ef7eb2e8f9f7	1479	/* Wait until DIR flag is set Transmitter mode */
<>	144:ef7eb2e8f9f7	1480	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK)
<>	144:ef7eb2e8f9f7	1481	{
<>	144:ef7eb2e8f9f7	1482	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1483	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1484	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1485	}
<>	144:ef7eb2e8f9f7	1486
<>	144:ef7eb2e8f9f7	1487	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	1488	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	1489
<>	144:ef7eb2e8f9f7	1490	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1491	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1492
<>	144:ef7eb2e8f9f7	1493	return HAL_OK;
<>	144:ef7eb2e8f9f7	1494	}
<>	144:ef7eb2e8f9f7	1495	else
<>	144:ef7eb2e8f9f7	1496	{
<>	144:ef7eb2e8f9f7	1497	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1498	}
<>	144:ef7eb2e8f9f7	1499	}
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	/**
<>	144:ef7eb2e8f9f7	1502	* @brief Receive in slave mode an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1503	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1504	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1505	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1506	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1507	* @retval HAL status
<>	144:ef7eb2e8f9f7	1508	*/
<>	144:ef7eb2e8f9f7	1509	HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1510	{
<>	144:ef7eb2e8f9f7	1511	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1512	{
<>	144:ef7eb2e8f9f7	1513	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1514	{
<>	144:ef7eb2e8f9f7	1515	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1516	}
<>	144:ef7eb2e8f9f7	1517	/* Process Locked */
<>	144:ef7eb2e8f9f7	1518	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1519
<>	144:ef7eb2e8f9f7	1520	hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1521	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1522
<>	144:ef7eb2e8f9f7	1523	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1524	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1525	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1526
<>	144:ef7eb2e8f9f7	1527	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1528	hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
<>	144:ef7eb2e8f9f7	1529
<>	144:ef7eb2e8f9f7	1530	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1531	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1532
<>	144:ef7eb2e8f9f7	1533	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1534	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size);
<>	144:ef7eb2e8f9f7	1535
<>	144:ef7eb2e8f9f7	1536	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1537	hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1538
<>	144:ef7eb2e8f9f7	1539	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	1540	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
<>	144:ef7eb2e8f9f7	1541	{
<>	144:ef7eb2e8f9f7	1542	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1543	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1544	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1545	}
<>	144:ef7eb2e8f9f7	1546
<>	144:ef7eb2e8f9f7	1547	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1548	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	1549
<>	144:ef7eb2e8f9f7	1550	/* Wait until DIR flag is set Receiver mode */
<>	144:ef7eb2e8f9f7	1551	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK)
<>	144:ef7eb2e8f9f7	1552	{
<>	144:ef7eb2e8f9f7	1553	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1554	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	1555	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1556	}
<>	144:ef7eb2e8f9f7	1557
<>	144:ef7eb2e8f9f7	1558	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	1559	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	1560
<>	144:ef7eb2e8f9f7	1561	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1562	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1563
<>	144:ef7eb2e8f9f7	1564	return HAL_OK;
<>	144:ef7eb2e8f9f7	1565	}
<>	144:ef7eb2e8f9f7	1566	else
<>	144:ef7eb2e8f9f7	1567	{
<>	144:ef7eb2e8f9f7	1568	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1569	}
<>	144:ef7eb2e8f9f7	1570	}
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	/**
<>	144:ef7eb2e8f9f7	1573	* @brief Write an amount of data in blocking mode to a specific memory address
<>	144:ef7eb2e8f9f7	1574	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1575	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1576	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	1577	* @param MemAddress: Internal memory address
<>	144:ef7eb2e8f9f7	1578	* @param MemAddSize: Size of internal memory address
<>	144:ef7eb2e8f9f7	1579	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1580	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1581	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	1582	* @retval HAL status
<>	144:ef7eb2e8f9f7	1583	*/
<>	144:ef7eb2e8f9f7	1584	HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1585	{
<>	144:ef7eb2e8f9f7	1586	uint32_t Sizetmp = 0;
<>	144:ef7eb2e8f9f7	1587
<>	144:ef7eb2e8f9f7	1588	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1589	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	1590
<>	144:ef7eb2e8f9f7	1591	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1592	{
<>	144:ef7eb2e8f9f7	1593	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1594	{
<>	144:ef7eb2e8f9f7	1595	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1596	}
<>	144:ef7eb2e8f9f7	1597
<>	144:ef7eb2e8f9f7	1598	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1599	{
<>	144:ef7eb2e8f9f7	1600	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1601	}
<>	144:ef7eb2e8f9f7	1602
<>	144:ef7eb2e8f9f7	1603	/* Process Locked */
<>	144:ef7eb2e8f9f7	1604	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1605
<>	144:ef7eb2e8f9f7	1606	hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
<>	144:ef7eb2e8f9f7	1607	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1608
<>	144:ef7eb2e8f9f7	1609	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	1610	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	1611	{
<>	144:ef7eb2e8f9f7	1612	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1613	{
<>	144:ef7eb2e8f9f7	1614	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1615	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1616	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1617	}
<>	144:ef7eb2e8f9f7	1618	else
<>	144:ef7eb2e8f9f7	1619	{
<>	144:ef7eb2e8f9f7	1620	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1621	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1622	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1623	}
<>	144:ef7eb2e8f9f7	1624	}
<>	144:ef7eb2e8f9f7	1625
<>	144:ef7eb2e8f9f7	1626	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	1627	/* Size > 255, need to set RELOAD bit */
<>	144:ef7eb2e8f9f7	1628	if(Size > 255)
<>	144:ef7eb2e8f9f7	1629	{
<>	144:ef7eb2e8f9f7	1630	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1631	Sizetmp = 255;
<>	144:ef7eb2e8f9f7	1632	}
<>	144:ef7eb2e8f9f7	1633	else
<>	144:ef7eb2e8f9f7	1634	{
<>	144:ef7eb2e8f9f7	1635	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1636	Sizetmp = Size;
<>	144:ef7eb2e8f9f7	1637	}
<>	144:ef7eb2e8f9f7	1638
<>	144:ef7eb2e8f9f7	1639	do
<>	144:ef7eb2e8f9f7	1640	{
<>	144:ef7eb2e8f9f7	1641	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	1642	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	1643	{
<>	144:ef7eb2e8f9f7	1644	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1645	{
<>	144:ef7eb2e8f9f7	1646	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1647	}
<>	144:ef7eb2e8f9f7	1648	else
<>	144:ef7eb2e8f9f7	1649	{
<>	144:ef7eb2e8f9f7	1650	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1651	}
<>	144:ef7eb2e8f9f7	1652	}
<>	144:ef7eb2e8f9f7	1653
<>	144:ef7eb2e8f9f7	1654	/* Write data to DR */
<>	144:ef7eb2e8f9f7	1655	hi2c->Instance->TXDR = (*pData++);
<>	144:ef7eb2e8f9f7	1656	Sizetmp--;
<>	144:ef7eb2e8f9f7	1657	Size--;
<>	144:ef7eb2e8f9f7	1658
<>	144:ef7eb2e8f9f7	1659	if((Sizetmp == 0)&&(Size!=0))
<>	144:ef7eb2e8f9f7	1660	{
<>	144:ef7eb2e8f9f7	1661	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	1662	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	1663	{
<>	144:ef7eb2e8f9f7	1664	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1665	}
<>	144:ef7eb2e8f9f7	1666
<>	144:ef7eb2e8f9f7	1667
<>	144:ef7eb2e8f9f7	1668	if(Size > 255)
<>	144:ef7eb2e8f9f7	1669	{
<>	144:ef7eb2e8f9f7	1670	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1671	Sizetmp = 255;
<>	144:ef7eb2e8f9f7	1672	}
<>	144:ef7eb2e8f9f7	1673	else
<>	144:ef7eb2e8f9f7	1674	{
<>	144:ef7eb2e8f9f7	1675	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1676	Sizetmp = Size;
<>	144:ef7eb2e8f9f7	1677	}
<>	144:ef7eb2e8f9f7	1678	}
<>	144:ef7eb2e8f9f7	1679
<>	144:ef7eb2e8f9f7	1680	}while(Size > 0);
<>	144:ef7eb2e8f9f7	1681
<>	144:ef7eb2e8f9f7	1682	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	1683	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	1684	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	1685	{
<>	144:ef7eb2e8f9f7	1686	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1687	{
<>	144:ef7eb2e8f9f7	1688	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1689	}
<>	144:ef7eb2e8f9f7	1690	else
<>	144:ef7eb2e8f9f7	1691	{
<>	144:ef7eb2e8f9f7	1692	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1693	}
<>	144:ef7eb2e8f9f7	1694	}
<>	144:ef7eb2e8f9f7	1695
<>	144:ef7eb2e8f9f7	1696	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	1697	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	1698
<>	144:ef7eb2e8f9f7	1699	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	1700	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	1701
<>	144:ef7eb2e8f9f7	1702	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1703
<>	144:ef7eb2e8f9f7	1704	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1705	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1706
<>	144:ef7eb2e8f9f7	1707	return HAL_OK;
<>	144:ef7eb2e8f9f7	1708	}
<>	144:ef7eb2e8f9f7	1709	else
<>	144:ef7eb2e8f9f7	1710	{
<>	144:ef7eb2e8f9f7	1711	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1712	}
<>	144:ef7eb2e8f9f7	1713	}
<>	144:ef7eb2e8f9f7	1714
<>	144:ef7eb2e8f9f7	1715	/**
<>	144:ef7eb2e8f9f7	1716	* @brief Read an amount of data in blocking mode from a specific memory address
<>	144:ef7eb2e8f9f7	1717	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1718	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1719	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	1720	* @param MemAddress: Internal memory address
<>	144:ef7eb2e8f9f7	1721	* @param MemAddSize: Size of internal memory address
<>	144:ef7eb2e8f9f7	1722	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1723	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1724	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	1725	* @retval HAL status
<>	144:ef7eb2e8f9f7	1726	*/
<>	144:ef7eb2e8f9f7	1727	HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1728	{
<>	144:ef7eb2e8f9f7	1729	uint32_t Sizetmp = 0;
<>	144:ef7eb2e8f9f7	1730
<>	144:ef7eb2e8f9f7	1731	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1732	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	1733
<>	144:ef7eb2e8f9f7	1734	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1735	{
<>	144:ef7eb2e8f9f7	1736	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1737	{
<>	144:ef7eb2e8f9f7	1738	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1739	}
<>	144:ef7eb2e8f9f7	1740
<>	144:ef7eb2e8f9f7	1741	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1742	{
<>	144:ef7eb2e8f9f7	1743	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1744	}
<>	144:ef7eb2e8f9f7	1745
<>	144:ef7eb2e8f9f7	1746	/* Process Locked */
<>	144:ef7eb2e8f9f7	1747	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1748
<>	144:ef7eb2e8f9f7	1749	hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
<>	144:ef7eb2e8f9f7	1750	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1751
<>	144:ef7eb2e8f9f7	1752	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	1753	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	1754	{
<>	144:ef7eb2e8f9f7	1755	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1756	{
<>	144:ef7eb2e8f9f7	1757	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1758	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1759	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1760	}
<>	144:ef7eb2e8f9f7	1761	else
<>	144:ef7eb2e8f9f7	1762	{
<>	144:ef7eb2e8f9f7	1763	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1764	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1765	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1766	}
<>	144:ef7eb2e8f9f7	1767	}
<>	144:ef7eb2e8f9f7	1768
<>	144:ef7eb2e8f9f7	1769	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	1770	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
<>	144:ef7eb2e8f9f7	1771	/* Size > 255, need to set RELOAD bit */
<>	144:ef7eb2e8f9f7	1772	if(Size > 255)
<>	144:ef7eb2e8f9f7	1773	{
<>	144:ef7eb2e8f9f7	1774	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1775	Sizetmp = 255;
<>	144:ef7eb2e8f9f7	1776	}
<>	144:ef7eb2e8f9f7	1777	else
<>	144:ef7eb2e8f9f7	1778	{
<>	144:ef7eb2e8f9f7	1779	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	1780	Sizetmp = Size;
<>	144:ef7eb2e8f9f7	1781	}
<>	144:ef7eb2e8f9f7	1782
<>	144:ef7eb2e8f9f7	1783	do
<>	144:ef7eb2e8f9f7	1784	{
<>	144:ef7eb2e8f9f7	1785	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	1786	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	1787	{
<>	144:ef7eb2e8f9f7	1788	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1789	}
<>	144:ef7eb2e8f9f7	1790
<>	144:ef7eb2e8f9f7	1791	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	1792	(*pData++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	/* Decrement the Size counter */
<>	144:ef7eb2e8f9f7	1795	Sizetmp--;
<>	144:ef7eb2e8f9f7	1796	Size--;
<>	144:ef7eb2e8f9f7	1797
<>	144:ef7eb2e8f9f7	1798	if((Sizetmp == 0)&&(Size!=0))
<>	144:ef7eb2e8f9f7	1799	{
<>	144:ef7eb2e8f9f7	1800	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	1801	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	1802	{
<>	144:ef7eb2e8f9f7	1803	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1804	}
<>	144:ef7eb2e8f9f7	1805
<>	144:ef7eb2e8f9f7	1806	if(Size > 255)
<>	144:ef7eb2e8f9f7	1807	{
<>	144:ef7eb2e8f9f7	1808	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1809	Sizetmp = 255;
<>	144:ef7eb2e8f9f7	1810	}
<>	144:ef7eb2e8f9f7	1811	else
<>	144:ef7eb2e8f9f7	1812	{
<>	144:ef7eb2e8f9f7	1813	I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1814	Sizetmp = Size;
<>	144:ef7eb2e8f9f7	1815	}
<>	144:ef7eb2e8f9f7	1816	}
<>	144:ef7eb2e8f9f7	1817
<>	144:ef7eb2e8f9f7	1818	}while(Size > 0);
<>	144:ef7eb2e8f9f7	1819
<>	144:ef7eb2e8f9f7	1820	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	1821	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	1822	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	1823	{
<>	144:ef7eb2e8f9f7	1824	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1825	{
<>	144:ef7eb2e8f9f7	1826	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1827	}
<>	144:ef7eb2e8f9f7	1828	else
<>	144:ef7eb2e8f9f7	1829	{
<>	144:ef7eb2e8f9f7	1830	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1831	}
<>	144:ef7eb2e8f9f7	1832	}
<>	144:ef7eb2e8f9f7	1833
<>	144:ef7eb2e8f9f7	1834	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	1835	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	1836
<>	144:ef7eb2e8f9f7	1837	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	1838	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	1839
<>	144:ef7eb2e8f9f7	1840	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1841
<>	144:ef7eb2e8f9f7	1842	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1843	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1844
<>	144:ef7eb2e8f9f7	1845	return HAL_OK;
<>	144:ef7eb2e8f9f7	1846	}
<>	144:ef7eb2e8f9f7	1847	else
<>	144:ef7eb2e8f9f7	1848	{
<>	144:ef7eb2e8f9f7	1849	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1850	}
<>	144:ef7eb2e8f9f7	1851	}
<>	144:ef7eb2e8f9f7	1852
<>	144:ef7eb2e8f9f7	1853	/**
<>	144:ef7eb2e8f9f7	1854	* @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
<>	144:ef7eb2e8f9f7	1855	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1856	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1857	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	1858	* @param MemAddress: Internal memory address
<>	144:ef7eb2e8f9f7	1859	* @param MemAddSize: Size of internal memory address
<>	144:ef7eb2e8f9f7	1860	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1861	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1862	* @retval HAL status
<>	144:ef7eb2e8f9f7	1863	*/
<>	144:ef7eb2e8f9f7	1864	HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1865	{
<>	144:ef7eb2e8f9f7	1866	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1867	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	1868
<>	144:ef7eb2e8f9f7	1869	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1870	{
<>	144:ef7eb2e8f9f7	1871	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1872	{
<>	144:ef7eb2e8f9f7	1873	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1874	}
<>	144:ef7eb2e8f9f7	1875
<>	144:ef7eb2e8f9f7	1876	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1877	{
<>	144:ef7eb2e8f9f7	1878	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1879	}
<>	144:ef7eb2e8f9f7	1880
<>	144:ef7eb2e8f9f7	1881	/* Process Locked */
<>	144:ef7eb2e8f9f7	1882	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1883
<>	144:ef7eb2e8f9f7	1884	hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
<>	144:ef7eb2e8f9f7	1885	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1886
<>	144:ef7eb2e8f9f7	1887	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1888	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1889	if(Size > 255)
<>	144:ef7eb2e8f9f7	1890	{
<>	144:ef7eb2e8f9f7	1891	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	1892	}
<>	144:ef7eb2e8f9f7	1893	else
<>	144:ef7eb2e8f9f7	1894	{
<>	144:ef7eb2e8f9f7	1895	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1896	}
<>	144:ef7eb2e8f9f7	1897
<>	144:ef7eb2e8f9f7	1898	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	1899	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
<>	144:ef7eb2e8f9f7	1900	{
<>	144:ef7eb2e8f9f7	1901	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1902	{
<>	144:ef7eb2e8f9f7	1903	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1904	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1905	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1906	}
<>	144:ef7eb2e8f9f7	1907	else
<>	144:ef7eb2e8f9f7	1908	{
<>	144:ef7eb2e8f9f7	1909	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1910	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1911	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1912	}
<>	144:ef7eb2e8f9f7	1913	}
<>	144:ef7eb2e8f9f7	1914
<>	144:ef7eb2e8f9f7	1915	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	1916	/* Size > 255, need to set RELOAD bit */
<>	144:ef7eb2e8f9f7	1917	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	1918	{
<>	144:ef7eb2e8f9f7	1919	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1920	}
<>	144:ef7eb2e8f9f7	1921	else
<>	144:ef7eb2e8f9f7	1922	{
<>	144:ef7eb2e8f9f7	1923	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	1924	}
<>	144:ef7eb2e8f9f7	1925
<>	144:ef7eb2e8f9f7	1926	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1927	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1928
<>	144:ef7eb2e8f9f7	1929	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1930	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1931	process unlock */
<>	144:ef7eb2e8f9f7	1932
<>	144:ef7eb2e8f9f7	1933	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
<>	144:ef7eb2e8f9f7	1934	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	1935	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	1936	__HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_TXI );
<>	144:ef7eb2e8f9f7	1937
<>	144:ef7eb2e8f9f7	1938	return HAL_OK;
<>	144:ef7eb2e8f9f7	1939	}
<>	144:ef7eb2e8f9f7	1940	else
<>	144:ef7eb2e8f9f7	1941	{
<>	144:ef7eb2e8f9f7	1942	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1943	}
<>	144:ef7eb2e8f9f7	1944	}
<>	144:ef7eb2e8f9f7	1945
<>	144:ef7eb2e8f9f7	1946	/**
<>	144:ef7eb2e8f9f7	1947	* @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
<>	144:ef7eb2e8f9f7	1948	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1949	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1950	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	1951	* @param MemAddress: Internal memory address
<>	144:ef7eb2e8f9f7	1952	* @param MemAddSize: Size of internal memory address
<>	144:ef7eb2e8f9f7	1953	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	1954	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	1955	* @retval HAL status
<>	144:ef7eb2e8f9f7	1956	*/
<>	144:ef7eb2e8f9f7	1957	HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1958	{
<>	144:ef7eb2e8f9f7	1959	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1960	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	1961
<>	144:ef7eb2e8f9f7	1962	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1963	{
<>	144:ef7eb2e8f9f7	1964	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1965	{
<>	144:ef7eb2e8f9f7	1966	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1967	}
<>	144:ef7eb2e8f9f7	1968
<>	144:ef7eb2e8f9f7	1969	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	1970	{
<>	144:ef7eb2e8f9f7	1971	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1972	}
<>	144:ef7eb2e8f9f7	1973
<>	144:ef7eb2e8f9f7	1974	/* Process Locked */
<>	144:ef7eb2e8f9f7	1975	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1976
<>	144:ef7eb2e8f9f7	1977	hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
<>	144:ef7eb2e8f9f7	1978
<>	144:ef7eb2e8f9f7	1979	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1980	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1981	if(Size > 255)
<>	144:ef7eb2e8f9f7	1982	{
<>	144:ef7eb2e8f9f7	1983	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	1984	}
<>	144:ef7eb2e8f9f7	1985	else
<>	144:ef7eb2e8f9f7	1986	{
<>	144:ef7eb2e8f9f7	1987	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1988	}
<>	144:ef7eb2e8f9f7	1989
<>	144:ef7eb2e8f9f7	1990	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	1991	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
<>	144:ef7eb2e8f9f7	1992	{
<>	144:ef7eb2e8f9f7	1993	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1994	{
<>	144:ef7eb2e8f9f7	1995	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1996	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1997	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1998	}
<>	144:ef7eb2e8f9f7	1999	else
<>	144:ef7eb2e8f9f7	2000	{
<>	144:ef7eb2e8f9f7	2001	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2002	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2003	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2004	}
<>	144:ef7eb2e8f9f7	2005	}
<>	144:ef7eb2e8f9f7	2006
<>	144:ef7eb2e8f9f7	2007	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
<>	144:ef7eb2e8f9f7	2008	/* Size > 255, need to set RELOAD bit */
<>	144:ef7eb2e8f9f7	2009	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	2010	{
<>	144:ef7eb2e8f9f7	2011	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	2012	}
<>	144:ef7eb2e8f9f7	2013	else
<>	144:ef7eb2e8f9f7	2014	{
<>	144:ef7eb2e8f9f7	2015	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	2016	}
<>	144:ef7eb2e8f9f7	2017
<>	144:ef7eb2e8f9f7	2018	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2019	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2020
<>	144:ef7eb2e8f9f7	2021	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2022	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2023	process unlock */
<>	144:ef7eb2e8f9f7	2024
<>	144:ef7eb2e8f9f7	2025	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
<>	144:ef7eb2e8f9f7	2026	/* possible to enable all of these */
<>	144:ef7eb2e8f9f7	2027	/* I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI */
<>	144:ef7eb2e8f9f7	2028	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_RXI );
<>	144:ef7eb2e8f9f7	2029
<>	144:ef7eb2e8f9f7	2030	return HAL_OK;
<>	144:ef7eb2e8f9f7	2031	}
<>	144:ef7eb2e8f9f7	2032	else
<>	144:ef7eb2e8f9f7	2033	{
<>	144:ef7eb2e8f9f7	2034	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2035	}
<>	144:ef7eb2e8f9f7	2036	}
<>	144:ef7eb2e8f9f7	2037
<>	144:ef7eb2e8f9f7	2038	/**
<>	144:ef7eb2e8f9f7	2039	* @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
<>	144:ef7eb2e8f9f7	2040	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2041	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2042	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	2043	* @param MemAddress: Internal memory address
<>	144:ef7eb2e8f9f7	2044	* @param MemAddSize: Size of internal memory address
<>	144:ef7eb2e8f9f7	2045	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	2046	* @param Size: Amount of data to be sent
<>	144:ef7eb2e8f9f7	2047	* @retval HAL status
<>	144:ef7eb2e8f9f7	2048	*/
<>	144:ef7eb2e8f9f7	2049	HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2050	{
<>	144:ef7eb2e8f9f7	2051	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2052	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2053
<>	144:ef7eb2e8f9f7	2054	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2055	{
<>	144:ef7eb2e8f9f7	2056	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	2057	{
<>	144:ef7eb2e8f9f7	2058	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2059	}
<>	144:ef7eb2e8f9f7	2060
<>	144:ef7eb2e8f9f7	2061	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	2062	{
<>	144:ef7eb2e8f9f7	2063	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2064	}
<>	144:ef7eb2e8f9f7	2065
<>	144:ef7eb2e8f9f7	2066	/* Process Locked */
<>	144:ef7eb2e8f9f7	2067	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2068
<>	144:ef7eb2e8f9f7	2069	hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
<>	144:ef7eb2e8f9f7	2070	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2071
<>	144:ef7eb2e8f9f7	2072	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2073	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2074	if(Size > 255)
<>	144:ef7eb2e8f9f7	2075	{
<>	144:ef7eb2e8f9f7	2076	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	2077	}
<>	144:ef7eb2e8f9f7	2078	else
<>	144:ef7eb2e8f9f7	2079	{
<>	144:ef7eb2e8f9f7	2080	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2081	}
<>	144:ef7eb2e8f9f7	2082
<>	144:ef7eb2e8f9f7	2083	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2084	hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
<>	144:ef7eb2e8f9f7	2085
<>	144:ef7eb2e8f9f7	2086	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2087	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2088
<>	144:ef7eb2e8f9f7	2089	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2090	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	2091
<>	144:ef7eb2e8f9f7	2092	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2093	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
<>	144:ef7eb2e8f9f7	2094	{
<>	144:ef7eb2e8f9f7	2095	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2096	{
<>	144:ef7eb2e8f9f7	2097	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2098	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2099	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2100	}
<>	144:ef7eb2e8f9f7	2101	else
<>	144:ef7eb2e8f9f7	2102	{
<>	144:ef7eb2e8f9f7	2103	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2104	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2105	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2106	}
<>	144:ef7eb2e8f9f7	2107	}
<>	144:ef7eb2e8f9f7	2108
<>	144:ef7eb2e8f9f7	2109	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	2110	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	2111	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	2112	{
<>	144:ef7eb2e8f9f7	2113	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	2114	}
<>	144:ef7eb2e8f9f7	2115	else
<>	144:ef7eb2e8f9f7	2116	{
<>	144:ef7eb2e8f9f7	2117	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	2118	}
<>	144:ef7eb2e8f9f7	2119
<>	144:ef7eb2e8f9f7	2120	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	2121	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
<>	144:ef7eb2e8f9f7	2122	{
<>	144:ef7eb2e8f9f7	2123	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2124	{
<>	144:ef7eb2e8f9f7	2125	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2126	}
<>	144:ef7eb2e8f9f7	2127	else
<>	144:ef7eb2e8f9f7	2128	{
<>	144:ef7eb2e8f9f7	2129	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2130	}
<>	144:ef7eb2e8f9f7	2131	}
<>	144:ef7eb2e8f9f7	2132
<>	144:ef7eb2e8f9f7	2133	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2134	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	2135
<>	144:ef7eb2e8f9f7	2136	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2137	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2138
<>	144:ef7eb2e8f9f7	2139	return HAL_OK;
<>	144:ef7eb2e8f9f7	2140	}
<>	144:ef7eb2e8f9f7	2141	else
<>	144:ef7eb2e8f9f7	2142	{
<>	144:ef7eb2e8f9f7	2143	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2144	}
<>	144:ef7eb2e8f9f7	2145	}
<>	144:ef7eb2e8f9f7	2146
<>	144:ef7eb2e8f9f7	2147	/**
<>	144:ef7eb2e8f9f7	2148	* @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
<>	144:ef7eb2e8f9f7	2149	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2150	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2151	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	2152	* @param MemAddress: Internal memory address
<>	144:ef7eb2e8f9f7	2153	* @param MemAddSize: Size of internal memory address
<>	144:ef7eb2e8f9f7	2154	* @param pData: Pointer to data buffer
<>	144:ef7eb2e8f9f7	2155	* @param Size: Amount of data to be read
<>	144:ef7eb2e8f9f7	2156	* @retval HAL status
<>	144:ef7eb2e8f9f7	2157	*/
<>	144:ef7eb2e8f9f7	2158	HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2159	{
<>	144:ef7eb2e8f9f7	2160	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2161	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2162
<>	144:ef7eb2e8f9f7	2163	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2164	{
<>	144:ef7eb2e8f9f7	2165	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	2166	{
<>	144:ef7eb2e8f9f7	2167	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2168	}
<>	144:ef7eb2e8f9f7	2169
<>	144:ef7eb2e8f9f7	2170	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	2171	{
<>	144:ef7eb2e8f9f7	2172	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2173	}
<>	144:ef7eb2e8f9f7	2174
<>	144:ef7eb2e8f9f7	2175	/* Process Locked */
<>	144:ef7eb2e8f9f7	2176	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2177
<>	144:ef7eb2e8f9f7	2178	hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
<>	144:ef7eb2e8f9f7	2179
<>	144:ef7eb2e8f9f7	2180	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2181	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2182	if(Size > 255)
<>	144:ef7eb2e8f9f7	2183	{
<>	144:ef7eb2e8f9f7	2184	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	2185	}
<>	144:ef7eb2e8f9f7	2186	else
<>	144:ef7eb2e8f9f7	2187	{
<>	144:ef7eb2e8f9f7	2188	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2189	}
<>	144:ef7eb2e8f9f7	2190
<>	144:ef7eb2e8f9f7	2191	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2192	hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
<>	144:ef7eb2e8f9f7	2193
<>	144:ef7eb2e8f9f7	2194	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2195	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2196
<>	144:ef7eb2e8f9f7	2197	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2198	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	2199
<>	144:ef7eb2e8f9f7	2200	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2201	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
<>	144:ef7eb2e8f9f7	2202	{
<>	144:ef7eb2e8f9f7	2203	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2204	{
<>	144:ef7eb2e8f9f7	2205	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2206	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2207	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2208	}
<>	144:ef7eb2e8f9f7	2209	else
<>	144:ef7eb2e8f9f7	2210	{
<>	144:ef7eb2e8f9f7	2211	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2212	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2213	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2214	}
<>	144:ef7eb2e8f9f7	2215	}
<>	144:ef7eb2e8f9f7	2216
<>	144:ef7eb2e8f9f7	2217	/* Set NBYTES to write and reload if size > 255 and generate RESTART */
<>	144:ef7eb2e8f9f7	2218	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	2219	{
<>	144:ef7eb2e8f9f7	2220	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	2221	}
<>	144:ef7eb2e8f9f7	2222	else
<>	144:ef7eb2e8f9f7	2223	{
<>	144:ef7eb2e8f9f7	2224	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<>	144:ef7eb2e8f9f7	2225	}
<>	144:ef7eb2e8f9f7	2226
<>	144:ef7eb2e8f9f7	2227	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	2228	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
<>	144:ef7eb2e8f9f7	2229	{
<>	144:ef7eb2e8f9f7	2230	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2231	}
<>	144:ef7eb2e8f9f7	2232
<>	144:ef7eb2e8f9f7	2233	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2234	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	2235
<>	144:ef7eb2e8f9f7	2236	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2237	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2238
<>	144:ef7eb2e8f9f7	2239	return HAL_OK;
<>	144:ef7eb2e8f9f7	2240	}
<>	144:ef7eb2e8f9f7	2241	else
<>	144:ef7eb2e8f9f7	2242	{
<>	144:ef7eb2e8f9f7	2243	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2244	}
<>	144:ef7eb2e8f9f7	2245	}
<>	144:ef7eb2e8f9f7	2246
<>	144:ef7eb2e8f9f7	2247	/**
<>	144:ef7eb2e8f9f7	2248	* @brief Checks if target device is ready for communication.
<>	144:ef7eb2e8f9f7	2249	* @note This function is used with Memory devices
<>	144:ef7eb2e8f9f7	2250	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2251	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2252	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	2253	* @param Trials: Number of trials
<>	144:ef7eb2e8f9f7	2254	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	2255	* @retval HAL status
<>	144:ef7eb2e8f9f7	2256	*/
<>	144:ef7eb2e8f9f7	2257	HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2258	{
<>	144:ef7eb2e8f9f7	2259	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	2260
<>	144:ef7eb2e8f9f7	2261	__IO uint32_t I2C_Trials = 0;
<>	144:ef7eb2e8f9f7	2262
<>	144:ef7eb2e8f9f7	2263	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2264	{
<>	144:ef7eb2e8f9f7	2265	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<>	144:ef7eb2e8f9f7	2266	{
<>	144:ef7eb2e8f9f7	2267	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2268	}
<>	144:ef7eb2e8f9f7	2269
<>	144:ef7eb2e8f9f7	2270	/* Process Locked */
<>	144:ef7eb2e8f9f7	2271	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2272
<>	144:ef7eb2e8f9f7	2273	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2274	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2275
<>	144:ef7eb2e8f9f7	2276	do
<>	144:ef7eb2e8f9f7	2277	{
<>	144:ef7eb2e8f9f7	2278	/* Generate Start */
<>	144:ef7eb2e8f9f7	2279	hi2c->Instance->CR2 = __I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
<>	144:ef7eb2e8f9f7	2280
<>	144:ef7eb2e8f9f7	2281	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	2282	/* Wait until STOPF flag is set or a NACK flag is set*/
<>	144:ef7eb2e8f9f7	2283	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2284	while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
<>	144:ef7eb2e8f9f7	2285	{
<>	144:ef7eb2e8f9f7	2286	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	2287	{
<>	144:ef7eb2e8f9f7	2288	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	2289	{
<>	144:ef7eb2e8f9f7	2290	/* Device is ready */
<>	144:ef7eb2e8f9f7	2291	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2292	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2293	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2294	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2295	}
<>	144:ef7eb2e8f9f7	2296	}
<>	144:ef7eb2e8f9f7	2297	}
<>	144:ef7eb2e8f9f7	2298
<>	144:ef7eb2e8f9f7	2299	/* Check if the NACKF flag has not been set */
<>	144:ef7eb2e8f9f7	2300	if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
<>	144:ef7eb2e8f9f7	2301	{
<>	144:ef7eb2e8f9f7	2302	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	2303	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	2304	{
<>	144:ef7eb2e8f9f7	2305	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2306	}
<>	144:ef7eb2e8f9f7	2307
<>	144:ef7eb2e8f9f7	2308	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	2309	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	2310
<>	144:ef7eb2e8f9f7	2311	/* Device is ready */
<>	144:ef7eb2e8f9f7	2312	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2313
<>	144:ef7eb2e8f9f7	2314	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2315	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2316
<>	144:ef7eb2e8f9f7	2317	return HAL_OK;
<>	144:ef7eb2e8f9f7	2318	}
<>	144:ef7eb2e8f9f7	2319	else
<>	144:ef7eb2e8f9f7	2320	{
<>	144:ef7eb2e8f9f7	2321	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	2322	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	2323	{
<>	144:ef7eb2e8f9f7	2324	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2325	}
<>	144:ef7eb2e8f9f7	2326
<>	144:ef7eb2e8f9f7	2327	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	2328	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	2329
<>	144:ef7eb2e8f9f7	2330	/* Clear STOP Flag, auto generated with autoend*/
<>	144:ef7eb2e8f9f7	2331	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	2332	}
<>	144:ef7eb2e8f9f7	2333
<>	144:ef7eb2e8f9f7	2334	/* Check if the maximum allowed number of trials has been reached */
<>	144:ef7eb2e8f9f7	2335	if (I2C_Trials++ == Trials)
<>	144:ef7eb2e8f9f7	2336	{
<>	144:ef7eb2e8f9f7	2337	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2338	hi2c->Instance->CR2 \|= I2C_CR2_STOP;
<>	144:ef7eb2e8f9f7	2339
<>	144:ef7eb2e8f9f7	2340	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	2341	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	2342	{
<>	144:ef7eb2e8f9f7	2343	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2344	}
<>	144:ef7eb2e8f9f7	2345
<>	144:ef7eb2e8f9f7	2346	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	2347	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	2348	}
<>	144:ef7eb2e8f9f7	2349	}while(I2C_Trials < Trials);
<>	144:ef7eb2e8f9f7	2350
<>	144:ef7eb2e8f9f7	2351	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2352
<>	144:ef7eb2e8f9f7	2353	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2354	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2355
<>	144:ef7eb2e8f9f7	2356	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2357	}
<>	144:ef7eb2e8f9f7	2358	else
<>	144:ef7eb2e8f9f7	2359	{
<>	144:ef7eb2e8f9f7	2360	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2361	}
<>	144:ef7eb2e8f9f7	2362	}
<>	144:ef7eb2e8f9f7	2363	/**
<>	144:ef7eb2e8f9f7	2364	* @}
<>	144:ef7eb2e8f9f7	2365	*/
<>	144:ef7eb2e8f9f7	2366
<>	144:ef7eb2e8f9f7	2367	/** @addtogroup IRQ_Handler_and_Callbacks
<>	144:ef7eb2e8f9f7	2368	* @{
<>	144:ef7eb2e8f9f7	2369	*/
<>	144:ef7eb2e8f9f7	2370
<>	144:ef7eb2e8f9f7	2371	/**
<>	144:ef7eb2e8f9f7	2372	* @brief This function handles I2C event interrupt request.
<>	144:ef7eb2e8f9f7	2373	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2374	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2375	* @retval None
<>	144:ef7eb2e8f9f7	2376	*/
<>	144:ef7eb2e8f9f7	2377	void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2378	{
<>	144:ef7eb2e8f9f7	2379	/* I2C in mode Transmitter ---------------------------------------------------*/
<>	144:ef7eb2e8f9f7	2380	if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_TXI \| I2C_IT_ADDRI)) == SET))
<>	144:ef7eb2e8f9f7	2381	{
<>	144:ef7eb2e8f9f7	2382	/* Slave mode selected */
<>	144:ef7eb2e8f9f7	2383	if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX)
<>	144:ef7eb2e8f9f7	2384	{
<>	144:ef7eb2e8f9f7	2385	I2C_SlaveTransmit_ISR(hi2c);
<>	144:ef7eb2e8f9f7	2386	}
<>	144:ef7eb2e8f9f7	2387	}
<>	144:ef7eb2e8f9f7	2388
<>	144:ef7eb2e8f9f7	2389	if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI \| I2C_IT_STOPI \| I2C_IT_NACKI \| I2C_IT_TXI)) == SET))
<>	144:ef7eb2e8f9f7	2390	{
<>	144:ef7eb2e8f9f7	2391	/* Master mode selected */
<>	144:ef7eb2e8f9f7	2392	if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) \|\| (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX))
<>	144:ef7eb2e8f9f7	2393	{
<>	144:ef7eb2e8f9f7	2394	I2C_MasterTransmit_ISR(hi2c);
<>	144:ef7eb2e8f9f7	2395	}
<>	144:ef7eb2e8f9f7	2396	}
<>	144:ef7eb2e8f9f7	2397
<>	144:ef7eb2e8f9f7	2398	/* I2C in mode Receiver ----------------------------------------------------*/
<>	144:ef7eb2e8f9f7	2399	if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_RXI \| I2C_IT_ADDRI)) == SET))
<>	144:ef7eb2e8f9f7	2400	{
<>	144:ef7eb2e8f9f7	2401	/* Slave mode selected */
<>	144:ef7eb2e8f9f7	2402	if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)
<>	144:ef7eb2e8f9f7	2403	{
<>	144:ef7eb2e8f9f7	2404	I2C_SlaveReceive_ISR(hi2c);
<>	144:ef7eb2e8f9f7	2405	}
<>	144:ef7eb2e8f9f7	2406	}
<>	144:ef7eb2e8f9f7	2407	if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) \|\| (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_RXI)) == SET))
<>	144:ef7eb2e8f9f7	2408	{
<>	144:ef7eb2e8f9f7	2409	/* Master mode selected */
<>	144:ef7eb2e8f9f7	2410	if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) \|\| (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
<>	144:ef7eb2e8f9f7	2411	{
<>	144:ef7eb2e8f9f7	2412	I2C_MasterReceive_ISR(hi2c);
<>	144:ef7eb2e8f9f7	2413	}
<>	144:ef7eb2e8f9f7	2414	}
<>	144:ef7eb2e8f9f7	2415	}
<>	144:ef7eb2e8f9f7	2416
<>	144:ef7eb2e8f9f7	2417	/**
<>	144:ef7eb2e8f9f7	2418	* @brief This function handles I2C error interrupt request.
<>	144:ef7eb2e8f9f7	2419	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2420	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2421	* @retval None
<>	144:ef7eb2e8f9f7	2422	*/
<>	144:ef7eb2e8f9f7	2423	void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2424	{
<>	144:ef7eb2e8f9f7	2425	/* I2C Bus error interrupt occurred ------------------------------------*/
<>	144:ef7eb2e8f9f7	2426	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
<>	144:ef7eb2e8f9f7	2427	{
<>	144:ef7eb2e8f9f7	2428	hi2c->ErrorCode \|= HAL_I2C_ERROR_BERR;
<>	144:ef7eb2e8f9f7	2429
<>	144:ef7eb2e8f9f7	2430	/* Clear BERR flag */
<>	144:ef7eb2e8f9f7	2431	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
<>	144:ef7eb2e8f9f7	2432	}
<>	144:ef7eb2e8f9f7	2433
<>	144:ef7eb2e8f9f7	2434	/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
<>	144:ef7eb2e8f9f7	2435	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
<>	144:ef7eb2e8f9f7	2436	{
<>	144:ef7eb2e8f9f7	2437	hi2c->ErrorCode \|= HAL_I2C_ERROR_OVR;
<>	144:ef7eb2e8f9f7	2438
<>	144:ef7eb2e8f9f7	2439	/* Clear OVR flag */
<>	144:ef7eb2e8f9f7	2440	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
<>	144:ef7eb2e8f9f7	2441	}
<>	144:ef7eb2e8f9f7	2442
<>	144:ef7eb2e8f9f7	2443	/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
<>	144:ef7eb2e8f9f7	2444	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
<>	144:ef7eb2e8f9f7	2445	{
<>	144:ef7eb2e8f9f7	2446	hi2c->ErrorCode \|= HAL_I2C_ERROR_ARLO;
<>	144:ef7eb2e8f9f7	2447
<>	144:ef7eb2e8f9f7	2448	/* Clear ARLO flag */
<>	144:ef7eb2e8f9f7	2449	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
<>	144:ef7eb2e8f9f7	2450	}
<>	144:ef7eb2e8f9f7	2451
<>	144:ef7eb2e8f9f7	2452	/* Call the Error Callback in case of Error detected */
<>	144:ef7eb2e8f9f7	2453	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2454	{
<>	144:ef7eb2e8f9f7	2455	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2456
<>	144:ef7eb2e8f9f7	2457	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	2458	}
<>	144:ef7eb2e8f9f7	2459	}
<>	144:ef7eb2e8f9f7	2460
<>	144:ef7eb2e8f9f7	2461	/**
<>	144:ef7eb2e8f9f7	2462	* @brief Master Tx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	2463	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2464	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2465	* @retval None
<>	144:ef7eb2e8f9f7	2466	*/
<>	144:ef7eb2e8f9f7	2467	__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2468	{
<>	144:ef7eb2e8f9f7	2469	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2470	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	2471
<>	144:ef7eb2e8f9f7	2472	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2473	the HAL_I2C_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2474	*/
<>	144:ef7eb2e8f9f7	2475	}
<>	144:ef7eb2e8f9f7	2476
<>	144:ef7eb2e8f9f7	2477	/**
<>	144:ef7eb2e8f9f7	2478	* @brief Master Rx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	2479	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2480	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2481	* @retval None
<>	144:ef7eb2e8f9f7	2482	*/
<>	144:ef7eb2e8f9f7	2483	__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2484	{
<>	144:ef7eb2e8f9f7	2485	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2486	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	2487
<>	144:ef7eb2e8f9f7	2488	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2489	the HAL_I2C_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2490	*/
<>	144:ef7eb2e8f9f7	2491	}
<>	144:ef7eb2e8f9f7	2492
<>	144:ef7eb2e8f9f7	2493	/** @brief Slave Tx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	2494	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2495	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2496	* @retval None
<>	144:ef7eb2e8f9f7	2497	*/
<>	144:ef7eb2e8f9f7	2498	__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2499	{
<>	144:ef7eb2e8f9f7	2500	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2501	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	2502
<>	144:ef7eb2e8f9f7	2503	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2504	the HAL_I2C_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2505	*/
<>	144:ef7eb2e8f9f7	2506	}
<>	144:ef7eb2e8f9f7	2507
<>	144:ef7eb2e8f9f7	2508	/**
<>	144:ef7eb2e8f9f7	2509	* @brief Slave Rx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	2510	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2511	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2512	* @retval None
<>	144:ef7eb2e8f9f7	2513	*/
<>	144:ef7eb2e8f9f7	2514	__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2515	{
<>	144:ef7eb2e8f9f7	2516	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2517	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	2518
<>	144:ef7eb2e8f9f7	2519	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2520	the HAL_I2C_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2521	*/
<>	144:ef7eb2e8f9f7	2522	}
<>	144:ef7eb2e8f9f7	2523
<>	144:ef7eb2e8f9f7	2524	/**
<>	144:ef7eb2e8f9f7	2525	* @brief Memory Tx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	2526	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2527	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2528	* @retval None
<>	144:ef7eb2e8f9f7	2529	*/
<>	144:ef7eb2e8f9f7	2530	__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2531	{
<>	144:ef7eb2e8f9f7	2532	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2533	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	2534
<>	144:ef7eb2e8f9f7	2535	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2536	the HAL_I2C_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2537	*/
<>	144:ef7eb2e8f9f7	2538	}
<>	144:ef7eb2e8f9f7	2539
<>	144:ef7eb2e8f9f7	2540	/**
<>	144:ef7eb2e8f9f7	2541	* @brief Memory Rx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	2542	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2543	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2544	* @retval None
<>	144:ef7eb2e8f9f7	2545	*/
<>	144:ef7eb2e8f9f7	2546	__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2547	{
<>	144:ef7eb2e8f9f7	2548	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2549	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	2550
<>	144:ef7eb2e8f9f7	2551	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2552	the HAL_I2C_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2553	*/
<>	144:ef7eb2e8f9f7	2554	}
<>	144:ef7eb2e8f9f7	2555
<>	144:ef7eb2e8f9f7	2556	/**
<>	144:ef7eb2e8f9f7	2557	* @brief I2C error callbacks.
<>	144:ef7eb2e8f9f7	2558	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2559	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2560	* @retval None
<>	144:ef7eb2e8f9f7	2561	*/
<>	144:ef7eb2e8f9f7	2562	__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2563	{
<>	144:ef7eb2e8f9f7	2564	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2565	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	2566
<>	144:ef7eb2e8f9f7	2567	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2568	the HAL_I2C_ErrorCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2569	*/
<>	144:ef7eb2e8f9f7	2570	}
<>	144:ef7eb2e8f9f7	2571
<>	144:ef7eb2e8f9f7	2572	/**
<>	144:ef7eb2e8f9f7	2573	* @}
<>	144:ef7eb2e8f9f7	2574	*/
<>	144:ef7eb2e8f9f7	2575
<>	144:ef7eb2e8f9f7	2576
<>	144:ef7eb2e8f9f7	2577	/** @addtogroup I2C_Exported_Functions_Group3
<>	144:ef7eb2e8f9f7	2578	* @brief Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	2579	*
<>	144:ef7eb2e8f9f7	2580	@verbatim
<>	144:ef7eb2e8f9f7	2581	===============================================================================
<>	144:ef7eb2e8f9f7	2582	##### Peripheral State and Errors functions #####
<>	144:ef7eb2e8f9f7	2583	===============================================================================
<>	144:ef7eb2e8f9f7	2584	[..]
<>	144:ef7eb2e8f9f7	2585	This subsection permit to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	2586	and the data flow.
<>	144:ef7eb2e8f9f7	2587
<>	144:ef7eb2e8f9f7	2588	@endverbatim
<>	144:ef7eb2e8f9f7	2589	* @{
<>	144:ef7eb2e8f9f7	2590	*/
<>	144:ef7eb2e8f9f7	2591
<>	144:ef7eb2e8f9f7	2592	/**
<>	144:ef7eb2e8f9f7	2593	* @brief Returns the I2C state.
<>	144:ef7eb2e8f9f7	2594	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2595	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2596	* @retval HAL state
<>	144:ef7eb2e8f9f7	2597	*/
<>	144:ef7eb2e8f9f7	2598	HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2599	{
<>	144:ef7eb2e8f9f7	2600	return hi2c->State;
<>	144:ef7eb2e8f9f7	2601	}
<>	144:ef7eb2e8f9f7	2602
<>	144:ef7eb2e8f9f7	2603	/**
<>	144:ef7eb2e8f9f7	2604	* @brief Return the I2C error code
<>	144:ef7eb2e8f9f7	2605	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2606	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2607	* @retval I2C Error Code
<>	144:ef7eb2e8f9f7	2608	*/
<>	144:ef7eb2e8f9f7	2609	uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2610	{
<>	144:ef7eb2e8f9f7	2611	return hi2c->ErrorCode;
<>	144:ef7eb2e8f9f7	2612	}
<>	144:ef7eb2e8f9f7	2613
<>	144:ef7eb2e8f9f7	2614	/**
<>	144:ef7eb2e8f9f7	2615	* @}
<>	144:ef7eb2e8f9f7	2616	*/
<>	144:ef7eb2e8f9f7	2617
<>	144:ef7eb2e8f9f7	2618	/**
<>	144:ef7eb2e8f9f7	2619	* @}
<>	144:ef7eb2e8f9f7	2620	*/
<>	144:ef7eb2e8f9f7	2621
<>	144:ef7eb2e8f9f7	2622	/** @addtogroup I2C_Private
<>	144:ef7eb2e8f9f7	2623	* @{
<>	144:ef7eb2e8f9f7	2624	*/
<>	144:ef7eb2e8f9f7	2625
<>	144:ef7eb2e8f9f7	2626	/**
<>	144:ef7eb2e8f9f7	2627	* @brief Handle Interrupt Flags Master Transmit Mode
<>	144:ef7eb2e8f9f7	2628	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2629	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2630	* @retval HAL status
<>	144:ef7eb2e8f9f7	2631	*/
<>	144:ef7eb2e8f9f7	2632	static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2633	{
<>	144:ef7eb2e8f9f7	2634	uint16_t DevAddress;
<>	144:ef7eb2e8f9f7	2635
<>	144:ef7eb2e8f9f7	2636	/* Process Locked */
<>	144:ef7eb2e8f9f7	2637	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2638
<>	144:ef7eb2e8f9f7	2639	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
<>	144:ef7eb2e8f9f7	2640	{
<>	144:ef7eb2e8f9f7	2641	/* Write data to TXDR */
<>	144:ef7eb2e8f9f7	2642	hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	2643	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2644	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2645	}
<>	144:ef7eb2e8f9f7	2646	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
<>	144:ef7eb2e8f9f7	2647	{
<>	144:ef7eb2e8f9f7	2648	if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
<>	144:ef7eb2e8f9f7	2649	{
<>	144:ef7eb2e8f9f7	2650	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
<>	144:ef7eb2e8f9f7	2651
<>	144:ef7eb2e8f9f7	2652	if(hi2c->XferCount > 255)
<>	144:ef7eb2e8f9f7	2653	{
<>	144:ef7eb2e8f9f7	2654	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	2655	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	2656	}
<>	144:ef7eb2e8f9f7	2657	else
<>	144:ef7eb2e8f9f7	2658	{
<>	144:ef7eb2e8f9f7	2659	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	2660	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2661	}
<>	144:ef7eb2e8f9f7	2662	}
<>	144:ef7eb2e8f9f7	2663	else
<>	144:ef7eb2e8f9f7	2664	{
<>	144:ef7eb2e8f9f7	2665	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2666	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2667
<>	144:ef7eb2e8f9f7	2668	/* Wrong size Status regarding TCR flag event */
<>	144:ef7eb2e8f9f7	2669	hi2c->ErrorCode \|= HAL_I2C_ERROR_SIZE;
<>	144:ef7eb2e8f9f7	2670	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	2671	}
<>	144:ef7eb2e8f9f7	2672	}
<>	144:ef7eb2e8f9f7	2673	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
<>	144:ef7eb2e8f9f7	2674	{
<>	144:ef7eb2e8f9f7	2675	if(hi2c->XferCount == 0)
<>	144:ef7eb2e8f9f7	2676	{
<>	144:ef7eb2e8f9f7	2677	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2678	hi2c->Instance->CR2 \|= I2C_CR2_STOP;
<>	144:ef7eb2e8f9f7	2679	}
<>	144:ef7eb2e8f9f7	2680	else
<>	144:ef7eb2e8f9f7	2681	{
<>	144:ef7eb2e8f9f7	2682	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2683	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2684
<>	144:ef7eb2e8f9f7	2685	/* Wrong size Status regarding TCR flag event */
<>	144:ef7eb2e8f9f7	2686	hi2c->ErrorCode \|= HAL_I2C_ERROR_SIZE;
<>	144:ef7eb2e8f9f7	2687	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	2688	}
<>	144:ef7eb2e8f9f7	2689	}
<>	144:ef7eb2e8f9f7	2690	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<>	144:ef7eb2e8f9f7	2691	{
<>	144:ef7eb2e8f9f7	2692	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	2693	{
<>	144:ef7eb2e8f9f7	2694	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	2695	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	2696
<>	144:ef7eb2e8f9f7	2697	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	2698	}
<>	144:ef7eb2e8f9f7	2699	/* Disable ERR, TC, STOP, NACK, TXI interrupts */
<>	144:ef7eb2e8f9f7	2700	__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_TXI );
<>	144:ef7eb2e8f9f7	2701
<>	144:ef7eb2e8f9f7	2702	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	2703	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	2704
<>	144:ef7eb2e8f9f7	2705	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	2706	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	2707
<>	144:ef7eb2e8f9f7	2708	/* Flush TX register if not empty */
<>	144:ef7eb2e8f9f7	2709	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
<>	144:ef7eb2e8f9f7	2710	{
<>	144:ef7eb2e8f9f7	2711	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
<>	144:ef7eb2e8f9f7	2712	}
<>	144:ef7eb2e8f9f7	2713
<>	144:ef7eb2e8f9f7	2714	/* Call the correct callback to inform upper layer */
<>	144:ef7eb2e8f9f7	2715	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2716	{
<>	144:ef7eb2e8f9f7	2717	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2718
<>	144:ef7eb2e8f9f7	2719	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2720	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2721
<>	144:ef7eb2e8f9f7	2722	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	2723	}
<>	144:ef7eb2e8f9f7	2724	else
<>	144:ef7eb2e8f9f7	2725	{
<>	144:ef7eb2e8f9f7	2726	if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
<>	144:ef7eb2e8f9f7	2727	{
<>	144:ef7eb2e8f9f7	2728	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2729
<>	144:ef7eb2e8f9f7	2730	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2731	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2732
<>	144:ef7eb2e8f9f7	2733	HAL_I2C_MemTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	2734	}
<>	144:ef7eb2e8f9f7	2735	else
<>	144:ef7eb2e8f9f7	2736	{
<>	144:ef7eb2e8f9f7	2737	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2738
<>	144:ef7eb2e8f9f7	2739	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2740	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2741
<>	144:ef7eb2e8f9f7	2742	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	2743	}
<>	144:ef7eb2e8f9f7	2744	}
<>	144:ef7eb2e8f9f7	2745	}
<>	144:ef7eb2e8f9f7	2746	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	2747	{
<>	144:ef7eb2e8f9f7	2748	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	2749	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	2750
<>	144:ef7eb2e8f9f7	2751	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2752	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2753
<>	144:ef7eb2e8f9f7	2754	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	2755	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	2756	}
<>	144:ef7eb2e8f9f7	2757
<>	144:ef7eb2e8f9f7	2758	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2759	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2760
<>	144:ef7eb2e8f9f7	2761	return HAL_OK;
<>	144:ef7eb2e8f9f7	2762	}
<>	144:ef7eb2e8f9f7	2763
<>	144:ef7eb2e8f9f7	2764	/**
<>	144:ef7eb2e8f9f7	2765	* @brief Handle Interrupt Flags Master Receive Mode
<>	144:ef7eb2e8f9f7	2766	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2767	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2768	* @retval HAL status
<>	144:ef7eb2e8f9f7	2769	*/
<>	144:ef7eb2e8f9f7	2770	static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2771	{
<>	144:ef7eb2e8f9f7	2772	uint16_t DevAddress;
<>	144:ef7eb2e8f9f7	2773
<>	144:ef7eb2e8f9f7	2774	/* Process Locked */
<>	144:ef7eb2e8f9f7	2775	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2776
<>	144:ef7eb2e8f9f7	2777	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	144:ef7eb2e8f9f7	2778	{
<>	144:ef7eb2e8f9f7	2779	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	2780	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	2781	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2782	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2783	}
<>	144:ef7eb2e8f9f7	2784	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
<>	144:ef7eb2e8f9f7	2785	{
<>	144:ef7eb2e8f9f7	2786	if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
<>	144:ef7eb2e8f9f7	2787	{
<>	144:ef7eb2e8f9f7	2788	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
<>	144:ef7eb2e8f9f7	2789
<>	144:ef7eb2e8f9f7	2790	if(hi2c->XferCount > 255)
<>	144:ef7eb2e8f9f7	2791	{
<>	144:ef7eb2e8f9f7	2792	I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	2793	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	2794	}
<>	144:ef7eb2e8f9f7	2795	else
<>	144:ef7eb2e8f9f7	2796	{
<>	144:ef7eb2e8f9f7	2797	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	2798	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2799	}
<>	144:ef7eb2e8f9f7	2800	}
<>	144:ef7eb2e8f9f7	2801	else
<>	144:ef7eb2e8f9f7	2802	{
<>	144:ef7eb2e8f9f7	2803	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2804	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2805
<>	144:ef7eb2e8f9f7	2806	/* Wrong size Status regarding TCR flag event */
<>	144:ef7eb2e8f9f7	2807	hi2c->ErrorCode \|= HAL_I2C_ERROR_SIZE;
<>	144:ef7eb2e8f9f7	2808	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	2809	}
<>	144:ef7eb2e8f9f7	2810	}
<>	144:ef7eb2e8f9f7	2811	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
<>	144:ef7eb2e8f9f7	2812	{
<>	144:ef7eb2e8f9f7	2813	if(hi2c->XferCount == 0)
<>	144:ef7eb2e8f9f7	2814	{
<>	144:ef7eb2e8f9f7	2815	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2816	hi2c->Instance->CR2 \|= I2C_CR2_STOP;
<>	144:ef7eb2e8f9f7	2817	}
<>	144:ef7eb2e8f9f7	2818	else
<>	144:ef7eb2e8f9f7	2819	{
<>	144:ef7eb2e8f9f7	2820	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2821	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2822
<>	144:ef7eb2e8f9f7	2823	/* Wrong size Status regarding TCR flag event */
<>	144:ef7eb2e8f9f7	2824	hi2c->ErrorCode \|= HAL_I2C_ERROR_SIZE;
<>	144:ef7eb2e8f9f7	2825	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	2826	}
<>	144:ef7eb2e8f9f7	2827	}
<>	144:ef7eb2e8f9f7	2828	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<>	144:ef7eb2e8f9f7	2829	{
<>	144:ef7eb2e8f9f7	2830	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	2831	{
<>	144:ef7eb2e8f9f7	2832	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	2833	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	2834
<>	144:ef7eb2e8f9f7	2835	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	2836	}
<>	144:ef7eb2e8f9f7	2837	/* Disable ERR, TC, STOP, NACK, RXI interrupts */
<>	144:ef7eb2e8f9f7	2838	__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_RXI );
<>	144:ef7eb2e8f9f7	2839
<>	144:ef7eb2e8f9f7	2840	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	2841	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	2842
<>	144:ef7eb2e8f9f7	2843	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	2844	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	2845
<>	144:ef7eb2e8f9f7	2846	/* Call the correct callback to inform upper layer */
<>	144:ef7eb2e8f9f7	2847	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2848	{
<>	144:ef7eb2e8f9f7	2849	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2850
<>	144:ef7eb2e8f9f7	2851	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2852	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2853
<>	144:ef7eb2e8f9f7	2854	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	2855	}
<>	144:ef7eb2e8f9f7	2856	else
<>	144:ef7eb2e8f9f7	2857	{
<>	144:ef7eb2e8f9f7	2858	if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
<>	144:ef7eb2e8f9f7	2859	{
<>	144:ef7eb2e8f9f7	2860	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2861
<>	144:ef7eb2e8f9f7	2862	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2863	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2864
<>	144:ef7eb2e8f9f7	2865	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	2866	}
<>	144:ef7eb2e8f9f7	2867	else
<>	144:ef7eb2e8f9f7	2868	{
<>	144:ef7eb2e8f9f7	2869	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2870
<>	144:ef7eb2e8f9f7	2871	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2872	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2873
<>	144:ef7eb2e8f9f7	2874	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	2875	}
<>	144:ef7eb2e8f9f7	2876	}
<>	144:ef7eb2e8f9f7	2877	}
<>	144:ef7eb2e8f9f7	2878	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	2879	{
<>	144:ef7eb2e8f9f7	2880	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	2881	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	2882
<>	144:ef7eb2e8f9f7	2883	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2884	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2885
<>	144:ef7eb2e8f9f7	2886	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	2887	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	2888	}
<>	144:ef7eb2e8f9f7	2889
<>	144:ef7eb2e8f9f7	2890	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2891	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2892
<>	144:ef7eb2e8f9f7	2893	return HAL_OK;
<>	144:ef7eb2e8f9f7	2894
<>	144:ef7eb2e8f9f7	2895	}
<>	144:ef7eb2e8f9f7	2896
<>	144:ef7eb2e8f9f7	2897	/**
<>	144:ef7eb2e8f9f7	2898	* @brief Handle Interrupt Flags Slave Transmit Mode
<>	144:ef7eb2e8f9f7	2899	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2900	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2901	* @retval HAL status
<>	144:ef7eb2e8f9f7	2902	*/
<>	144:ef7eb2e8f9f7	2903	static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2904	{
<>	144:ef7eb2e8f9f7	2905	/* Process locked */
<>	144:ef7eb2e8f9f7	2906	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2907
<>	144:ef7eb2e8f9f7	2908	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
<>	144:ef7eb2e8f9f7	2909	{
<>	144:ef7eb2e8f9f7	2910	/* Check that I2C transfer finished */
<>	144:ef7eb2e8f9f7	2911	/* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */
<>	144:ef7eb2e8f9f7	2912	/* Mean XferCount == 0*/
<>	144:ef7eb2e8f9f7	2913	/* So clear Flag NACKF only */
<>	144:ef7eb2e8f9f7	2914	if(hi2c->XferCount == 0)
<>	144:ef7eb2e8f9f7	2915	{
<>	144:ef7eb2e8f9f7	2916	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	2917	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	2918
<>	144:ef7eb2e8f9f7	2919	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2920	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2921	}
<>	144:ef7eb2e8f9f7	2922	else
<>	144:ef7eb2e8f9f7	2923	{
<>	144:ef7eb2e8f9f7	2924	/* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/
<>	144:ef7eb2e8f9f7	2925	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	2926	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	2927
<>	144:ef7eb2e8f9f7	2928	/* Set ErrorCode corresponding to a Non-Acknowledge */
<>	144:ef7eb2e8f9f7	2929	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	2930
<>	144:ef7eb2e8f9f7	2931	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2932	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2933
<>	144:ef7eb2e8f9f7	2934	/* Call the Error callback to prevent upper layer */
<>	144:ef7eb2e8f9f7	2935	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	2936	}
<>	144:ef7eb2e8f9f7	2937	}
<>	144:ef7eb2e8f9f7	2938	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
<>	144:ef7eb2e8f9f7	2939	{
<>	144:ef7eb2e8f9f7	2940	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2941	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	2942	}
<>	144:ef7eb2e8f9f7	2943	/* Check first if STOPF is set */
<>	144:ef7eb2e8f9f7	2944	/* to prevent a Write Data in TX buffer */
<>	144:ef7eb2e8f9f7	2945	/* which is stuck in TXDR until next */
<>	144:ef7eb2e8f9f7	2946	/* communication with Master */
<>	144:ef7eb2e8f9f7	2947	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<>	144:ef7eb2e8f9f7	2948	{
<>	144:ef7eb2e8f9f7	2949	/* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupts */
<>	144:ef7eb2e8f9f7	2950	__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI );
<>	144:ef7eb2e8f9f7	2951
<>	144:ef7eb2e8f9f7	2952	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	2953	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	2954
<>	144:ef7eb2e8f9f7	2955	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	2956	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	2957
<>	144:ef7eb2e8f9f7	2958	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2959
<>	144:ef7eb2e8f9f7	2960	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2961	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2962
<>	144:ef7eb2e8f9f7	2963	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	2964	}
<>	144:ef7eb2e8f9f7	2965	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
<>	144:ef7eb2e8f9f7	2966	{
<>	144:ef7eb2e8f9f7	2967	/* Write data to TXDR only if XferCount not reach "0" */
<>	144:ef7eb2e8f9f7	2968	/* A TXIS flag can be set, during STOP treatment */
<>	144:ef7eb2e8f9f7	2969	if(hi2c->XferCount > 0)
<>	144:ef7eb2e8f9f7	2970	{
<>	144:ef7eb2e8f9f7	2971	/* Write data to TXDR */
<>	144:ef7eb2e8f9f7	2972	hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	2973	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2974	}
<>	144:ef7eb2e8f9f7	2975	}
<>	144:ef7eb2e8f9f7	2976
<>	144:ef7eb2e8f9f7	2977	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2978	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2979
<>	144:ef7eb2e8f9f7	2980	return HAL_OK;
<>	144:ef7eb2e8f9f7	2981	}
<>	144:ef7eb2e8f9f7	2982
<>	144:ef7eb2e8f9f7	2983	/**
<>	144:ef7eb2e8f9f7	2984	* @brief Handle Interrupt Flags Slave Receive Mode
<>	144:ef7eb2e8f9f7	2985	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2986	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2987	* @retval HAL status
<>	144:ef7eb2e8f9f7	2988	*/
<>	144:ef7eb2e8f9f7	2989	static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	2990	{
<>	144:ef7eb2e8f9f7	2991	/* Process Locked */
<>	144:ef7eb2e8f9f7	2992	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2993
<>	144:ef7eb2e8f9f7	2994	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
<>	144:ef7eb2e8f9f7	2995	{
<>	144:ef7eb2e8f9f7	2996	/* Clear NACK Flag */
<>	144:ef7eb2e8f9f7	2997	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	2998
<>	144:ef7eb2e8f9f7	2999	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3000	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3001
<>	144:ef7eb2e8f9f7	3002	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3003	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3004	}
<>	144:ef7eb2e8f9f7	3005	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
<>	144:ef7eb2e8f9f7	3006	{
<>	144:ef7eb2e8f9f7	3007	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3008	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3009	}
<>	144:ef7eb2e8f9f7	3010	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	144:ef7eb2e8f9f7	3011	{
<>	144:ef7eb2e8f9f7	3012	/* Read data from RXDR */
<>	144:ef7eb2e8f9f7	3013	(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<>	144:ef7eb2e8f9f7	3014	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	3015	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3016	}
<>	144:ef7eb2e8f9f7	3017	else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<>	144:ef7eb2e8f9f7	3018	{
<>	144:ef7eb2e8f9f7	3019	/* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupts */
<>	144:ef7eb2e8f9f7	3020	__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI \| I2C_IT_TCI\| I2C_IT_STOPI\| I2C_IT_NACKI \| I2C_IT_ADDRI \| I2C_IT_RXI \| I2C_IT_TXI );
<>	144:ef7eb2e8f9f7	3021
<>	144:ef7eb2e8f9f7	3022	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	3023	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	3024
<>	144:ef7eb2e8f9f7	3025	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3026	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3027
<>	144:ef7eb2e8f9f7	3028	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3029
<>	144:ef7eb2e8f9f7	3030	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3031	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3032
<>	144:ef7eb2e8f9f7	3033	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3034	}
<>	144:ef7eb2e8f9f7	3035
<>	144:ef7eb2e8f9f7	3036	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3037	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3038
<>	144:ef7eb2e8f9f7	3039	return HAL_OK;
<>	144:ef7eb2e8f9f7	3040	}
<>	144:ef7eb2e8f9f7	3041
<>	144:ef7eb2e8f9f7	3042	/**
<>	144:ef7eb2e8f9f7	3043	* @brief Master sends target device address followed by internal memory address for write request.
<>	144:ef7eb2e8f9f7	3044	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3045	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3046	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	3047	* @param MemAddress: Internal memory address
<>	144:ef7eb2e8f9f7	3048	* @param MemAddSize: Size of internal memory address
<>	144:ef7eb2e8f9f7	3049	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	3050	* @retval HAL status
<>	144:ef7eb2e8f9f7	3051	*/
<>	144:ef7eb2e8f9f7	3052	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	3053	{
<>	144:ef7eb2e8f9f7	3054	I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	3055
<>	144:ef7eb2e8f9f7	3056	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	3057	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	3058	{
<>	144:ef7eb2e8f9f7	3059	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3060	{
<>	144:ef7eb2e8f9f7	3061	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3062	}
<>	144:ef7eb2e8f9f7	3063	else
<>	144:ef7eb2e8f9f7	3064	{
<>	144:ef7eb2e8f9f7	3065	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3066	}
<>	144:ef7eb2e8f9f7	3067	}
<>	144:ef7eb2e8f9f7	3068
<>	144:ef7eb2e8f9f7	3069	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	3070	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	3071	{
<>	144:ef7eb2e8f9f7	3072	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	3073	hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	3074	}
<>	144:ef7eb2e8f9f7	3075	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	3076	else
<>	144:ef7eb2e8f9f7	3077	{
<>	144:ef7eb2e8f9f7	3078	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	3079	hi2c->Instance->TXDR = __I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	3080
<>	144:ef7eb2e8f9f7	3081	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	3082	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	3083	{
<>	144:ef7eb2e8f9f7	3084	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3085	{
<>	144:ef7eb2e8f9f7	3086	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3087	}
<>	144:ef7eb2e8f9f7	3088	else
<>	144:ef7eb2e8f9f7	3089	{
<>	144:ef7eb2e8f9f7	3090	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3091	}
<>	144:ef7eb2e8f9f7	3092	}
<>	144:ef7eb2e8f9f7	3093
<>	144:ef7eb2e8f9f7	3094	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	3095	hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	3096	}
<>	144:ef7eb2e8f9f7	3097
<>	144:ef7eb2e8f9f7	3098	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	3099	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	3100	{
<>	144:ef7eb2e8f9f7	3101	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3102	}
<>	144:ef7eb2e8f9f7	3103
<>	144:ef7eb2e8f9f7	3104	return HAL_OK;
<>	144:ef7eb2e8f9f7	3105	}
<>	144:ef7eb2e8f9f7	3106
<>	144:ef7eb2e8f9f7	3107	/**
<>	144:ef7eb2e8f9f7	3108	* @brief Master sends target device address followed by internal memory address for read request.
<>	144:ef7eb2e8f9f7	3109	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3110	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3111	* @param DevAddress: Target device address
<>	144:ef7eb2e8f9f7	3112	* @param MemAddress: Internal memory address
<>	144:ef7eb2e8f9f7	3113	* @param MemAddSize: Size of internal memory address
<>	144:ef7eb2e8f9f7	3114	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	3115	* @retval HAL status
<>	144:ef7eb2e8f9f7	3116	*/
<>	144:ef7eb2e8f9f7	3117	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	3118	{
<>	144:ef7eb2e8f9f7	3119	I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
<>	144:ef7eb2e8f9f7	3120
<>	144:ef7eb2e8f9f7	3121	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	3122	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	3123	{
<>	144:ef7eb2e8f9f7	3124	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3125	{
<>	144:ef7eb2e8f9f7	3126	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3127	}
<>	144:ef7eb2e8f9f7	3128	else
<>	144:ef7eb2e8f9f7	3129	{
<>	144:ef7eb2e8f9f7	3130	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3131	}
<>	144:ef7eb2e8f9f7	3132	}
<>	144:ef7eb2e8f9f7	3133
<>	144:ef7eb2e8f9f7	3134	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	3135	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	3136	{
<>	144:ef7eb2e8f9f7	3137	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	3138	hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	3139	}
<>	144:ef7eb2e8f9f7	3140	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	3141	else
<>	144:ef7eb2e8f9f7	3142	{
<>	144:ef7eb2e8f9f7	3143	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	3144	hi2c->Instance->TXDR = __I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	3145
<>	144:ef7eb2e8f9f7	3146	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	3147	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	3148	{
<>	144:ef7eb2e8f9f7	3149	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3150	{
<>	144:ef7eb2e8f9f7	3151	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3152	}
<>	144:ef7eb2e8f9f7	3153	else
<>	144:ef7eb2e8f9f7	3154	{
<>	144:ef7eb2e8f9f7	3155	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3156	}
<>	144:ef7eb2e8f9f7	3157	}
<>	144:ef7eb2e8f9f7	3158
<>	144:ef7eb2e8f9f7	3159	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	3160	hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	3161	}
<>	144:ef7eb2e8f9f7	3162
<>	144:ef7eb2e8f9f7	3163	/* Wait until TC flag is set */
<>	144:ef7eb2e8f9f7	3164	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	3165	{
<>	144:ef7eb2e8f9f7	3166	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3167	}
<>	144:ef7eb2e8f9f7	3168
<>	144:ef7eb2e8f9f7	3169	return HAL_OK;
<>	144:ef7eb2e8f9f7	3170	}
<>	144:ef7eb2e8f9f7	3171
<>	144:ef7eb2e8f9f7	3172	/**
<>	144:ef7eb2e8f9f7	3173	* @brief DMA I2C master transmit process complete callback.
<>	144:ef7eb2e8f9f7	3174	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	3175	* @retval None
<>	144:ef7eb2e8f9f7	3176	*/
<>	144:ef7eb2e8f9f7	3177	static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	3178	{
<>	144:ef7eb2e8f9f7	3179	uint16_t DevAddress;
<>	144:ef7eb2e8f9f7	3180	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	3181
<>	144:ef7eb2e8f9f7	3182	/* Check if last DMA request was done with RELOAD */
<>	144:ef7eb2e8f9f7	3183	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	3184	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	3185	{
<>	144:ef7eb2e8f9f7	3186	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	3187	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
<>	144:ef7eb2e8f9f7	3188	{
<>	144:ef7eb2e8f9f7	3189	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3190	}
<>	144:ef7eb2e8f9f7	3191
<>	144:ef7eb2e8f9f7	3192	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	3193	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	3194
<>	144:ef7eb2e8f9f7	3195	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3196	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3197	{
<>	144:ef7eb2e8f9f7	3198	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3199	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3200	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3201	{
<>	144:ef7eb2e8f9f7	3202	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3203	{
<>	144:ef7eb2e8f9f7	3204	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3205	}
<>	144:ef7eb2e8f9f7	3206	else
<>	144:ef7eb2e8f9f7	3207	{
<>	144:ef7eb2e8f9f7	3208	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3209	}
<>	144:ef7eb2e8f9f7	3210	}
<>	144:ef7eb2e8f9f7	3211
<>	144:ef7eb2e8f9f7	3212	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3213	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3214
<>	144:ef7eb2e8f9f7	3215	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3216	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3217
<>	144:ef7eb2e8f9f7	3218	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3219
<>	144:ef7eb2e8f9f7	3220	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3221	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3222	}
<>	144:ef7eb2e8f9f7	3223	else
<>	144:ef7eb2e8f9f7	3224	{
<>	144:ef7eb2e8f9f7	3225	hi2c->pBuffPtr += hi2c->XferSize;
<>	144:ef7eb2e8f9f7	3226	hi2c->XferCount -= hi2c->XferSize;
<>	144:ef7eb2e8f9f7	3227	if(hi2c->XferCount > 255)
<>	144:ef7eb2e8f9f7	3228	{
<>	144:ef7eb2e8f9f7	3229	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	3230	}
<>	144:ef7eb2e8f9f7	3231	else
<>	144:ef7eb2e8f9f7	3232	{
<>	144:ef7eb2e8f9f7	3233	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3234	}
<>	144:ef7eb2e8f9f7	3235
<>	144:ef7eb2e8f9f7	3236	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
<>	144:ef7eb2e8f9f7	3237
<>	144:ef7eb2e8f9f7	3238	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3239	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	3240
<>	144:ef7eb2e8f9f7	3241	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	3242	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	3243	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	3244	{
<>	144:ef7eb2e8f9f7	3245	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3246	}
<>	144:ef7eb2e8f9f7	3247	else
<>	144:ef7eb2e8f9f7	3248	{
<>	144:ef7eb2e8f9f7	3249	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3250	}
<>	144:ef7eb2e8f9f7	3251
<>	144:ef7eb2e8f9f7	3252	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	3253	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
<>	144:ef7eb2e8f9f7	3254	{
<>	144:ef7eb2e8f9f7	3255	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3256	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3257	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3258	{
<>	144:ef7eb2e8f9f7	3259	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3260	{
<>	144:ef7eb2e8f9f7	3261	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3262	}
<>	144:ef7eb2e8f9f7	3263	else
<>	144:ef7eb2e8f9f7	3264	{
<>	144:ef7eb2e8f9f7	3265	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3266	}
<>	144:ef7eb2e8f9f7	3267	}
<>	144:ef7eb2e8f9f7	3268
<>	144:ef7eb2e8f9f7	3269	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3270	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3271
<>	144:ef7eb2e8f9f7	3272	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3273	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3274
<>	144:ef7eb2e8f9f7	3275	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3276
<>	144:ef7eb2e8f9f7	3277	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3278	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3279	}
<>	144:ef7eb2e8f9f7	3280	else
<>	144:ef7eb2e8f9f7	3281	{
<>	144:ef7eb2e8f9f7	3282	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	3283	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	3284	}
<>	144:ef7eb2e8f9f7	3285	}
<>	144:ef7eb2e8f9f7	3286	}
<>	144:ef7eb2e8f9f7	3287	else
<>	144:ef7eb2e8f9f7	3288	{
<>	144:ef7eb2e8f9f7	3289	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3290	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3291	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3292	{
<>	144:ef7eb2e8f9f7	3293	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3294	{
<>	144:ef7eb2e8f9f7	3295	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3296	}
<>	144:ef7eb2e8f9f7	3297	else
<>	144:ef7eb2e8f9f7	3298	{
<>	144:ef7eb2e8f9f7	3299	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3300	}
<>	144:ef7eb2e8f9f7	3301	}
<>	144:ef7eb2e8f9f7	3302
<>	144:ef7eb2e8f9f7	3303	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3304	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3305
<>	144:ef7eb2e8f9f7	3306	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3307	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3308
<>	144:ef7eb2e8f9f7	3309	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	3310	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	3311
<>	144:ef7eb2e8f9f7	3312	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3313
<>	144:ef7eb2e8f9f7	3314	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3315
<>	144:ef7eb2e8f9f7	3316	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3317	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3318	{
<>	144:ef7eb2e8f9f7	3319	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3320	}
<>	144:ef7eb2e8f9f7	3321	else
<>	144:ef7eb2e8f9f7	3322	{
<>	144:ef7eb2e8f9f7	3323	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3324	}
<>	144:ef7eb2e8f9f7	3325	}
<>	144:ef7eb2e8f9f7	3326	}
<>	144:ef7eb2e8f9f7	3327
<>	144:ef7eb2e8f9f7	3328	/**
<>	144:ef7eb2e8f9f7	3329	* @brief DMA I2C slave transmit process complete callback.
<>	144:ef7eb2e8f9f7	3330	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	3331	* @retval None
<>	144:ef7eb2e8f9f7	3332	*/
<>	144:ef7eb2e8f9f7	3333	static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	3334	{
<>	144:ef7eb2e8f9f7	3335	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	3336
<>	144:ef7eb2e8f9f7	3337	/* Wait until STOP flag is set */
<>	144:ef7eb2e8f9f7	3338	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3339	{
<>	144:ef7eb2e8f9f7	3340	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3341	{
<>	144:ef7eb2e8f9f7	3342	/* Normal Use case, a AF is generated by master */
<>	144:ef7eb2e8f9f7	3343	/* to inform slave the end of transfer */
<>	144:ef7eb2e8f9f7	3344	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	3345	}
<>	144:ef7eb2e8f9f7	3346	else
<>	144:ef7eb2e8f9f7	3347	{
<>	144:ef7eb2e8f9f7	3348	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3349	}
<>	144:ef7eb2e8f9f7	3350	}
<>	144:ef7eb2e8f9f7	3351
<>	144:ef7eb2e8f9f7	3352	/* Clear STOP flag */
<>	144:ef7eb2e8f9f7	3353	__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3354
<>	144:ef7eb2e8f9f7	3355	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3356	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
<>	144:ef7eb2e8f9f7	3357	{
<>	144:ef7eb2e8f9f7	3358	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3359	}
<>	144:ef7eb2e8f9f7	3360
<>	144:ef7eb2e8f9f7	3361	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	3362	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	3363
<>	144:ef7eb2e8f9f7	3364	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3365
<>	144:ef7eb2e8f9f7	3366	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3367
<>	144:ef7eb2e8f9f7	3368	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3369	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3370	{
<>	144:ef7eb2e8f9f7	3371	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3372	}
<>	144:ef7eb2e8f9f7	3373	else
<>	144:ef7eb2e8f9f7	3374	{
<>	144:ef7eb2e8f9f7	3375	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3376	}
<>	144:ef7eb2e8f9f7	3377	}
<>	144:ef7eb2e8f9f7	3378
<>	144:ef7eb2e8f9f7	3379	/**
<>	144:ef7eb2e8f9f7	3380	* @brief DMA I2C master receive process complete callback
<>	144:ef7eb2e8f9f7	3381	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	3382	* @retval None
<>	144:ef7eb2e8f9f7	3383	*/
<>	144:ef7eb2e8f9f7	3384	static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	3385	{
<>	144:ef7eb2e8f9f7	3386	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	3387	uint16_t DevAddress;
<>	144:ef7eb2e8f9f7	3388
<>	144:ef7eb2e8f9f7	3389	/* Check if last DMA request was done with RELOAD */
<>	144:ef7eb2e8f9f7	3390	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	3391	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	3392	{
<>	144:ef7eb2e8f9f7	3393	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	3394	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
<>	144:ef7eb2e8f9f7	3395	{
<>	144:ef7eb2e8f9f7	3396	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3397	}
<>	144:ef7eb2e8f9f7	3398
<>	144:ef7eb2e8f9f7	3399	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	3400	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	3401
<>	144:ef7eb2e8f9f7	3402	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3403	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3404	{
<>	144:ef7eb2e8f9f7	3405	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3406	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3407	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3408	{
<>	144:ef7eb2e8f9f7	3409	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3410	{
<>	144:ef7eb2e8f9f7	3411	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3412	}
<>	144:ef7eb2e8f9f7	3413	else
<>	144:ef7eb2e8f9f7	3414	{
<>	144:ef7eb2e8f9f7	3415	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3416	}
<>	144:ef7eb2e8f9f7	3417	}
<>	144:ef7eb2e8f9f7	3418
<>	144:ef7eb2e8f9f7	3419	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3420	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3421
<>	144:ef7eb2e8f9f7	3422	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3423	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3424
<>	144:ef7eb2e8f9f7	3425	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3426
<>	144:ef7eb2e8f9f7	3427	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3428	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3429	}
<>	144:ef7eb2e8f9f7	3430	else
<>	144:ef7eb2e8f9f7	3431	{
<>	144:ef7eb2e8f9f7	3432	hi2c->pBuffPtr += hi2c->XferSize;
<>	144:ef7eb2e8f9f7	3433	hi2c->XferCount -= hi2c->XferSize;
<>	144:ef7eb2e8f9f7	3434	if(hi2c->XferCount > 255)
<>	144:ef7eb2e8f9f7	3435	{
<>	144:ef7eb2e8f9f7	3436	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	3437	}
<>	144:ef7eb2e8f9f7	3438	else
<>	144:ef7eb2e8f9f7	3439	{
<>	144:ef7eb2e8f9f7	3440	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3441	}
<>	144:ef7eb2e8f9f7	3442
<>	144:ef7eb2e8f9f7	3443	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
<>	144:ef7eb2e8f9f7	3444
<>	144:ef7eb2e8f9f7	3445	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3446	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	3447
<>	144:ef7eb2e8f9f7	3448	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	3449	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	3450	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	3451	{
<>	144:ef7eb2e8f9f7	3452	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3453	}
<>	144:ef7eb2e8f9f7	3454	else
<>	144:ef7eb2e8f9f7	3455	{
<>	144:ef7eb2e8f9f7	3456	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3457	}
<>	144:ef7eb2e8f9f7	3458
<>	144:ef7eb2e8f9f7	3459	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	3460	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
<>	144:ef7eb2e8f9f7	3461	{
<>	144:ef7eb2e8f9f7	3462	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3463	}
<>	144:ef7eb2e8f9f7	3464
<>	144:ef7eb2e8f9f7	3465	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3466	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3467	{
<>	144:ef7eb2e8f9f7	3468	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3469	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3470	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3471	{
<>	144:ef7eb2e8f9f7	3472	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3473	{
<>	144:ef7eb2e8f9f7	3474	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3475	}
<>	144:ef7eb2e8f9f7	3476	else
<>	144:ef7eb2e8f9f7	3477	{
<>	144:ef7eb2e8f9f7	3478	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3479	}
<>	144:ef7eb2e8f9f7	3480	}
<>	144:ef7eb2e8f9f7	3481
<>	144:ef7eb2e8f9f7	3482	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3483	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3484
<>	144:ef7eb2e8f9f7	3485	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3486	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3487
<>	144:ef7eb2e8f9f7	3488	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3489
<>	144:ef7eb2e8f9f7	3490	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3491
<>	144:ef7eb2e8f9f7	3492	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3493	}
<>	144:ef7eb2e8f9f7	3494	else
<>	144:ef7eb2e8f9f7	3495	{
<>	144:ef7eb2e8f9f7	3496	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	3497	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	3498	}
<>	144:ef7eb2e8f9f7	3499	}
<>	144:ef7eb2e8f9f7	3500	}
<>	144:ef7eb2e8f9f7	3501	else
<>	144:ef7eb2e8f9f7	3502	{
<>	144:ef7eb2e8f9f7	3503	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3504	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3505	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3506	{
<>	144:ef7eb2e8f9f7	3507	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3508	{
<>	144:ef7eb2e8f9f7	3509	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3510	}
<>	144:ef7eb2e8f9f7	3511	else
<>	144:ef7eb2e8f9f7	3512	{
<>	144:ef7eb2e8f9f7	3513	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3514	}
<>	144:ef7eb2e8f9f7	3515	}
<>	144:ef7eb2e8f9f7	3516
<>	144:ef7eb2e8f9f7	3517	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3518	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3519
<>	144:ef7eb2e8f9f7	3520	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3521	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3522
<>	144:ef7eb2e8f9f7	3523	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	3524	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	3525
<>	144:ef7eb2e8f9f7	3526	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3527
<>	144:ef7eb2e8f9f7	3528	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3529
<>	144:ef7eb2e8f9f7	3530	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3531	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3532	{
<>	144:ef7eb2e8f9f7	3533	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3534	}
<>	144:ef7eb2e8f9f7	3535	else
<>	144:ef7eb2e8f9f7	3536	{
<>	144:ef7eb2e8f9f7	3537	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3538	}
<>	144:ef7eb2e8f9f7	3539	}
<>	144:ef7eb2e8f9f7	3540	}
<>	144:ef7eb2e8f9f7	3541
<>	144:ef7eb2e8f9f7	3542	/**
<>	144:ef7eb2e8f9f7	3543	* @brief DMA I2C slave receive process complete callback.
<>	144:ef7eb2e8f9f7	3544	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	3545	* @retval None
<>	144:ef7eb2e8f9f7	3546	*/
<>	144:ef7eb2e8f9f7	3547	static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	3548	{
<>	144:ef7eb2e8f9f7	3549	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	3550
<>	144:ef7eb2e8f9f7	3551	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3552	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3553	{
<>	144:ef7eb2e8f9f7	3554	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3555	{
<>	144:ef7eb2e8f9f7	3556	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3557	}
<>	144:ef7eb2e8f9f7	3558	else
<>	144:ef7eb2e8f9f7	3559	{
<>	144:ef7eb2e8f9f7	3560	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3561	}
<>	144:ef7eb2e8f9f7	3562	}
<>	144:ef7eb2e8f9f7	3563
<>	144:ef7eb2e8f9f7	3564	/* Clear STOPF flag */
<>	144:ef7eb2e8f9f7	3565	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3566
<>	144:ef7eb2e8f9f7	3567	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3568	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
<>	144:ef7eb2e8f9f7	3569	{
<>	144:ef7eb2e8f9f7	3570	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3571	}
<>	144:ef7eb2e8f9f7	3572
<>	144:ef7eb2e8f9f7	3573	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	3574	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	3575
<>	144:ef7eb2e8f9f7	3576	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	3577	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	3578
<>	144:ef7eb2e8f9f7	3579	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3580
<>	144:ef7eb2e8f9f7	3581	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3582
<>	144:ef7eb2e8f9f7	3583	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3584	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3585	{
<>	144:ef7eb2e8f9f7	3586	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3587	}
<>	144:ef7eb2e8f9f7	3588	else
<>	144:ef7eb2e8f9f7	3589	{
<>	144:ef7eb2e8f9f7	3590	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3591	}
<>	144:ef7eb2e8f9f7	3592	}
<>	144:ef7eb2e8f9f7	3593
<>	144:ef7eb2e8f9f7	3594	/**
<>	144:ef7eb2e8f9f7	3595	* @brief DMA I2C Memory Write process complete callback
<>	144:ef7eb2e8f9f7	3596	* @param hdma : DMA handle
<>	144:ef7eb2e8f9f7	3597	* @retval None
<>	144:ef7eb2e8f9f7	3598	*/
<>	144:ef7eb2e8f9f7	3599	static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	3600	{
<>	144:ef7eb2e8f9f7	3601	uint16_t DevAddress;
<>	144:ef7eb2e8f9f7	3602	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	3603
<>	144:ef7eb2e8f9f7	3604	/* Check if last DMA request was done with RELOAD */
<>	144:ef7eb2e8f9f7	3605	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	3606	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	3607	{
<>	144:ef7eb2e8f9f7	3608	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	3609	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
<>	144:ef7eb2e8f9f7	3610	{
<>	144:ef7eb2e8f9f7	3611	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3612	}
<>	144:ef7eb2e8f9f7	3613
<>	144:ef7eb2e8f9f7	3614	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	3615	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	3616
<>	144:ef7eb2e8f9f7	3617	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3618	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3619	{
<>	144:ef7eb2e8f9f7	3620	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3621	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3622	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3623	{
<>	144:ef7eb2e8f9f7	3624	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3625	{
<>	144:ef7eb2e8f9f7	3626	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3627	}
<>	144:ef7eb2e8f9f7	3628	else
<>	144:ef7eb2e8f9f7	3629	{
<>	144:ef7eb2e8f9f7	3630	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3631	}
<>	144:ef7eb2e8f9f7	3632	}
<>	144:ef7eb2e8f9f7	3633
<>	144:ef7eb2e8f9f7	3634	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3635	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3636
<>	144:ef7eb2e8f9f7	3637	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3638	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3639
<>	144:ef7eb2e8f9f7	3640	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3641
<>	144:ef7eb2e8f9f7	3642	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3643	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3644	}
<>	144:ef7eb2e8f9f7	3645	else
<>	144:ef7eb2e8f9f7	3646	{
<>	144:ef7eb2e8f9f7	3647	hi2c->pBuffPtr += hi2c->XferSize;
<>	144:ef7eb2e8f9f7	3648	hi2c->XferCount -= hi2c->XferSize;
<>	144:ef7eb2e8f9f7	3649	if(hi2c->XferCount > 255)
<>	144:ef7eb2e8f9f7	3650	{
<>	144:ef7eb2e8f9f7	3651	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	3652	}
<>	144:ef7eb2e8f9f7	3653	else
<>	144:ef7eb2e8f9f7	3654	{
<>	144:ef7eb2e8f9f7	3655	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3656	}
<>	144:ef7eb2e8f9f7	3657
<>	144:ef7eb2e8f9f7	3658	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
<>	144:ef7eb2e8f9f7	3659
<>	144:ef7eb2e8f9f7	3660	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3661	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	3662
<>	144:ef7eb2e8f9f7	3663	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	3664	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	3665	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	3666	{
<>	144:ef7eb2e8f9f7	3667	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3668	}
<>	144:ef7eb2e8f9f7	3669	else
<>	144:ef7eb2e8f9f7	3670	{
<>	144:ef7eb2e8f9f7	3671	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3672	}
<>	144:ef7eb2e8f9f7	3673
<>	144:ef7eb2e8f9f7	3674	/* Wait until TXIS flag is set */
<>	144:ef7eb2e8f9f7	3675	if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
<>	144:ef7eb2e8f9f7	3676	{
<>	144:ef7eb2e8f9f7	3677	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3678	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3679	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3680	{
<>	144:ef7eb2e8f9f7	3681	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3682	{
<>	144:ef7eb2e8f9f7	3683	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3684	}
<>	144:ef7eb2e8f9f7	3685	else
<>	144:ef7eb2e8f9f7	3686	{
<>	144:ef7eb2e8f9f7	3687	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3688	}
<>	144:ef7eb2e8f9f7	3689	}
<>	144:ef7eb2e8f9f7	3690
<>	144:ef7eb2e8f9f7	3691	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3692	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3693
<>	144:ef7eb2e8f9f7	3694	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3695	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3696
<>	144:ef7eb2e8f9f7	3697	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3698
<>	144:ef7eb2e8f9f7	3699	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3700	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3701	}
<>	144:ef7eb2e8f9f7	3702	else
<>	144:ef7eb2e8f9f7	3703	{
<>	144:ef7eb2e8f9f7	3704	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	3705	hi2c->Instance->CR1 \|= I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	3706	}
<>	144:ef7eb2e8f9f7	3707	}
<>	144:ef7eb2e8f9f7	3708	}
<>	144:ef7eb2e8f9f7	3709	else
<>	144:ef7eb2e8f9f7	3710	{
<>	144:ef7eb2e8f9f7	3711	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3712	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3713	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3714	{
<>	144:ef7eb2e8f9f7	3715	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3716	{
<>	144:ef7eb2e8f9f7	3717	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3718	}
<>	144:ef7eb2e8f9f7	3719	else
<>	144:ef7eb2e8f9f7	3720	{
<>	144:ef7eb2e8f9f7	3721	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3722	}
<>	144:ef7eb2e8f9f7	3723	}
<>	144:ef7eb2e8f9f7	3724
<>	144:ef7eb2e8f9f7	3725	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3726	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3727
<>	144:ef7eb2e8f9f7	3728	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3729	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3730
<>	144:ef7eb2e8f9f7	3731	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	3732	hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
<>	144:ef7eb2e8f9f7	3733
<>	144:ef7eb2e8f9f7	3734	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3735
<>	144:ef7eb2e8f9f7	3736	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3737
<>	144:ef7eb2e8f9f7	3738	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3739	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3740	{
<>	144:ef7eb2e8f9f7	3741	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3742	}
<>	144:ef7eb2e8f9f7	3743	else
<>	144:ef7eb2e8f9f7	3744	{
<>	144:ef7eb2e8f9f7	3745	HAL_I2C_MemTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3746	}
<>	144:ef7eb2e8f9f7	3747	}
<>	144:ef7eb2e8f9f7	3748	}
<>	144:ef7eb2e8f9f7	3749
<>	144:ef7eb2e8f9f7	3750	/**
<>	144:ef7eb2e8f9f7	3751	* @brief DMA I2C Memory Read process complete callback
<>	144:ef7eb2e8f9f7	3752	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	3753	* @retval None
<>	144:ef7eb2e8f9f7	3754	*/
<>	144:ef7eb2e8f9f7	3755	static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	3756	{
<>	144:ef7eb2e8f9f7	3757	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	3758	uint16_t DevAddress;
<>	144:ef7eb2e8f9f7	3759
<>	144:ef7eb2e8f9f7	3760	/* Check if last DMA request was done with RELOAD */
<>	144:ef7eb2e8f9f7	3761	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	3762	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	3763	{
<>	144:ef7eb2e8f9f7	3764	/* Wait until TCR flag is set */
<>	144:ef7eb2e8f9f7	3765	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
<>	144:ef7eb2e8f9f7	3766	{
<>	144:ef7eb2e8f9f7	3767	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3768	}
<>	144:ef7eb2e8f9f7	3769
<>	144:ef7eb2e8f9f7	3770	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	3771	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	3772
<>	144:ef7eb2e8f9f7	3773	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3774	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3775	{
<>	144:ef7eb2e8f9f7	3776	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3777	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3778	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3779	{
<>	144:ef7eb2e8f9f7	3780	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3781	{
<>	144:ef7eb2e8f9f7	3782	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3783	}
<>	144:ef7eb2e8f9f7	3784	else
<>	144:ef7eb2e8f9f7	3785	{
<>	144:ef7eb2e8f9f7	3786	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3787	}
<>	144:ef7eb2e8f9f7	3788	}
<>	144:ef7eb2e8f9f7	3789
<>	144:ef7eb2e8f9f7	3790	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3791	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3792
<>	144:ef7eb2e8f9f7	3793	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3794	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3795
<>	144:ef7eb2e8f9f7	3796	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3797
<>	144:ef7eb2e8f9f7	3798	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3799	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3800	}
<>	144:ef7eb2e8f9f7	3801	else
<>	144:ef7eb2e8f9f7	3802	{
<>	144:ef7eb2e8f9f7	3803	hi2c->pBuffPtr += hi2c->XferSize;
<>	144:ef7eb2e8f9f7	3804	hi2c->XferCount -= hi2c->XferSize;
<>	144:ef7eb2e8f9f7	3805	if(hi2c->XferCount > 255)
<>	144:ef7eb2e8f9f7	3806	{
<>	144:ef7eb2e8f9f7	3807	hi2c->XferSize = 255;
<>	144:ef7eb2e8f9f7	3808	}
<>	144:ef7eb2e8f9f7	3809	else
<>	144:ef7eb2e8f9f7	3810	{
<>	144:ef7eb2e8f9f7	3811	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3812	}
<>	144:ef7eb2e8f9f7	3813
<>	144:ef7eb2e8f9f7	3814	DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
<>	144:ef7eb2e8f9f7	3815
<>	144:ef7eb2e8f9f7	3816	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	3817	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	3818
<>	144:ef7eb2e8f9f7	3819	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	3820	/* Set NBYTES to write and reload if size > 255 */
<>	144:ef7eb2e8f9f7	3821	if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
<>	144:ef7eb2e8f9f7	3822	{
<>	144:ef7eb2e8f9f7	3823	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3824	}
<>	144:ef7eb2e8f9f7	3825	else
<>	144:ef7eb2e8f9f7	3826	{
<>	144:ef7eb2e8f9f7	3827	I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<>	144:ef7eb2e8f9f7	3828	}
<>	144:ef7eb2e8f9f7	3829
<>	144:ef7eb2e8f9f7	3830	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	3831	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
<>	144:ef7eb2e8f9f7	3832	{
<>	144:ef7eb2e8f9f7	3833	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3834	}
<>	144:ef7eb2e8f9f7	3835
<>	144:ef7eb2e8f9f7	3836	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3837	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3838	{
<>	144:ef7eb2e8f9f7	3839	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3840	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3841	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3842	{
<>	144:ef7eb2e8f9f7	3843	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3844	{
<>	144:ef7eb2e8f9f7	3845	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3846	}
<>	144:ef7eb2e8f9f7	3847	else
<>	144:ef7eb2e8f9f7	3848	{
<>	144:ef7eb2e8f9f7	3849	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3850	}
<>	144:ef7eb2e8f9f7	3851	}
<>	144:ef7eb2e8f9f7	3852
<>	144:ef7eb2e8f9f7	3853	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3854	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3855
<>	144:ef7eb2e8f9f7	3856	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3857	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3858
<>	144:ef7eb2e8f9f7	3859	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3860
<>	144:ef7eb2e8f9f7	3861	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3862	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3863	}
<>	144:ef7eb2e8f9f7	3864	else
<>	144:ef7eb2e8f9f7	3865	{
<>	144:ef7eb2e8f9f7	3866	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	3867	hi2c->Instance->CR1 \|= I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	3868	}
<>	144:ef7eb2e8f9f7	3869	}
<>	144:ef7eb2e8f9f7	3870	}
<>	144:ef7eb2e8f9f7	3871	else
<>	144:ef7eb2e8f9f7	3872	{
<>	144:ef7eb2e8f9f7	3873	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<>	144:ef7eb2e8f9f7	3874	/* Wait until STOPF flag is reset */
<>	144:ef7eb2e8f9f7	3875	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
<>	144:ef7eb2e8f9f7	3876	{
<>	144:ef7eb2e8f9f7	3877	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3878	{
<>	144:ef7eb2e8f9f7	3879	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3880	}
<>	144:ef7eb2e8f9f7	3881	else
<>	144:ef7eb2e8f9f7	3882	{
<>	144:ef7eb2e8f9f7	3883	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	3884	}
<>	144:ef7eb2e8f9f7	3885	}
<>	144:ef7eb2e8f9f7	3886
<>	144:ef7eb2e8f9f7	3887	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	3888	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	3889
<>	144:ef7eb2e8f9f7	3890	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	3891	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	3892
<>	144:ef7eb2e8f9f7	3893	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	3894	hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
<>	144:ef7eb2e8f9f7	3895
<>	144:ef7eb2e8f9f7	3896	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3897
<>	144:ef7eb2e8f9f7	3898	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3899
<>	144:ef7eb2e8f9f7	3900	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	3901	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3902	{
<>	144:ef7eb2e8f9f7	3903	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3904	}
<>	144:ef7eb2e8f9f7	3905	else
<>	144:ef7eb2e8f9f7	3906	{
<>	144:ef7eb2e8f9f7	3907	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3908	}
<>	144:ef7eb2e8f9f7	3909	}
<>	144:ef7eb2e8f9f7	3910	}
<>	144:ef7eb2e8f9f7	3911
<>	144:ef7eb2e8f9f7	3912	/**
<>	144:ef7eb2e8f9f7	3913	* @brief DMA I2C communication error callback.
<>	144:ef7eb2e8f9f7	3914	* @param hdma : DMA handle
<>	144:ef7eb2e8f9f7	3915	* @retval None
<>	144:ef7eb2e8f9f7	3916	*/
<>	144:ef7eb2e8f9f7	3917	static void I2C_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	3918	{
<>	144:ef7eb2e8f9f7	3919	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	3920
<>	144:ef7eb2e8f9f7	3921	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	3922	hi2c->Instance->CR2 \|= I2C_CR2_NACK;
<>	144:ef7eb2e8f9f7	3923
<>	144:ef7eb2e8f9f7	3924	hi2c->XferCount = 0;
<>	144:ef7eb2e8f9f7	3925
<>	144:ef7eb2e8f9f7	3926	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3927
<>	144:ef7eb2e8f9f7	3928	hi2c->ErrorCode \|= HAL_I2C_ERROR_DMA;
<>	144:ef7eb2e8f9f7	3929
<>	144:ef7eb2e8f9f7	3930	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	3931	}
<>	144:ef7eb2e8f9f7	3932
<>	144:ef7eb2e8f9f7	3933	/**
<>	144:ef7eb2e8f9f7	3934	* @brief This function handles I2C Communication Timeout.
<>	144:ef7eb2e8f9f7	3935	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3936	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3937	* @param Flag: specifies the I2C flag to check.
<>	144:ef7eb2e8f9f7	3938	* @param Status: The new Flag status (SET or RESET).
<>	144:ef7eb2e8f9f7	3939	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	3940	* @retval HAL status
<>	144:ef7eb2e8f9f7	3941	*/
<>	144:ef7eb2e8f9f7	3942	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	3943	{
<>	144:ef7eb2e8f9f7	3944	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3945
<>	144:ef7eb2e8f9f7	3946	/* Wait until flag is set */
<>	144:ef7eb2e8f9f7	3947	if(Status == RESET)
<>	144:ef7eb2e8f9f7	3948	{
<>	144:ef7eb2e8f9f7	3949	while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
<>	144:ef7eb2e8f9f7	3950	{
<>	144:ef7eb2e8f9f7	3951	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	3952	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	3953	{
<>	144:ef7eb2e8f9f7	3954	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	3955	{
<>	144:ef7eb2e8f9f7	3956	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3957	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3958	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3959	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3960	}
<>	144:ef7eb2e8f9f7	3961	}
<>	144:ef7eb2e8f9f7	3962	}
<>	144:ef7eb2e8f9f7	3963	}
<>	144:ef7eb2e8f9f7	3964	else
<>	144:ef7eb2e8f9f7	3965	{
<>	144:ef7eb2e8f9f7	3966	while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
<>	144:ef7eb2e8f9f7	3967	{
<>	144:ef7eb2e8f9f7	3968	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	3969	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	3970	{
<>	144:ef7eb2e8f9f7	3971	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	3972	{
<>	144:ef7eb2e8f9f7	3973	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3974	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3975	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3976	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3977	}
<>	144:ef7eb2e8f9f7	3978	}
<>	144:ef7eb2e8f9f7	3979	}
<>	144:ef7eb2e8f9f7	3980	}
<>	144:ef7eb2e8f9f7	3981	return HAL_OK;
<>	144:ef7eb2e8f9f7	3982	}
<>	144:ef7eb2e8f9f7	3983
<>	144:ef7eb2e8f9f7	3984	/**
<>	144:ef7eb2e8f9f7	3985	* @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
<>	144:ef7eb2e8f9f7	3986	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3987	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3988	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	3989	* @retval HAL status
<>	144:ef7eb2e8f9f7	3990	*/
<>	144:ef7eb2e8f9f7	3991	static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	3992	{
<>	144:ef7eb2e8f9f7	3993	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3994
<>	144:ef7eb2e8f9f7	3995	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
<>	144:ef7eb2e8f9f7	3996	{
<>	144:ef7eb2e8f9f7	3997	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	3998	if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	3999	{
<>	144:ef7eb2e8f9f7	4000	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4001	}
<>	144:ef7eb2e8f9f7	4002
<>	144:ef7eb2e8f9f7	4003	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	4004	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	4005	{
<>	144:ef7eb2e8f9f7	4006	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	4007	{
<>	144:ef7eb2e8f9f7	4008	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	4009	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4010
<>	144:ef7eb2e8f9f7	4011	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4012	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4013
<>	144:ef7eb2e8f9f7	4014	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4015	}
<>	144:ef7eb2e8f9f7	4016	}
<>	144:ef7eb2e8f9f7	4017	}
<>	144:ef7eb2e8f9f7	4018	return HAL_OK;
<>	144:ef7eb2e8f9f7	4019	}
<>	144:ef7eb2e8f9f7	4020
<>	144:ef7eb2e8f9f7	4021	/**
<>	144:ef7eb2e8f9f7	4022	* @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
<>	144:ef7eb2e8f9f7	4023	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4024	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	4025	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	4026	* @retval HAL status
<>	144:ef7eb2e8f9f7	4027	*/
<>	144:ef7eb2e8f9f7	4028	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	4029	{
<>	144:ef7eb2e8f9f7	4030	uint32_t tickstart = 0x00;
<>	144:ef7eb2e8f9f7	4031	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	4032
<>	144:ef7eb2e8f9f7	4033	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
<>	144:ef7eb2e8f9f7	4034	{
<>	144:ef7eb2e8f9f7	4035	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	4036	if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	4037	{
<>	144:ef7eb2e8f9f7	4038	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4039	}
<>	144:ef7eb2e8f9f7	4040
<>	144:ef7eb2e8f9f7	4041	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	4042	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	4043	{
<>	144:ef7eb2e8f9f7	4044	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	4045	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4046
<>	144:ef7eb2e8f9f7	4047	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4048	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4049
<>	144:ef7eb2e8f9f7	4050	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4051	}
<>	144:ef7eb2e8f9f7	4052	}
<>	144:ef7eb2e8f9f7	4053	return HAL_OK;
<>	144:ef7eb2e8f9f7	4054	}
<>	144:ef7eb2e8f9f7	4055
<>	144:ef7eb2e8f9f7	4056	/**
<>	144:ef7eb2e8f9f7	4057	* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
<>	144:ef7eb2e8f9f7	4058	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4059	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	4060	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	4061	* @retval HAL status
<>	144:ef7eb2e8f9f7	4062	*/
<>	144:ef7eb2e8f9f7	4063	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	4064	{
<>	144:ef7eb2e8f9f7	4065	uint32_t tickstart = 0x00;
<>	144:ef7eb2e8f9f7	4066	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	4067
<>	144:ef7eb2e8f9f7	4068	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
<>	144:ef7eb2e8f9f7	4069	{
<>	144:ef7eb2e8f9f7	4070	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	4071	if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	4072	{
<>	144:ef7eb2e8f9f7	4073	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4074	}
<>	144:ef7eb2e8f9f7	4075	/* Check if a STOPF is detected */
<>	144:ef7eb2e8f9f7	4076	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<>	144:ef7eb2e8f9f7	4077	{
<>	144:ef7eb2e8f9f7	4078	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	4079	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	4080
<>	144:ef7eb2e8f9f7	4081	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	4082	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	4083
<>	144:ef7eb2e8f9f7	4084	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	4085	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4086
<>	144:ef7eb2e8f9f7	4087	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4088	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4089
<>	144:ef7eb2e8f9f7	4090	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4091	}
<>	144:ef7eb2e8f9f7	4092
<>	144:ef7eb2e8f9f7	4093	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	4094	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	4095	{
<>	144:ef7eb2e8f9f7	4096	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	4097	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4098
<>	144:ef7eb2e8f9f7	4099	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4100	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4101
<>	144:ef7eb2e8f9f7	4102	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4103	}
<>	144:ef7eb2e8f9f7	4104	}
<>	144:ef7eb2e8f9f7	4105	return HAL_OK;
<>	144:ef7eb2e8f9f7	4106	}
<>	144:ef7eb2e8f9f7	4107
<>	144:ef7eb2e8f9f7	4108	/**
<>	144:ef7eb2e8f9f7	4109	* @brief This function handles Acknowledge failed detection during an I2C Communication.
<>	144:ef7eb2e8f9f7	4110	* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4111	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	4112	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	4113	* @retval HAL status
<>	144:ef7eb2e8f9f7	4114	*/
<>	144:ef7eb2e8f9f7	4115	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	4116	{
<>	144:ef7eb2e8f9f7	4117	uint32_t tickstart = 0x00;
<>	144:ef7eb2e8f9f7	4118	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	4119
<>	144:ef7eb2e8f9f7	4120	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	4121	{
<>	144:ef7eb2e8f9f7	4122	/* Generate stop if necessary only in case of I2C peripheral in MASTER mode */
<>	144:ef7eb2e8f9f7	4123	if((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) \|\| (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
<>	144:ef7eb2e8f9f7	4124	\|\| (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
<>	144:ef7eb2e8f9f7	4125	{
<>	144:ef7eb2e8f9f7	4126	/* No need to generate the STOP condition if AUTOEND mode is enabled */
<>	144:ef7eb2e8f9f7	4127	/* Generate the STOP condition only in case of SOFTEND mode is enabled */
<>	144:ef7eb2e8f9f7	4128	if((hi2c->Instance->CR2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE)
<>	144:ef7eb2e8f9f7	4129	{
<>	144:ef7eb2e8f9f7	4130	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4131	hi2c->Instance->CR2 \|= I2C_CR2_STOP;
<>	144:ef7eb2e8f9f7	4132	}
<>	144:ef7eb2e8f9f7	4133	}
<>	144:ef7eb2e8f9f7	4134
<>	144:ef7eb2e8f9f7	4135	/* Wait until STOP Flag is reset */
<>	144:ef7eb2e8f9f7	4136	/* AutoEnd should be initiate after AF */
<>	144:ef7eb2e8f9f7	4137	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
<>	144:ef7eb2e8f9f7	4138	{
<>	144:ef7eb2e8f9f7	4139	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	4140	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	4141	{
<>	144:ef7eb2e8f9f7	4142	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	4143	{
<>	144:ef7eb2e8f9f7	4144	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4145	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4146	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4147	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4148	}
<>	144:ef7eb2e8f9f7	4149	}
<>	144:ef7eb2e8f9f7	4150	}
<>	144:ef7eb2e8f9f7	4151
<>	144:ef7eb2e8f9f7	4152	/* Clear NACKF Flag */
<>	144:ef7eb2e8f9f7	4153	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4154
<>	144:ef7eb2e8f9f7	4155	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	4156	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	4157
<>	144:ef7eb2e8f9f7	4158	/* Flush TX register if not empty */
<>	144:ef7eb2e8f9f7	4159	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
<>	144:ef7eb2e8f9f7	4160	{
<>	144:ef7eb2e8f9f7	4161	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
<>	144:ef7eb2e8f9f7	4162	}
<>	144:ef7eb2e8f9f7	4163	/* Clear Configuration Register 2 */
<>	144:ef7eb2e8f9f7	4164	__I2C_RESET_CR2(hi2c);
<>	144:ef7eb2e8f9f7	4165
<>	144:ef7eb2e8f9f7	4166	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	4167	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4168
<>	144:ef7eb2e8f9f7	4169	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	4170	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	4171
<>	144:ef7eb2e8f9f7	4172	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4173	}
<>	144:ef7eb2e8f9f7	4174	return HAL_OK;
<>	144:ef7eb2e8f9f7	4175	}
<>	144:ef7eb2e8f9f7	4176
<>	144:ef7eb2e8f9f7	4177	/**
<>	144:ef7eb2e8f9f7	4178	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
<>	144:ef7eb2e8f9f7	4179	* @param hi2c: I2C handle.
<>	144:ef7eb2e8f9f7	4180	* @param DevAddress: specifies the slave address to be programmed.
<>	144:ef7eb2e8f9f7	4181	* @param Size: specifies the number of bytes to be programmed.
<>	144:ef7eb2e8f9f7	4182	* This parameter must be a value between 0 and 255.
<>	144:ef7eb2e8f9f7	4183	* @param Mode: new state of the I2C START condition generation.
<>	144:ef7eb2e8f9f7	4184	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4185	* @arg I2C_RELOAD_MODE: Enable Reload mode .
<>	144:ef7eb2e8f9f7	4186	* @arg I2C_AUTOEND_MODE: Enable Automatic end mode.
<>	144:ef7eb2e8f9f7	4187	* @arg I2C_SOFTEND_MODE: Enable Software end mode.
<>	144:ef7eb2e8f9f7	4188	* @param Request: new state of the I2C START condition generation.
<>	144:ef7eb2e8f9f7	4189	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4190	* @arg I2C_NO_STARTSTOP: Do not Generate stop and start condition.
<>	144:ef7eb2e8f9f7	4191	* @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
<>	144:ef7eb2e8f9f7	4192	* @arg I2C_GENERATE_START_READ: Generate Restart for read request.
<>	144:ef7eb2e8f9f7	4193	* @arg I2C_GENERATE_START_WRITE: Generate Restart for write request.
<>	144:ef7eb2e8f9f7	4194	* @retval None
<>	144:ef7eb2e8f9f7	4195	*/
<>	144:ef7eb2e8f9f7	4196	static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
<>	144:ef7eb2e8f9f7	4197	{
<>	144:ef7eb2e8f9f7	4198	uint32_t tmpreg = 0;
<>	144:ef7eb2e8f9f7	4199
<>	144:ef7eb2e8f9f7	4200	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4201	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	4202	assert_param(IS_TRANSFER_MODE(Mode));
<>	144:ef7eb2e8f9f7	4203	assert_param(IS_TRANSFER_REQUEST(Request));
<>	144:ef7eb2e8f9f7	4204
<>	144:ef7eb2e8f9f7	4205	/* Get the CR2 register value */
<>	144:ef7eb2e8f9f7	4206	tmpreg = hi2c->Instance->CR2;
<>	144:ef7eb2e8f9f7	4207
<>	144:ef7eb2e8f9f7	4208	/* clear tmpreg specific bits */
<>	144:ef7eb2e8f9f7	4209	tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD \| I2C_CR2_NBYTES \| I2C_CR2_RELOAD \| I2C_CR2_AUTOEND \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP));
<>	144:ef7eb2e8f9f7	4210
<>	144:ef7eb2e8f9f7	4211	/* update tmpreg */
<>	144:ef7eb2e8f9f7	4212	tmpreg \|= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) \| (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) \| \
<>	144:ef7eb2e8f9f7	4213	(uint32_t)Mode \| (uint32_t)Request);
<>	144:ef7eb2e8f9f7	4214
<>	144:ef7eb2e8f9f7	4215	/* update CR2 register */
<>	144:ef7eb2e8f9f7	4216	hi2c->Instance->CR2 = tmpreg;
<>	144:ef7eb2e8f9f7	4217	}
<>	144:ef7eb2e8f9f7	4218
<>	144:ef7eb2e8f9f7	4219	/**
<>	144:ef7eb2e8f9f7	4220	* @}
<>	144:ef7eb2e8f9f7	4221	*/
<>	144:ef7eb2e8f9f7	4222
<>	144:ef7eb2e8f9f7	4223	/**
<>	144:ef7eb2e8f9f7	4224	* @}
<>	144:ef7eb2e8f9f7	4225	*/
<>	144:ef7eb2e8f9f7	4226
<>	144:ef7eb2e8f9f7	4227	#endif /* HAL_I2C_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	4228
<>	144:ef7eb2e8f9f7	4229	/**
<>	144:ef7eb2e8f9f7	4230	* @}
<>	144:ef7eb2e8f9f7	4231	*/
<>	144:ef7eb2e8f9f7	4232
<>	144:ef7eb2e8f9f7	4233	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	4234

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Type:	Library
Created:	18 Dec 2017
Imports:	6
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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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