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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_sram.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief SRAM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a generic firmware to drive SRAM memories
<> 144:ef7eb2e8f9f7 9 * mounted as external device.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 17 control SRAM memories. It uses the FMC layer functions to interface
<> 144:ef7eb2e8f9f7 18 with SRAM devices.
<> 144:ef7eb2e8f9f7 19 The following sequence should be followed to configure the FMC to interface
<> 144:ef7eb2e8f9f7 20 with SRAM/PSRAM memories:
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 23 SRAM_HandleTypeDef hsram; and:
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
<> 144:ef7eb2e8f9f7 26 values of the structure member.
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
<> 144:ef7eb2e8f9f7 29 base register instance for NOR or SRAM device
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
<> 144:ef7eb2e8f9f7 32 base register instance for NOR or SRAM extended mode
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
<> 144:ef7eb2e8f9f7 35 mode timings; for example:
<> 144:ef7eb2e8f9f7 36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
<> 144:ef7eb2e8f9f7 37 and fill its fields with the allowed values of the structure member.
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
<> 144:ef7eb2e8f9f7 40 performs the following sequence:
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
<> 144:ef7eb2e8f9f7 43 (##) Control register configuration using the FMC NORSRAM interface function
<> 144:ef7eb2e8f9f7 44 FMC_NORSRAM_Init()
<> 144:ef7eb2e8f9f7 45 (##) Timing register configuration using the FMC NORSRAM interface function
<> 144:ef7eb2e8f9f7 46 FMC_NORSRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
<> 144:ef7eb2e8f9f7 48 FMC_NORSRAM_Extended_Timing_Init()
<> 144:ef7eb2e8f9f7 49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) At this stage you can perform read/write accesses from/to the memory connected
<> 144:ef7eb2e8f9f7 52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
<> 144:ef7eb2e8f9f7 53 following APIs:
<> 144:ef7eb2e8f9f7 54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
<> 144:ef7eb2e8f9f7 55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
<> 144:ef7eb2e8f9f7 58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (#) You can continuously monitor the SRAM device HAL state by calling the function
<> 144:ef7eb2e8f9f7 61 HAL_SRAM_GetState()
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 @endverbatim
<> 144:ef7eb2e8f9f7 64 ******************************************************************************
<> 144:ef7eb2e8f9f7 65 * @attention
<> 144:ef7eb2e8f9f7 66 *
<> 144:ef7eb2e8f9f7 67 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 68 *
<> 144:ef7eb2e8f9f7 69 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 70 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 71 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 72 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 73 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 74 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 75 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 77 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 78 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 90 *
<> 144:ef7eb2e8f9f7 91 ******************************************************************************
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 100 * @{
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #ifdef HAL_SRAM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup SRAM SRAM
<> 144:ef7eb2e8f9f7 106 * @brief SRAM HAL module driver
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 110 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 111 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 112 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 113 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
<> 144:ef7eb2e8f9f7 117 * @{
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 121 * @brief Initialization and Configuration functions.
<> 144:ef7eb2e8f9f7 122 *
<> 144:ef7eb2e8f9f7 123 @verbatim
<> 144:ef7eb2e8f9f7 124 ==============================================================================
<> 144:ef7eb2e8f9f7 125 ##### SRAM Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 126 ==============================================================================
<> 144:ef7eb2e8f9f7 127 [..] This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 128 the SRAM memory
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 @endverbatim
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @brief Performs the SRAM device initialization sequence
<> 144:ef7eb2e8f9f7 136 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 137 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 138 * @param Timing: Pointer to SRAM control timing structure
<> 144:ef7eb2e8f9f7 139 * @param ExtTiming: Pointer to SRAM extended mode timing structure
<> 144:ef7eb2e8f9f7 140 * @retval HAL status
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
<> 144:ef7eb2e8f9f7 143 {
<> 144:ef7eb2e8f9f7 144 /* Check the SRAM handle parameter */
<> 144:ef7eb2e8f9f7 145 if(hsram == NULL)
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 if(hsram->State == HAL_SRAM_STATE_RESET)
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 153 hsram->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 156 HAL_SRAM_MspInit(hsram);
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* Initialize SRAM control Interface */
<> 144:ef7eb2e8f9f7 160 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Initialize SRAM timing Interface */
<> 144:ef7eb2e8f9f7 163 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* Initialize SRAM extended mode timing Interface */
<> 144:ef7eb2e8f9f7 166 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Enable the NORSRAM device */
<> 144:ef7eb2e8f9f7 169 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 return HAL_OK;
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @brief Performs the SRAM device De-initialization sequence.
<> 144:ef7eb2e8f9f7 176 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 177 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 178 * @retval HAL status
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 181 {
<> 144:ef7eb2e8f9f7 182 /* De-Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 183 HAL_SRAM_MspDeInit(hsram);
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Configure the SRAM registers with their reset values */
<> 144:ef7eb2e8f9f7 186 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 hsram->State = HAL_SRAM_STATE_RESET;
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /* Release Lock */
<> 144:ef7eb2e8f9f7 191 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 return HAL_OK;
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /**
<> 144:ef7eb2e8f9f7 197 * @brief SRAM MSP Init.
<> 144:ef7eb2e8f9f7 198 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 199 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 200 * @retval None
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 203 {
<> 144:ef7eb2e8f9f7 204 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 205 UNUSED(hsram);
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 208 the HAL_SRAM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @brief SRAM MSP DeInit.
<> 144:ef7eb2e8f9f7 214 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 215 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 216 * @retval None
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 221 UNUSED(hsram);
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 224 the HAL_SRAM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @brief DMA transfer complete callback.
<> 144:ef7eb2e8f9f7 230 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 231 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 232 * @retval None
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 237 UNUSED(hdma);
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 240 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @brief DMA transfer complete error callback.
<> 144:ef7eb2e8f9f7 246 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 247 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 248 * @retval None
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 253 UNUSED(hdma);
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 256 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @}
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
<> 144:ef7eb2e8f9f7 265 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 266 *
<> 144:ef7eb2e8f9f7 267 @verbatim
<> 144:ef7eb2e8f9f7 268 ==============================================================================
<> 144:ef7eb2e8f9f7 269 ##### SRAM Input and Output functions #####
<> 144:ef7eb2e8f9f7 270 ==============================================================================
<> 144:ef7eb2e8f9f7 271 [..]
<> 144:ef7eb2e8f9f7 272 This section provides functions allowing to use and control the SRAM memory
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 @endverbatim
<> 144:ef7eb2e8f9f7 275 * @{
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief Reads 8-bit buffer from SRAM memory.
<> 144:ef7eb2e8f9f7 280 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 281 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 282 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 283 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 284 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 285 * @retval HAL status
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Process Locked */
<> 144:ef7eb2e8f9f7 292 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 295 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Read data from memory */
<> 144:ef7eb2e8f9f7 298 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 299 {
<> 144:ef7eb2e8f9f7 300 *pDstBuffer = *(__IO uint8_t *)psramaddress;
<> 144:ef7eb2e8f9f7 301 pDstBuffer++;
<> 144:ef7eb2e8f9f7 302 psramaddress++;
<> 144:ef7eb2e8f9f7 303 }
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 306 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Process unlocked */
<> 144:ef7eb2e8f9f7 309 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 return HAL_OK;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Writes 8-bit buffer to SRAM memory.
<> 144:ef7eb2e8f9f7 316 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 317 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 318 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 319 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 320 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 321 * @retval HAL status
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 328 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 331 }
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Process Locked */
<> 144:ef7eb2e8f9f7 334 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 337 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Write data to memory */
<> 144:ef7eb2e8f9f7 340 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 *(__IO uint8_t *)psramaddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 343 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 344 psramaddress++;
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 348 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* Process unlocked */
<> 144:ef7eb2e8f9f7 351 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 return HAL_OK;
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /**
<> 144:ef7eb2e8f9f7 357 * @brief Reads 16-bit buffer from SRAM memory.
<> 144:ef7eb2e8f9f7 358 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 359 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 360 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 361 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 362 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 363 * @retval HAL status
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Process Locked */
<> 144:ef7eb2e8f9f7 370 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 373 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Read data from memory */
<> 144:ef7eb2e8f9f7 376 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 377 {
<> 144:ef7eb2e8f9f7 378 *pDstBuffer = *(__IO uint16_t *)psramaddress;
<> 144:ef7eb2e8f9f7 379 pDstBuffer++;
<> 144:ef7eb2e8f9f7 380 psramaddress++;
<> 144:ef7eb2e8f9f7 381 }
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 384 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Process unlocked */
<> 144:ef7eb2e8f9f7 387 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 return HAL_OK;
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /**
<> 144:ef7eb2e8f9f7 393 * @brief Writes 16-bit buffer to SRAM memory.
<> 144:ef7eb2e8f9f7 394 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 395 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 396 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 397 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 398 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 399 * @retval HAL status
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 406 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Process Locked */
<> 144:ef7eb2e8f9f7 412 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 415 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Write data to memory */
<> 144:ef7eb2e8f9f7 418 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 *(__IO uint16_t *)psramaddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 421 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 422 psramaddress++;
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 426 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Process unlocked */
<> 144:ef7eb2e8f9f7 429 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 return HAL_OK;
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /**
<> 144:ef7eb2e8f9f7 435 * @brief Reads 32-bit buffer from SRAM memory.
<> 144:ef7eb2e8f9f7 436 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 437 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 438 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 439 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 440 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 441 * @retval HAL status
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 /* Process Locked */
<> 144:ef7eb2e8f9f7 446 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 449 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Read data from memory */
<> 144:ef7eb2e8f9f7 452 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 *pDstBuffer = *(__IO uint32_t *)pAddress;
<> 144:ef7eb2e8f9f7 455 pDstBuffer++;
<> 144:ef7eb2e8f9f7 456 pAddress++;
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 460 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /* Process unlocked */
<> 144:ef7eb2e8f9f7 463 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 return HAL_OK;
<> 144:ef7eb2e8f9f7 466 }
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /**
<> 144:ef7eb2e8f9f7 469 * @brief Writes 32-bit buffer to SRAM memory.
<> 144:ef7eb2e8f9f7 470 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 471 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 472 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 473 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 474 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 475 * @retval HAL status
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 480 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 483 }
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /* Process Locked */
<> 144:ef7eb2e8f9f7 486 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 489 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Write data to memory */
<> 144:ef7eb2e8f9f7 492 for(; BufferSize != 0; BufferSize--)
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 *(__IO uint32_t *)pAddress = *pSrcBuffer;
<> 144:ef7eb2e8f9f7 495 pSrcBuffer++;
<> 144:ef7eb2e8f9f7 496 pAddress++;
<> 144:ef7eb2e8f9f7 497 }
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 500 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Process unlocked */
<> 144:ef7eb2e8f9f7 503 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 return HAL_OK;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @brief Reads a Words data from the SRAM memory using DMA transfer.
<> 144:ef7eb2e8f9f7 510 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 511 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 512 * @param pAddress: Pointer to read start address
<> 144:ef7eb2e8f9f7 513 * @param pDstBuffer: Pointer to destination buffer
<> 144:ef7eb2e8f9f7 514 * @param BufferSize: Size of the buffer to read from memory
<> 144:ef7eb2e8f9f7 515 * @retval HAL status
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 518 {
<> 144:ef7eb2e8f9f7 519 /* Process Locked */
<> 144:ef7eb2e8f9f7 520 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 523 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* Configure DMA user callbacks */
<> 144:ef7eb2e8f9f7 526 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
<> 144:ef7eb2e8f9f7 527 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Enable the DMA Channel */
<> 144:ef7eb2e8f9f7 530 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 533 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Process unlocked */
<> 144:ef7eb2e8f9f7 536 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 return HAL_OK;
<> 144:ef7eb2e8f9f7 539 }
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /**
<> 144:ef7eb2e8f9f7 542 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
<> 144:ef7eb2e8f9f7 543 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 544 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 545 * @param pAddress: Pointer to write start address
<> 144:ef7eb2e8f9f7 546 * @param pSrcBuffer: Pointer to source buffer to write
<> 144:ef7eb2e8f9f7 547 * @param BufferSize: Size of the buffer to write to memory
<> 144:ef7eb2e8f9f7 548 * @retval HAL status
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 /* Check the SRAM controller state */
<> 144:ef7eb2e8f9f7 553 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /* Process Locked */
<> 144:ef7eb2e8f9f7 559 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 562 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /* Configure DMA user callbacks */
<> 144:ef7eb2e8f9f7 565 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
<> 144:ef7eb2e8f9f7 566 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Enable the DMA Channel */
<> 144:ef7eb2e8f9f7 569 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 572 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Process unlocked */
<> 144:ef7eb2e8f9f7 575 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 return HAL_OK;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @}
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
<> 144:ef7eb2e8f9f7 585 * @brief Control functions
<> 144:ef7eb2e8f9f7 586 *
<> 144:ef7eb2e8f9f7 587 @verbatim
<> 144:ef7eb2e8f9f7 588 ==============================================================================
<> 144:ef7eb2e8f9f7 589 ##### SRAM Control functions #####
<> 144:ef7eb2e8f9f7 590 ==============================================================================
<> 144:ef7eb2e8f9f7 591 [..]
<> 144:ef7eb2e8f9f7 592 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 593 the SRAM interface.
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 @endverbatim
<> 144:ef7eb2e8f9f7 596 * @{
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /**
<> 144:ef7eb2e8f9f7 600 * @brief Enables dynamically SRAM write operation.
<> 144:ef7eb2e8f9f7 601 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 602 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 603 * @retval HAL status
<> 144:ef7eb2e8f9f7 604 */
<> 144:ef7eb2e8f9f7 605 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 606 {
<> 144:ef7eb2e8f9f7 607 /* Process Locked */
<> 144:ef7eb2e8f9f7 608 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Enable write operation */
<> 144:ef7eb2e8f9f7 611 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 614 hsram->State = HAL_SRAM_STATE_READY;
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* Process unlocked */
<> 144:ef7eb2e8f9f7 617 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 return HAL_OK;
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /**
<> 144:ef7eb2e8f9f7 623 * @brief Disables dynamically SRAM write operation.
<> 144:ef7eb2e8f9f7 624 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 625 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 626 * @retval HAL status
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 /* Process Locked */
<> 144:ef7eb2e8f9f7 631 __HAL_LOCK(hsram);
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 634 hsram->State = HAL_SRAM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Disable write operation */
<> 144:ef7eb2e8f9f7 637 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 640 hsram->State = HAL_SRAM_STATE_PROTECTED;
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* Process unlocked */
<> 144:ef7eb2e8f9f7 643 __HAL_UNLOCK(hsram);
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 return HAL_OK;
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /**
<> 144:ef7eb2e8f9f7 649 * @}
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 653 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 654 *
<> 144:ef7eb2e8f9f7 655 @verbatim
<> 144:ef7eb2e8f9f7 656 ==============================================================================
<> 144:ef7eb2e8f9f7 657 ##### SRAM State functions #####
<> 144:ef7eb2e8f9f7 658 ==============================================================================
<> 144:ef7eb2e8f9f7 659 [..]
<> 144:ef7eb2e8f9f7 660 This subsection permits to get in run-time the status of the SRAM controller
<> 144:ef7eb2e8f9f7 661 and the data flow.
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 @endverbatim
<> 144:ef7eb2e8f9f7 664 * @{
<> 144:ef7eb2e8f9f7 665 */
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /**
<> 144:ef7eb2e8f9f7 668 * @brief Returns the SRAM controller state
<> 144:ef7eb2e8f9f7 669 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 670 * the configuration information for SRAM module.
<> 144:ef7eb2e8f9f7 671 * @retval HAL state
<> 144:ef7eb2e8f9f7 672 */
<> 144:ef7eb2e8f9f7 673 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 return hsram->State;
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /**
<> 144:ef7eb2e8f9f7 679 * @}
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /**
<> 144:ef7eb2e8f9f7 683 * @}
<> 144:ef7eb2e8f9f7 684 */
<> 144:ef7eb2e8f9f7 685 /**
<> 144:ef7eb2e8f9f7 686 * @}
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688 #endif /* HAL_SRAM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /**
<> 144:ef7eb2e8f9f7 691 * @}
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/