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targets/cmsis/TARGET_Maxim/TARGET_MAX32620/adc_regs.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_ADC_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_ADC_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*
<> 144:ef7eb2e8f9f7 44 If types are not defined elsewhere (CMSIS) define them here
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46 #ifndef __IO
<> 144:ef7eb2e8f9f7 47 #define __IO volatile
<> 144:ef7eb2e8f9f7 48 #endif
<> 144:ef7eb2e8f9f7 49 #ifndef __I
<> 144:ef7eb2e8f9f7 50 #define __I volatile const
<> 144:ef7eb2e8f9f7 51 #endif
<> 144:ef7eb2e8f9f7 52 #ifndef __O
<> 144:ef7eb2e8f9f7 53 #define __O volatile
<> 144:ef7eb2e8f9f7 54 #endif
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*
<> 144:ef7eb2e8f9f7 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 144:ef7eb2e8f9f7 59 access to each register in module.
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Offset Register Description
<> 144:ef7eb2e8f9f7 63 ============= ============================================================================ */
<> 144:ef7eb2e8f9f7 64 typedef struct {
<> 144:ef7eb2e8f9f7 65 __IO uint32_t ctrl; /* 0x0000 ADC Control */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t status; /* 0x0004 ADC Status */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t data; /* 0x0008 ADC Output Data */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t intr; /* 0x000C ADC Interrupt Control Register */
<> 144:ef7eb2e8f9f7 69 __IO uint32_t limit[4]; /* 0x0010-0x001C ADC Limit 0..3 */
<> 144:ef7eb2e8f9f7 70 __IO uint32_t afe_ctrl; /* 0x0020 AFE Control Register */
<> 144:ef7eb2e8f9f7 71 __IO uint32_t ro_cal0; /* 0x0024 RO Trim Calibration Register 0 */
<> 144:ef7eb2e8f9f7 72 __IO uint32_t ro_cal1; /* 0x0028 RO Trim Calibration Register 1 */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t ro_cal2; /* 0x002C RO Trim Calibration Register 2 */
<> 144:ef7eb2e8f9f7 74 } mxc_adc_regs_t;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /*
<> 144:ef7eb2e8f9f7 78 Register offsets for module ADC.
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 82 #define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 83 #define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 84 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 85 #define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 86 #define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 87 #define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 88 #define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL)
<> 144:ef7eb2e8f9f7 89 #define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL)
<> 144:ef7eb2e8f9f7 90 #define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL)
<> 144:ef7eb2e8f9f7 91 #define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL)
<> 144:ef7eb2e8f9f7 92 #define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL)
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /*
<> 144:ef7eb2e8f9f7 96 Field positions and masks for module ADC.
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0
<> 144:ef7eb2e8f9f7 100 #define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS))
<> 144:ef7eb2e8f9f7 101 #define MXC_F_ADC_CTRL_ADC_PU_POS 1
<> 144:ef7eb2e8f9f7 102 #define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS))
<> 144:ef7eb2e8f9f7 103 #define MXC_F_ADC_CTRL_BUF_PU_POS 2
<> 144:ef7eb2e8f9f7 104 #define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS))
<> 144:ef7eb2e8f9f7 105 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3
<> 144:ef7eb2e8f9f7 106 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS))
<> 144:ef7eb2e8f9f7 107 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4
<> 144:ef7eb2e8f9f7 108 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS))
<> 144:ef7eb2e8f9f7 109 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5
<> 144:ef7eb2e8f9f7 110 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS))
<> 144:ef7eb2e8f9f7 111 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6
<> 144:ef7eb2e8f9f7 112 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS))
<> 144:ef7eb2e8f9f7 113 #define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7
<> 144:ef7eb2e8f9f7 114 #define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS))
<> 144:ef7eb2e8f9f7 115 #define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8
<> 144:ef7eb2e8f9f7 116 #define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS))
<> 144:ef7eb2e8f9f7 117 #define MXC_F_ADC_CTRL_ADC_SCALE_POS 9
<> 144:ef7eb2e8f9f7 118 #define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS))
<> 144:ef7eb2e8f9f7 119 #define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10
<> 144:ef7eb2e8f9f7 120 #define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS))
<> 144:ef7eb2e8f9f7 121 #define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11
<> 144:ef7eb2e8f9f7 122 #define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS))
<> 144:ef7eb2e8f9f7 123 #define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12
<> 144:ef7eb2e8f9f7 124 #define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS))
<> 144:ef7eb2e8f9f7 125 #define MXC_F_ADC_CTRL_ADC_XREF_POS 16
<> 144:ef7eb2e8f9f7 126 #define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS))
<> 144:ef7eb2e8f9f7 127 #define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17
<> 144:ef7eb2e8f9f7 128 #define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS))
<> 144:ef7eb2e8f9f7 129 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24
<> 144:ef7eb2e8f9f7 130 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS))
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0
<> 144:ef7eb2e8f9f7 133 #define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 134 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1
<> 144:ef7eb2e8f9f7 135 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 136 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2
<> 144:ef7eb2e8f9f7 137 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 138 #define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3
<> 144:ef7eb2e8f9f7 139 #define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS))
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 #define MXC_F_ADC_DATA_ADC_DATA_POS 0
<> 144:ef7eb2e8f9f7 142 #define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS))
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 #define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0
<> 144:ef7eb2e8f9f7 145 #define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS))
<> 144:ef7eb2e8f9f7 146 #define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1
<> 144:ef7eb2e8f9f7 147 #define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS))
<> 144:ef7eb2e8f9f7 148 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2
<> 144:ef7eb2e8f9f7 149 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS))
<> 144:ef7eb2e8f9f7 150 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3
<> 144:ef7eb2e8f9f7 151 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS))
<> 144:ef7eb2e8f9f7 152 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4
<> 144:ef7eb2e8f9f7 153 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS))
<> 144:ef7eb2e8f9f7 154 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5
<> 144:ef7eb2e8f9f7 155 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS))
<> 144:ef7eb2e8f9f7 156 #define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16
<> 144:ef7eb2e8f9f7 157 #define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS))
<> 144:ef7eb2e8f9f7 158 #define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17
<> 144:ef7eb2e8f9f7 159 #define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS))
<> 144:ef7eb2e8f9f7 160 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18
<> 144:ef7eb2e8f9f7 161 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS))
<> 144:ef7eb2e8f9f7 162 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19
<> 144:ef7eb2e8f9f7 163 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS))
<> 144:ef7eb2e8f9f7 164 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20
<> 144:ef7eb2e8f9f7 165 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS))
<> 144:ef7eb2e8f9f7 166 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21
<> 144:ef7eb2e8f9f7 167 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS))
<> 144:ef7eb2e8f9f7 168 #define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22
<> 144:ef7eb2e8f9f7 169 #define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS))
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0
<> 144:ef7eb2e8f9f7 172 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS))
<> 144:ef7eb2e8f9f7 173 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12
<> 144:ef7eb2e8f9f7 174 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS))
<> 144:ef7eb2e8f9f7 175 #define MXC_F_ADC_LIMIT0_CH_SEL_POS 24
<> 144:ef7eb2e8f9f7 176 #define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS))
<> 144:ef7eb2e8f9f7 177 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28
<> 144:ef7eb2e8f9f7 178 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS))
<> 144:ef7eb2e8f9f7 179 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29
<> 144:ef7eb2e8f9f7 180 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS))
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0
<> 144:ef7eb2e8f9f7 183 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS))
<> 144:ef7eb2e8f9f7 184 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12
<> 144:ef7eb2e8f9f7 185 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS))
<> 144:ef7eb2e8f9f7 186 #define MXC_F_ADC_LIMIT1_CH_SEL_POS 24
<> 144:ef7eb2e8f9f7 187 #define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS))
<> 144:ef7eb2e8f9f7 188 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28
<> 144:ef7eb2e8f9f7 189 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS))
<> 144:ef7eb2e8f9f7 190 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29
<> 144:ef7eb2e8f9f7 191 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS))
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0
<> 144:ef7eb2e8f9f7 194 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS))
<> 144:ef7eb2e8f9f7 195 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12
<> 144:ef7eb2e8f9f7 196 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS))
<> 144:ef7eb2e8f9f7 197 #define MXC_F_ADC_LIMIT2_CH_SEL_POS 24
<> 144:ef7eb2e8f9f7 198 #define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS))
<> 144:ef7eb2e8f9f7 199 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28
<> 144:ef7eb2e8f9f7 200 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS))
<> 144:ef7eb2e8f9f7 201 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29
<> 144:ef7eb2e8f9f7 202 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS))
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0
<> 144:ef7eb2e8f9f7 205 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS))
<> 144:ef7eb2e8f9f7 206 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12
<> 144:ef7eb2e8f9f7 207 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS))
<> 144:ef7eb2e8f9f7 208 #define MXC_F_ADC_LIMIT3_CH_SEL_POS 24
<> 144:ef7eb2e8f9f7 209 #define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS))
<> 144:ef7eb2e8f9f7 210 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28
<> 144:ef7eb2e8f9f7 211 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS))
<> 144:ef7eb2e8f9f7 212 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29
<> 144:ef7eb2e8f9f7 213 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS))
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8
<> 144:ef7eb2e8f9f7 216 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS))
<> 144:ef7eb2e8f9f7 217 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9
<> 144:ef7eb2e8f9f7 218 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS))
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
<> 144:ef7eb2e8f9f7 221 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
<> 144:ef7eb2e8f9f7 222 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
<> 144:ef7eb2e8f9f7 223 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
<> 144:ef7eb2e8f9f7 224 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
<> 144:ef7eb2e8f9f7 225 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
<> 144:ef7eb2e8f9f7 226 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4
<> 144:ef7eb2e8f9f7 227 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS))
<> 144:ef7eb2e8f9f7 228 #define MXC_F_ADC_RO_CAL0_DUMMY_POS 5
<> 144:ef7eb2e8f9f7 229 #define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS))
<> 144:ef7eb2e8f9f7 230 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
<> 144:ef7eb2e8f9f7 231 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
<> 144:ef7eb2e8f9f7 232 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
<> 144:ef7eb2e8f9f7 233 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
<> 144:ef7eb2e8f9f7 236 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
<> 144:ef7eb2e8f9f7 237 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
<> 144:ef7eb2e8f9f7 238 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
<> 144:ef7eb2e8f9f7 239 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
<> 144:ef7eb2e8f9f7 240 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0
<> 144:ef7eb2e8f9f7 243 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS))
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249 #endif
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 #endif /* _MXC_ADC_REGS_H_ */
<> 144:ef7eb2e8f9f7 252