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targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_ppi.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ppi.h@149:156823d33999 
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015 Nordic Semiconductor ASA
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * 1. Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
<> 144:ef7eb2e8f9f7 12 * integrated circuit in a product or a software update for such product, must reproduce
<> 144:ef7eb2e8f9f7 13 * the above copyright notice, this list of conditions and the following disclaimer in
<> 144:ef7eb2e8f9f7 14 * the documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
<> 144:ef7eb2e8f9f7 17 * used to endorse or promote products derived from this software without specific prior
<> 144:ef7eb2e8f9f7 18 * written permission.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * 4. This software, with or without modification, must only be used with a
<> 144:ef7eb2e8f9f7 21 * Nordic Semiconductor ASA integrated circuit.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * 5. Any software provided in binary or object form under this license must not be reverse
<> 144:ef7eb2e8f9f7 24 * engineered, decompiled, modified and/or disassembled.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 36 *
<> 144:ef7eb2e8f9f7 37 */
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifndef NRF_PPI_H__
<> 144:ef7eb2e8f9f7 41 #define NRF_PPI_H__
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #include <stddef.h>
<> 144:ef7eb2e8f9f7 44 #include "nrf.h"
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /**
<> 144:ef7eb2e8f9f7 47 * @defgroup nrf_ppi_hal PPI HAL
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 * @ingroup nrf_ppi
<> 144:ef7eb2e8f9f7 50 * @brief Hardware access layer for setting up Programmable Peripheral Interconnect (PPI) channels.
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #define NRF_PPI_TASK_SET (1UL)
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /**
<> 144:ef7eb2e8f9f7 56 * @enum nrf_ppi_channel_t
<> 144:ef7eb2e8f9f7 57 * @brief PPI channels.
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59 typedef enum
<> 144:ef7eb2e8f9f7 60 {
<> 144:ef7eb2e8f9f7 61 NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */
<> 144:ef7eb2e8f9f7 62 NRF_PPI_CHANNEL1 = PPI_CHEN_CH1_Pos, /**< Channel 1. */
<> 144:ef7eb2e8f9f7 63 NRF_PPI_CHANNEL2 = PPI_CHEN_CH2_Pos, /**< Channel 2. */
<> 144:ef7eb2e8f9f7 64 NRF_PPI_CHANNEL3 = PPI_CHEN_CH3_Pos, /**< Channel 3. */
<> 144:ef7eb2e8f9f7 65 NRF_PPI_CHANNEL4 = PPI_CHEN_CH4_Pos, /**< Channel 4. */
<> 144:ef7eb2e8f9f7 66 NRF_PPI_CHANNEL5 = PPI_CHEN_CH5_Pos, /**< Channel 5. */
<> 144:ef7eb2e8f9f7 67 NRF_PPI_CHANNEL6 = PPI_CHEN_CH6_Pos, /**< Channel 6. */
<> 144:ef7eb2e8f9f7 68 NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */
<> 144:ef7eb2e8f9f7 69 NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */
<> 144:ef7eb2e8f9f7 70 NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */
<> 144:ef7eb2e8f9f7 71 NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */
<> 144:ef7eb2e8f9f7 72 NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */
<> 144:ef7eb2e8f9f7 73 NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */
<> 144:ef7eb2e8f9f7 74 NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */
<> 144:ef7eb2e8f9f7 75 NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */
<> 144:ef7eb2e8f9f7 76 NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */
<> 144:ef7eb2e8f9f7 77 #ifdef NRF52
<> 144:ef7eb2e8f9f7 78 NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */
<> 144:ef7eb2e8f9f7 79 NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */
<> 144:ef7eb2e8f9f7 80 NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */
<> 144:ef7eb2e8f9f7 81 NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */
<> 144:ef7eb2e8f9f7 82 #endif
<> 144:ef7eb2e8f9f7 83 NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */
<> 144:ef7eb2e8f9f7 84 NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */
<> 144:ef7eb2e8f9f7 85 NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */
<> 144:ef7eb2e8f9f7 86 NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */
<> 144:ef7eb2e8f9f7 87 NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */
<> 144:ef7eb2e8f9f7 88 NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */
<> 144:ef7eb2e8f9f7 89 NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */
<> 144:ef7eb2e8f9f7 90 NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */
<> 144:ef7eb2e8f9f7 91 NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */
<> 144:ef7eb2e8f9f7 92 NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */
<> 144:ef7eb2e8f9f7 93 NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */
<> 144:ef7eb2e8f9f7 94 NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos /**< Channel 31. */
<> 144:ef7eb2e8f9f7 95 } nrf_ppi_channel_t;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /**
<> 144:ef7eb2e8f9f7 98 * @enum nrf_ppi_channel_group_t
<> 144:ef7eb2e8f9f7 99 * @brief PPI channel groups.
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 typedef enum
<> 144:ef7eb2e8f9f7 102 {
<> 144:ef7eb2e8f9f7 103 NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
<> 144:ef7eb2e8f9f7 104 NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
<> 144:ef7eb2e8f9f7 105 NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
<> 144:ef7eb2e8f9f7 106 NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
<> 144:ef7eb2e8f9f7 107 #ifdef NRF52
<> 144:ef7eb2e8f9f7 108 NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
<> 144:ef7eb2e8f9f7 109 NRF_PPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
<> 144:ef7eb2e8f9f7 110 #endif
<> 144:ef7eb2e8f9f7 111 } nrf_ppi_channel_group_t;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /**
<> 144:ef7eb2e8f9f7 114 * @enum nrf_ppi_channel_include_t
<> 144:ef7eb2e8f9f7 115 * @brief Definition of which PPI channels belong to a group.
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 typedef enum
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119 NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */
<> 144:ef7eb2e8f9f7 120 NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included /**< Channel included in a group. */
<> 144:ef7eb2e8f9f7 121 } nrf_ppi_channel_include_t;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @enum nrf_ppi_channel_enable_t
<> 144:ef7eb2e8f9f7 125 * @brief Definition if a PPI channel is enabled.
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 typedef enum
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */
<> 144:ef7eb2e8f9f7 130 NRF_PPI_CHANNEL_ENABLED = PPI_CHEN_CH0_Enabled /**< Channel enabled. */
<> 144:ef7eb2e8f9f7 131 } nrf_ppi_channel_enable_t;
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @enum nrf_ppi_task_t
<> 144:ef7eb2e8f9f7 135 * @brief PPI tasks.
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 typedef enum
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 /*lint -save -e30 -esym(628,__INTADDR__)*/
<> 144:ef7eb2e8f9f7 140 NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0 */
<> 144:ef7eb2e8f9f7 141 NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0 */
<> 144:ef7eb2e8f9f7 142 NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1 */
<> 144:ef7eb2e8f9f7 143 NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1 */
<> 144:ef7eb2e8f9f7 144 NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2 */
<> 144:ef7eb2e8f9f7 145 NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */
<> 144:ef7eb2e8f9f7 146 NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3 */
<> 144:ef7eb2e8f9f7 147 NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */
<> 144:ef7eb2e8f9f7 148 #ifdef NRF52
<> 144:ef7eb2e8f9f7 149 NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4 */
<> 144:ef7eb2e8f9f7 150 NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */
<> 144:ef7eb2e8f9f7 151 NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5 */
<> 144:ef7eb2e8f9f7 152 NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5 */
<> 144:ef7eb2e8f9f7 153 #endif
<> 144:ef7eb2e8f9f7 154 /*lint -restore*/
<> 144:ef7eb2e8f9f7 155 } nrf_ppi_task_t;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @brief Function for enabling a given PPI channel.
<> 144:ef7eb2e8f9f7 159 *
<> 144:ef7eb2e8f9f7 160 * @details This function enables only one channel.
<> 144:ef7eb2e8f9f7 161 *
<> 144:ef7eb2e8f9f7 162 * @param[in] channel Channel to enable.
<> 144:ef7eb2e8f9f7 163 *
<> 144:ef7eb2e8f9f7 164 * */
<> 144:ef7eb2e8f9f7 165 __STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel)
<> 144:ef7eb2e8f9f7 166 {
<> 144:ef7eb2e8f9f7 167 NRF_PPI->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel);
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @brief Function for disabling a given PPI channel.
<> 144:ef7eb2e8f9f7 173 *
<> 144:ef7eb2e8f9f7 174 * @details This function disables only one channel.
<> 144:ef7eb2e8f9f7 175 *
<> 144:ef7eb2e8f9f7 176 * @param[in] channel Channel to disable.
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178 __STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel)
<> 144:ef7eb2e8f9f7 179 {
<> 144:ef7eb2e8f9f7 180 NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel);
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /**
<> 144:ef7eb2e8f9f7 185 * @brief Function for checking if a given PPI channel is enabled.
<> 144:ef7eb2e8f9f7 186 *
<> 144:ef7eb2e8f9f7 187 * @details This function checks only one channel.
<> 144:ef7eb2e8f9f7 188 *
<> 144:ef7eb2e8f9f7 189 * @param[in] channel Channel to check.
<> 144:ef7eb2e8f9f7 190 *
<> 144:ef7eb2e8f9f7 191 * @retval NRF_PPI_CHANNEL_ENABLED If the channel is enabled.
<> 144:ef7eb2e8f9f7 192 * @retval NRF_PPI_CHANNEL_DISABLED If the channel is not enabled.
<> 144:ef7eb2e8f9f7 193 *
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 __STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 if (NRF_PPI->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel)))
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 return NRF_PPI_CHANNEL_ENABLED;
<> 144:ef7eb2e8f9f7 200 }
<> 144:ef7eb2e8f9f7 201 else
<> 144:ef7eb2e8f9f7 202 {
<> 144:ef7eb2e8f9f7 203 return NRF_PPI_CHANNEL_DISABLED;
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief Function for disabling all PPI channels.
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 __STATIC_INLINE void nrf_ppi_channel_disable_all(void)
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /**
<> 144:ef7eb2e8f9f7 217 * @brief Function for disabling multiple PPI channels.
<> 144:ef7eb2e8f9f7 218 *
<> 144:ef7eb2e8f9f7 219 * @param[in] mask Channel mask.
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 __STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask)
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 NRF_PPI->CHENCLR = mask;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @brief Function for setting up event and task endpoints for a given PPI channel.
<> 144:ef7eb2e8f9f7 228 *
<> 144:ef7eb2e8f9f7 229 * @param[in] eep Event register address.
<> 144:ef7eb2e8f9f7 230 *
<> 144:ef7eb2e8f9f7 231 * @param[in] tep Task register address.
<> 144:ef7eb2e8f9f7 232 *
<> 144:ef7eb2e8f9f7 233 * @param[in] channel Channel to which the given endpoints are assigned.
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 __STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
<> 144:ef7eb2e8f9f7 236 uint32_t eep,
<> 144:ef7eb2e8f9f7 237 uint32_t tep)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 NRF_PPI->CH[(uint32_t) channel].EEP = eep;
<> 144:ef7eb2e8f9f7 240 NRF_PPI->CH[(uint32_t) channel].TEP = tep;
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 #ifdef NRF52
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @brief Function for setting up task endpoint for a given PPI fork.
<> 144:ef7eb2e8f9f7 246 *
<> 144:ef7eb2e8f9f7 247 * @param[in] fork_tep Task register address.
<> 144:ef7eb2e8f9f7 248 *
<> 144:ef7eb2e8f9f7 249 * @param[in] channel Channel to which the given fork endpoint is assigned.
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 __STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
<> 144:ef7eb2e8f9f7 252 uint32_t fork_tep)
<> 144:ef7eb2e8f9f7 253 {
<> 144:ef7eb2e8f9f7 254 NRF_PPI->FORK[(uint32_t) channel].TEP = fork_tep;
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief Function for setting up event and task endpoints for a given PPI channel and fork.
<> 144:ef7eb2e8f9f7 259 *
<> 144:ef7eb2e8f9f7 260 * @param[in] eep Event register address.
<> 144:ef7eb2e8f9f7 261 *
<> 144:ef7eb2e8f9f7 262 * @param[in] tep Task register address.
<> 144:ef7eb2e8f9f7 263 *
<> 144:ef7eb2e8f9f7 264 * @param[in] fork_tep Fork task register address (register value).
<> 144:ef7eb2e8f9f7 265 *
<> 144:ef7eb2e8f9f7 266 * @param[in] channel Channel to which the given endpoints are assigned.
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 __STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel,
<> 144:ef7eb2e8f9f7 269 uint32_t eep,
<> 144:ef7eb2e8f9f7 270 uint32_t tep,
<> 144:ef7eb2e8f9f7 271 uint32_t fork_tep)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 nrf_ppi_channel_endpoint_setup(channel, eep, tep);
<> 144:ef7eb2e8f9f7 274 nrf_ppi_fork_endpoint_setup(channel, fork_tep);
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276 #endif
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief Function for including a PPI channel in a channel group.
<> 144:ef7eb2e8f9f7 280 *
<> 144:ef7eb2e8f9f7 281 * @details This function adds only one channel to the group.
<> 144:ef7eb2e8f9f7 282 *
<> 144:ef7eb2e8f9f7 283 * @param[in] channel Channel to be included in the group.
<> 144:ef7eb2e8f9f7 284 *
<> 144:ef7eb2e8f9f7 285 * @param[in] channel_group Channel group.
<> 144:ef7eb2e8f9f7 286 *
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288 __STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel,
<> 144:ef7eb2e8f9f7 289 nrf_ppi_channel_group_t channel_group)
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 NRF_PPI->CHG[(uint32_t) channel_group] =
<> 144:ef7eb2e8f9f7 292 NRF_PPI->CHG[(uint32_t) channel_group] | (PPI_CHG_CH0_Included << ((uint32_t) channel));
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @brief Function for including multiple PPI channels in a channel group.
<> 144:ef7eb2e8f9f7 297 *
<> 144:ef7eb2e8f9f7 298 * @details This function adds all specified channels to the group.
<> 144:ef7eb2e8f9f7 299 *
<> 144:ef7eb2e8f9f7 300 * @param[in] channel_mask Channels to be included in the group.
<> 144:ef7eb2e8f9f7 301 *
<> 144:ef7eb2e8f9f7 302 * @param[in] channel_group Channel group.
<> 144:ef7eb2e8f9f7 303 *
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305 __STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask,
<> 144:ef7eb2e8f9f7 306 nrf_ppi_channel_group_t channel_group)
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 NRF_PPI->CHG[(uint32_t) channel_group] =
<> 144:ef7eb2e8f9f7 309 NRF_PPI->CHG[(uint32_t) channel_group] | (channel_mask);
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @brief Function for removing a PPI channel from a channel group.
<> 144:ef7eb2e8f9f7 315 *
<> 144:ef7eb2e8f9f7 316 * @details This function removes only one channel from the group.
<> 144:ef7eb2e8f9f7 317 *
<> 144:ef7eb2e8f9f7 318 * @param[in] channel Channel to be removed from the group.
<> 144:ef7eb2e8f9f7 319 *
<> 144:ef7eb2e8f9f7 320 * @param[in] channel_group Channel group.
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 __STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel,
<> 144:ef7eb2e8f9f7 323 nrf_ppi_channel_group_t channel_group)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 NRF_PPI->CHG[(uint32_t) channel_group] =
<> 144:ef7eb2e8f9f7 326 NRF_PPI->CHG[(uint32_t) channel_group] & ~(PPI_CHG_CH0_Included << ((uint32_t) channel));
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief Function for removing multiple PPI channels from a channel group.
<> 144:ef7eb2e8f9f7 331 *
<> 144:ef7eb2e8f9f7 332 * @details This function removes all specified channels from the group.
<> 144:ef7eb2e8f9f7 333 *
<> 144:ef7eb2e8f9f7 334 * @param[in] channel_mask Channels to be removed from the group.
<> 144:ef7eb2e8f9f7 335 *
<> 144:ef7eb2e8f9f7 336 * @param[in] channel_group Channel group.
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338 __STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask,
<> 144:ef7eb2e8f9f7 339 nrf_ppi_channel_group_t channel_group)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 NRF_PPI->CHG[(uint32_t) channel_group] =
<> 144:ef7eb2e8f9f7 342 NRF_PPI->CHG[(uint32_t) channel_group] & ~(channel_mask);
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /**
<> 144:ef7eb2e8f9f7 347 * @brief Function for removing all PPI channels from a channel group.
<> 144:ef7eb2e8f9f7 348 *
<> 144:ef7eb2e8f9f7 349 * @param[in] group Channel group.
<> 144:ef7eb2e8f9f7 350 *
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 __STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 NRF_PPI->CHG[(uint32_t) group] = 0;
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /**
<> 144:ef7eb2e8f9f7 359 * @brief Function for enabling a channel group.
<> 144:ef7eb2e8f9f7 360 *
<> 144:ef7eb2e8f9f7 361 * @param[in] group Channel group.
<> 144:ef7eb2e8f9f7 362 *
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364 __STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 NRF_PPI->TASKS_CHG[(uint32_t) group].EN = NRF_PPI_TASK_SET;
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /**
<> 144:ef7eb2e8f9f7 371 * @brief Function for disabling a channel group.
<> 144:ef7eb2e8f9f7 372 *
<> 144:ef7eb2e8f9f7 373 * @param[in] group Channel group.
<> 144:ef7eb2e8f9f7 374 *
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 __STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group)
<> 144:ef7eb2e8f9f7 377 {
<> 144:ef7eb2e8f9f7 378 NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = NRF_PPI_TASK_SET;
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /**
<> 144:ef7eb2e8f9f7 383 * @brief Function for setting a PPI task.
<> 144:ef7eb2e8f9f7 384 *
<> 144:ef7eb2e8f9f7 385 * @param[in] ppi_task PPI task to set.
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 __STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 *((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = NRF_PPI_TASK_SET;
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @brief Function for returning the address of a specific PPI task register.
<> 144:ef7eb2e8f9f7 395 *
<> 144:ef7eb2e8f9f7 396 * @param[in] ppi_task PPI task.
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398 __STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 return (uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task);
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /**
<> 144:ef7eb2e8f9f7 404 * @brief Function for returning the PPI enable task address of a specific group.
<> 144:ef7eb2e8f9f7 405 *
<> 144:ef7eb2e8f9f7 406 * @param[in] group PPI group.
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408 __STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group)
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].EN;
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /**
<> 144:ef7eb2e8f9f7 414 * @brief Function for returning the PPI disable task address of a specific group.
<> 144:ef7eb2e8f9f7 415 *
<> 144:ef7eb2e8f9f7 416 * @param[in] group PPI group.
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418 __STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].DIS;
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 *@}
<> 144:ef7eb2e8f9f7 426 **/
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /*lint --flb "Leave library region" */
<> 144:ef7eb2e8f9f7 429 #endif // NRF_PPI_H__