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targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_ARM_MICRO/stm32l152re.sct@180:d79f997829d6, 2017-12-18 (annotated)

Committer:
Anythingconnected
Date:
Mon Dec 18 10:14:27 2017 +0000
Revision:
180:d79f997829d6
Parent:
149:156823d33999 
Getting byte by byte read to work

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ; Scatter-Loading Description File
<> 144:ef7eb2e8f9f7 2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 144:ef7eb2e8f9f7 3 ; Copyright (c) 2014, STMicroelectronics
<> 144:ef7eb2e8f9f7 4 ; All rights reserved.
<> 144:ef7eb2e8f9f7 5 ;
<> 144:ef7eb2e8f9f7 6 ; Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 7 ; modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 8 ;
<> 144:ef7eb2e8f9f7 9 ; 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 10 ; this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 11 ; 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 12 ; this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 13 ; and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 ; 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 15 ; may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 16 ; without specific prior written permission.
<> 144:ef7eb2e8f9f7 17 ;
<> 144:ef7eb2e8f9f7 18 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 19 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 20 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 21 ; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 22 ; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 23 ; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 24 ; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 25 ; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 26 ; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 27 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 ; STM32L152RE: 512KB FLASH + 80KB SRAM
<> 144:ef7eb2e8f9f7 31 LR_IROM1 0x08000000 0x80000 { ; load region size_region
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 ER_IROM1 0x08000000 0x80000 { ; load address = execution address
<> 144:ef7eb2e8f9f7 34 *.o (RESET, +First)
<> 144:ef7eb2e8f9f7 35 *(InRoot$$Sections)
<> 144:ef7eb2e8f9f7 36 .ANY (+RO)
<> 144:ef7eb2e8f9f7 37 }
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
<> 144:ef7eb2e8f9f7 40 RW_IRAM1 (0x20000000+0x124) (0x14000-0x124) { ; RW data
<> 144:ef7eb2e8f9f7 41 .ANY (+RW +ZI)
<> 144:ef7eb2e8f9f7 42 }
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 }
<> 144:ef7eb2e8f9f7 45