anyThing Connected Team / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   BREAK_SENSOR_LED

Fork of mbed-dev by mbed official

targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/gic.h@180:d79f997829d6, 2017-12-18 (annotated)

Committer:
Anythingconnected
Date:
Mon Dec 18 10:14:27 2017 +0000
Revision:
180:d79f997829d6
Parent:
149:156823d33999 
Getting byte by byte read to work

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file gic.h
<> 144:ef7eb2e8f9f7 3 * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
<> 144:ef7eb2e8f9f7 4 * @version
<> 144:ef7eb2e8f9f7 5 * @date 29 August 2013
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * @note
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 ******************************************************************************/
<> 144:ef7eb2e8f9f7 10 /* Copyright (c) 2011 - 2013 ARM LIMITED
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 All rights reserved.
<> 144:ef7eb2e8f9f7 13 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 14 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 18 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 19 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 21 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 22 specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 34 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifndef GIC_H_
<> 144:ef7eb2e8f9f7 38 #define GIC_H_
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /* IO definitions (access restrictions to peripheral registers) */
<> 144:ef7eb2e8f9f7 41 /**
<> 144:ef7eb2e8f9f7 42 */
<> 144:ef7eb2e8f9f7 43 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 44 #define __I volatile /*!< Defines 'read only' permissions */
<> 144:ef7eb2e8f9f7 45 #else
<> 144:ef7eb2e8f9f7 46 #define __I volatile const /*!< Defines 'read only' permissions */
<> 144:ef7eb2e8f9f7 47 #endif
<> 144:ef7eb2e8f9f7 48 #define __O volatile /*!< Defines 'write only' permissions */
<> 144:ef7eb2e8f9f7 49 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53 typedef struct
<> 144:ef7eb2e8f9f7 54 {
<> 144:ef7eb2e8f9f7 55 __IO uint32_t ICDDCR;
<> 144:ef7eb2e8f9f7 56 __I uint32_t ICDICTR;
<> 144:ef7eb2e8f9f7 57 __I uint32_t ICDIIDR;
<> 144:ef7eb2e8f9f7 58 uint32_t RESERVED0[29];
<> 144:ef7eb2e8f9f7 59 __IO uint32_t ICDISR[32];
<> 144:ef7eb2e8f9f7 60 __IO uint32_t ICDISER[32];
<> 144:ef7eb2e8f9f7 61 __IO uint32_t ICDICER[32];
<> 144:ef7eb2e8f9f7 62 __IO uint32_t ICDISPR[32];
<> 144:ef7eb2e8f9f7 63 __IO uint32_t ICDICPR[32];
<> 144:ef7eb2e8f9f7 64 __I uint32_t ICDABR[32];
<> 144:ef7eb2e8f9f7 65 uint32_t RESERVED1[32];
<> 144:ef7eb2e8f9f7 66 __IO uint32_t ICDIPR[256];
<> 144:ef7eb2e8f9f7 67 __IO uint32_t ICDIPTR[256];
<> 144:ef7eb2e8f9f7 68 __IO uint32_t ICDICFR[64];
<> 144:ef7eb2e8f9f7 69 uint32_t RESERVED2[128];
<> 144:ef7eb2e8f9f7 70 __IO uint32_t ICDSGIR;
<> 144:ef7eb2e8f9f7 71 } GICDistributor_Type;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /** \brief Structure type to access the Controller Interface (GICC)
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75 typedef struct
<> 144:ef7eb2e8f9f7 76 {
<> 144:ef7eb2e8f9f7 77 __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register
<> 144:ef7eb2e8f9f7 78 __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register
<> 144:ef7eb2e8f9f7 79 __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register
<> 144:ef7eb2e8f9f7 80 __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register
<> 144:ef7eb2e8f9f7 81 __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register
<> 144:ef7eb2e8f9f7 82 __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register
<> 144:ef7eb2e8f9f7 83 __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register
<> 144:ef7eb2e8f9f7 84 __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t RESERVED[55];
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register
<> 144:ef7eb2e8f9f7 89 } GICInterface_Type;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /*@} end of GICD */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* ########################## GIC functions #################################### */
<> 144:ef7eb2e8f9f7 94 /** \brief Functions that manage interrupts via the GIC.
<> 144:ef7eb2e8f9f7 95 @{
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 Enables the forwarding of pending interrupts to the CPU interfaces.
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 void GIC_EnableDistributor(void);
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** \brief Disable Distributor
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 Disables the forwarding of pending interrupts to the CPU interfaces.
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110 void GIC_DisableDistributor(void);
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /** \brief Provides information about the configuration of the GIC.
<> 144:ef7eb2e8f9f7 113 Provides information about the configuration of the GIC.
<> 144:ef7eb2e8f9f7 114 - whether the GIC implements the Security Extensions
<> 144:ef7eb2e8f9f7 115 - the maximum number of interrupt IDs that the GIC supports
<> 144:ef7eb2e8f9f7 116 - the number of CPU interfaces implemented
<> 144:ef7eb2e8f9f7 117 - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 \return Distributor Information.
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 uint32_t GIC_DistributorInfo(void);
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** \brief Distributor Implementer Identification Register.
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 Distributor Implementer Identification Register
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 \return Implementer Information.
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 uint32_t GIC_DistributorImplementer(void);
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** \brief Set list of processors that the interrupt is sent to if it is asserted.
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
<> 144:ef7eb2e8f9f7 134 This field stores the list of processors that the interrupt is sent to if it is asserted.
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 \param [in] IRQn Interrupt number.
<> 144:ef7eb2e8f9f7 137 \param [in] target CPU target
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139 void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /** \brief Get list of processors that the interrupt is sent to if it is asserted.
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
<> 144:ef7eb2e8f9f7 144 This field stores the list of processors that the interrupt is sent to if it is asserted.
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 \param [in] IRQn Interrupt number.
<> 144:ef7eb2e8f9f7 147 \param [in] target CPU target
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 uint32_t GIC_GetTarget(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /** \brief Enable Interface
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 Enables the signalling of interrupts to the target processors.
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 void GIC_EnableInterface(void);
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /** \brief Disable Interface
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 Disables the signalling of interrupts to the target processors.
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 void GIC_DisableInterface(void);
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** \brief Acknowledge Interrupt
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 The function acknowledges the highest priority pending interrupt and returns its IRQ number.
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 \return Interrupt number
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171 IRQn_Type GIC_AcknowledgePending(void);
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /** \brief End Interrupt
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 \param [in] IRQn Interrupt number.
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179 void GIC_EndInterrupt(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /** \brief Enable Interrupt
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 Set-enable bit for each interrupt supported by the GIC.
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 \param [in] IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 void GIC_EnableIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /** \brief Disable Interrupt
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 Clear-enable bit for each interrupt supported by the GIC.
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 \param [in] IRQn Number of the external interrupt to disable
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 void GIC_DisableIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /** \brief Set Pending Interrupt
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 Set-pending bit for each interrupt supported by the GIC.
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 \param [in] IRQn Interrupt number.
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204 void GIC_SetPendingIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /** \brief Clear Pending Interrupt
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 Clear-pending bit for each interrupt supported by the GIC
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 \param [in] IRQn Number of the interrupt for clear pending
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212 void GIC_ClearPendingIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /** \brief Int_config field for each interrupt supported by the GIC.
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 This field identifies whether the corresponding interrupt is:
<> 144:ef7eb2e8f9f7 217 (1) edge-triggered or (0) level-sensitive
<> 144:ef7eb2e8f9f7 218 (1) 1-N model or (0) N-N model
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 \param [in] IRQn Interrupt number.
<> 144:ef7eb2e8f9f7 221 \param [in] edge_level (1) edge-triggered or (0) level-sensitive
<> 144:ef7eb2e8f9f7 222 \param [in] model (1) 1-N model or (0) N-N model
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** \brief Set Interrupt Priority
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 The function sets the priority of an interrupt.
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 \param [in] IRQn Interrupt number.
<> 144:ef7eb2e8f9f7 232 \param [in] priority Priority to set.
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234 void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /** \brief Get Interrupt Priority
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 The function reads the priority of an interrupt.
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 \param [in] IRQn Interrupt number.
<> 144:ef7eb2e8f9f7 241 \return Interrupt Priority.
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 uint32_t GIC_GetPriority(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /** \brief CPU Interface Priority Mask Register
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
<> 144:ef7eb2e8f9f7 248 value indicated by this field, the interface signals the interrupt to the processor.
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 \param [in] Mask.
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 void GIC_InterfacePriorityMask(uint32_t priority);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /** \brief Set the binary point.
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 \param [in] Mask.
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 void GIC_SetBinaryPoint(uint32_t binary_point);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /** \brief Get the binary point.
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 \return Binary point.
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /** \brief Get Interrupt state.
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 Get the interrupt state, whether pending and/or active
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /** \brief Send Software Generated interrupt
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
<> 144:ef7eb2e8f9f7 281 GIC_InterfacePriorityMask
<> 144:ef7eb2e8f9f7 282 \param [in] IRQn The Interrupt ID of the SGI.
<> 144:ef7eb2e8f9f7 283 \param [in] target_list CPUTargetList
<> 144:ef7eb2e8f9f7 284 \param [in] filter_list TargetListFilter
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /** \brief API call to initialise the interrupt distributor
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 API call to initialise the interrupt distributor
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 void GIC_DistInit(void);
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /** \brief API call to initialise the CPU interface
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 API call to initialise the CPU interface
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 void GIC_CPUInterfaceInit(void);
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /** \brief API call to set the Interrupt Configuration Registers
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 API call to initialise the Interrupt Configuration Registers
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307 void GIC_SetICDICFR (const uint32_t *ICDICFRn);
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /** \brief API call to Enable the GIC
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 API call to Enable the GIC
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314 void GIC_Enable(void);
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 #endif /* GIC_H_ */