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targets/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c@180:d79f997829d6, 2017-12-18 (annotated)

Committer:
Anythingconnected
Date:
Mon Dec 18 10:14:27 2017 +0000
Revision:
180:d79f997829d6
Parent:
149:156823d33999 
Getting byte by byte read to work

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include <stddef.h>
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 19 #include "gpio_irq_api.h"
<> 144:ef7eb2e8f9f7 20 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 #define CHANNEL_NUM 8
<> 144:ef7eb2e8f9f7 23 #define LPC_GPIO_X LPC_PIN_INT
<> 144:ef7eb2e8f9f7 24 #define PININT_IRQ PININT0_IRQn
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
<> 144:ef7eb2e8f9f7 27 static gpio_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 static inline void handle_interrupt_in(uint32_t channel) {
<> 144:ef7eb2e8f9f7 30 uint32_t ch_bit = (1 << channel);
<> 144:ef7eb2e8f9f7 31 // Return immediately if:
<> 144:ef7eb2e8f9f7 32 // * The interrupt was already served
<> 144:ef7eb2e8f9f7 33 // * There is no user handler
<> 144:ef7eb2e8f9f7 34 // * It is a level interrupt, not an edge interrupt
<> 144:ef7eb2e8f9f7 35 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
<> 144:ef7eb2e8f9f7 36 (channel_ids[channel] == 0 ) ||
<> 144:ef7eb2e8f9f7 37 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
<> 144:ef7eb2e8f9f7 40 irq_handler(channel_ids[channel], IRQ_RISE);
<> 144:ef7eb2e8f9f7 41 LPC_GPIO_X->RISE = ch_bit;
<> 144:ef7eb2e8f9f7 42 }
<> 144:ef7eb2e8f9f7 43 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
<> 144:ef7eb2e8f9f7 44 irq_handler(channel_ids[channel], IRQ_FALL);
<> 144:ef7eb2e8f9f7 45 }
<> 144:ef7eb2e8f9f7 46 LPC_GPIO_X->IST = ch_bit;
<> 144:ef7eb2e8f9f7 47 }
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 void gpio_irq0(void) {handle_interrupt_in(0);}
<> 144:ef7eb2e8f9f7 50 void gpio_irq1(void) {handle_interrupt_in(1);}
<> 144:ef7eb2e8f9f7 51 void gpio_irq2(void) {handle_interrupt_in(2);}
<> 144:ef7eb2e8f9f7 52 void gpio_irq3(void) {handle_interrupt_in(3);}
<> 144:ef7eb2e8f9f7 53 void gpio_irq4(void) {handle_interrupt_in(4);}
<> 144:ef7eb2e8f9f7 54 void gpio_irq5(void) {handle_interrupt_in(5);}
<> 144:ef7eb2e8f9f7 55 void gpio_irq6(void) {handle_interrupt_in(6);}
<> 144:ef7eb2e8f9f7 56 void gpio_irq7(void) {handle_interrupt_in(7);}
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
<> 144:ef7eb2e8f9f7 59 if (pin == NC) return -1;
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 irq_handler = handler;
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 int found_free_channel = 0;
<> 144:ef7eb2e8f9f7 64 int i = 0;
<> 144:ef7eb2e8f9f7 65 for (i=0; i<CHANNEL_NUM; i++) {
<> 144:ef7eb2e8f9f7 66 if (channel_ids[i] == 0) {
<> 144:ef7eb2e8f9f7 67 channel_ids[i] = id;
<> 144:ef7eb2e8f9f7 68 obj->ch = i;
<> 144:ef7eb2e8f9f7 69 found_free_channel = 1;
<> 144:ef7eb2e8f9f7 70 break;
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72 }
<> 144:ef7eb2e8f9f7 73 if (!found_free_channel) return -1;
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* Enable AHB clock to the GPIO domain. */
<> 144:ef7eb2e8f9f7 76 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 LPC_SYSCON->PINTSEL[obj->ch] = pin;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 // Interrupt Wake-Up Enable
<> 144:ef7eb2e8f9f7 81 LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 void (*channels_irq)(void) = NULL;
<> 144:ef7eb2e8f9f7 84 switch (obj->ch) {
<> 144:ef7eb2e8f9f7 85 case 0: channels_irq = &gpio_irq0; break;
<> 144:ef7eb2e8f9f7 86 case 1: channels_irq = &gpio_irq1; break;
<> 144:ef7eb2e8f9f7 87 case 2: channels_irq = &gpio_irq2; break;
<> 144:ef7eb2e8f9f7 88 case 3: channels_irq = &gpio_irq3; break;
<> 144:ef7eb2e8f9f7 89 case 4: channels_irq = &gpio_irq4; break;
<> 144:ef7eb2e8f9f7 90 case 5: channels_irq = &gpio_irq5; break;
<> 144:ef7eb2e8f9f7 91 case 6: channels_irq = &gpio_irq6; break;
<> 144:ef7eb2e8f9f7 92 case 7: channels_irq = &gpio_irq7; break;
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
<> 144:ef7eb2e8f9f7 95 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 return 0;
<> 144:ef7eb2e8f9f7 98 }
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 void gpio_irq_free(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 101 channel_ids[obj->ch] = 0;
<> 144:ef7eb2e8f9f7 102 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
<> 144:ef7eb2e8f9f7 103 }
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
<> 144:ef7eb2e8f9f7 106 unsigned int ch_bit = (1 << obj->ch);
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 // Clear interrupt
<> 144:ef7eb2e8f9f7 109 if (!(LPC_GPIO_X->ISEL & ch_bit))
<> 144:ef7eb2e8f9f7 110 LPC_GPIO_X->IST = ch_bit;
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 // Edge trigger
<> 144:ef7eb2e8f9f7 113 LPC_GPIO_X->ISEL &= ~ch_bit;
<> 144:ef7eb2e8f9f7 114 if (event == IRQ_RISE) {
<> 144:ef7eb2e8f9f7 115 if (enable) {
<> 144:ef7eb2e8f9f7 116 LPC_GPIO_X->IENR |= ch_bit;
<> 144:ef7eb2e8f9f7 117 } else {
<> 144:ef7eb2e8f9f7 118 LPC_GPIO_X->IENR &= ~ch_bit;
<> 144:ef7eb2e8f9f7 119 }
<> 144:ef7eb2e8f9f7 120 } else {
<> 144:ef7eb2e8f9f7 121 if (enable) {
<> 144:ef7eb2e8f9f7 122 LPC_GPIO_X->IENF |= ch_bit;
<> 144:ef7eb2e8f9f7 123 } else {
<> 144:ef7eb2e8f9f7 124 LPC_GPIO_X->IENF &= ~ch_bit;
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126 }
<> 144:ef7eb2e8f9f7 127 }
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 void gpio_irq_enable(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 130 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 void gpio_irq_disable(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 134 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
<> 144:ef7eb2e8f9f7 135 }