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targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S@180:d79f997829d6, 2017-12-18 (annotated)

Committer:
Anythingconnected
Date:
Mon Dec 18 10:14:27 2017 +0000
Revision:
180:d79f997829d6
Parent:
149:156823d33999 
Getting byte by byte read to work

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /*******************************************************************************
<> 149:156823d33999 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 149:156823d33999 5 * copy of this software and associated documentation files (the "Software"),
<> 149:156823d33999 6 * to deal in the Software without restriction, including without limitation
<> 149:156823d33999 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 149:156823d33999 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 149:156823d33999 9 * Software is furnished to do so, subject to the following conditions:
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * The above copyright notice and this permission notice shall be included
<> 149:156823d33999 12 * in all copies or substantial portions of the Software.
<> 149:156823d33999 13 *
<> 149:156823d33999 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 149:156823d33999 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 149:156823d33999 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 149:156823d33999 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 149:156823d33999 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 149:156823d33999 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 149:156823d33999 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * Except as contained in this notice, the name of Maxim Integrated
<> 149:156823d33999 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 149:156823d33999 24 * Products, Inc. Branding Policy.
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * The mere transfer of this software does not imply any licenses
<> 149:156823d33999 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 149:156823d33999 28 * trademarks, maskwork rights, or any other form of intellectual
<> 149:156823d33999 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 149:156823d33999 30 * ownership rights.
<> 149:156823d33999 31 *******************************************************************************
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34 .syntax unified
<> 149:156823d33999 35 .arch armv7-m
<> 149:156823d33999 36
<> 149:156823d33999 37 /* Memory Model
<> 149:156823d33999 38 The HEAP starts at the end of the DATA section and grows upward.
<> 149:156823d33999 39
<> 149:156823d33999 40 The STACK starts at the end of the RAM and grows downward.
<> 149:156823d33999 41
<> 149:156823d33999 42 The HEAP and stack STACK are only checked at compile time:
<> 149:156823d33999 43 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
<> 149:156823d33999 44
<> 149:156823d33999 45 This is just a check for the bare minimum for the Heap+Stack area before
<> 149:156823d33999 46 aborting compilation, it is not the run time limit:
<> 149:156823d33999 47 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
<> 149:156823d33999 48 */
<> 149:156823d33999 49 .section .stack
<> 149:156823d33999 50 .align 3
<> 149:156823d33999 51 #ifdef __STACK_SIZE
<> 149:156823d33999 52 .equ Stack_Size, __STACK_SIZE
<> 149:156823d33999 53 #else
<> 149:156823d33999 54 .equ Stack_Size, 0x00001000
<> 149:156823d33999 55 #endif
<> 149:156823d33999 56 .globl __StackTop
<> 149:156823d33999 57 .globl __StackLimit
<> 149:156823d33999 58 __StackLimit:
<> 149:156823d33999 59 .space Stack_Size
<> 149:156823d33999 60 .size __StackLimit, . - __StackLimit
<> 149:156823d33999 61 __StackTop:
<> 149:156823d33999 62 .size __StackTop, . - __StackTop
<> 149:156823d33999 63
<> 149:156823d33999 64 .section .heap
<> 149:156823d33999 65 .align 3
<> 149:156823d33999 66 #ifdef __HEAP_SIZE
<> 149:156823d33999 67 .equ Heap_Size, __HEAP_SIZE
<> 149:156823d33999 68 #else
<> 149:156823d33999 69 .equ Heap_Size, 0x00004000
<> 149:156823d33999 70 #endif
<> 149:156823d33999 71 .globl __HeapBase
<> 149:156823d33999 72 .globl __HeapLimit
<> 149:156823d33999 73 __HeapBase:
<> 149:156823d33999 74 .space Heap_Size
<> 149:156823d33999 75 .size __HeapBase, . - __HeapBase
<> 149:156823d33999 76 __HeapLimit:
<> 149:156823d33999 77 .size __HeapLimit, . - __HeapLimit
<> 149:156823d33999 78
<> 149:156823d33999 79 .section .isr_vector
<> 149:156823d33999 80 .align 2
<> 149:156823d33999 81 .globl __isr_vector
<> 149:156823d33999 82 __isr_vector:
<> 149:156823d33999 83 .long __StackTop /* Top of Stack */
<> 149:156823d33999 84 .long Reset_Handler /* Reset Handler */
<> 149:156823d33999 85 .long NMI_Handler /* NMI Handler */
<> 149:156823d33999 86 .long HardFault_Handler /* Hard Fault Handler */
<> 149:156823d33999 87 .long MemManage_Handler /* MPU Fault Handler */
<> 149:156823d33999 88 .long BusFault_Handler /* Bus Fault Handler */
<> 149:156823d33999 89 .long UsageFault_Handler /* Usage Fault Handler */
<> 149:156823d33999 90 .long 0 /* Reserved */
<> 149:156823d33999 91 .long 0 /* Reserved */
<> 149:156823d33999 92 .long 0 /* Reserved */
<> 149:156823d33999 93 .long 0 /* Reserved */
<> 149:156823d33999 94 .long SVC_Handler /* SVCall Handler */
<> 149:156823d33999 95 .long DebugMon_Handler /* Debug Monitor Handler */
<> 149:156823d33999 96 .long 0 /* Reserved */
<> 149:156823d33999 97 .long PendSV_Handler /* PendSV Handler */
<> 149:156823d33999 98 .long SysTick_Handler /* SysTick Handler */
<> 149:156823d33999 99
<> 149:156823d33999 100 /* Externals interrupts */
<> 149:156823d33999 101 .long CLKMAN_IRQHandler /* 16:01 CLKMAN */
<> 149:156823d33999 102 .long PWRMAN_IRQHandler /* 17:02 PWRMAN */
<> 149:156823d33999 103 .long FLC_IRQHandler /* 18:03 Flash Controller */
<> 149:156823d33999 104 .long RTC0_IRQHandler /* 19:04 RTC INT0 */
<> 149:156823d33999 105 .long RTC1_IRQHandler /* 20:05 RTC INT1 */
<> 149:156823d33999 106 .long RTC2_IRQHandler /* 21:06 RTC INT2 */
<> 149:156823d33999 107 .long RTC3_IRQHandler /* 22:07 RTC INT3 */
<> 149:156823d33999 108 .long PMU_IRQHandler /* 23:08 PMU */
<> 149:156823d33999 109 .long USB_IRQHandler /* 24:09 USB */
<> 149:156823d33999 110 .long AES_IRQHandler /* 25:10 AES */
<> 149:156823d33999 111 .long MAA_IRQHandler /* 26:11 MAA */
<> 149:156823d33999 112 .long WDT0_IRQHandler /* 27:12 WATCHDOG0 */
<> 149:156823d33999 113 .long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
<> 149:156823d33999 114 .long WDT1_IRQHandler /* 29:14 WATCHDOG1 */
<> 149:156823d33999 115 .long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
<> 149:156823d33999 116 .long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
<> 149:156823d33999 117 .long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
<> 149:156823d33999 118 .long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
<> 149:156823d33999 119 .long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
<> 149:156823d33999 120 .long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
<> 149:156823d33999 121 .long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
<> 149:156823d33999 122 .long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
<> 149:156823d33999 123 .long TMR0_IRQHandler /* 38:23 Timer32-0 */
<> 149:156823d33999 124 .long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
<> 149:156823d33999 125 .long TMR1_IRQHandler /* 40:25 Timer32-1 */
<> 149:156823d33999 126 .long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
<> 149:156823d33999 127 .long TMR2_IRQHandler /* 42:27 Timer32-2 */
<> 149:156823d33999 128 .long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
<> 149:156823d33999 129 .long TMR3_IRQHandler /* 44:29 Timer32-3 */
<> 149:156823d33999 130 .long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
<> 149:156823d33999 131 .long TMR4_IRQHandler /* 46:31 Timer32-4 */
<> 149:156823d33999 132 .long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
<> 149:156823d33999 133 .long TMR5_IRQHandler /* 48:33 Timer32-5 */
<> 149:156823d33999 134 .long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
<> 149:156823d33999 135 .long UART0_IRQHandler /* 50:35 UART0 */
<> 149:156823d33999 136 .long UART1_IRQHandler /* 51:36 UART1 */
<> 149:156823d33999 137 .long UART2_IRQHandler /* 52:37 UART0 */
<> 149:156823d33999 138 .long UART3_IRQHandler /* 53:38 UART1 */
<> 149:156823d33999 139 .long PT_IRQHandler /* 54:39 PT */
<> 149:156823d33999 140 .long I2CM0_IRQHandler /* 55:40 I2C Master 0 */
<> 149:156823d33999 141 .long I2CM1_IRQHandler /* 56:41 I2C Master 1 */
<> 149:156823d33999 142 .long I2CM2_IRQHandler /* 57:42 I2C Master 2 */
<> 149:156823d33999 143 .long I2CS_IRQHandler /* 58:43 I2C Slave */
<> 149:156823d33999 144 .long SPI0_IRQHandler /* 59:44 SPI0 */
<> 149:156823d33999 145 .long SPI1_IRQHandler /* 60:45 SPI1 */
<> 149:156823d33999 146 .long SPI2_IRQHandler /* 61:46 SPI2 */
<> 149:156823d33999 147 .long SPIB_IRQHandler /* 62:47 SPI Bridge */
<> 149:156823d33999 148 .long OWM_IRQHandler /* 63:48 1-Wire Master */
<> 149:156823d33999 149 .long AFE_IRQHandler /* 64:49 AFE */
<> 149:156823d33999 150
<> 149:156823d33999 151 .text
<> 149:156823d33999 152 .thumb
<> 149:156823d33999 153 .thumb_func
<> 149:156823d33999 154 .align 2
<> 149:156823d33999 155 .globl Reset_Handler
<> 149:156823d33999 156 .type Reset_Handler, %function
<> 149:156823d33999 157 Reset_Handler:
<> 149:156823d33999 158 /* In order to have the same boot sequence with all Toolchains, we must call
<> 149:156823d33999 159 * SystemInit before initalizing the data segments, and calling the static
<> 149:156823d33999 160 * initalization. */
<> 149:156823d33999 161 ldr r0, =SystemInit
<> 149:156823d33999 162 blx r0
<> 149:156823d33999 163
<> 149:156823d33999 164 /* Loop to copy data from read only memory to RAM. The ranges
<> 149:156823d33999 165 * of copy from/to are specified by following symbols evaluated in
<> 149:156823d33999 166 * linker script.
<> 149:156823d33999 167 * __etext: End of code section, i.e., begin of data sections to copy from.
<> 149:156823d33999 168 * __data_start__/__data_end__: RAM address range that data should be
<> 149:156823d33999 169 * copied to. Both must be aligned to 4 bytes boundary. */
<> 149:156823d33999 170
<> 149:156823d33999 171 ldr r1, =__etext
<> 149:156823d33999 172 ldr r2, =__data_start__
<> 149:156823d33999 173 ldr r3, =__data_end__
<> 149:156823d33999 174
<> 149:156823d33999 175 .Lflash_to_ram_loop:
<> 149:156823d33999 176 cmp r2, r3
<> 149:156823d33999 177 ittt lt
<> 149:156823d33999 178 ldrlt r0, [r1], #4
<> 149:156823d33999 179 strlt r0, [r2], #4
<> 149:156823d33999 180 blt .Lflash_to_ram_loop
<> 149:156823d33999 181
<> 149:156823d33999 182 .Lflash_to_ram_loop_end:
<> 149:156823d33999 183 ldr r0, =_start
<> 149:156823d33999 184 bx r0
<> 149:156823d33999 185 .pool
<> 149:156823d33999 186 .size Reset_Handler, . - Reset_Handler
<> 149:156823d33999 187
<> 149:156823d33999 188 .text
<> 149:156823d33999 189 /* Macro to define default handlers. Default handler
<> 149:156823d33999 190 * will be weak symbol and just dead loops. They can be
<> 149:156823d33999 191 * overwritten by other handlers */
<> 149:156823d33999 192 .macro def_default_handler handler_name
<> 149:156823d33999 193 .align 1
<> 149:156823d33999 194 .thumb_func
<> 149:156823d33999 195 .weak \handler_name
<> 149:156823d33999 196 .type \handler_name, %function
<> 149:156823d33999 197 \handler_name :
<> 149:156823d33999 198 b .
<> 149:156823d33999 199 .size \handler_name, . - \handler_name
<> 149:156823d33999 200 .endm
<> 149:156823d33999 201
<> 149:156823d33999 202 def_default_handler NMI_Handler
<> 149:156823d33999 203 def_default_handler HardFault_Handler
<> 149:156823d33999 204 def_default_handler MemManage_Handler
<> 149:156823d33999 205 def_default_handler BusFault_Handler
<> 149:156823d33999 206 def_default_handler UsageFault_Handler
<> 149:156823d33999 207 def_default_handler SVC_Handler
<> 149:156823d33999 208 def_default_handler DebugMon_Handler
<> 149:156823d33999 209 def_default_handler PendSV_Handler
<> 149:156823d33999 210 def_default_handler SysTick_Handler
<> 149:156823d33999 211 def_default_handler Default_Handler
<> 149:156823d33999 212
<> 149:156823d33999 213 .macro def_irq_default_handler handler_name
<> 149:156823d33999 214 .weak \handler_name
<> 149:156823d33999 215 .set \handler_name, Default_Handler
<> 149:156823d33999 216 .endm
<> 149:156823d33999 217
<> 149:156823d33999 218 def_irq_default_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */
<> 149:156823d33999 219 def_irq_default_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */
<> 149:156823d33999 220 def_irq_default_handler FLC_IRQHandler /* 18:03 Flash Controller */
<> 149:156823d33999 221 def_irq_default_handler RTC0_IRQHandler /* 19:04 RTC INT0 */
<> 149:156823d33999 222 def_irq_default_handler RTC1_IRQHandler /* 20:05 RTC INT1 */
<> 149:156823d33999 223 def_irq_default_handler RTC2_IRQHandler /* 21:06 RTC INT2 */
<> 149:156823d33999 224 def_irq_default_handler RTC3_IRQHandler /* 22:07 RTC INT3 */
<> 149:156823d33999 225 def_irq_default_handler PMU_IRQHandler /* 23:08 PMU */
<> 149:156823d33999 226 def_irq_default_handler USB_IRQHandler /* 24:09 USB */
<> 149:156823d33999 227 def_irq_default_handler AES_IRQHandler /* 25:10 AES */
<> 149:156823d33999 228 def_irq_default_handler MAA_IRQHandler /* 26:11 MAA */
<> 149:156823d33999 229 def_irq_default_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */
<> 149:156823d33999 230 def_irq_default_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
<> 149:156823d33999 231 def_irq_default_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */
<> 149:156823d33999 232 def_irq_default_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
<> 149:156823d33999 233 def_irq_default_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
<> 149:156823d33999 234 def_irq_default_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
<> 149:156823d33999 235 def_irq_default_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
<> 149:156823d33999 236 def_irq_default_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
<> 149:156823d33999 237 def_irq_default_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
<> 149:156823d33999 238 def_irq_default_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
<> 149:156823d33999 239 def_irq_default_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
<> 149:156823d33999 240 def_irq_default_handler TMR0_IRQHandler /* 38:23 Timer32-0 */
<> 149:156823d33999 241 def_irq_default_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
<> 149:156823d33999 242 def_irq_default_handler TMR1_IRQHandler /* 40:25 Timer32-1 */
<> 149:156823d33999 243 def_irq_default_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
<> 149:156823d33999 244 def_irq_default_handler TMR2_IRQHandler /* 42:27 Timer32-2 */
<> 149:156823d33999 245 def_irq_default_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
<> 149:156823d33999 246 def_irq_default_handler TMR3_IRQHandler /* 44:29 Timer32-3 */
<> 149:156823d33999 247 def_irq_default_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
<> 149:156823d33999 248 def_irq_default_handler TMR4_IRQHandler /* 46:31 Timer32-4 */
<> 149:156823d33999 249 def_irq_default_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
<> 149:156823d33999 250 def_irq_default_handler TMR5_IRQHandler /* 48:33 Timer32-5 */
<> 149:156823d33999 251 def_irq_default_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
<> 149:156823d33999 252 def_irq_default_handler PT_IRQHandler /* 50:35 PT */
<> 149:156823d33999 253 def_irq_default_handler UART0_IRQHandler /* 51:36 UART0 */
<> 149:156823d33999 254 def_irq_default_handler UART1_IRQHandler /* 52:37 UART1 */
<> 149:156823d33999 255 def_irq_default_handler UART2_IRQHandler /* 53:38 UART0 */
<> 149:156823d33999 256 def_irq_default_handler UART3_IRQHandler /* 54:39 UART1 */
<> 149:156823d33999 257 def_irq_default_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */
<> 149:156823d33999 258 def_irq_default_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */
<> 149:156823d33999 259 def_irq_default_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */
<> 149:156823d33999 260 def_irq_default_handler I2CS_IRQHandler /* 58:43 I2C Slave */
<> 149:156823d33999 261 def_irq_default_handler SPI0_IRQHandler /* 59:44 SPI0 */
<> 149:156823d33999 262 def_irq_default_handler SPI1_IRQHandler /* 60:45 SPI1 */
<> 149:156823d33999 263 def_irq_default_handler SPI2_IRQHandler /* 61:46 SPI2 */
<> 149:156823d33999 264 def_irq_default_handler SPIB_IRQHandler /* 62:47 SPI Bridge */
<> 149:156823d33999 265 def_irq_default_handler OWM_IRQHandler /* 63:48 SPI Bridge */
<> 149:156823d33999 266 def_irq_default_handler AFE_IRQHandler /* 64:49 AFE */
<> 149:156823d33999 267
<> 149:156823d33999 268 .end
<> 149:156823d33999 269