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targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h@180:d79f997829d6, 2017-12-18 (annotated)
- Committer:
- Anythingconnected
- Date:
- Mon Dec 18 10:14:27 2017 +0000
- Revision:
- 180:d79f997829d6
- Parent:
- 178:79309dc6340a
Getting byte by byte read to work
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 178:79309dc6340a | 1 | /*! |
| AnnaBridge | 178:79309dc6340a | 2 | ***************************************************************************** |
| AnnaBridge | 178:79309dc6340a | 3 | @file: adi_rtc_config.h |
| AnnaBridge | 178:79309dc6340a | 4 | @brief: Configuration options for Real Time Clock device driver. |
| AnnaBridge | 178:79309dc6340a | 5 | This is specific to the RTC driver and will be included by the driver. |
| AnnaBridge | 178:79309dc6340a | 6 | It is not required for the application to include this header file. |
| AnnaBridge | 178:79309dc6340a | 7 | @version: $Revision: 33005 $ |
| AnnaBridge | 178:79309dc6340a | 8 | @date: $Date: 2015-12-12 10:43:13 -0500 (Sat, 12 Dec 2015) $ |
| AnnaBridge | 178:79309dc6340a | 9 | ----------------------------------------------------------------------------- |
| AnnaBridge | 178:79309dc6340a | 10 | |
| AnnaBridge | 178:79309dc6340a | 11 | Copyright (c) 2012-2016 Analog Devices, Inc. |
| AnnaBridge | 178:79309dc6340a | 12 | |
| AnnaBridge | 178:79309dc6340a | 13 | All rights reserved. |
| AnnaBridge | 178:79309dc6340a | 14 | |
| AnnaBridge | 178:79309dc6340a | 15 | Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 178:79309dc6340a | 16 | are permitted provided that the following conditions are met: |
| AnnaBridge | 178:79309dc6340a | 17 | - Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 178:79309dc6340a | 18 | this list of conditions and the following disclaimer. |
| AnnaBridge | 178:79309dc6340a | 19 | - Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 178:79309dc6340a | 20 | this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 178:79309dc6340a | 21 | and/or other materials provided with the distribution. |
| AnnaBridge | 178:79309dc6340a | 22 | - Modified versions of the software must be conspicuously marked as such. |
| AnnaBridge | 178:79309dc6340a | 23 | - This software is licensed solely and exclusively for use with processors |
| AnnaBridge | 178:79309dc6340a | 24 | manufactured by or for Analog Devices, Inc. |
| AnnaBridge | 178:79309dc6340a | 25 | - This software may not be combined or merged with other code in any manner |
| AnnaBridge | 178:79309dc6340a | 26 | that would cause the software to become subject to terms and conditions |
| AnnaBridge | 178:79309dc6340a | 27 | which differ from those listed here. |
| AnnaBridge | 178:79309dc6340a | 28 | - Neither the name of Analog Devices, Inc. nor the names of its |
| AnnaBridge | 178:79309dc6340a | 29 | contributors may be used to endorse or promote products derived |
| AnnaBridge | 178:79309dc6340a | 30 | from this software without specific prior written permission. |
| AnnaBridge | 178:79309dc6340a | 31 | - The use of this software may or may not infringe the patent rights of one |
| AnnaBridge | 178:79309dc6340a | 32 | or more patent holders. This license does not release you from the |
| AnnaBridge | 178:79309dc6340a | 33 | requirement that you obtain separate licenses from these patent holders |
| AnnaBridge | 178:79309dc6340a | 34 | to use this software. |
| AnnaBridge | 178:79309dc6340a | 35 | |
| AnnaBridge | 178:79309dc6340a | 36 | THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY |
| AnnaBridge | 178:79309dc6340a | 37 | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, |
| AnnaBridge | 178:79309dc6340a | 38 | TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| AnnaBridge | 178:79309dc6340a | 39 | NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
| AnnaBridge | 178:79309dc6340a | 40 | INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES |
| AnnaBridge | 178:79309dc6340a | 41 | (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL |
| AnnaBridge | 178:79309dc6340a | 42 | PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| AnnaBridge | 178:79309dc6340a | 43 | OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| AnnaBridge | 178:79309dc6340a | 44 | THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| AnnaBridge | 178:79309dc6340a | 45 | NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
| AnnaBridge | 178:79309dc6340a | 46 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 178:79309dc6340a | 47 | |
| AnnaBridge | 178:79309dc6340a | 48 | *****************************************************************************/ |
| AnnaBridge | 178:79309dc6340a | 49 | |
| AnnaBridge | 178:79309dc6340a | 50 | #ifndef ADI_RTC_CONFIG_H__ |
| AnnaBridge | 178:79309dc6340a | 51 | #define ADI_RTC_CONFIG_H__ |
| AnnaBridge | 178:79309dc6340a | 52 | #include <adi_global_config.h> |
| AnnaBridge | 178:79309dc6340a | 53 | |
| AnnaBridge | 178:79309dc6340a | 54 | /** @addtogroup RTC_Driver_Config Static Configuration |
| AnnaBridge | 178:79309dc6340a | 55 | * @ingroup RTC_Driver |
| AnnaBridge | 178:79309dc6340a | 56 | * @{ |
| AnnaBridge | 178:79309dc6340a | 57 | */ |
| AnnaBridge | 178:79309dc6340a | 58 | |
| AnnaBridge | 178:79309dc6340a | 59 | /*! |
| AnnaBridge | 178:79309dc6340a | 60 | * The safe write mode insures any pending writes that have not yet synchronized between the faster core clock |
| AnnaBridge | 178:79309dc6340a | 61 | * domain and the internal RTC 32kHz clock domain are reconciled before multiple writes to the same RTC register |
| AnnaBridge | 178:79309dc6340a | 62 | * are allowed |
| AnnaBridge | 178:79309dc6340a | 63 | */ |
| AnnaBridge | 178:79309dc6340a | 64 | |
| AnnaBridge | 178:79309dc6340a | 65 | #define ADI_RTC_CFG_ENABLE_SAFE_WRITE 1 |
| AnnaBridge | 178:79309dc6340a | 66 | |
| AnnaBridge | 178:79309dc6340a | 67 | |
| AnnaBridge | 178:79309dc6340a | 68 | /** @addtogroup RTC_Driver_Config_RTC0 RTC0 Static Configuration |
| AnnaBridge | 178:79309dc6340a | 69 | * @ingroup RTC_Driver_Config |
| AnnaBridge | 178:79309dc6340a | 70 | * @{ |
| AnnaBridge | 178:79309dc6340a | 71 | */ |
| AnnaBridge | 178:79309dc6340a | 72 | |
| AnnaBridge | 178:79309dc6340a | 73 | /* |
| AnnaBridge | 178:79309dc6340a | 74 | =================================================================== |
| AnnaBridge | 178:79309dc6340a | 75 | ------------------------RTC-0 CONFIGURATION MACRO----------------- |
| AnnaBridge | 178:79309dc6340a | 76 | =================================================================== |
| AnnaBridge | 178:79309dc6340a | 77 | */ |
| AnnaBridge | 178:79309dc6340a | 78 | /*! Enable the Alarm */ |
| AnnaBridge | 178:79309dc6340a | 79 | #define RTC0_CFG_ENABLE_ALARM 0 |
| AnnaBridge | 178:79309dc6340a | 80 | |
| AnnaBridge | 178:79309dc6340a | 81 | /*! Enable the Alarm interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 82 | #define RTC0_CFG_ENABLE_ALARM_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 83 | |
| AnnaBridge | 178:79309dc6340a | 84 | /*! Enable the Trim */ |
| AnnaBridge | 178:79309dc6340a | 85 | #define RTC0_CFG_ENABLE_TRIM 0 |
| AnnaBridge | 178:79309dc6340a | 86 | |
| AnnaBridge | 178:79309dc6340a | 87 | /*! Enable the PENDERROR interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 88 | #define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 89 | |
| AnnaBridge | 178:79309dc6340a | 90 | /*! Enable the write sync interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 91 | #define RTC0_CFG_ENABLE_WSYNC_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 92 | |
| AnnaBridge | 178:79309dc6340a | 93 | /*! Enable the pend write interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 94 | #define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 95 | |
| AnnaBridge | 178:79309dc6340a | 96 | /*! Initial the count Value*/ |
| AnnaBridge | 178:79309dc6340a | 97 | #define RTC0_CFG_COUNT_VALUE 0 |
| AnnaBridge | 178:79309dc6340a | 98 | |
| AnnaBridge | 178:79309dc6340a | 99 | /*! Initial the count Value-0*/ |
| AnnaBridge | 178:79309dc6340a | 100 | #define RTC0_CFG_COUNT_VALUE_0 0 |
| AnnaBridge | 178:79309dc6340a | 101 | |
| AnnaBridge | 178:79309dc6340a | 102 | /*! Initial the count Value-1*/ |
| AnnaBridge | 178:79309dc6340a | 103 | #define RTC0_CFG_COUNT_VALUE_1 0 |
| AnnaBridge | 178:79309dc6340a | 104 | |
| AnnaBridge | 178:79309dc6340a | 105 | /*! Alarm-0 Value*/ |
| AnnaBridge | 178:79309dc6340a | 106 | #define RTC0_CFG_ALARM_VALUE_0 0 |
| AnnaBridge | 178:79309dc6340a | 107 | |
| AnnaBridge | 178:79309dc6340a | 108 | /*! Alarm-1 Value*/ |
| AnnaBridge | 178:79309dc6340a | 109 | #define RTC0_CFG_ALARM_VALUE_1 0 |
| AnnaBridge | 178:79309dc6340a | 110 | |
| AnnaBridge | 178:79309dc6340a | 111 | /*! Trim interval*/ |
| AnnaBridge | 178:79309dc6340a | 112 | #define RTC0_CFG_TRIM_INTERVAL 0 |
| AnnaBridge | 178:79309dc6340a | 113 | |
| AnnaBridge | 178:79309dc6340a | 114 | /*! Trim interval with power of 2*/ |
| AnnaBridge | 178:79309dc6340a | 115 | #define RTC0_CFG_POW2_TRIM_INTERVAL 0 |
| AnnaBridge | 178:79309dc6340a | 116 | |
| AnnaBridge | 178:79309dc6340a | 117 | /*! Trim operation to be performed for RTC0*/ |
| AnnaBridge | 178:79309dc6340a | 118 | #define RTC0_CFG_TRIM_OPERATION 0 |
| AnnaBridge | 178:79309dc6340a | 119 | |
| AnnaBridge | 178:79309dc6340a | 120 | /*! Trim Value for RTC-0*/ |
| AnnaBridge | 178:79309dc6340a | 121 | #define RTC0_CFG_TRIM_VALUE 0 |
| AnnaBridge | 178:79309dc6340a | 122 | |
| AnnaBridge | 178:79309dc6340a | 123 | /*! GPIO Sample around Rising Edge of Sensor Strobe Channel 3. |
| AnnaBridge | 178:79309dc6340a | 124 | * Enables sampling of Sensor Strobe GPIO inputs around rising edge of Sensor Strobe Channel 3 pulse. |
| AnnaBridge | 178:79309dc6340a | 125 | * |
| AnnaBridge | 178:79309dc6340a | 126 | * 0 No sampling of input around rising edge. |
| AnnaBridge | 178:79309dc6340a | 127 | * 1 Input sampled one clock cycle before rising edge of Sensor Strobe. |
| AnnaBridge | 178:79309dc6340a | 128 | * 10 Input sampled at rising edge of Sensor Strobe. |
| AnnaBridge | 178:79309dc6340a | 129 | * 11 Input sampled one clock cycle after rising edge of Sensor Strobe. |
| AnnaBridge | 178:79309dc6340a | 130 | */ |
| AnnaBridge | 178:79309dc6340a | 131 | #define RTC0_SS3_SMPONRE 0 |
| AnnaBridge | 178:79309dc6340a | 132 | |
| AnnaBridge | 178:79309dc6340a | 133 | /*! GPIO Sample around Falling Edge of Sensor Strobe Channel 3. |
| AnnaBridge | 178:79309dc6340a | 134 | * Enables sampling of Sensor Strobe GPIO inputs around falling edge of Sensor Strobe Channel 3 pulse. |
| AnnaBridge | 178:79309dc6340a | 135 | * |
| AnnaBridge | 178:79309dc6340a | 136 | * 0 No sampling of input around rising edge. |
| AnnaBridge | 178:79309dc6340a | 137 | * 1 Input sampled one clock cycle before rising edge of Sensor Strobe. |
| AnnaBridge | 178:79309dc6340a | 138 | * 10 Input sampled at rising edge of Sensor Strobe. |
| AnnaBridge | 178:79309dc6340a | 139 | * 11 Input sampled one clock cycle after rising edge of Sensor Strobe. |
| AnnaBridge | 178:79309dc6340a | 140 | */ |
| AnnaBridge | 178:79309dc6340a | 141 | #define RTC0_SS3_SMPONFE 0 |
| AnnaBridge | 178:79309dc6340a | 142 | /*! GPIO Sample around Falling Edge of Sensor Strobe Channel 2. */ |
| AnnaBridge | 178:79309dc6340a | 143 | #define RTC0_SS2_SMPONFE 0 |
| AnnaBridge | 178:79309dc6340a | 144 | /*! GPIO Sample around Rising Edge of Sensor Strobe Channel 1. */ |
| AnnaBridge | 178:79309dc6340a | 145 | #define RTC0_SS1_SMPONRE 0 |
| AnnaBridge | 178:79309dc6340a | 146 | /*! GPIO Sample around Falling Edge of Sensor Strobe Channel 1. */ |
| AnnaBridge | 178:79309dc6340a | 147 | #define RTC0_SS1_SMPONFE 0 |
| AnnaBridge | 178:79309dc6340a | 148 | |
| AnnaBridge | 178:79309dc6340a | 149 | |
| AnnaBridge | 178:79309dc6340a | 150 | /*! Sensor Strobe's GP Input Sampling Mux |
| AnnaBridge | 178:79309dc6340a | 151 | * SS 2 GPIO Pin 1 |
| AnnaBridge | 178:79309dc6340a | 152 | * |
| AnnaBridge | 178:79309dc6340a | 153 | * GPMUX0/1.SSxGPINySEL 3b000 3b001 3b010 3b011 3b100 3b101 3b110 3b111 |
| AnnaBridge | 178:79309dc6340a | 154 | * RTCSSxGPIny p0[12] p2[0] p0[9] p0[8] p1[13] p1[2] p2[7] p2[9] |
| AnnaBridge | 178:79309dc6340a | 155 | */ |
| AnnaBridge | 178:79309dc6340a | 156 | #define RTC0_SS2_GPIN1SEL 0x4 |
| AnnaBridge | 178:79309dc6340a | 157 | /*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/ |
| AnnaBridge | 178:79309dc6340a | 158 | #define RTC0_SS2_GPIN0SEL 0x3 |
| AnnaBridge | 178:79309dc6340a | 159 | /*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/ |
| AnnaBridge | 178:79309dc6340a | 160 | #define RTC0_SS1_GPIN2SEL 0x2 |
| AnnaBridge | 178:79309dc6340a | 161 | /*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/ |
| AnnaBridge | 178:79309dc6340a | 162 | #define RTC0_SS1_GPIN1SEL 0x1 |
| AnnaBridge | 178:79309dc6340a | 163 | /*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/ |
| AnnaBridge | 178:79309dc6340a | 164 | #define RTC0_SS1_GPIN0SEL 0x0 |
| AnnaBridge | 178:79309dc6340a | 165 | /*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/ |
| AnnaBridge | 178:79309dc6340a | 166 | #define RTC0_SS3_GPIN2SEL 0x0 |
| AnnaBridge | 178:79309dc6340a | 167 | /*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/ |
| AnnaBridge | 178:79309dc6340a | 168 | #define RTC0_SS3_GPIN1SEL 0x7 |
| AnnaBridge | 178:79309dc6340a | 169 | /*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/ |
| AnnaBridge | 178:79309dc6340a | 170 | #define RTC0_SS3_GPIN0SEL 0x6 |
| AnnaBridge | 178:79309dc6340a | 171 | /*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/ |
| AnnaBridge | 178:79309dc6340a | 172 | #define RTC0_SS2_GPIN2SEL 0x5 |
| AnnaBridge | 178:79309dc6340a | 173 | |
| AnnaBridge | 178:79309dc6340a | 174 | /*! Differential output option for Sensor Strobe channel 3. |
| AnnaBridge | 178:79309dc6340a | 175 | * Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out |
| AnnaBridge | 178:79309dc6340a | 176 | * for this channel is available in corresponding GPIO. |
| AnnaBridge | 178:79309dc6340a | 177 | * RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3. |
| AnnaBridge | 178:79309dc6340a | 178 | */ |
| AnnaBridge | 178:79309dc6340a | 179 | #define RTC0_SS3_DIFFOUT 0 |
| AnnaBridge | 178:79309dc6340a | 180 | /*! Differential output option for Sensor Strobe channel 1. |
| AnnaBridge | 178:79309dc6340a | 181 | * Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out |
| AnnaBridge | 178:79309dc6340a | 182 | * for this channel is available in corresponding GPIO. |
| AnnaBridge | 178:79309dc6340a | 183 | * RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1. |
| AnnaBridge | 178:79309dc6340a | 184 | */ |
| AnnaBridge | 178:79309dc6340a | 185 | #define RTC0_SS1_DIFFOUT 0 |
| AnnaBridge | 178:79309dc6340a | 186 | |
| AnnaBridge | 178:79309dc6340a | 187 | |
| AnnaBridge | 178:79309dc6340a | 188 | |
| AnnaBridge | 178:79309dc6340a | 189 | /*! @} */ |
| AnnaBridge | 178:79309dc6340a | 190 | |
| AnnaBridge | 178:79309dc6340a | 191 | /* |
| AnnaBridge | 178:79309dc6340a | 192 | =================================================================== |
| AnnaBridge | 178:79309dc6340a | 193 | ------------------------RTC-1 CONFIGURATION MACRO----------------- |
| AnnaBridge | 178:79309dc6340a | 194 | =================================================================== |
| AnnaBridge | 178:79309dc6340a | 195 | */ |
| AnnaBridge | 178:79309dc6340a | 196 | |
| AnnaBridge | 178:79309dc6340a | 197 | /** @addtogroup RTC_Driver_Config_RTC1 RTC1 Static Configuration |
| AnnaBridge | 178:79309dc6340a | 198 | * @ingroup RTC_Driver_Config |
| AnnaBridge | 178:79309dc6340a | 199 | * @{ |
| AnnaBridge | 178:79309dc6340a | 200 | */ |
| AnnaBridge | 178:79309dc6340a | 201 | |
| AnnaBridge | 178:79309dc6340a | 202 | |
| AnnaBridge | 178:79309dc6340a | 203 | |
| AnnaBridge | 178:79309dc6340a | 204 | /*! Enable the Alarm */ |
| AnnaBridge | 178:79309dc6340a | 205 | #define RTC1_CFG_ENABLE_ALARM 0 |
| AnnaBridge | 178:79309dc6340a | 206 | |
| AnnaBridge | 178:79309dc6340a | 207 | /*! Enable the Alarm interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 208 | #define RTC1_CFG_ENABLE_ALARM_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 209 | |
| AnnaBridge | 178:79309dc6340a | 210 | /*! Enable the Trim */ |
| AnnaBridge | 178:79309dc6340a | 211 | #define RTC1_CFG_ENABLE_TRIM 0 |
| AnnaBridge | 178:79309dc6340a | 212 | |
| AnnaBridge | 178:79309dc6340a | 213 | /*! Enable the mod-60 Alarm */ |
| AnnaBridge | 178:79309dc6340a | 214 | #define RTC1_CFG_ENABLE_MOD60_ALARM 0 |
| AnnaBridge | 178:79309dc6340a | 215 | |
| AnnaBridge | 178:79309dc6340a | 216 | /*! Enable the mod-60 Alarm period*/ |
| AnnaBridge | 178:79309dc6340a | 217 | #define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD 0 |
| AnnaBridge | 178:79309dc6340a | 218 | |
| AnnaBridge | 178:79309dc6340a | 219 | /*! Enable the Alarm interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 220 | #define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 221 | |
| AnnaBridge | 178:79309dc6340a | 222 | /*! Enable the ISOINT interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 223 | #define RTC1_CFG_ENABLE_ISO_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 224 | |
| AnnaBridge | 178:79309dc6340a | 225 | /*! Enable the PENDERROR interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 226 | #define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 227 | |
| AnnaBridge | 178:79309dc6340a | 228 | /*! Enable the write sync interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 229 | #define RTC1_CFG_ENABLE_WSYNC_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 230 | |
| AnnaBridge | 178:79309dc6340a | 231 | /*! Enable the pend write interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 232 | #define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 233 | |
| AnnaBridge | 178:79309dc6340a | 234 | /*! Enable the RTC count interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 235 | #define RTC1_CFG_ENABLE_COUNT_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 236 | |
| AnnaBridge | 178:79309dc6340a | 237 | /*! Enable the prescaled modulo-1 interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 238 | #define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 239 | |
| AnnaBridge | 178:79309dc6340a | 240 | /*! Enable the Trim interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 241 | #define RTC1_CFG_ENABLE_TRIM_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 242 | |
| AnnaBridge | 178:79309dc6340a | 243 | /*! Enable the Mod60 roll over interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 244 | #define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 245 | |
| AnnaBridge | 178:79309dc6340a | 246 | /*! Prescale value for the RTC1*/ |
| AnnaBridge | 178:79309dc6340a | 247 | #define RTC1_CFG_PRESCALE 0 |
| AnnaBridge | 178:79309dc6340a | 248 | |
| AnnaBridge | 178:79309dc6340a | 249 | /*! Enable the counter roll over interrupt*/ |
| AnnaBridge | 178:79309dc6340a | 250 | #define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT 0 |
| AnnaBridge | 178:79309dc6340a | 251 | |
| AnnaBridge | 178:79309dc6340a | 252 | /*! Initial the count Value-0*/ |
| AnnaBridge | 178:79309dc6340a | 253 | #define RTC1_CFG_COUNT_VALUE_0 0 |
| AnnaBridge | 178:79309dc6340a | 254 | |
| AnnaBridge | 178:79309dc6340a | 255 | /*! Initial the count Value-1*/ |
| AnnaBridge | 178:79309dc6340a | 256 | #define RTC1_CFG_COUNT_VALUE_1 0 |
| AnnaBridge | 178:79309dc6340a | 257 | |
| AnnaBridge | 178:79309dc6340a | 258 | /*! Alarm Value-0*/ |
| AnnaBridge | 178:79309dc6340a | 259 | #define RTC1_CFG_ALARM_VALUE_0 0 |
| AnnaBridge | 178:79309dc6340a | 260 | |
| AnnaBridge | 178:79309dc6340a | 261 | /*! Alarm Value-1*/ |
| AnnaBridge | 178:79309dc6340a | 262 | #define RTC1_CFG_ALARM_VALUE_1 0 |
| AnnaBridge | 178:79309dc6340a | 263 | |
| AnnaBridge | 178:79309dc6340a | 264 | /*! Alarm Value-2*/ |
| AnnaBridge | 178:79309dc6340a | 265 | #define RTC1_CFG_ALARM_VALUE_2 0 |
| AnnaBridge | 178:79309dc6340a | 266 | |
| AnnaBridge | 178:79309dc6340a | 267 | /*! Trim interval*/ |
| AnnaBridge | 178:79309dc6340a | 268 | #define RTC1_CFG_TRIM_INTERVAL 0 |
| AnnaBridge | 178:79309dc6340a | 269 | |
| AnnaBridge | 178:79309dc6340a | 270 | /*! Trim interval with power of 2*/ |
| AnnaBridge | 178:79309dc6340a | 271 | #define RTC1_CFG_POW2_TRIM_INTERVAL 0 |
| AnnaBridge | 178:79309dc6340a | 272 | |
| AnnaBridge | 178:79309dc6340a | 273 | /*! Trim operation to be performed for RTC1*/ |
| AnnaBridge | 178:79309dc6340a | 274 | #define RTC1_CFG_TRIM_OPERATION 0 |
| AnnaBridge | 178:79309dc6340a | 275 | |
| AnnaBridge | 178:79309dc6340a | 276 | /*! Trim Value for RTC-1*/ |
| AnnaBridge | 178:79309dc6340a | 277 | #define RTC1_CFG_TRIM_VALUE 0 |
| AnnaBridge | 178:79309dc6340a | 278 | |
| AnnaBridge | 178:79309dc6340a | 279 | /*! Enable the input capture channel-0*/ |
| AnnaBridge | 178:79309dc6340a | 280 | #define RTC1_CFG_IC0_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 281 | |
| AnnaBridge | 178:79309dc6340a | 282 | /*! Enable the input capture channel-2*/ |
| AnnaBridge | 178:79309dc6340a | 283 | #define RTC1_CFG_IC2_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 284 | |
| AnnaBridge | 178:79309dc6340a | 285 | /*! Enable the input capture channel-3*/ |
| AnnaBridge | 178:79309dc6340a | 286 | #define RTC1_CFG_IC3_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 287 | |
| AnnaBridge | 178:79309dc6340a | 288 | /*! Enable the input capture channel-4*/ |
| AnnaBridge | 178:79309dc6340a | 289 | #define RTC1_CFG_IC4_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 290 | |
| AnnaBridge | 178:79309dc6340a | 291 | /*! Enable the Sensor Strobe channel-1*/ |
| AnnaBridge | 178:79309dc6340a | 292 | #define RTC1_CFG_SS1_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 293 | /*! Enable the Sensor Strobe channel-2*/ |
| AnnaBridge | 178:79309dc6340a | 294 | #define RTC1_CFG_SS2_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 295 | /*! Enable the Sensor Strobe channel-3*/ |
| AnnaBridge | 178:79309dc6340a | 296 | #define RTC1_CFG_SS3_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 297 | /*! Enable the Sensor Strobe channel-4*/ |
| AnnaBridge | 178:79309dc6340a | 298 | #define RTC1_CFG_SS4_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 299 | |
| AnnaBridge | 178:79309dc6340a | 300 | /*! Enable the interrupt for input capture channel-0*/ |
| AnnaBridge | 178:79309dc6340a | 301 | #define RTC1_CFG_IC0_INT_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 302 | |
| AnnaBridge | 178:79309dc6340a | 303 | /*! Enable the interrupt for input capture channel-2*/ |
| AnnaBridge | 178:79309dc6340a | 304 | #define RTC1_CFG_IC2_INT_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 305 | |
| AnnaBridge | 178:79309dc6340a | 306 | /*! Enable the interrupt for input capture channel-3*/ |
| AnnaBridge | 178:79309dc6340a | 307 | #define RTC1_CFG_IC3_INT_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 308 | |
| AnnaBridge | 178:79309dc6340a | 309 | /*! Enable the interrupt for input capture channel-4*/ |
| AnnaBridge | 178:79309dc6340a | 310 | #define RTC1_CFG_IC4_INT_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 311 | |
| AnnaBridge | 178:79309dc6340a | 312 | /*! Enable the over write input capture channels*/ |
| AnnaBridge | 178:79309dc6340a | 313 | #define RTC1_CFG_IC_OVER_WRITE_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 314 | |
| AnnaBridge | 178:79309dc6340a | 315 | /*! Polarity for input capture channel-0*/ |
| AnnaBridge | 178:79309dc6340a | 316 | #define RTC1_CFG_IC0_EDGE_POLARITY 0 |
| AnnaBridge | 178:79309dc6340a | 317 | |
| AnnaBridge | 178:79309dc6340a | 318 | /*! Polarity for input capture channel-2*/ |
| AnnaBridge | 178:79309dc6340a | 319 | #define RTC1_CFG_IC2_EDGE_POLARITY 0 |
| AnnaBridge | 178:79309dc6340a | 320 | |
| AnnaBridge | 178:79309dc6340a | 321 | /*! Polarity for input capture channel-3*/ |
| AnnaBridge | 178:79309dc6340a | 322 | #define RTC1_CFG_IC3_EDGE_POLARITY 0 |
| AnnaBridge | 178:79309dc6340a | 323 | |
| AnnaBridge | 178:79309dc6340a | 324 | /*! Polarity for input capture channel-4*/ |
| AnnaBridge | 178:79309dc6340a | 325 | #define RTC1_CFG_IC4_EDGE_POLARITY 0 |
| AnnaBridge | 178:79309dc6340a | 326 | |
| AnnaBridge | 178:79309dc6340a | 327 | /*! Enable the interrupt for Sensor Strobe channel-1*/ |
| AnnaBridge | 178:79309dc6340a | 328 | #define RTC1_CFG_SS1_INT_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 329 | /*! Enable the interrupt for Sensor Strobe channel-2*/ |
| AnnaBridge | 178:79309dc6340a | 330 | #define RTC1_CFG_SS2_INT_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 331 | /*! Enable the interrupt for Sensor Strobe channel-3*/ |
| AnnaBridge | 178:79309dc6340a | 332 | #define RTC1_CFG_SS3_INT_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 333 | /*! Enable the interrupt for Sensor Strobe channel-4*/ |
| AnnaBridge | 178:79309dc6340a | 334 | #define RTC1_CFG_SS4_INT_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 335 | |
| AnnaBridge | 178:79309dc6340a | 336 | /*! Enable the masking for Sensor Strobe channel-1*/ |
| AnnaBridge | 178:79309dc6340a | 337 | #define RTC1_CFG_SS1_MASK_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 338 | /*! Enable the masking for Sensor Strobe channel-2*/ |
| AnnaBridge | 178:79309dc6340a | 339 | #define RTC1_CFG_SS2_MASK_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 340 | /*! Enable the masking for Sensor Strobe channel-3*/ |
| AnnaBridge | 178:79309dc6340a | 341 | #define RTC1_CFG_SS3_MASK_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 342 | /*! Enable the masking for Sensor Strobe channel-4*/ |
| AnnaBridge | 178:79309dc6340a | 343 | #define RTC1_CFG_SS4_MASK_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 344 | |
| AnnaBridge | 178:79309dc6340a | 345 | /*! Enable the auto-reloading for Sensor Strobe channel-0*/ |
| AnnaBridge | 178:79309dc6340a | 346 | #define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE 0 |
| AnnaBridge | 178:79309dc6340a | 347 | |
| AnnaBridge | 178:79309dc6340a | 348 | /*! Mask for Sensor Strobe channel-0 */ |
| AnnaBridge | 178:79309dc6340a | 349 | #define RTC1_CFG_SS1_MASK_VALUE 0 |
| AnnaBridge | 178:79309dc6340a | 350 | |
| AnnaBridge | 178:79309dc6340a | 351 | |
| AnnaBridge | 178:79309dc6340a | 352 | /*! Auto reload value for Sensor Strobe channel-0 */ |
| AnnaBridge | 178:79309dc6340a | 353 | #define RTC1_CFG_SS1_AUTO_RELOAD_VALUE 32768/2 |
| AnnaBridge | 178:79309dc6340a | 354 | |
| AnnaBridge | 178:79309dc6340a | 355 | |
| AnnaBridge | 178:79309dc6340a | 356 | /*! Sensor Strobe GP Input Sampling Mux |
| AnnaBridge | 178:79309dc6340a | 357 | * SS2 GPIO Pin 1 |
| AnnaBridge | 178:79309dc6340a | 358 | * |
| AnnaBridge | 178:79309dc6340a | 359 | * GPMUX0/1.SSxGPINySEL 3b000 3b001 3b010 3b011 3b100 3b101 3b110 3b111 |
| AnnaBridge | 178:79309dc6340a | 360 | * RTCSSxGPIny p0[12] p2[0] p0[9] p0[8] p1[13] p1[2] p2[7] p2[9] |
| AnnaBridge | 178:79309dc6340a | 361 | */ |
| AnnaBridge | 178:79309dc6340a | 362 | #define RTC1_SS2_GPIN1SEL 0x4 |
| AnnaBridge | 178:79309dc6340a | 363 | /*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/ |
| AnnaBridge | 178:79309dc6340a | 364 | #define RTC1_SS2_GPIN0SEL 0x3 |
| AnnaBridge | 178:79309dc6340a | 365 | /*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/ |
| AnnaBridge | 178:79309dc6340a | 366 | #define RTC1_SS1_GPIN2SEL 0x2 |
| AnnaBridge | 178:79309dc6340a | 367 | /*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/ |
| AnnaBridge | 178:79309dc6340a | 368 | #define RTC1_SS1_GPIN1SEL 0x1 |
| AnnaBridge | 178:79309dc6340a | 369 | /*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/ |
| AnnaBridge | 178:79309dc6340a | 370 | #define RTC1_SS1_GPIN0SEL 0x0 |
| AnnaBridge | 178:79309dc6340a | 371 | /*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/ |
| AnnaBridge | 178:79309dc6340a | 372 | #define RTC1_SS3_GPIN2SEL 0x0 |
| AnnaBridge | 178:79309dc6340a | 373 | /*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/ |
| AnnaBridge | 178:79309dc6340a | 374 | #define RTC1_SS3_GPIN1SEL 0x7 |
| AnnaBridge | 178:79309dc6340a | 375 | /*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/ |
| AnnaBridge | 178:79309dc6340a | 376 | #define RTC1_SS3_GPIN0SEL 0x6 |
| AnnaBridge | 178:79309dc6340a | 377 | /*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/ |
| AnnaBridge | 178:79309dc6340a | 378 | #define RTC1_SS2_GPIN2SEL 0x5 |
| AnnaBridge | 178:79309dc6340a | 379 | |
| AnnaBridge | 178:79309dc6340a | 380 | /*! Differential output option for Sensor Strobe channel 3. |
| AnnaBridge | 178:79309dc6340a | 381 | * Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out |
| AnnaBridge | 178:79309dc6340a | 382 | * for this channel is available in corresponding GPIO. |
| AnnaBridge | 178:79309dc6340a | 383 | * RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3. |
| AnnaBridge | 178:79309dc6340a | 384 | */ |
| AnnaBridge | 178:79309dc6340a | 385 | #define RTC1_SS3_DIFFOUT 0 |
| AnnaBridge | 178:79309dc6340a | 386 | /*! Differential output option for Sensor Strobe channel 1. |
| AnnaBridge | 178:79309dc6340a | 387 | * Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out |
| AnnaBridge | 178:79309dc6340a | 388 | * for this channel is available in corresponding GPIO. |
| AnnaBridge | 178:79309dc6340a | 389 | * RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1. |
| AnnaBridge | 178:79309dc6340a | 390 | */ |
| AnnaBridge | 178:79309dc6340a | 391 | #define RTC1_SS1_DIFFOUT 0 |
| AnnaBridge | 178:79309dc6340a | 392 | |
| AnnaBridge | 178:79309dc6340a | 393 | |
| AnnaBridge | 178:79309dc6340a | 394 | /*! @} */ |
| AnnaBridge | 178:79309dc6340a | 395 | |
| AnnaBridge | 178:79309dc6340a | 396 | /*! @} */ |
| AnnaBridge | 178:79309dc6340a | 397 | #endif /* ADI_RTC_CONFIG_H__ */ |