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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.h@175:af195413fb11, 2017-10-11 (annotated)

Committer:
AnnaBridge
Date:
Wed Oct 11 12:45:49 2017 +0100
Revision:
175:af195413fb11
Parent:
154:37f96f9d4de2 
This updates the lib to the mbed lib v 153

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 175:af195413fb11 3 * Copyright 2016-2017 NXP
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
AnnaBridge 175:af195413fb11 15 * o Neither the name of the copyright holder nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #ifndef _FSL_PDB_H_
<> 154:37f96f9d4de2 32 #define _FSL_PDB_H_
<> 154:37f96f9d4de2 33
<> 154:37f96f9d4de2 34 #include "fsl_common.h"
<> 154:37f96f9d4de2 35
<> 154:37f96f9d4de2 36 /*!
<> 154:37f96f9d4de2 37 * @addtogroup pdb
<> 154:37f96f9d4de2 38 * @{
<> 154:37f96f9d4de2 39 */
<> 154:37f96f9d4de2 40
<> 154:37f96f9d4de2 41
<> 154:37f96f9d4de2 42 /*******************************************************************************
<> 154:37f96f9d4de2 43 * Definitions
<> 154:37f96f9d4de2 44 ******************************************************************************/
<> 154:37f96f9d4de2 45
<> 154:37f96f9d4de2 46 /*! @name Driver version */
<> 154:37f96f9d4de2 47 /*@{*/
<> 154:37f96f9d4de2 48 /*! @brief PDB driver version 2.0.1. */
<> 154:37f96f9d4de2 49 #define FSL_PDB_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
<> 154:37f96f9d4de2 50 /*@}*/
<> 154:37f96f9d4de2 51
<> 154:37f96f9d4de2 52 /*!
<> 154:37f96f9d4de2 53 * @brief PDB flags.
<> 154:37f96f9d4de2 54 */
<> 154:37f96f9d4de2 55 enum _pdb_status_flags
<> 154:37f96f9d4de2 56 {
<> 154:37f96f9d4de2 57 kPDB_LoadOKFlag = PDB_SC_LDOK_MASK, /*!< This flag is automatically cleared when the values in buffers are
<> 154:37f96f9d4de2 58 loaded into the internal registers after the LDOK bit is set or the
<> 154:37f96f9d4de2 59 PDBEN is cleared. */
<> 154:37f96f9d4de2 60 kPDB_DelayEventFlag = PDB_SC_PDBIF_MASK, /*!< PDB timer delay event flag. */
<> 154:37f96f9d4de2 61 };
<> 154:37f96f9d4de2 62
<> 154:37f96f9d4de2 63 /*!
<> 154:37f96f9d4de2 64 * @brief PDB ADC PreTrigger channel flags.
<> 154:37f96f9d4de2 65 */
<> 154:37f96f9d4de2 66 enum _pdb_adc_pretrigger_flags
<> 154:37f96f9d4de2 67 {
<> 154:37f96f9d4de2 68 /* PDB PreTrigger channel match flags. */
AnnaBridge 175:af195413fb11 69 kPDB_ADCPreTriggerChannel0Flag = PDB_S_CF(1U << 0), /*!< Pre-trigger 0 flag. */
AnnaBridge 175:af195413fb11 70 kPDB_ADCPreTriggerChannel1Flag = PDB_S_CF(1U << 1), /*!< Pre-trigger 1 flag. */
AnnaBridge 175:af195413fb11 71 #if (PDB_DLY_COUNT2 > 2)
AnnaBridge 175:af195413fb11 72 kPDB_ADCPreTriggerChannel2Flag = PDB_S_CF(1U << 2), /*!< Pre-trigger 2 flag. */
AnnaBridge 175:af195413fb11 73 kPDB_ADCPreTriggerChannel3Flag = PDB_S_CF(1U << 3), /*!< Pre-trigger 3 flag. */
AnnaBridge 175:af195413fb11 74 #endif /* PDB_DLY_COUNT2 > 2 */
AnnaBridge 175:af195413fb11 75 #if (PDB_DLY_COUNT2 > 4)
AnnaBridge 175:af195413fb11 76 kPDB_ADCPreTriggerChannel4Flag = PDB_S_CF(1U << 4), /*!< Pre-trigger 4 flag. */
AnnaBridge 175:af195413fb11 77 kPDB_ADCPreTriggerChannel5Flag = PDB_S_CF(1U << 5), /*!< Pre-trigger 5 flag. */
AnnaBridge 175:af195413fb11 78 kPDB_ADCPreTriggerChannel6Flag = PDB_S_CF(1U << 6), /*!< Pre-trigger 6 flag. */
AnnaBridge 175:af195413fb11 79 kPDB_ADCPreTriggerChannel7Flag = PDB_S_CF(1U << 7), /*!< Pre-trigger 7 flag. */
AnnaBridge 175:af195413fb11 80 #endif /* PDB_DLY_COUNT2 > 4 */
<> 154:37f96f9d4de2 81
<> 154:37f96f9d4de2 82 /* PDB PreTrigger channel error flags. */
AnnaBridge 175:af195413fb11 83 kPDB_ADCPreTriggerChannel0ErrorFlag = PDB_S_ERR(1U << 0), /*!< Pre-trigger 0 Error. */
AnnaBridge 175:af195413fb11 84 kPDB_ADCPreTriggerChannel1ErrorFlag = PDB_S_ERR(1U << 1), /*!< Pre-trigger 1 Error. */
AnnaBridge 175:af195413fb11 85 #if (PDB_DLY_COUNT2 > 2)
AnnaBridge 175:af195413fb11 86 kPDB_ADCPreTriggerChannel2ErrorFlag = PDB_S_ERR(1U << 2), /*!< Pre-trigger 2 Error. */
AnnaBridge 175:af195413fb11 87 kPDB_ADCPreTriggerChannel3ErrorFlag = PDB_S_ERR(1U << 3), /*!< Pre-trigger 3 Error. */
AnnaBridge 175:af195413fb11 88 #endif /* PDB_DLY_COUNT2 > 2 */
AnnaBridge 175:af195413fb11 89 #if (PDB_DLY_COUNT2 > 4)
AnnaBridge 175:af195413fb11 90 kPDB_ADCPreTriggerChannel4ErrorFlag = PDB_S_ERR(1U << 4), /*!< Pre-trigger 4 Error. */
AnnaBridge 175:af195413fb11 91 kPDB_ADCPreTriggerChannel5ErrorFlag = PDB_S_ERR(1U << 5), /*!< Pre-trigger 5 Error. */
AnnaBridge 175:af195413fb11 92 kPDB_ADCPreTriggerChannel6ErrorFlag = PDB_S_ERR(1U << 6), /*!< Pre-trigger 6 Error. */
AnnaBridge 175:af195413fb11 93 kPDB_ADCPreTriggerChannel7ErrorFlag = PDB_S_ERR(1U << 7), /*!< Pre-trigger 7 Error. */
AnnaBridge 175:af195413fb11 94 #endif /* PDB_DLY_COUNT2 > 4 */
<> 154:37f96f9d4de2 95 };
<> 154:37f96f9d4de2 96
<> 154:37f96f9d4de2 97 /*!
<> 154:37f96f9d4de2 98 * @brief PDB buffer interrupts.
<> 154:37f96f9d4de2 99 */
<> 154:37f96f9d4de2 100 enum _pdb_interrupt_enable
<> 154:37f96f9d4de2 101 {
<> 154:37f96f9d4de2 102 kPDB_SequenceErrorInterruptEnable = PDB_SC_PDBEIE_MASK, /*!< PDB sequence error interrupt enable. */
<> 154:37f96f9d4de2 103 kPDB_DelayInterruptEnable = PDB_SC_PDBIE_MASK, /*!< PDB delay interrupt enable. */
<> 154:37f96f9d4de2 104 };
<> 154:37f96f9d4de2 105
<> 154:37f96f9d4de2 106 /*!
<> 154:37f96f9d4de2 107 * @brief PDB load value mode.
<> 154:37f96f9d4de2 108 *
<> 154:37f96f9d4de2 109 * Selects the mode to load the internal values after doing the load operation (write 1 to PDBx_SC[LDOK]).
AnnaBridge 175:af195413fb11 110 * These values are for the following operations.
<> 154:37f96f9d4de2 111 * - PDB counter (PDBx_MOD, PDBx_IDLY)
<> 154:37f96f9d4de2 112 * - ADC trigger (PDBx_CHnDLYm)
<> 154:37f96f9d4de2 113 * - DAC trigger (PDBx_DACINTx)
<> 154:37f96f9d4de2 114 * - CMP trigger (PDBx_POyDLY)
<> 154:37f96f9d4de2 115 */
<> 154:37f96f9d4de2 116 typedef enum _pdb_load_value_mode
<> 154:37f96f9d4de2 117 {
<> 154:37f96f9d4de2 118 kPDB_LoadValueImmediately = 0U, /*!< Load immediately after 1 is written to LDOK. */
<> 154:37f96f9d4de2 119 kPDB_LoadValueOnCounterOverflow = 1U, /*!< Load when the PDB counter overflows (reaches the MOD
<> 154:37f96f9d4de2 120 register value). */
<> 154:37f96f9d4de2 121 kPDB_LoadValueOnTriggerInput = 2U, /*!< Load a trigger input event is detected. */
<> 154:37f96f9d4de2 122 kPDB_LoadValueOnCounterOverflowOrTriggerInput = 3U, /*!< Load either when the PDB counter overflows or a trigger
<> 154:37f96f9d4de2 123 input is detected. */
<> 154:37f96f9d4de2 124 } pdb_load_value_mode_t;
<> 154:37f96f9d4de2 125
<> 154:37f96f9d4de2 126 /*!
<> 154:37f96f9d4de2 127 * @brief Prescaler divider.
<> 154:37f96f9d4de2 128 *
<> 154:37f96f9d4de2 129 * Counting uses the peripheral clock divided by multiplication factor selected by times of MULT.
<> 154:37f96f9d4de2 130 */
<> 154:37f96f9d4de2 131 typedef enum _pdb_prescaler_divider
<> 154:37f96f9d4de2 132 {
<> 154:37f96f9d4de2 133 kPDB_PrescalerDivider1 = 0U, /*!< Divider x1. */
<> 154:37f96f9d4de2 134 kPDB_PrescalerDivider2 = 1U, /*!< Divider x2. */
<> 154:37f96f9d4de2 135 kPDB_PrescalerDivider4 = 2U, /*!< Divider x4. */
<> 154:37f96f9d4de2 136 kPDB_PrescalerDivider8 = 3U, /*!< Divider x8. */
<> 154:37f96f9d4de2 137 kPDB_PrescalerDivider16 = 4U, /*!< Divider x16. */
<> 154:37f96f9d4de2 138 kPDB_PrescalerDivider32 = 5U, /*!< Divider x32. */
<> 154:37f96f9d4de2 139 kPDB_PrescalerDivider64 = 6U, /*!< Divider x64. */
<> 154:37f96f9d4de2 140 kPDB_PrescalerDivider128 = 7U, /*!< Divider x128. */
<> 154:37f96f9d4de2 141 } pdb_prescaler_divider_t;
<> 154:37f96f9d4de2 142
<> 154:37f96f9d4de2 143 /*!
<> 154:37f96f9d4de2 144 * @brief Multiplication factor select for prescaler.
<> 154:37f96f9d4de2 145 *
<> 154:37f96f9d4de2 146 * Selects the multiplication factor of the prescaler divider for the counter clock.
<> 154:37f96f9d4de2 147 */
<> 154:37f96f9d4de2 148 typedef enum _pdb_divider_multiplication_factor
<> 154:37f96f9d4de2 149 {
<> 154:37f96f9d4de2 150 kPDB_DividerMultiplicationFactor1 = 0U, /*!< Multiplication factor is 1. */
<> 154:37f96f9d4de2 151 kPDB_DividerMultiplicationFactor10 = 1U, /*!< Multiplication factor is 10. */
<> 154:37f96f9d4de2 152 kPDB_DividerMultiplicationFactor20 = 2U, /*!< Multiplication factor is 20. */
<> 154:37f96f9d4de2 153 kPDB_DividerMultiplicationFactor40 = 3U, /*!< Multiplication factor is 40. */
<> 154:37f96f9d4de2 154 } pdb_divider_multiplication_factor_t;
<> 154:37f96f9d4de2 155
<> 154:37f96f9d4de2 156 /*!
<> 154:37f96f9d4de2 157 * @brief Trigger input source
<> 154:37f96f9d4de2 158 *
<> 154:37f96f9d4de2 159 * Selects the trigger input source for the PDB. The trigger input source can be internal or external (EXTRG pin), or
AnnaBridge 175:af195413fb11 160 * the software trigger. See chip configuration details for the actual PDB input trigger connections.
<> 154:37f96f9d4de2 161 */
<> 154:37f96f9d4de2 162 typedef enum _pdb_trigger_input_source
<> 154:37f96f9d4de2 163 {
<> 154:37f96f9d4de2 164 kPDB_TriggerInput0 = 0U, /*!< Trigger-In 0. */
<> 154:37f96f9d4de2 165 kPDB_TriggerInput1 = 1U, /*!< Trigger-In 1. */
<> 154:37f96f9d4de2 166 kPDB_TriggerInput2 = 2U, /*!< Trigger-In 2. */
<> 154:37f96f9d4de2 167 kPDB_TriggerInput3 = 3U, /*!< Trigger-In 3. */
<> 154:37f96f9d4de2 168 kPDB_TriggerInput4 = 4U, /*!< Trigger-In 4. */
<> 154:37f96f9d4de2 169 kPDB_TriggerInput5 = 5U, /*!< Trigger-In 5. */
<> 154:37f96f9d4de2 170 kPDB_TriggerInput6 = 6U, /*!< Trigger-In 6. */
<> 154:37f96f9d4de2 171 kPDB_TriggerInput7 = 7U, /*!< Trigger-In 7. */
<> 154:37f96f9d4de2 172 kPDB_TriggerInput8 = 8U, /*!< Trigger-In 8. */
<> 154:37f96f9d4de2 173 kPDB_TriggerInput9 = 9U, /*!< Trigger-In 9. */
<> 154:37f96f9d4de2 174 kPDB_TriggerInput10 = 10U, /*!< Trigger-In 10. */
<> 154:37f96f9d4de2 175 kPDB_TriggerInput11 = 11U, /*!< Trigger-In 11. */
<> 154:37f96f9d4de2 176 kPDB_TriggerInput12 = 12U, /*!< Trigger-In 12. */
<> 154:37f96f9d4de2 177 kPDB_TriggerInput13 = 13U, /*!< Trigger-In 13. */
<> 154:37f96f9d4de2 178 kPDB_TriggerInput14 = 14U, /*!< Trigger-In 14. */
AnnaBridge 175:af195413fb11 179 kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15, software trigger. */
<> 154:37f96f9d4de2 180 } pdb_trigger_input_source_t;
<> 154:37f96f9d4de2 181
<> 154:37f96f9d4de2 182 /*!
<> 154:37f96f9d4de2 183 * @brief PDB module configuration.
<> 154:37f96f9d4de2 184 */
<> 154:37f96f9d4de2 185 typedef struct _pdb_config
<> 154:37f96f9d4de2 186 {
<> 154:37f96f9d4de2 187 pdb_load_value_mode_t loadValueMode; /*!< Select the load value mode. */
<> 154:37f96f9d4de2 188 pdb_prescaler_divider_t prescalerDivider; /*!< Select the prescaler divider. */
<> 154:37f96f9d4de2 189 pdb_divider_multiplication_factor_t dividerMultiplicationFactor; /*!< Multiplication factor select for prescaler. */
<> 154:37f96f9d4de2 190 pdb_trigger_input_source_t triggerInputSource; /*!< Select the trigger input source. */
<> 154:37f96f9d4de2 191 bool enableContinuousMode; /*!< Enable the PDB operation in Continuous mode.*/
<> 154:37f96f9d4de2 192 } pdb_config_t;
<> 154:37f96f9d4de2 193
<> 154:37f96f9d4de2 194 /*!
AnnaBridge 175:af195413fb11 195 * @brief PDB ADC Pre-trigger configuration.
<> 154:37f96f9d4de2 196 */
<> 154:37f96f9d4de2 197 typedef struct _pdb_adc_pretrigger_config
<> 154:37f96f9d4de2 198 {
AnnaBridge 175:af195413fb11 199 uint32_t enablePreTriggerMask; /*!< PDB Channel Pre-trigger Enable. */
AnnaBridge 175:af195413fb11 200 uint32_t enableOutputMask; /*!< PDB Channel Pre-trigger Output Select.
<> 154:37f96f9d4de2 201 PDB channel's corresponding pre-trigger asserts when the counter
<> 154:37f96f9d4de2 202 reaches the channel delay register. */
AnnaBridge 175:af195413fb11 203 uint32_t enableBackToBackOperationMask; /*!< PDB Channel pre-trigger Back-to-Back Operation Enable.
<> 154:37f96f9d4de2 204 Back-to-back operation enables the ADC conversions complete to trigger
<> 154:37f96f9d4de2 205 the next PDB channel pre-trigger and trigger output, so that the ADC
<> 154:37f96f9d4de2 206 conversions can be triggered on next set of configuration and results
<> 154:37f96f9d4de2 207 registers.*/
<> 154:37f96f9d4de2 208 } pdb_adc_pretrigger_config_t;
<> 154:37f96f9d4de2 209
<> 154:37f96f9d4de2 210 /*!
<> 154:37f96f9d4de2 211 * @brief PDB DAC trigger configuration.
<> 154:37f96f9d4de2 212 */
<> 154:37f96f9d4de2 213 typedef struct _pdb_dac_trigger_config
<> 154:37f96f9d4de2 214 {
<> 154:37f96f9d4de2 215 bool enableExternalTriggerInput; /*!< Enables the external trigger for DAC interval counter. */
<> 154:37f96f9d4de2 216 bool enableIntervalTrigger; /*!< Enables the DAC interval trigger. */
<> 154:37f96f9d4de2 217 } pdb_dac_trigger_config_t;
<> 154:37f96f9d4de2 218
<> 154:37f96f9d4de2 219 /*******************************************************************************
<> 154:37f96f9d4de2 220 * API
<> 154:37f96f9d4de2 221 ******************************************************************************/
<> 154:37f96f9d4de2 222 #if defined(__cplusplus)
<> 154:37f96f9d4de2 223 extern "C" {
<> 154:37f96f9d4de2 224 #endif
<> 154:37f96f9d4de2 225
<> 154:37f96f9d4de2 226 /*!
<> 154:37f96f9d4de2 227 * @name Initialization
<> 154:37f96f9d4de2 228 * @{
<> 154:37f96f9d4de2 229 */
<> 154:37f96f9d4de2 230
<> 154:37f96f9d4de2 231 /*!
AnnaBridge 175:af195413fb11 232 * @brief Initializes the PDB module.
<> 154:37f96f9d4de2 233 *
AnnaBridge 175:af195413fb11 234 * This function initializes the PDB module. The operations included are as follows.
<> 154:37f96f9d4de2 235 * - Enable the clock for PDB instance.
<> 154:37f96f9d4de2 236 * - Configure the PDB module.
<> 154:37f96f9d4de2 237 * - Enable the PDB module.
<> 154:37f96f9d4de2 238 *
<> 154:37f96f9d4de2 239 * @param base PDB peripheral base address.
AnnaBridge 175:af195413fb11 240 * @param config Pointer to the configuration structure. See "pdb_config_t".
<> 154:37f96f9d4de2 241 */
<> 154:37f96f9d4de2 242 void PDB_Init(PDB_Type *base, const pdb_config_t *config);
<> 154:37f96f9d4de2 243
<> 154:37f96f9d4de2 244 /*!
AnnaBridge 175:af195413fb11 245 * @brief De-initializes the PDB module.
<> 154:37f96f9d4de2 246 *
<> 154:37f96f9d4de2 247 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 248 */
<> 154:37f96f9d4de2 249 void PDB_Deinit(PDB_Type *base);
<> 154:37f96f9d4de2 250
<> 154:37f96f9d4de2 251 /*!
AnnaBridge 175:af195413fb11 252 * @brief Initializes the PDB user configuration structure.
<> 154:37f96f9d4de2 253 *
AnnaBridge 175:af195413fb11 254 * This function initializes the user configuration structure to a default value. The default values are as follows.
<> 154:37f96f9d4de2 255 * @code
<> 154:37f96f9d4de2 256 * config->loadValueMode = kPDB_LoadValueImmediately;
<> 154:37f96f9d4de2 257 * config->prescalerDivider = kPDB_PrescalerDivider1;
<> 154:37f96f9d4de2 258 * config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1;
<> 154:37f96f9d4de2 259 * config->triggerInputSource = kPDB_TriggerSoftware;
<> 154:37f96f9d4de2 260 * config->enableContinuousMode = false;
<> 154:37f96f9d4de2 261 * @endcode
<> 154:37f96f9d4de2 262 * @param config Pointer to configuration structure. See "pdb_config_t".
<> 154:37f96f9d4de2 263 */
<> 154:37f96f9d4de2 264 void PDB_GetDefaultConfig(pdb_config_t *config);
<> 154:37f96f9d4de2 265
<> 154:37f96f9d4de2 266 /*!
<> 154:37f96f9d4de2 267 * @brief Enables the PDB module.
<> 154:37f96f9d4de2 268 *
<> 154:37f96f9d4de2 269 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 270 * @param enable Enable the module or not.
<> 154:37f96f9d4de2 271 */
<> 154:37f96f9d4de2 272 static inline void PDB_Enable(PDB_Type *base, bool enable)
<> 154:37f96f9d4de2 273 {
<> 154:37f96f9d4de2 274 if (enable)
<> 154:37f96f9d4de2 275 {
<> 154:37f96f9d4de2 276 base->SC |= PDB_SC_PDBEN_MASK;
<> 154:37f96f9d4de2 277 }
<> 154:37f96f9d4de2 278 else
<> 154:37f96f9d4de2 279 {
<> 154:37f96f9d4de2 280 base->SC &= ~PDB_SC_PDBEN_MASK;
<> 154:37f96f9d4de2 281 }
<> 154:37f96f9d4de2 282 }
<> 154:37f96f9d4de2 283
<> 154:37f96f9d4de2 284 /* @} */
<> 154:37f96f9d4de2 285
<> 154:37f96f9d4de2 286 /*!
<> 154:37f96f9d4de2 287 * @name Basic Counter
<> 154:37f96f9d4de2 288 * @{
<> 154:37f96f9d4de2 289 */
<> 154:37f96f9d4de2 290
<> 154:37f96f9d4de2 291 /*!
<> 154:37f96f9d4de2 292 * @brief Triggers the PDB counter by software.
<> 154:37f96f9d4de2 293 *
<> 154:37f96f9d4de2 294 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 295 */
<> 154:37f96f9d4de2 296 static inline void PDB_DoSoftwareTrigger(PDB_Type *base)
<> 154:37f96f9d4de2 297 {
<> 154:37f96f9d4de2 298 base->SC |= PDB_SC_SWTRIG_MASK;
<> 154:37f96f9d4de2 299 }
<> 154:37f96f9d4de2 300
<> 154:37f96f9d4de2 301 /*!
<> 154:37f96f9d4de2 302 * @brief Loads the counter values.
<> 154:37f96f9d4de2 303 *
AnnaBridge 175:af195413fb11 304 * This function loads the counter values from the internal buffer.
<> 154:37f96f9d4de2 305 * See "pdb_load_value_mode_t" about PDB's load mode.
<> 154:37f96f9d4de2 306 *
<> 154:37f96f9d4de2 307 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 308 */
<> 154:37f96f9d4de2 309 static inline void PDB_DoLoadValues(PDB_Type *base)
<> 154:37f96f9d4de2 310 {
<> 154:37f96f9d4de2 311 base->SC |= PDB_SC_LDOK_MASK;
<> 154:37f96f9d4de2 312 }
<> 154:37f96f9d4de2 313
<> 154:37f96f9d4de2 314 /*!
<> 154:37f96f9d4de2 315 * @brief Enables the DMA for the PDB module.
<> 154:37f96f9d4de2 316 *
<> 154:37f96f9d4de2 317 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 318 * @param enable Enable the feature or not.
<> 154:37f96f9d4de2 319 */
<> 154:37f96f9d4de2 320 static inline void PDB_EnableDMA(PDB_Type *base, bool enable)
<> 154:37f96f9d4de2 321 {
<> 154:37f96f9d4de2 322 if (enable)
<> 154:37f96f9d4de2 323 {
<> 154:37f96f9d4de2 324 base->SC |= PDB_SC_DMAEN_MASK;
<> 154:37f96f9d4de2 325 }
<> 154:37f96f9d4de2 326 else
<> 154:37f96f9d4de2 327 {
<> 154:37f96f9d4de2 328 base->SC &= ~PDB_SC_DMAEN_MASK;
<> 154:37f96f9d4de2 329 }
<> 154:37f96f9d4de2 330 }
<> 154:37f96f9d4de2 331
<> 154:37f96f9d4de2 332 /*!
<> 154:37f96f9d4de2 333 * @brief Enables the interrupts for the PDB module.
<> 154:37f96f9d4de2 334 *
<> 154:37f96f9d4de2 335 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 336 * @param mask Mask value for interrupts. See "_pdb_interrupt_enable".
<> 154:37f96f9d4de2 337 */
<> 154:37f96f9d4de2 338 static inline void PDB_EnableInterrupts(PDB_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 339 {
<> 154:37f96f9d4de2 340 assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK)));
<> 154:37f96f9d4de2 341
<> 154:37f96f9d4de2 342 base->SC |= mask;
<> 154:37f96f9d4de2 343 }
<> 154:37f96f9d4de2 344
<> 154:37f96f9d4de2 345 /*!
<> 154:37f96f9d4de2 346 * @brief Disables the interrupts for the PDB module.
<> 154:37f96f9d4de2 347 *
<> 154:37f96f9d4de2 348 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 349 * @param mask Mask value for interrupts. See "_pdb_interrupt_enable".
<> 154:37f96f9d4de2 350 */
<> 154:37f96f9d4de2 351 static inline void PDB_DisableInterrupts(PDB_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 352 {
<> 154:37f96f9d4de2 353 assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK)));
<> 154:37f96f9d4de2 354
<> 154:37f96f9d4de2 355 base->SC &= ~mask;
<> 154:37f96f9d4de2 356 }
<> 154:37f96f9d4de2 357
<> 154:37f96f9d4de2 358 /*!
<> 154:37f96f9d4de2 359 * @brief Gets the status flags of the PDB module.
<> 154:37f96f9d4de2 360 *
<> 154:37f96f9d4de2 361 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 362 *
<> 154:37f96f9d4de2 363 * @return Mask value for asserted flags. See "_pdb_status_flags".
<> 154:37f96f9d4de2 364 */
<> 154:37f96f9d4de2 365 static inline uint32_t PDB_GetStatusFlags(PDB_Type *base)
<> 154:37f96f9d4de2 366 {
<> 154:37f96f9d4de2 367 return base->SC & (PDB_SC_PDBIF_MASK | PDB_SC_LDOK_MASK);
<> 154:37f96f9d4de2 368 }
<> 154:37f96f9d4de2 369
<> 154:37f96f9d4de2 370 /*!
<> 154:37f96f9d4de2 371 * @brief Clears the status flags of the PDB module.
<> 154:37f96f9d4de2 372 *
<> 154:37f96f9d4de2 373 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 374 * @param mask Mask value of flags. See "_pdb_status_flags".
<> 154:37f96f9d4de2 375 */
<> 154:37f96f9d4de2 376 static inline void PDB_ClearStatusFlags(PDB_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 377 {
<> 154:37f96f9d4de2 378 assert(0U == (mask & ~PDB_SC_PDBIF_MASK));
<> 154:37f96f9d4de2 379
<> 154:37f96f9d4de2 380 base->SC &= ~mask;
<> 154:37f96f9d4de2 381 }
<> 154:37f96f9d4de2 382
<> 154:37f96f9d4de2 383 /*!
AnnaBridge 175:af195413fb11 384 * @brief Specifies the counter period.
<> 154:37f96f9d4de2 385 *
<> 154:37f96f9d4de2 386 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 387 * @param value Setting value for the modulus. 16-bit is available.
<> 154:37f96f9d4de2 388 */
<> 154:37f96f9d4de2 389 static inline void PDB_SetModulusValue(PDB_Type *base, uint32_t value)
<> 154:37f96f9d4de2 390 {
<> 154:37f96f9d4de2 391 base->MOD = PDB_MOD_MOD(value);
<> 154:37f96f9d4de2 392 }
<> 154:37f96f9d4de2 393
<> 154:37f96f9d4de2 394 /*!
<> 154:37f96f9d4de2 395 * @brief Gets the PDB counter's current value.
<> 154:37f96f9d4de2 396 *
<> 154:37f96f9d4de2 397 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 398 *
<> 154:37f96f9d4de2 399 * @return PDB counter's current value.
<> 154:37f96f9d4de2 400 */
<> 154:37f96f9d4de2 401 static inline uint32_t PDB_GetCounterValue(PDB_Type *base)
<> 154:37f96f9d4de2 402 {
<> 154:37f96f9d4de2 403 return base->CNT;
<> 154:37f96f9d4de2 404 }
<> 154:37f96f9d4de2 405
<> 154:37f96f9d4de2 406 /*!
AnnaBridge 175:af195413fb11 407 * @brief Sets the value for the PDB counter delay event.
<> 154:37f96f9d4de2 408 *
<> 154:37f96f9d4de2 409 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 410 * @param value Setting value for PDB counter delay event. 16-bit is available.
<> 154:37f96f9d4de2 411 */
<> 154:37f96f9d4de2 412 static inline void PDB_SetCounterDelayValue(PDB_Type *base, uint32_t value)
<> 154:37f96f9d4de2 413 {
<> 154:37f96f9d4de2 414 base->IDLY = PDB_IDLY_IDLY(value);
<> 154:37f96f9d4de2 415 }
<> 154:37f96f9d4de2 416 /* @} */
<> 154:37f96f9d4de2 417
<> 154:37f96f9d4de2 418 /*!
AnnaBridge 175:af195413fb11 419 * @name ADC Pre-trigger
<> 154:37f96f9d4de2 420 * @{
<> 154:37f96f9d4de2 421 */
<> 154:37f96f9d4de2 422
<> 154:37f96f9d4de2 423 /*!
AnnaBridge 175:af195413fb11 424 * @brief Configures the ADC pre-trigger in the PDB module.
<> 154:37f96f9d4de2 425 *
<> 154:37f96f9d4de2 426 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 427 * @param channel Channel index for ADC instance.
AnnaBridge 175:af195413fb11 428 * @param config Pointer to the configuration structure. See "pdb_adc_pretrigger_config_t".
<> 154:37f96f9d4de2 429 */
<> 154:37f96f9d4de2 430 static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel, pdb_adc_pretrigger_config_t *config)
<> 154:37f96f9d4de2 431 {
<> 154:37f96f9d4de2 432 assert(channel < PDB_C1_COUNT);
<> 154:37f96f9d4de2 433 assert(NULL != config);
<> 154:37f96f9d4de2 434
<> 154:37f96f9d4de2 435 base->CH[channel].C1 = PDB_C1_BB(config->enableBackToBackOperationMask) | PDB_C1_TOS(config->enableOutputMask) |
AnnaBridge 175:af195413fb11 436 PDB_C1_EN(config->enablePreTriggerMask);
<> 154:37f96f9d4de2 437 }
<> 154:37f96f9d4de2 438
<> 154:37f96f9d4de2 439 /*!
AnnaBridge 175:af195413fb11 440 * @brief Sets the value for the ADC pre-trigger delay event.
<> 154:37f96f9d4de2 441 *
AnnaBridge 175:af195413fb11 442 * This function sets the value for ADC pre-trigger delay event. It specifies the delay value for the channel's
AnnaBridge 175:af195413fb11 443 * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the set value.
<> 154:37f96f9d4de2 444 *
<> 154:37f96f9d4de2 445 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 446 * @param channel Channel index for ADC instance.
<> 154:37f96f9d4de2 447 * @param preChannel Channel group index for ADC instance.
AnnaBridge 175:af195413fb11 448 * @param value Setting value for ADC pre-trigger delay event. 16-bit is available.
<> 154:37f96f9d4de2 449 */
<> 154:37f96f9d4de2 450 static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t preChannel, uint32_t value)
<> 154:37f96f9d4de2 451 {
<> 154:37f96f9d4de2 452 assert(channel < PDB_C1_COUNT);
AnnaBridge 175:af195413fb11 453 assert(preChannel < PDB_DLY_COUNT2);
AnnaBridge 175:af195413fb11 454 /* xx_COUNT2 is actually the count for pre-triggers in header file. xx_COUNT is used for the count of channels. */
<> 154:37f96f9d4de2 455
<> 154:37f96f9d4de2 456 base->CH[channel].DLY[preChannel] = PDB_DLY_DLY(value);
<> 154:37f96f9d4de2 457 }
<> 154:37f96f9d4de2 458
<> 154:37f96f9d4de2 459 /*!
AnnaBridge 175:af195413fb11 460 * @brief Gets the ADC pre-trigger's status flags.
<> 154:37f96f9d4de2 461 *
<> 154:37f96f9d4de2 462 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 463 * @param channel Channel index for ADC instance.
<> 154:37f96f9d4de2 464 *
<> 154:37f96f9d4de2 465 * @return Mask value for asserted flags. See "_pdb_adc_pretrigger_flags".
<> 154:37f96f9d4de2 466 */
<> 154:37f96f9d4de2 467 static inline uint32_t PDB_GetADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel)
<> 154:37f96f9d4de2 468 {
<> 154:37f96f9d4de2 469 assert(channel < PDB_C1_COUNT);
<> 154:37f96f9d4de2 470
<> 154:37f96f9d4de2 471 return base->CH[channel].S;
<> 154:37f96f9d4de2 472 }
<> 154:37f96f9d4de2 473
<> 154:37f96f9d4de2 474 /*!
AnnaBridge 175:af195413fb11 475 * @brief Clears the ADC pre-trigger status flags.
<> 154:37f96f9d4de2 476 *
<> 154:37f96f9d4de2 477 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 478 * @param channel Channel index for ADC instance.
<> 154:37f96f9d4de2 479 * @param mask Mask value for flags. See "_pdb_adc_pretrigger_flags".
<> 154:37f96f9d4de2 480 */
<> 154:37f96f9d4de2 481 static inline void PDB_ClearADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel, uint32_t mask)
<> 154:37f96f9d4de2 482 {
<> 154:37f96f9d4de2 483 assert(channel < PDB_C1_COUNT);
<> 154:37f96f9d4de2 484
<> 154:37f96f9d4de2 485 base->CH[channel].S &= ~mask;
<> 154:37f96f9d4de2 486 }
<> 154:37f96f9d4de2 487
<> 154:37f96f9d4de2 488 /* @} */
<> 154:37f96f9d4de2 489
<> 154:37f96f9d4de2 490 #if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC
<> 154:37f96f9d4de2 491 /*!
<> 154:37f96f9d4de2 492 * @name DAC Interval Trigger
<> 154:37f96f9d4de2 493 * @{
<> 154:37f96f9d4de2 494 */
<> 154:37f96f9d4de2 495
<> 154:37f96f9d4de2 496 /*!
AnnaBridge 175:af195413fb11 497 * @brief Configures the DAC trigger in the PDB module.
<> 154:37f96f9d4de2 498 *
<> 154:37f96f9d4de2 499 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 500 * @param channel Channel index for DAC instance.
AnnaBridge 175:af195413fb11 501 * @param config Pointer to the configuration structure. See "pdb_dac_trigger_config_t".
<> 154:37f96f9d4de2 502 */
<> 154:37f96f9d4de2 503 void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config);
<> 154:37f96f9d4de2 504
<> 154:37f96f9d4de2 505 /*!
<> 154:37f96f9d4de2 506 * @brief Sets the value for the DAC interval event.
<> 154:37f96f9d4de2 507 *
AnnaBridge 175:af195413fb11 508 * This fucntion sets the value for DAC interval event. DAC interval trigger triggers the DAC module to update
AnnaBridge 175:af195413fb11 509 * the buffer when the DAC interval counter is equal to the set value.
<> 154:37f96f9d4de2 510 *
<> 154:37f96f9d4de2 511 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 512 * @param channel Channel index for DAC instance.
<> 154:37f96f9d4de2 513 * @param value Setting value for the DAC interval event.
<> 154:37f96f9d4de2 514 */
<> 154:37f96f9d4de2 515 static inline void PDB_SetDACTriggerIntervalValue(PDB_Type *base, uint32_t channel, uint32_t value)
<> 154:37f96f9d4de2 516 {
<> 154:37f96f9d4de2 517 assert(channel < PDB_INT_COUNT);
<> 154:37f96f9d4de2 518
<> 154:37f96f9d4de2 519 base->DAC[channel].INT = PDB_INT_INT(value);
<> 154:37f96f9d4de2 520 }
<> 154:37f96f9d4de2 521
<> 154:37f96f9d4de2 522 /* @} */
<> 154:37f96f9d4de2 523 #endif /* FSL_FEATURE_PDB_HAS_DAC */
<> 154:37f96f9d4de2 524
<> 154:37f96f9d4de2 525 /*!
<> 154:37f96f9d4de2 526 * @name Pulse-Out Trigger
<> 154:37f96f9d4de2 527 * @{
<> 154:37f96f9d4de2 528 */
<> 154:37f96f9d4de2 529
<> 154:37f96f9d4de2 530 /*!
<> 154:37f96f9d4de2 531 * @brief Enables the pulse out trigger channels.
<> 154:37f96f9d4de2 532 *
<> 154:37f96f9d4de2 533 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 534 * @param channelMask Channel mask value for multiple pulse out trigger channel.
AnnaBridge 175:af195413fb11 535 * @param enable Whether the feature is enabled or not.
<> 154:37f96f9d4de2 536 */
<> 154:37f96f9d4de2 537 static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMask, bool enable)
<> 154:37f96f9d4de2 538 {
<> 154:37f96f9d4de2 539 if (enable)
<> 154:37f96f9d4de2 540 {
<> 154:37f96f9d4de2 541 base->POEN |= PDB_POEN_POEN(channelMask);
<> 154:37f96f9d4de2 542 }
<> 154:37f96f9d4de2 543 else
<> 154:37f96f9d4de2 544 {
<> 154:37f96f9d4de2 545 base->POEN &= ~(PDB_POEN_POEN(channelMask));
<> 154:37f96f9d4de2 546 }
<> 154:37f96f9d4de2 547 }
<> 154:37f96f9d4de2 548
<> 154:37f96f9d4de2 549 /*!
AnnaBridge 175:af195413fb11 550 * @brief Sets event values for the pulse out trigger.
<> 154:37f96f9d4de2 551 *
AnnaBridge 175:af195413fb11 552 * This function is used to set event values for the pulse output trigger.
AnnaBridge 175:af195413fb11 553 * These pulse output trigger delay values specify the delay for the PDB Pulse-out. Pulse-out goes high when the PDB
AnnaBridge 175:af195413fb11 554 * counter is equal to the pulse output high value (value1). Pulse-out goes low when the PDB counter is equal to the
<> 154:37f96f9d4de2 555 * pulse output low value (value2).
<> 154:37f96f9d4de2 556 *
<> 154:37f96f9d4de2 557 * @param base PDB peripheral base address.
<> 154:37f96f9d4de2 558 * @param channel Channel index for pulse out trigger channel.
<> 154:37f96f9d4de2 559 * @param value1 Setting value for pulse out high.
<> 154:37f96f9d4de2 560 * @param value2 Setting value for pulse out low.
<> 154:37f96f9d4de2 561 */
<> 154:37f96f9d4de2 562 static inline void PDB_SetPulseOutTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t value1, uint32_t value2)
<> 154:37f96f9d4de2 563 {
<> 154:37f96f9d4de2 564 assert(channel < PDB_PODLY_COUNT);
<> 154:37f96f9d4de2 565
<> 154:37f96f9d4de2 566 base->PODLY[channel] = PDB_PODLY_DLY1(value1) | PDB_PODLY_DLY2(value2);
<> 154:37f96f9d4de2 567 }
<> 154:37f96f9d4de2 568
<> 154:37f96f9d4de2 569 /* @} */
<> 154:37f96f9d4de2 570 #if defined(__cplusplus)
<> 154:37f96f9d4de2 571 }
<> 154:37f96f9d4de2 572 #endif
<> 154:37f96f9d4de2 573 /*!
<> 154:37f96f9d4de2 574 * @}
<> 154:37f96f9d4de2 575 */
<> 154:37f96f9d4de2 576 #endif /* _FSL_PDB_H_ */