anyThing Connected Team / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   BREAK_SENSOR_LED

Fork of mbed-dev by mbed official

targets/hal/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
bogdanm 0:9b334a45a8ff 17 */
bogdanm 0:9b334a45a8ff 18 #include "mbed_assert.h"
bogdanm 0:9b334a45a8ff 19 #include "pwmout_api.h"
bogdanm 0:9b334a45a8ff 20 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 21 #include "pinmap.h"
bogdanm 0:9b334a45a8ff 22 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 // PWM implementation for the LPC43xx using State Configurable Timer (SCT)
bogdanm 0:9b334a45a8ff 25 // * PWM_0 to PWM_15 on mbed use CTOUT_0 to CTOUT_15 outputs on LPC43xx
bogdanm 0:9b334a45a8ff 26 // * Event 0 is PWM period, events 1 to PWM_EVENT_MAX are PWM channels
bogdanm 0:9b334a45a8ff 27 // * Default is unified 32-bit timer, but could be configured to use
bogdanm 0:9b334a45a8ff 28 // a 16-bit timer so a timer is available for other SCT functions
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 // configuration options
bogdanm 0:9b334a45a8ff 31 #define PWM_FREQ_BASE 1000000 // Base frequency 1 MHz = 1000000
bogdanm 0:9b334a45a8ff 32 #define PWM_MODE 1 // 0 = 32-bit, 1 = 16-bit low, 2 = 16-bit high
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 // macros
bogdanm 0:9b334a45a8ff 35 #define PWM_SETCOUNT(x) (x - 1) // set count value
bogdanm 0:9b334a45a8ff 36 #define PWM_GETCOUNT(x) (x + 1) // get count value
bogdanm 0:9b334a45a8ff 37 #if (PWM_MODE == 0) // unified 32-bit counter, events 1 to 15
bogdanm 0:9b334a45a8ff 38 #define PWM_EVENT_MAX (CONFIG_SCT_nEV - 1) // Max PWM channels
bogdanm 0:9b334a45a8ff 39 #define PWM_CONFIG SCT_CONFIG_32BIT_COUNTER // default config
bogdanm 0:9b334a45a8ff 40 #define PWM_CTRL &LPC_SCT->CTRL_U // control register
bogdanm 0:9b334a45a8ff 41 #define PWM_HALT SCT_CTRL_HALT_L // halt counter
bogdanm 0:9b334a45a8ff 42 #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
bogdanm 0:9b334a45a8ff 43 #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
bogdanm 0:9b334a45a8ff 44 #define PWM_EVT_MASK (1 << 12) // event control mask
bogdanm 0:9b334a45a8ff 45 #define PWM_LIMIT &LPC_SCT->LIMIT_L // limit register
bogdanm 0:9b334a45a8ff 46 #define PWM_MATCH(x) &LPC_SCT->MATCH[x].U // match register
bogdanm 0:9b334a45a8ff 47 #define PWM_MR(x) &LPC_SCT->MATCHREL[x].U // 32-bit match reload register
bogdanm 0:9b334a45a8ff 48 #elif (PWM_MODE == 1) // 16-bit low counter, events 1 to 7
bogdanm 0:9b334a45a8ff 49 #define PWM_EVENT_MAX (CONFIG_SCT_nEV/2 - 1) // Max PWM channels
bogdanm 0:9b334a45a8ff 50 #define PWM_CONFIG SCT_CONFIG_16BIT_COUNTER // default config
bogdanm 0:9b334a45a8ff 51 #define PWM_CTRL &LPC_SCT->CTRL_L // control register
bogdanm 0:9b334a45a8ff 52 #define PWM_HALT SCT_CTRL_HALT_L // halt counter
bogdanm 0:9b334a45a8ff 53 #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
bogdanm 0:9b334a45a8ff 54 #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
bogdanm 0:9b334a45a8ff 55 #define PWM_EVT_MASK (1 << 12) // event control mask
bogdanm 0:9b334a45a8ff 56 #define PWM_LIMIT &LPC_SCT->LIMIT_L // limit register
bogdanm 0:9b334a45a8ff 57 #define PWM_MATCH(x) &LPC_SCT->MATCH[x].L // match register
bogdanm 0:9b334a45a8ff 58 #define PWM_MR(x) &LPC_SCT->MATCHREL[x].L // 16-bit match reload register
bogdanm 0:9b334a45a8ff 59 #elif (PWM_MODE == 2) // 16-bit high counter, events 1 to 7
bogdanm 0:9b334a45a8ff 60 // [TODO] use events 8 to 15 on mode 2
bogdanm 0:9b334a45a8ff 61 #define PWM_EVENT_MAX (CONFIG_SCT_nEV/2 - 1) // Max PWM channels
bogdanm 0:9b334a45a8ff 62 #define PWM_CONFIG SCT_CONFIG_16BIT_COUNTER // default config
bogdanm 0:9b334a45a8ff 63 #define PWM_CTRL &LPC_SCT->CTRL_H // control register
bogdanm 0:9b334a45a8ff 64 #define PWM_HALT SCT_CTRL_HALT_L // halt counter
bogdanm 0:9b334a45a8ff 65 #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
bogdanm 0:9b334a45a8ff 66 #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
bogdanm 0:9b334a45a8ff 67 #define PWM_EVT_MASK ((1 << 4) | (1 << 12)) // event control mask
bogdanm 0:9b334a45a8ff 68 #define PWM_LIMIT &LPC_SCT->LIMIT_H // limit register
bogdanm 0:9b334a45a8ff 69 #define PWM_MATCH(x) &LPC_SCT->MATCH[x].H // match register
bogdanm 0:9b334a45a8ff 70 #define PWM_MR(x) &LPC_SCT->MATCHREL[x].H // 16-bit match reload register
bogdanm 0:9b334a45a8ff 71 #else
bogdanm 0:9b334a45a8ff 72 #error "PWM mode not implemented"
bogdanm 0:9b334a45a8ff 73 #endif
bogdanm 0:9b334a45a8ff 74 #define PWM_MR0 PWM_MR(0) // MR register 0 is for period
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 static uint8_t event = 0;
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 // PORT ID, PWM ID, Pin function
bogdanm 0:9b334a45a8ff 79 static const PinMap PinMap_PWM[] = {
bogdanm 0:9b334a45a8ff 80 {P1_1, PWM_7, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 81 {P1_2, PWM_6, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 82 {P1_3, PWM_8, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 83 {P1_4, PWM_9, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 84 {P1_5, PWM_10, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 85 {P1_7, PWM_13, (SCU_PINIO_FAST | 2)},
bogdanm 0:9b334a45a8ff 86 {P1_8, PWM_12, (SCU_PINIO_FAST | 2)},
bogdanm 0:9b334a45a8ff 87 {P1_9, PWM_11, (SCU_PINIO_FAST | 2)},
bogdanm 0:9b334a45a8ff 88 {P1_10, PWM_14, (SCU_PINIO_FAST | 2)},
bogdanm 0:9b334a45a8ff 89 {P1_11, PWM_15, (SCU_PINIO_FAST | 2)},
bogdanm 0:9b334a45a8ff 90 {P2_7, PWM_1, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 91 {P2_8, PWM_0, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 92 {P2_9, PWM_3, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 93 {P2_10, PWM_2, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 94 {P2_11, PWM_5, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 95 {P2_12, PWM_4, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 96 {P4_1, PWM_1, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 97 {P4_2, PWM_0, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 98 {P4_3, PWM_3, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 99 {P4_4, PWM_2, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 100 {P4_5, PWM_5, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 101 {P4_6, PWM_4, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 102 {P6_5, PWM_6, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 103 {P6_12, PWM_7, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 104 {P7_0, PWM_14, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 105 {P7_1, PWM_15, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 106 {P7_4, PWM_13, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 107 {P7_5, PWM_12, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 108 {P7_6, PWM_11, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 109 {P7_7, PWM_8, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 110 {PA_4, PWM_9, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 111 {PB_0, PWM_10, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 112 {PB_1, PWM_6, (SCU_PINIO_FAST | 5)},
bogdanm 0:9b334a45a8ff 113 {PB_2, PWM_7, (SCU_PINIO_FAST | 5)},
bogdanm 0:9b334a45a8ff 114 {PB_3, PWM_8, (SCU_PINIO_FAST | 5)},
bogdanm 0:9b334a45a8ff 115 {PD_0, PWM_15, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 116 {PD_2, PWM_7, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 117 {PD_3, PWM_6, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 118 {PD_4, PWM_8, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 119 {PD_5, PWM_9, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 120 {PD_6, PWM_10, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 121 {PD_9, PWM_13, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 122 {PD_11, PWM_14, (SCU_PINIO_FAST | 6)},
bogdanm 0:9b334a45a8ff 123 {PD_12, PWM_10, (SCU_PINIO_FAST | 6)},
bogdanm 0:9b334a45a8ff 124 {PD_13, PWM_13, (SCU_PINIO_FAST | 6)},
bogdanm 0:9b334a45a8ff 125 {PD_14, PWM_11, (SCU_PINIO_FAST | 6)},
bogdanm 0:9b334a45a8ff 126 {PD_15, PWM_8, (SCU_PINIO_FAST | 6)},
bogdanm 0:9b334a45a8ff 127 {PD_16, PWM_12, (SCU_PINIO_FAST | 6)},
bogdanm 0:9b334a45a8ff 128 {PE_5, PWM_3, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 129 {PE_6, PWM_2, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 130 {PE_7, PWM_5, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 131 {PE_8, PWM_4, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 132 {PE_11, PWM_12, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 133 {PE_12, PWM_11, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 134 {PE_13, PWM_14, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 135 {PE_15, PWM_0, (SCU_PINIO_FAST | 1)},
bogdanm 0:9b334a45a8ff 136 {PF_9, PWM_1, (SCU_PINIO_FAST | 2)},
bogdanm 0:9b334a45a8ff 137 {NC, NC, 0}
bogdanm 0:9b334a45a8ff 138 };
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 static unsigned int pwm_clock_mhz;
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 static void _pwmout_dev_init() {
bogdanm 0:9b334a45a8ff 143 uint32_t i;
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 // set SCT clock and config
bogdanm 0:9b334a45a8ff 146 LPC_CCU1->CLKCCU[CLK_MX_SCT].CFG = (1 << 0); // enable SCT clock in CCU1
bogdanm 0:9b334a45a8ff 147 LPC_SCT->CONFIG |= PWM_CONFIG; // set config options
bogdanm 0:9b334a45a8ff 148 *PWM_CTRL |= PWM_HALT; // set HALT bit to stop counter
bogdanm 0:9b334a45a8ff 149 // clear counter and set prescaler for desired freq
bogdanm 0:9b334a45a8ff 150 *PWM_CTRL |= PWM_CLEAR | PWM_PRE(SystemCoreClock / PWM_FREQ_BASE - 1);
bogdanm 0:9b334a45a8ff 151 pwm_clock_mhz = PWM_FREQ_BASE / 1000000;
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 // configure SCT events
bogdanm 0:9b334a45a8ff 154 for (i = 0; i < PWM_EVENT_MAX; i++) {
bogdanm 0:9b334a45a8ff 155 *PWM_MATCH(i) = 0; // match register
bogdanm 0:9b334a45a8ff 156 *PWM_MR(i) = 0; // match reload register
bogdanm 0:9b334a45a8ff 157 LPC_SCT->EVENT[i].STATE = 0xFFFFFFFF; // event happens in all states
bogdanm 0:9b334a45a8ff 158 LPC_SCT->EVENT[i].CTRL = (i << 0) | PWM_EVT_MASK; // match condition only
bogdanm 0:9b334a45a8ff 159 }
bogdanm 0:9b334a45a8ff 160 *PWM_LIMIT = (1 << 0) ; // set event 0 as limit
bogdanm 0:9b334a45a8ff 161 // initialize period to 20ms: standard for servos, and fine for e.g. brightness control
bogdanm 0:9b334a45a8ff 162 *PWM_MR0 = PWM_SETCOUNT((uint32_t)(((20 * PWM_FREQ_BASE) / 1000000) * 1000));
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 // initialize SCT outputs
bogdanm 0:9b334a45a8ff 165 for (i = 0; i < CONFIG_SCT_nOU; i++) {
bogdanm 0:9b334a45a8ff 166 LPC_SCT->OUT[i].SET = (1 << 0); // event 0 will set SCTOUT_xx
bogdanm 0:9b334a45a8ff 167 LPC_SCT->OUT[i].CLR = 0; // set clear event when duty cycle
bogdanm 0:9b334a45a8ff 168 }
bogdanm 0:9b334a45a8ff 169 LPC_SCT->OUTPUT = 0; // default outputs to clear
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 *PWM_CTRL &= ~PWM_HALT; // clear HALT bit to start counter
bogdanm 0:9b334a45a8ff 172 }
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 void pwmout_init(pwmout_t* obj, PinName pin) {
bogdanm 0:9b334a45a8ff 175 // determine the channel
bogdanm 0:9b334a45a8ff 176 PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
bogdanm 0:9b334a45a8ff 177 MBED_ASSERT((pwm != (PWMName)NC) && (event < PWM_EVENT_MAX));
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 // init SCT clock and outputs on first PWM init
bogdanm 0:9b334a45a8ff 180 if (event == 0) {
bogdanm 0:9b334a45a8ff 181 _pwmout_dev_init();
bogdanm 0:9b334a45a8ff 182 }
bogdanm 0:9b334a45a8ff 183 // init PWM object
bogdanm 0:9b334a45a8ff 184 event++;
bogdanm 0:9b334a45a8ff 185 obj->pwm = pwm; // pwm output
bogdanm 0:9b334a45a8ff 186 obj->mr = event; // index of match reload register
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 // initial duty cycle is 0
bogdanm 0:9b334a45a8ff 189 pwmout_write(obj, 0);
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 // Wire pinout
bogdanm 0:9b334a45a8ff 192 pinmap_pinout(pin, PinMap_PWM);
bogdanm 0:9b334a45a8ff 193 }
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 void pwmout_free(pwmout_t* obj) {
bogdanm 0:9b334a45a8ff 196 // [TODO]
bogdanm 0:9b334a45a8ff 197 }
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 void pwmout_write(pwmout_t* obj, float value) {
bogdanm 0:9b334a45a8ff 200 if (value < 0.0f) {
bogdanm 0:9b334a45a8ff 201 value = 0.0;
bogdanm 0:9b334a45a8ff 202 } else if (value > 1.0f) {
bogdanm 0:9b334a45a8ff 203 value = 1.0;
bogdanm 0:9b334a45a8ff 204 }
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 // set new pulse width
bogdanm 0:9b334a45a8ff 207 uint32_t us = (uint32_t)((float)PWM_GETCOUNT(*PWM_MR0) * value) * pwm_clock_mhz;
bogdanm 0:9b334a45a8ff 208 pwmout_pulsewidth_us(obj, us);
bogdanm 0:9b334a45a8ff 209 }
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 float pwmout_read(pwmout_t* obj) {
bogdanm 0:9b334a45a8ff 212 float v = (float)PWM_GETCOUNT(*PWM_MR(obj->mr)) / (float)PWM_GETCOUNT(*PWM_MR0);
bogdanm 0:9b334a45a8ff 213 return (v > 1.0f) ? (1.0f) : (v);
bogdanm 0:9b334a45a8ff 214 }
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 void pwmout_period(pwmout_t* obj, float seconds) {
bogdanm 0:9b334a45a8ff 217 pwmout_period_us(obj, seconds * 1000000.0f);
bogdanm 0:9b334a45a8ff 218 }
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 void pwmout_period_ms(pwmout_t* obj, int ms) {
bogdanm 0:9b334a45a8ff 221 pwmout_period_us(obj, ms * 1000);
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 // Set the PWM period, keeping the duty cycle the same.
bogdanm 0:9b334a45a8ff 225 void pwmout_period_us(pwmout_t* obj, int us) {
bogdanm 0:9b334a45a8ff 226 // calculate number of ticks
bogdanm 0:9b334a45a8ff 227 uint32_t ticks = pwm_clock_mhz * us;
bogdanm 0:9b334a45a8ff 228 uint32_t old_ticks = PWM_GETCOUNT(*PWM_MR0);
bogdanm 0:9b334a45a8ff 229 uint32_t i, v;
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 // set new period
bogdanm 0:9b334a45a8ff 232 *PWM_MR0 = PWM_SETCOUNT(ticks);
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 // Scale pulse widths to preserve the duty ratio
bogdanm 0:9b334a45a8ff 235 for (i = 1; i < PWM_EVENT_MAX; i++) {
bogdanm 0:9b334a45a8ff 236 v = PWM_GETCOUNT(*PWM_MR(i));
bogdanm 0:9b334a45a8ff 237 if (v > 1) {
bogdanm 0:9b334a45a8ff 238 v = (v * ticks) / old_ticks;
bogdanm 0:9b334a45a8ff 239 *PWM_MR(i) = PWM_SETCOUNT(v);
bogdanm 0:9b334a45a8ff 240 }
bogdanm 0:9b334a45a8ff 241 }
bogdanm 0:9b334a45a8ff 242 }
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
bogdanm 0:9b334a45a8ff 245 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
bogdanm 0:9b334a45a8ff 246 }
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
bogdanm 0:9b334a45a8ff 249 pwmout_pulsewidth_us(obj, ms * 1000);
bogdanm 0:9b334a45a8ff 250 }
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
bogdanm 0:9b334a45a8ff 253 // calculate number of ticks
bogdanm 0:9b334a45a8ff 254 uint32_t v = pwm_clock_mhz * us;
bogdanm 0:9b334a45a8ff 255 //MBED_ASSERT(PWM_GETCOUNT(*PWM_MR0) >= v);
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 if (v > 0) {
bogdanm 0:9b334a45a8ff 258 // set new match register value and enable SCT output
bogdanm 0:9b334a45a8ff 259 *PWM_MR(obj->mr) = PWM_SETCOUNT(v);
bogdanm 0:9b334a45a8ff 260 LPC_SCT->OUT[obj->pwm].CLR = (1 << obj->mr); // on event will clear PWM_XX
bogdanm 0:9b334a45a8ff 261 } else {
bogdanm 0:9b334a45a8ff 262 // set match to zero and disable SCT output
bogdanm 0:9b334a45a8ff 263 *PWM_MR(obj->mr) = 0;
bogdanm 0:9b334a45a8ff 264 LPC_SCT->OUT[obj->pwm].CLR = 0;
bogdanm 0:9b334a45a8ff 265 }
bogdanm 0:9b334a45a8ff 266 }