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targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h@178:79309dc6340a, 2017-11-23 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 23 11:57:25 2017 +0000
- Revision:
- 178:79309dc6340a
mbed-dev library. Release version 156
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 178:79309dc6340a | 1 | /*! |
| AnnaBridge | 178:79309dc6340a | 2 | ***************************************************************************** |
| AnnaBridge | 178:79309dc6340a | 3 | @file: adi_spi_config.h |
| AnnaBridge | 178:79309dc6340a | 4 | @brief: Configuration options for SPI driver. |
| AnnaBridge | 178:79309dc6340a | 5 | This is specific to the SPI driver and will be included by the driver. |
| AnnaBridge | 178:79309dc6340a | 6 | It is not required for the application to include this header file. |
| AnnaBridge | 178:79309dc6340a | 7 | ----------------------------------------------------------------------------- |
| AnnaBridge | 178:79309dc6340a | 8 | |
| AnnaBridge | 178:79309dc6340a | 9 | Copyright (c) 2016 Analog Devices, Inc. |
| AnnaBridge | 178:79309dc6340a | 10 | |
| AnnaBridge | 178:79309dc6340a | 11 | All rights reserved. |
| AnnaBridge | 178:79309dc6340a | 12 | |
| AnnaBridge | 178:79309dc6340a | 13 | Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 178:79309dc6340a | 14 | are permitted provided that the following conditions are met: |
| AnnaBridge | 178:79309dc6340a | 15 | - Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 178:79309dc6340a | 16 | this list of conditions and the following disclaimer. |
| AnnaBridge | 178:79309dc6340a | 17 | - Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 178:79309dc6340a | 18 | this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 178:79309dc6340a | 19 | and/or other materials provided with the distribution. |
| AnnaBridge | 178:79309dc6340a | 20 | - Modified versions of the software must be conspicuously marked as such. |
| AnnaBridge | 178:79309dc6340a | 21 | - This software is licensed solely and exclusively for use with processors |
| AnnaBridge | 178:79309dc6340a | 22 | manufactured by or for Analog Devices, Inc. |
| AnnaBridge | 178:79309dc6340a | 23 | - This software may not be combined or merged with other code in any manner |
| AnnaBridge | 178:79309dc6340a | 24 | that would cause the software to become subject to terms and conditions |
| AnnaBridge | 178:79309dc6340a | 25 | which differ from those listed here. |
| AnnaBridge | 178:79309dc6340a | 26 | - Neither the name of Analog Devices, Inc. nor the names of its |
| AnnaBridge | 178:79309dc6340a | 27 | contributors may be used to endorse or promote products derived |
| AnnaBridge | 178:79309dc6340a | 28 | from this software without specific prior written permission. |
| AnnaBridge | 178:79309dc6340a | 29 | - The use of this software may or may not infringe the patent rights of one |
| AnnaBridge | 178:79309dc6340a | 30 | or more patent holders. This license does not release you from the |
| AnnaBridge | 178:79309dc6340a | 31 | requirement that you obtain separate licenses from these patent holders |
| AnnaBridge | 178:79309dc6340a | 32 | to use this software. |
| AnnaBridge | 178:79309dc6340a | 33 | |
| AnnaBridge | 178:79309dc6340a | 34 | THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY |
| AnnaBridge | 178:79309dc6340a | 35 | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, |
| AnnaBridge | 178:79309dc6340a | 36 | TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| AnnaBridge | 178:79309dc6340a | 37 | NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
| AnnaBridge | 178:79309dc6340a | 38 | INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES |
| AnnaBridge | 178:79309dc6340a | 39 | (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL |
| AnnaBridge | 178:79309dc6340a | 40 | PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| AnnaBridge | 178:79309dc6340a | 41 | OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| AnnaBridge | 178:79309dc6340a | 42 | THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| AnnaBridge | 178:79309dc6340a | 43 | NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
| AnnaBridge | 178:79309dc6340a | 44 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 178:79309dc6340a | 45 | |
| AnnaBridge | 178:79309dc6340a | 46 | *****************************************************************************/ |
| AnnaBridge | 178:79309dc6340a | 47 | |
| AnnaBridge | 178:79309dc6340a | 48 | #ifndef ADI_SPI_CONFIG_H__ |
| AnnaBridge | 178:79309dc6340a | 49 | #define ADI_SPI_CONFIG_H__ |
| AnnaBridge | 178:79309dc6340a | 50 | #include <adi_global_config.h> |
| AnnaBridge | 178:79309dc6340a | 51 | /** @addtogroup SPI_Driver_Config Static Configuration |
| AnnaBridge | 178:79309dc6340a | 52 | * @ingroup SPI_Driver |
| AnnaBridge | 178:79309dc6340a | 53 | * @{ |
| AnnaBridge | 178:79309dc6340a | 54 | */ |
| AnnaBridge | 178:79309dc6340a | 55 | |
| AnnaBridge | 178:79309dc6340a | 56 | |
| AnnaBridge | 178:79309dc6340a | 57 | /*! Set this macro to the system clock frequency in hertz*/ |
| AnnaBridge | 178:79309dc6340a | 58 | #define ADI_CFG_SYSTEM_CLOCK_HZ (26000000u) |
| AnnaBridge | 178:79309dc6340a | 59 | |
| AnnaBridge | 178:79309dc6340a | 60 | /************* SPI controller configurations ***************/ |
| AnnaBridge | 178:79309dc6340a | 61 | |
| AnnaBridge | 178:79309dc6340a | 62 | /* There are three SPI instances SPI0, SPI1 and SPI2 */ |
| AnnaBridge | 178:79309dc6340a | 63 | /* Each SPI has its own configuration macros */ |
| AnnaBridge | 178:79309dc6340a | 64 | |
| AnnaBridge | 178:79309dc6340a | 65 | |
| AnnaBridge | 178:79309dc6340a | 66 | /*----------------------------------------------------------*/ |
| AnnaBridge | 178:79309dc6340a | 67 | /* -------------------- SPI0 -------------------------------*/ |
| AnnaBridge | 178:79309dc6340a | 68 | /*----------------------------------------------------------*/ |
| AnnaBridge | 178:79309dc6340a | 69 | |
| AnnaBridge | 178:79309dc6340a | 70 | /** @addtogroup SPI_Driver_Config_SPI0 SPI0 Static Configuration |
| AnnaBridge | 178:79309dc6340a | 71 | * @ingroup SPI_Driver_Config |
| AnnaBridge | 178:79309dc6340a | 72 | * @{ |
| AnnaBridge | 178:79309dc6340a | 73 | */ |
| AnnaBridge | 178:79309dc6340a | 74 | |
| AnnaBridge | 178:79309dc6340a | 75 | /*! If using SPI0 in master mode set this macro to 1. For slave mode set this macro to 0. */ |
| AnnaBridge | 178:79309dc6340a | 76 | #define ADI_SPI0_MASTER_MODE (1u) |
| AnnaBridge | 178:79309dc6340a | 77 | |
| AnnaBridge | 178:79309dc6340a | 78 | |
| AnnaBridge | 178:79309dc6340a | 79 | /*! Set this macro to the SPI0 bit rate in hertz */ |
| AnnaBridge | 178:79309dc6340a | 80 | #define ADI_SPI0_CFG_BIT_RATE (2000000u) |
| AnnaBridge | 178:79309dc6340a | 81 | |
| AnnaBridge | 178:79309dc6340a | 82 | /*! SPI0 enable\n |
| AnnaBridge | 178:79309dc6340a | 83 | SPI configuration register: Bit[0]\n |
| AnnaBridge | 178:79309dc6340a | 84 | 1 - Enable SPI\n |
| AnnaBridge | 178:79309dc6340a | 85 | 0 - Disable SPI */ |
| AnnaBridge | 178:79309dc6340a | 86 | #define ADI_SPI0_CFG_ENABLE (0u) |
| AnnaBridge | 178:79309dc6340a | 87 | |
| AnnaBridge | 178:79309dc6340a | 88 | /*! SPI0 clock phase mode\n |
| AnnaBridge | 178:79309dc6340a | 89 | SPI configuration register: Bit[2]\n |
| AnnaBridge | 178:79309dc6340a | 90 | 1 - Serial clock pulses at the beginning of each serial bit transfer.\n |
| AnnaBridge | 178:79309dc6340a | 91 | 0 - Serial clock pulses at the end of each serial bit transfer. */ |
| AnnaBridge | 178:79309dc6340a | 92 | #define ADI_SPI0_CFG_CLK_PHASE (0u) |
| AnnaBridge | 178:79309dc6340a | 93 | |
| AnnaBridge | 178:79309dc6340a | 94 | |
| AnnaBridge | 178:79309dc6340a | 95 | |
| AnnaBridge | 178:79309dc6340a | 96 | |
| AnnaBridge | 178:79309dc6340a | 97 | |
| AnnaBridge | 178:79309dc6340a | 98 | /*! SPI0 clock polarity\n |
| AnnaBridge | 178:79309dc6340a | 99 | SPI configuration register: Bit[3]\n |
| AnnaBridge | 178:79309dc6340a | 100 | 1 - Serial clock idles high.\n |
| AnnaBridge | 178:79309dc6340a | 101 | 0 - Serial clock idles low. */ |
| AnnaBridge | 178:79309dc6340a | 102 | #define ADI_SPI0_CFG_CLK_POLARITY (0u) |
| AnnaBridge | 178:79309dc6340a | 103 | |
| AnnaBridge | 178:79309dc6340a | 104 | |
| AnnaBridge | 178:79309dc6340a | 105 | /*! SPI0 wired OR mode\n |
| AnnaBridge | 178:79309dc6340a | 106 | SPI configuration register: Bit[4]\n |
| AnnaBridge | 178:79309dc6340a | 107 | 1 - Enables open circuit output enable.\n |
| AnnaBridge | 178:79309dc6340a | 108 | 0 - Normal output levels. */ |
| AnnaBridge | 178:79309dc6340a | 109 | #define ADI_SPI0_CFG_WIRED_OR (0u) |
| AnnaBridge | 178:79309dc6340a | 110 | |
| AnnaBridge | 178:79309dc6340a | 111 | |
| AnnaBridge | 178:79309dc6340a | 112 | /*! SPI0 LSB/MSB\n |
| AnnaBridge | 178:79309dc6340a | 113 | SPI configuration register: Bit[5]\n |
| AnnaBridge | 178:79309dc6340a | 114 | 1 - MSB transmitted first.\n |
| AnnaBridge | 178:79309dc6340a | 115 | 0 - LSB transmitted first. */ |
| AnnaBridge | 178:79309dc6340a | 116 | #define ADI_SPI0_CFG_LSB_MSB (0u) |
| AnnaBridge | 178:79309dc6340a | 117 | |
| AnnaBridge | 178:79309dc6340a | 118 | |
| AnnaBridge | 178:79309dc6340a | 119 | /*! SPI0 transfer initiate\n |
| AnnaBridge | 178:79309dc6340a | 120 | SPI configuration register: Bit[6]\n |
| AnnaBridge | 178:79309dc6340a | 121 | 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n |
| AnnaBridge | 178:79309dc6340a | 122 | 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ |
| AnnaBridge | 178:79309dc6340a | 123 | #define ADI_SPI0_CFG_TRANSFER_INITIATE (0u) |
| AnnaBridge | 178:79309dc6340a | 124 | |
| AnnaBridge | 178:79309dc6340a | 125 | |
| AnnaBridge | 178:79309dc6340a | 126 | /*! SPI0 Tx FIFO transfers zeros or last bit upon underflow\n |
| AnnaBridge | 178:79309dc6340a | 127 | SPI configuration register: Bit[7]\n |
| AnnaBridge | 178:79309dc6340a | 128 | 1 - Tx FIFO sends zeros upon underflow.\n |
| AnnaBridge | 178:79309dc6340a | 129 | 0 - Tx FIFO repeats last bit upon underflow. */ |
| AnnaBridge | 178:79309dc6340a | 130 | #define ADI_SPI0_CFG_TX_UNDERFLOW (0u) |
| AnnaBridge | 178:79309dc6340a | 131 | |
| AnnaBridge | 178:79309dc6340a | 132 | |
| AnnaBridge | 178:79309dc6340a | 133 | /*! SPI0 Rx FIFO overflows with received data or data is discarded\n |
| AnnaBridge | 178:79309dc6340a | 134 | SPI configuration register: Bit[8]\n |
| AnnaBridge | 178:79309dc6340a | 135 | 1 - Rx FIFO receives data upon overflow.\n |
| AnnaBridge | 178:79309dc6340a | 136 | 0 - Rx FIFO discards received data upon overflow. */ |
| AnnaBridge | 178:79309dc6340a | 137 | #define ADI_SPI0_CFG_RX_OVERFLOW (0u) |
| AnnaBridge | 178:79309dc6340a | 138 | |
| AnnaBridge | 178:79309dc6340a | 139 | |
| AnnaBridge | 178:79309dc6340a | 140 | /*! SPI0 slave mode MISO enable\n |
| AnnaBridge | 178:79309dc6340a | 141 | SPI configuration register: Bit[9]\n |
| AnnaBridge | 178:79309dc6340a | 142 | 1 - MISO operates as normal in slave mode.\n |
| AnnaBridge | 178:79309dc6340a | 143 | 0 - MISO is disabled in slave mode. */ |
| AnnaBridge | 178:79309dc6340a | 144 | #define ADI_SPI0_CFG_MISO_ENABLE (0u) |
| AnnaBridge | 178:79309dc6340a | 145 | |
| AnnaBridge | 178:79309dc6340a | 146 | |
| AnnaBridge | 178:79309dc6340a | 147 | /*! SPI0 internal loopback enable\n |
| AnnaBridge | 178:79309dc6340a | 148 | SPI configuration register: Bit[10]\n |
| AnnaBridge | 178:79309dc6340a | 149 | 1 - MISO and MOSI is loopbacked internally.\n |
| AnnaBridge | 178:79309dc6340a | 150 | 0 - MISO and MOSI operates normally. */ |
| AnnaBridge | 178:79309dc6340a | 151 | #define ADI_SPI0_CFG_LOOPBACK (0u) |
| AnnaBridge | 178:79309dc6340a | 152 | |
| AnnaBridge | 178:79309dc6340a | 153 | /*! SPI0 transfer and interrupt mode\n |
| AnnaBridge | 178:79309dc6340a | 154 | SPI configuration register: Bit[11]\n |
| AnnaBridge | 178:79309dc6340a | 155 | 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n |
| AnnaBridge | 178:79309dc6340a | 156 | 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ |
| AnnaBridge | 178:79309dc6340a | 157 | #define ADI_SPI0_CFG_CONTINUOUS (0u) |
| AnnaBridge | 178:79309dc6340a | 158 | |
| AnnaBridge | 178:79309dc6340a | 159 | /*! SPI0 Rx FIFO flush enable\n |
| AnnaBridge | 178:79309dc6340a | 160 | SPI configuration register: Bit[12]\n |
| AnnaBridge | 178:79309dc6340a | 161 | 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n |
| AnnaBridge | 178:79309dc6340a | 162 | 0 - Rx FIFO flush is disabled. */ |
| AnnaBridge | 178:79309dc6340a | 163 | #define ADI_SPI0_CFG_RX_FLUSH (0u) |
| AnnaBridge | 178:79309dc6340a | 164 | |
| AnnaBridge | 178:79309dc6340a | 165 | |
| AnnaBridge | 178:79309dc6340a | 166 | /*! SPI0 Tx FIFO flush enable\n |
| AnnaBridge | 178:79309dc6340a | 167 | SPI configuration register: Bit[13]\n |
| AnnaBridge | 178:79309dc6340a | 168 | 1 - Tx FIFO is flushed.\n |
| AnnaBridge | 178:79309dc6340a | 169 | 0 - Tx FIFO flush is disabled. */ |
| AnnaBridge | 178:79309dc6340a | 170 | #define ADI_SPI0_CFG_TX_FLUSH (0u) |
| AnnaBridge | 178:79309dc6340a | 171 | |
| AnnaBridge | 178:79309dc6340a | 172 | |
| AnnaBridge | 178:79309dc6340a | 173 | /*! Reset Mode for CSERR. \n |
| AnnaBridge | 178:79309dc6340a | 174 | SPI0 configuration register: Bit[14]\n |
| AnnaBridge | 178:79309dc6340a | 175 | 0 - To continue from where it stopped. SPI can receive the remaining bits |
| AnnaBridge | 178:79309dc6340a | 176 | when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n |
| AnnaBridge | 178:79309dc6340a | 177 | 1 - To enable resetting the bit counter and reset if there is a |
| AnnaBridge | 178:79309dc6340a | 178 | CS error condition and the Cortex is expected to clear the SPI_EN bit. |
| AnnaBridge | 178:79309dc6340a | 179 | */ |
| AnnaBridge | 178:79309dc6340a | 180 | #define ADI_SPI0_CFG_CSERR_RESET (0u) |
| AnnaBridge | 178:79309dc6340a | 181 | |
| AnnaBridge | 178:79309dc6340a | 182 | |
| AnnaBridge | 178:79309dc6340a | 183 | /*! SPI0 clock divide\n |
| AnnaBridge | 178:79309dc6340a | 184 | SPI baud rate selection register: Bit[0:5]\n |
| AnnaBridge | 178:79309dc6340a | 185 | Value between 0-63 that is used to divide the UCLK to generate |
| AnnaBridge | 178:79309dc6340a | 186 | the SPI serial clock. */ |
| AnnaBridge | 178:79309dc6340a | 187 | #define ADI_SPI0_CFG_CLK_DIV (0u) |
| AnnaBridge | 178:79309dc6340a | 188 | |
| AnnaBridge | 178:79309dc6340a | 189 | |
| AnnaBridge | 178:79309dc6340a | 190 | /*! SPI0 high frequency mode\n |
| AnnaBridge | 178:79309dc6340a | 191 | SPI baud rate selection register: Bit[6]\n |
| AnnaBridge | 178:79309dc6340a | 192 | 1 - High frequency mode enabled.\n |
| AnnaBridge | 178:79309dc6340a | 193 | 0 - High frequency mode disabled. */ |
| AnnaBridge | 178:79309dc6340a | 194 | #define ADI_SPI0_CFG_HFM (0u) |
| AnnaBridge | 178:79309dc6340a | 195 | |
| AnnaBridge | 178:79309dc6340a | 196 | |
| AnnaBridge | 178:79309dc6340a | 197 | /*! SPI0 reset mode for CSERR\n |
| AnnaBridge | 178:79309dc6340a | 198 | SPI baud rate selection register: Bit[7]\n |
| AnnaBridge | 178:79309dc6340a | 199 | 1 - clear bit counter on CS error.\n |
| AnnaBridge | 178:79309dc6340a | 200 | 0 - do not clear bit counter on CS error. */ |
| AnnaBridge | 178:79309dc6340a | 201 | #define ADI_SPI0_CFG_CS_ERR (0u) |
| AnnaBridge | 178:79309dc6340a | 202 | |
| AnnaBridge | 178:79309dc6340a | 203 | |
| AnnaBridge | 178:79309dc6340a | 204 | /*! SPI0 CS interrupt\n |
| AnnaBridge | 178:79309dc6340a | 205 | SPI baud rate selection register: Bit[8]\n |
| AnnaBridge | 178:79309dc6340a | 206 | 1 - In continuous mode, generate interrupt on CS.\n |
| AnnaBridge | 178:79309dc6340a | 207 | 0 - In continuous mode, do not generate interrupt on CS. */ |
| AnnaBridge | 178:79309dc6340a | 208 | #define ADI_SPI0_CFG_CS_IRQ (0u) |
| AnnaBridge | 178:79309dc6340a | 209 | |
| AnnaBridge | 178:79309dc6340a | 210 | |
| AnnaBridge | 178:79309dc6340a | 211 | /*! @} */ |
| AnnaBridge | 178:79309dc6340a | 212 | |
| AnnaBridge | 178:79309dc6340a | 213 | /*----------------------------------------------------------*/ |
| AnnaBridge | 178:79309dc6340a | 214 | /* -------------------- SPI1 -------------------------------*/ |
| AnnaBridge | 178:79309dc6340a | 215 | /*----------------------------------------------------------*/ |
| AnnaBridge | 178:79309dc6340a | 216 | |
| AnnaBridge | 178:79309dc6340a | 217 | /** @addtogroup SPI_Driver_Config_SPI1 SPI1 Static Configuration |
| AnnaBridge | 178:79309dc6340a | 218 | * @ingroup SPI_Driver_Config |
| AnnaBridge | 178:79309dc6340a | 219 | * @{ |
| AnnaBridge | 178:79309dc6340a | 220 | */ |
| AnnaBridge | 178:79309dc6340a | 221 | |
| AnnaBridge | 178:79309dc6340a | 222 | /*! If using SPI1 in master mode set this macro to 1. For slave mode set this macro to 0. */ |
| AnnaBridge | 178:79309dc6340a | 223 | #define ADI_SPI1_MASTER_MODE (1u) |
| AnnaBridge | 178:79309dc6340a | 224 | |
| AnnaBridge | 178:79309dc6340a | 225 | /*! Set this macro to the SPI1 bit rate in hertz */ |
| AnnaBridge | 178:79309dc6340a | 226 | #define ADI_SPI1_CFG_BIT_RATE (2000000u) |
| AnnaBridge | 178:79309dc6340a | 227 | |
| AnnaBridge | 178:79309dc6340a | 228 | /*! SPI1 enable\n |
| AnnaBridge | 178:79309dc6340a | 229 | SPI configuration register: Bit[0]\n |
| AnnaBridge | 178:79309dc6340a | 230 | 1 - Enable SPI\n |
| AnnaBridge | 178:79309dc6340a | 231 | 0 - Disable SPI */ |
| AnnaBridge | 178:79309dc6340a | 232 | #define ADI_SPI1_CFG_ENABLE (0u) |
| AnnaBridge | 178:79309dc6340a | 233 | |
| AnnaBridge | 178:79309dc6340a | 234 | /*! SPI1 clock phase mode\n |
| AnnaBridge | 178:79309dc6340a | 235 | SPI configuration register: Bit[2]\n |
| AnnaBridge | 178:79309dc6340a | 236 | 1 - Serial clock pulses at the beginning of each serial bit transfer.\n |
| AnnaBridge | 178:79309dc6340a | 237 | 0 - Serial clock pulses at the end of each serial bit transfer. */ |
| AnnaBridge | 178:79309dc6340a | 238 | #define ADI_SPI1_CFG_CLK_PHASE (0u) |
| AnnaBridge | 178:79309dc6340a | 239 | |
| AnnaBridge | 178:79309dc6340a | 240 | |
| AnnaBridge | 178:79309dc6340a | 241 | |
| AnnaBridge | 178:79309dc6340a | 242 | |
| AnnaBridge | 178:79309dc6340a | 243 | |
| AnnaBridge | 178:79309dc6340a | 244 | /*! SPI1 clock polarity\n |
| AnnaBridge | 178:79309dc6340a | 245 | SPI configuration register: Bit[3]\n |
| AnnaBridge | 178:79309dc6340a | 246 | 1 - Serial clock idles high.\n |
| AnnaBridge | 178:79309dc6340a | 247 | 0 - Serial clock idles low. */ |
| AnnaBridge | 178:79309dc6340a | 248 | #define ADI_SPI1_CFG_CLK_POLARITY (0u) |
| AnnaBridge | 178:79309dc6340a | 249 | |
| AnnaBridge | 178:79309dc6340a | 250 | |
| AnnaBridge | 178:79309dc6340a | 251 | /*! SPI1 wired OR mode\n |
| AnnaBridge | 178:79309dc6340a | 252 | SPI configuration register: Bit[4]\n |
| AnnaBridge | 178:79309dc6340a | 253 | 1 - Enables open circuit output enable.\n |
| AnnaBridge | 178:79309dc6340a | 254 | 0 - Normal output levels. */ |
| AnnaBridge | 178:79309dc6340a | 255 | #define ADI_SPI1_CFG_WIRED_OR (0u) |
| AnnaBridge | 178:79309dc6340a | 256 | |
| AnnaBridge | 178:79309dc6340a | 257 | |
| AnnaBridge | 178:79309dc6340a | 258 | /*! SPI1 LSB/MSB\n |
| AnnaBridge | 178:79309dc6340a | 259 | SPI configuration register: Bit[5]\n |
| AnnaBridge | 178:79309dc6340a | 260 | 1 - MSB transmitted first.\n |
| AnnaBridge | 178:79309dc6340a | 261 | 0 - LSB transmitted first. */ |
| AnnaBridge | 178:79309dc6340a | 262 | #define ADI_SPI1_CFG_LSB_MSB (0u) |
| AnnaBridge | 178:79309dc6340a | 263 | |
| AnnaBridge | 178:79309dc6340a | 264 | |
| AnnaBridge | 178:79309dc6340a | 265 | /*! SPI1 transfer initiate\n |
| AnnaBridge | 178:79309dc6340a | 266 | SPI configuration register: Bit[6]\n |
| AnnaBridge | 178:79309dc6340a | 267 | 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n |
| AnnaBridge | 178:79309dc6340a | 268 | 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ |
| AnnaBridge | 178:79309dc6340a | 269 | #define ADI_SPI1_CFG_TRANSFER_INITIATE (0u) |
| AnnaBridge | 178:79309dc6340a | 270 | |
| AnnaBridge | 178:79309dc6340a | 271 | |
| AnnaBridge | 178:79309dc6340a | 272 | /*! SPI1 Tx FIFO transfers zeros or last bit upon underflow\n |
| AnnaBridge | 178:79309dc6340a | 273 | SPI configuration register: Bit[7]\n |
| AnnaBridge | 178:79309dc6340a | 274 | 1 - Tx FIFO sends zeros upon underflow.\n |
| AnnaBridge | 178:79309dc6340a | 275 | 0 - Tx FIFO repeats last bit upon underflow. */ |
| AnnaBridge | 178:79309dc6340a | 276 | #define ADI_SPI1_CFG_TX_UNDERFLOW (0u) |
| AnnaBridge | 178:79309dc6340a | 277 | |
| AnnaBridge | 178:79309dc6340a | 278 | |
| AnnaBridge | 178:79309dc6340a | 279 | /*! SPI1 Rx FIFO overflows with received data or data is discarded\n |
| AnnaBridge | 178:79309dc6340a | 280 | SPI configuration register: Bit[8]\n |
| AnnaBridge | 178:79309dc6340a | 281 | 1 - Rx FIFO receives data upon overflow.\n |
| AnnaBridge | 178:79309dc6340a | 282 | 0 - Rx FIFO discards received data upon overflow. */ |
| AnnaBridge | 178:79309dc6340a | 283 | #define ADI_SPI1_CFG_RX_OVERFLOW (0u) |
| AnnaBridge | 178:79309dc6340a | 284 | |
| AnnaBridge | 178:79309dc6340a | 285 | |
| AnnaBridge | 178:79309dc6340a | 286 | /*! SPI1 slave mode MISO enable\n |
| AnnaBridge | 178:79309dc6340a | 287 | SPI configuration register: Bit[9]\n |
| AnnaBridge | 178:79309dc6340a | 288 | 1 - MISO operates as normal in slave mode.\n |
| AnnaBridge | 178:79309dc6340a | 289 | 0 - MISO is disabled in slave mode. */ |
| AnnaBridge | 178:79309dc6340a | 290 | #define ADI_SPI1_CFG_MISO_ENABLE (0u) |
| AnnaBridge | 178:79309dc6340a | 291 | |
| AnnaBridge | 178:79309dc6340a | 292 | |
| AnnaBridge | 178:79309dc6340a | 293 | /*! SPI1 internal loopback enable\n |
| AnnaBridge | 178:79309dc6340a | 294 | SPI configuration register: Bit[10]\n |
| AnnaBridge | 178:79309dc6340a | 295 | 1 - MISO and MOSI is loopbacked internally.\n |
| AnnaBridge | 178:79309dc6340a | 296 | 0 - MISO and MOSI operates normally. */ |
| AnnaBridge | 178:79309dc6340a | 297 | #define ADI_SPI1_CFG_LOOPBACK (0u) |
| AnnaBridge | 178:79309dc6340a | 298 | |
| AnnaBridge | 178:79309dc6340a | 299 | /*! SPI1 transfer and interrupt mode\n |
| AnnaBridge | 178:79309dc6340a | 300 | SPI configuration register: Bit[11]\n |
| AnnaBridge | 178:79309dc6340a | 301 | 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n |
| AnnaBridge | 178:79309dc6340a | 302 | 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ |
| AnnaBridge | 178:79309dc6340a | 303 | #define ADI_SPI1_CFG_CONTINUOUS (0u) |
| AnnaBridge | 178:79309dc6340a | 304 | |
| AnnaBridge | 178:79309dc6340a | 305 | /*! SPI1 Rx FIFO flush enable\n |
| AnnaBridge | 178:79309dc6340a | 306 | SPI configuration register: Bit[12]\n |
| AnnaBridge | 178:79309dc6340a | 307 | 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n |
| AnnaBridge | 178:79309dc6340a | 308 | 0 - Rx FIFO flush is disabled. */ |
| AnnaBridge | 178:79309dc6340a | 309 | #define ADI_SPI1_CFG_RX_FLUSH (0u) |
| AnnaBridge | 178:79309dc6340a | 310 | |
| AnnaBridge | 178:79309dc6340a | 311 | |
| AnnaBridge | 178:79309dc6340a | 312 | /*! SPI1 Tx FIFO flush enable\n |
| AnnaBridge | 178:79309dc6340a | 313 | SPI configuration register: Bit[13]\n |
| AnnaBridge | 178:79309dc6340a | 314 | 1 - Tx FIFO is flushed.\n |
| AnnaBridge | 178:79309dc6340a | 315 | 0 - Tx FIFO flush is disabled. */ |
| AnnaBridge | 178:79309dc6340a | 316 | #define ADI_SPI1_CFG_TX_FLUSH (0u) |
| AnnaBridge | 178:79309dc6340a | 317 | |
| AnnaBridge | 178:79309dc6340a | 318 | |
| AnnaBridge | 178:79309dc6340a | 319 | /*! Reset Mode for CSERR. \n |
| AnnaBridge | 178:79309dc6340a | 320 | SPI1 configuration register: Bit[14]\n |
| AnnaBridge | 178:79309dc6340a | 321 | 0 - To continue from where it stopped. SPI can receive the remaining bits |
| AnnaBridge | 178:79309dc6340a | 322 | when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n |
| AnnaBridge | 178:79309dc6340a | 323 | 1 - To enable resetting the bit counter and reset if there is a |
| AnnaBridge | 178:79309dc6340a | 324 | CS error condition and the Cortex is expected to clear the SPI_EN bit. |
| AnnaBridge | 178:79309dc6340a | 325 | */ |
| AnnaBridge | 178:79309dc6340a | 326 | #define ADI_SPI1_CFG_CSERR_RESET (0u) |
| AnnaBridge | 178:79309dc6340a | 327 | |
| AnnaBridge | 178:79309dc6340a | 328 | |
| AnnaBridge | 178:79309dc6340a | 329 | /*! SPI1 clock divide\n |
| AnnaBridge | 178:79309dc6340a | 330 | SPI baud rate selection register: Bit[0:5]\n |
| AnnaBridge | 178:79309dc6340a | 331 | Value between 0-63 that is used to divide the UCLK to generate |
| AnnaBridge | 178:79309dc6340a | 332 | the SPI serial clock. */ |
| AnnaBridge | 178:79309dc6340a | 333 | #define ADI_SPI1_CFG_CLK_DIV (0u) |
| AnnaBridge | 178:79309dc6340a | 334 | |
| AnnaBridge | 178:79309dc6340a | 335 | |
| AnnaBridge | 178:79309dc6340a | 336 | /*! SPI1 high frequency mode\n |
| AnnaBridge | 178:79309dc6340a | 337 | SPI baud rate selection register: Bit[6]\n |
| AnnaBridge | 178:79309dc6340a | 338 | 1 - High frequency mode enabled.\n |
| AnnaBridge | 178:79309dc6340a | 339 | 0 - High frequency mode disabled. */ |
| AnnaBridge | 178:79309dc6340a | 340 | #define ADI_SPI1_CFG_HFM (0u) |
| AnnaBridge | 178:79309dc6340a | 341 | |
| AnnaBridge | 178:79309dc6340a | 342 | |
| AnnaBridge | 178:79309dc6340a | 343 | /*! SPI1 reset mode for CSERR\n |
| AnnaBridge | 178:79309dc6340a | 344 | SPI baud rate selection register: Bit[7]\n |
| AnnaBridge | 178:79309dc6340a | 345 | 1 - clear bit counter on CS error.\n |
| AnnaBridge | 178:79309dc6340a | 346 | 0 - do not clear bit counter on CS error. */ |
| AnnaBridge | 178:79309dc6340a | 347 | #define ADI_SPI1_CFG_CS_ERR (0u) |
| AnnaBridge | 178:79309dc6340a | 348 | |
| AnnaBridge | 178:79309dc6340a | 349 | |
| AnnaBridge | 178:79309dc6340a | 350 | /*! SPI1 CS interrupt\n |
| AnnaBridge | 178:79309dc6340a | 351 | SPI baud rate selection register: Bit[8]\n |
| AnnaBridge | 178:79309dc6340a | 352 | 1 - In continuous mode, generate interrupt on CS.\n |
| AnnaBridge | 178:79309dc6340a | 353 | 0 - In continuous mode, do not generate interrupt on CS. */ |
| AnnaBridge | 178:79309dc6340a | 354 | #define ADI_SPI1_CFG_CS_IRQ |
| AnnaBridge | 178:79309dc6340a | 355 | |
| AnnaBridge | 178:79309dc6340a | 356 | /*! @} */ |
| AnnaBridge | 178:79309dc6340a | 357 | |
| AnnaBridge | 178:79309dc6340a | 358 | /*----------------------------------------------------------*/ |
| AnnaBridge | 178:79309dc6340a | 359 | /* -------------------- SPI2 -------------------------------*/ |
| AnnaBridge | 178:79309dc6340a | 360 | /*----------------------------------------------------------*/ |
| AnnaBridge | 178:79309dc6340a | 361 | |
| AnnaBridge | 178:79309dc6340a | 362 | /** @addtogroup SPI_Driver_Config_SPI2 SPI2 Static Configuration |
| AnnaBridge | 178:79309dc6340a | 363 | * @ingroup SP2_Driver_Config |
| AnnaBridge | 178:79309dc6340a | 364 | * @{ |
| AnnaBridge | 178:79309dc6340a | 365 | */ |
| AnnaBridge | 178:79309dc6340a | 366 | |
| AnnaBridge | 178:79309dc6340a | 367 | /*! If using SPI2 in master mode set this macro to 1. For slave mode set this macro to 0. */ |
| AnnaBridge | 178:79309dc6340a | 368 | #define ADI_SPI2_MASTER_MODE (1u) |
| AnnaBridge | 178:79309dc6340a | 369 | |
| AnnaBridge | 178:79309dc6340a | 370 | /*! Set this macro to the SPI2 bit rate in hertz */ |
| AnnaBridge | 178:79309dc6340a | 371 | #define ADI_SPI2_CFG_BIT_RATE (2000000u) |
| AnnaBridge | 178:79309dc6340a | 372 | |
| AnnaBridge | 178:79309dc6340a | 373 | /*! SPI2 enable\n |
| AnnaBridge | 178:79309dc6340a | 374 | SPI configuration register: Bit[0]\n |
| AnnaBridge | 178:79309dc6340a | 375 | 1 - Enable SPI\n |
| AnnaBridge | 178:79309dc6340a | 376 | 0 - Disable SPI */ |
| AnnaBridge | 178:79309dc6340a | 377 | #define ADI_SPI2_CFG_ENABLE (0u) |
| AnnaBridge | 178:79309dc6340a | 378 | |
| AnnaBridge | 178:79309dc6340a | 379 | /*! SPI2 clock phase mode\n |
| AnnaBridge | 178:79309dc6340a | 380 | SPI configuration register: Bit[2]\n |
| AnnaBridge | 178:79309dc6340a | 381 | 1 - Serial clock pulses at the beginning of each serial bit transfer.\n |
| AnnaBridge | 178:79309dc6340a | 382 | 0 - Serial clock pulses at the end of each serial bit transfer. */ |
| AnnaBridge | 178:79309dc6340a | 383 | #define ADI_SPI2_CFG_CLK_PHASE (0u) |
| AnnaBridge | 178:79309dc6340a | 384 | |
| AnnaBridge | 178:79309dc6340a | 385 | |
| AnnaBridge | 178:79309dc6340a | 386 | |
| AnnaBridge | 178:79309dc6340a | 387 | |
| AnnaBridge | 178:79309dc6340a | 388 | |
| AnnaBridge | 178:79309dc6340a | 389 | /*! SPI2 clock polarity\n |
| AnnaBridge | 178:79309dc6340a | 390 | SPI configuration register: Bit[3]\n |
| AnnaBridge | 178:79309dc6340a | 391 | 1 - Serial clock idles high.\n |
| AnnaBridge | 178:79309dc6340a | 392 | 0 - Serial clock idles low. */ |
| AnnaBridge | 178:79309dc6340a | 393 | #define ADI_SPI2_CFG_CLK_POLARITY (0u) |
| AnnaBridge | 178:79309dc6340a | 394 | |
| AnnaBridge | 178:79309dc6340a | 395 | |
| AnnaBridge | 178:79309dc6340a | 396 | /*! SPI2 wired OR mode\n |
| AnnaBridge | 178:79309dc6340a | 397 | SPI configuration register: Bit[4]\n |
| AnnaBridge | 178:79309dc6340a | 398 | 1 - Enables open circuit output enable.\n |
| AnnaBridge | 178:79309dc6340a | 399 | 0 - Normal output levels. */ |
| AnnaBridge | 178:79309dc6340a | 400 | #define ADI_SPI2_CFG_WIRED_OR (0u) |
| AnnaBridge | 178:79309dc6340a | 401 | |
| AnnaBridge | 178:79309dc6340a | 402 | |
| AnnaBridge | 178:79309dc6340a | 403 | /*! SPI2 LSB/MSB\n |
| AnnaBridge | 178:79309dc6340a | 404 | SPI configuration register: Bit[5]\n |
| AnnaBridge | 178:79309dc6340a | 405 | 1 - MSB transmitted first.\n |
| AnnaBridge | 178:79309dc6340a | 406 | 0 - LSB transmitted first. */ |
| AnnaBridge | 178:79309dc6340a | 407 | #define ADI_SPI2_CFG_LSB_MSB (0u) |
| AnnaBridge | 178:79309dc6340a | 408 | |
| AnnaBridge | 178:79309dc6340a | 409 | |
| AnnaBridge | 178:79309dc6340a | 410 | /*! SPI2 transfer initiate\n |
| AnnaBridge | 178:79309dc6340a | 411 | SPI configuration register: Bit[6]\n |
| AnnaBridge | 178:79309dc6340a | 412 | 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n |
| AnnaBridge | 178:79309dc6340a | 413 | 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ |
| AnnaBridge | 178:79309dc6340a | 414 | #define ADI_SPI2_CFG_TRANSFER_INITIATE (0u) |
| AnnaBridge | 178:79309dc6340a | 415 | |
| AnnaBridge | 178:79309dc6340a | 416 | |
| AnnaBridge | 178:79309dc6340a | 417 | /*! SPI2 Tx FIFO transfers zeros or last bit upon underflow\n |
| AnnaBridge | 178:79309dc6340a | 418 | SPI configuration register: Bit[7]\n |
| AnnaBridge | 178:79309dc6340a | 419 | 1 - Tx FIFO sends zeros upon underflow.\n |
| AnnaBridge | 178:79309dc6340a | 420 | 0 - Tx FIFO repeats last bit upon underflow. */ |
| AnnaBridge | 178:79309dc6340a | 421 | #define ADI_SPI2_CFG_TX_UNDERFLOW (0u) |
| AnnaBridge | 178:79309dc6340a | 422 | |
| AnnaBridge | 178:79309dc6340a | 423 | |
| AnnaBridge | 178:79309dc6340a | 424 | /*! SPI2 Rx FIFO overflows with received data or data is discarded\n |
| AnnaBridge | 178:79309dc6340a | 425 | SPI configuration register: Bit[8]\n |
| AnnaBridge | 178:79309dc6340a | 426 | 1 - Rx FIFO receives data upon overflow.\n |
| AnnaBridge | 178:79309dc6340a | 427 | 0 - Rx FIFO discards received data upon overflow. */ |
| AnnaBridge | 178:79309dc6340a | 428 | #define ADI_SPI2_CFG_RX_OVERFLOW (0u) |
| AnnaBridge | 178:79309dc6340a | 429 | |
| AnnaBridge | 178:79309dc6340a | 430 | |
| AnnaBridge | 178:79309dc6340a | 431 | /*! SPI2 slave mode MISO enable\n |
| AnnaBridge | 178:79309dc6340a | 432 | SPI configuration register: Bit[9]\n |
| AnnaBridge | 178:79309dc6340a | 433 | 1 - MISO operates as normal in slave mode.\n |
| AnnaBridge | 178:79309dc6340a | 434 | 0 - MISO is disabled in slave mode. */ |
| AnnaBridge | 178:79309dc6340a | 435 | #define ADI_SPI2_CFG_MISO_ENABLE (0u) |
| AnnaBridge | 178:79309dc6340a | 436 | |
| AnnaBridge | 178:79309dc6340a | 437 | |
| AnnaBridge | 178:79309dc6340a | 438 | /*! SPI2 internal loopback enable\n |
| AnnaBridge | 178:79309dc6340a | 439 | SPI configuration register: Bit[10]\n |
| AnnaBridge | 178:79309dc6340a | 440 | 1 - MISO and MOSI is loopbacked internally.\n |
| AnnaBridge | 178:79309dc6340a | 441 | 0 - MISO and MOSI operates normally. */ |
| AnnaBridge | 178:79309dc6340a | 442 | #define ADI_SPI2_CFG_LOOPBACK (0u) |
| AnnaBridge | 178:79309dc6340a | 443 | |
| AnnaBridge | 178:79309dc6340a | 444 | /*! SPI2 transfer and interrupt mode\n |
| AnnaBridge | 178:79309dc6340a | 445 | SPI configuration register: Bit[11]\n |
| AnnaBridge | 178:79309dc6340a | 446 | 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n |
| AnnaBridge | 178:79309dc6340a | 447 | 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ |
| AnnaBridge | 178:79309dc6340a | 448 | #define ADI_SPI2_CFG_CONTINUOUS (0u) |
| AnnaBridge | 178:79309dc6340a | 449 | |
| AnnaBridge | 178:79309dc6340a | 450 | /*! SPI2 Rx FIFO flush enable\n |
| AnnaBridge | 178:79309dc6340a | 451 | SPI configuration register: Bit[12]\n |
| AnnaBridge | 178:79309dc6340a | 452 | 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n |
| AnnaBridge | 178:79309dc6340a | 453 | 0 - Rx FIFO flush is disabled. */ |
| AnnaBridge | 178:79309dc6340a | 454 | #define ADI_SPI2_CFG_RX_FLUSH (0u) |
| AnnaBridge | 178:79309dc6340a | 455 | |
| AnnaBridge | 178:79309dc6340a | 456 | |
| AnnaBridge | 178:79309dc6340a | 457 | /*! SPI2 Tx FIFO flush enable\n |
| AnnaBridge | 178:79309dc6340a | 458 | SPI configuration register: Bit[13]\n |
| AnnaBridge | 178:79309dc6340a | 459 | 1 - Tx FIFO is flushed.\n |
| AnnaBridge | 178:79309dc6340a | 460 | 0 - Tx FIFO flush is disabled. */ |
| AnnaBridge | 178:79309dc6340a | 461 | #define ADI_SPI2_CFG_TX_FLUSH (0u) |
| AnnaBridge | 178:79309dc6340a | 462 | |
| AnnaBridge | 178:79309dc6340a | 463 | |
| AnnaBridge | 178:79309dc6340a | 464 | /*! Reset Mode for CSERR. \n |
| AnnaBridge | 178:79309dc6340a | 465 | SPI2 configuration register: Bit[14]\n |
| AnnaBridge | 178:79309dc6340a | 466 | 0 - To continue from where it stopped. SPI can receive the remaining bits |
| AnnaBridge | 178:79309dc6340a | 467 | when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n |
| AnnaBridge | 178:79309dc6340a | 468 | 1 - To enable resetting the bit counter and reset if there is a |
| AnnaBridge | 178:79309dc6340a | 469 | CS error condition and the Cortex is expected to clear the SPI_EN bit. |
| AnnaBridge | 178:79309dc6340a | 470 | */ |
| AnnaBridge | 178:79309dc6340a | 471 | #define ADI_SPI2_CFG_CSERR_RESET (0u) |
| AnnaBridge | 178:79309dc6340a | 472 | |
| AnnaBridge | 178:79309dc6340a | 473 | |
| AnnaBridge | 178:79309dc6340a | 474 | /*! SPI2 clock divide\n |
| AnnaBridge | 178:79309dc6340a | 475 | SPI baud rate selection register: Bit[0:5]\n |
| AnnaBridge | 178:79309dc6340a | 476 | Value between 0-63 that is used to divide the UCLK to generate |
| AnnaBridge | 178:79309dc6340a | 477 | the SPI serial clock. */ |
| AnnaBridge | 178:79309dc6340a | 478 | #define ADI_SPI2_CFG_CLK_DIV (0u) |
| AnnaBridge | 178:79309dc6340a | 479 | |
| AnnaBridge | 178:79309dc6340a | 480 | |
| AnnaBridge | 178:79309dc6340a | 481 | /*! SPI2 high frequency mode\n |
| AnnaBridge | 178:79309dc6340a | 482 | SPI baud rate selection register: Bit[6]\n |
| AnnaBridge | 178:79309dc6340a | 483 | 1 - High frequency mode enabled.\n |
| AnnaBridge | 178:79309dc6340a | 484 | 0 - High frequency mode disabled. */ |
| AnnaBridge | 178:79309dc6340a | 485 | #define ADI_SPI2_CFG_HFM (0u) |
| AnnaBridge | 178:79309dc6340a | 486 | |
| AnnaBridge | 178:79309dc6340a | 487 | |
| AnnaBridge | 178:79309dc6340a | 488 | /*! SPI2 reset mode for CSERR\n |
| AnnaBridge | 178:79309dc6340a | 489 | SPI baud rate selection register: Bit[7]\n |
| AnnaBridge | 178:79309dc6340a | 490 | 1 - clear bit counter on CS error.\n |
| AnnaBridge | 178:79309dc6340a | 491 | 0 - do not clear bit counter on CS error. */ |
| AnnaBridge | 178:79309dc6340a | 492 | #define ADI_SPI2_CFG_CS_ERR (0u) |
| AnnaBridge | 178:79309dc6340a | 493 | |
| AnnaBridge | 178:79309dc6340a | 494 | |
| AnnaBridge | 178:79309dc6340a | 495 | /*! SPI2 CS interrupt\n |
| AnnaBridge | 178:79309dc6340a | 496 | SPI baud rate selection register: Bit[8]\n |
| AnnaBridge | 178:79309dc6340a | 497 | 1 - In continuous mode, generate interrupt on CS.\n |
| AnnaBridge | 178:79309dc6340a | 498 | 0 - In continuous mode, do not generate interrupt on CS. */ |
| AnnaBridge | 178:79309dc6340a | 499 | #define ADI_SPI2_CFG_CS_IRQ |
| AnnaBridge | 178:79309dc6340a | 500 | |
| AnnaBridge | 178:79309dc6340a | 501 | /*! @} */ |
| AnnaBridge | 178:79309dc6340a | 502 | |
| AnnaBridge | 178:79309dc6340a | 503 | /************** Macro validation *****************************/ |
| AnnaBridge | 178:79309dc6340a | 504 | |
| AnnaBridge | 178:79309dc6340a | 505 | #if ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \ |
| AnnaBridge | 178:79309dc6340a | 506 | ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \ |
| AnnaBridge | 178:79309dc6340a | 507 | ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) |
| AnnaBridge | 178:79309dc6340a | 508 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 509 | #endif |
| AnnaBridge | 178:79309dc6340a | 510 | |
| AnnaBridge | 178:79309dc6340a | 511 | #if ( ADI_SPI0_CFG_ENABLE > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 512 | ( ADI_SPI1_CFG_ENABLE > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 513 | ( ADI_SPI2_CFG_ENABLE > 1u ) |
| AnnaBridge | 178:79309dc6340a | 514 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 515 | #endif |
| AnnaBridge | 178:79309dc6340a | 516 | |
| AnnaBridge | 178:79309dc6340a | 517 | #if ( ADI_SPI0_CFG_CLK_PHASE > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 518 | ( ADI_SPI1_CFG_CLK_PHASE > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 519 | ( ADI_SPI2_CFG_CLK_PHASE > 1u ) |
| AnnaBridge | 178:79309dc6340a | 520 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 521 | #endif |
| AnnaBridge | 178:79309dc6340a | 522 | |
| AnnaBridge | 178:79309dc6340a | 523 | #if ( ADI_SPI0_CFG_CLK_POLARITY > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 524 | ( ADI_SPI1_CFG_CLK_POLARITY > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 525 | ( ADI_SPI2_CFG_CLK_POLARITY > 1u ) |
| AnnaBridge | 178:79309dc6340a | 526 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 527 | #endif |
| AnnaBridge | 178:79309dc6340a | 528 | |
| AnnaBridge | 178:79309dc6340a | 529 | #if ( ADI_SPI0_CFG_WIRED_OR > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 530 | ( ADI_SPI1_CFG_WIRED_OR > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 531 | ( ADI_SPI2_CFG_WIRED_OR > 1u ) |
| AnnaBridge | 178:79309dc6340a | 532 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 533 | #endif |
| AnnaBridge | 178:79309dc6340a | 534 | |
| AnnaBridge | 178:79309dc6340a | 535 | #if ( ADI_SPI0_CFG_LSB_MSB > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 536 | ( ADI_SPI1_CFG_LSB_MSB > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 537 | ( ADI_SPI2_CFG_LSB_MSB > 1u ) |
| AnnaBridge | 178:79309dc6340a | 538 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 539 | #endif |
| AnnaBridge | 178:79309dc6340a | 540 | |
| AnnaBridge | 178:79309dc6340a | 541 | #if ( ADI_SPI0_CFG_TRANSFER_INITIATE > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 542 | ( ADI_SPI1_CFG_TRANSFER_INITIATE > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 543 | ( ADI_SPI2_CFG_TRANSFER_INITIATE > 1u ) |
| AnnaBridge | 178:79309dc6340a | 544 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 545 | #endif |
| AnnaBridge | 178:79309dc6340a | 546 | |
| AnnaBridge | 178:79309dc6340a | 547 | #if ( ADI_SPI0_CFG_TX_UNDERFLOW > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 548 | ( ADI_SPI1_CFG_TX_UNDERFLOW > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 549 | ( ADI_SPI2_CFG_TX_UNDERFLOW > 1u ) |
| AnnaBridge | 178:79309dc6340a | 550 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 551 | #endif |
| AnnaBridge | 178:79309dc6340a | 552 | |
| AnnaBridge | 178:79309dc6340a | 553 | #if ( ADI_SPI0_CFG_RX_OVERFLOW > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 554 | ( ADI_SPI1_CFG_RX_OVERFLOW > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 555 | ( ADI_SPI2_CFG_RX_OVERFLOW > 1u ) |
| AnnaBridge | 178:79309dc6340a | 556 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 557 | #endif |
| AnnaBridge | 178:79309dc6340a | 558 | |
| AnnaBridge | 178:79309dc6340a | 559 | #if ( ADI_SPI0_CFG_MISO_ENABLE > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 560 | ( ADI_SPI1_CFG_MISO_ENABLE > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 561 | ( ADI_SPI2_CFG_MISO_ENABLE > 1u ) |
| AnnaBridge | 178:79309dc6340a | 562 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 563 | #endif |
| AnnaBridge | 178:79309dc6340a | 564 | |
| AnnaBridge | 178:79309dc6340a | 565 | #if ( ADI_SPI0_CFG_LOOPBACK > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 566 | ( ADI_SPI1_CFG_LOOPBACK > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 567 | ( ADI_SPI2_CFG_LOOPBACK > 1u ) |
| AnnaBridge | 178:79309dc6340a | 568 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 569 | #endif |
| AnnaBridge | 178:79309dc6340a | 570 | |
| AnnaBridge | 178:79309dc6340a | 571 | #if ( ADI_SPI0_CFG_CONTINUOUS > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 572 | ( ADI_SPI1_CFG_CONTINUOUS > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 573 | ( ADI_SPI2_CFG_CONTINUOUS > 1u ) |
| AnnaBridge | 178:79309dc6340a | 574 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 575 | #endif |
| AnnaBridge | 178:79309dc6340a | 576 | |
| AnnaBridge | 178:79309dc6340a | 577 | #if ( ADI_SPI0_CFG_RX_FLUSH > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 578 | ( ADI_SPI1_CFG_RX_FLUSH > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 579 | ( ADI_SPI2_CFG_RX_FLUSH > 1u ) |
| AnnaBridge | 178:79309dc6340a | 580 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 581 | #endif |
| AnnaBridge | 178:79309dc6340a | 582 | |
| AnnaBridge | 178:79309dc6340a | 583 | #if ( ADI_SPI0_CFG_TX_FLUSH > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 584 | ( ADI_SPI1_CFG_TX_FLUSH > 1u ) || \ |
| AnnaBridge | 178:79309dc6340a | 585 | ( ADI_SPI2_CFG_TX_FLUSH > 1u ) |
| AnnaBridge | 178:79309dc6340a | 586 | #error "Invalid configuration" |
| AnnaBridge | 178:79309dc6340a | 587 | #endif |
| AnnaBridge | 178:79309dc6340a | 588 | |
| AnnaBridge | 178:79309dc6340a | 589 | |
| AnnaBridge | 178:79309dc6340a | 590 | /*! @} */ |
| AnnaBridge | 178:79309dc6340a | 591 | |
| AnnaBridge | 178:79309dc6340a | 592 | #endif /* ADI_SPI_CONFIG_H__ */ |