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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_pwr.c@151:5eaa88a5bcc7, 2016-11-24 (annotated)

Committer:
<>
Date:
Thu Nov 24 17:03:03 2016 +0000
Revision:
151:5eaa88a5bcc7
Parent:
149:156823d33999 
This updates the lib to the mbed lib v130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_pwr.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 151:5eaa88a5bcc7 5 * @version V1.7.0
<> 151:5eaa88a5bcc7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief PWR HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Power Controller (PWR) peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 ******************************************************************************
<> 144:ef7eb2e8f9f7 15 * @attention
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 20 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 21 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 22 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 24 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 25 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 27 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 28 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 29 *
<> 144:ef7eb2e8f9f7 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 40 *
<> 144:ef7eb2e8f9f7 41 ******************************************************************************
<> 144:ef7eb2e8f9f7 42 */
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 #ifdef HAL_PWR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 48 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @addtogroup PWR
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /** @addtogroup PWR_Private
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 151:5eaa88a5bcc7 63 #define PVD_MODE_IT ((uint32_t)0x00010000U)
<> 151:5eaa88a5bcc7 64 #define PVD_MODE_EVT ((uint32_t)0x00020000U)
<> 151:5eaa88a5bcc7 65 #define PVD_RISING_EDGE ((uint32_t)0x00000001U)
<> 151:5eaa88a5bcc7 66 #define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 67 /**
<> 144:ef7eb2e8f9f7 68 * @}
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /**
<> 144:ef7eb2e8f9f7 72 * @}
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /** @addtogroup PWR_Exported_Functions
<> 144:ef7eb2e8f9f7 77 * @{
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /** @addtogroup PWR_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 81 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 82 *
<> 144:ef7eb2e8f9f7 83 @verbatim
<> 144:ef7eb2e8f9f7 84 ===============================================================================
<> 144:ef7eb2e8f9f7 85 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 86 ===============================================================================
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 @endverbatim
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /**
<> 144:ef7eb2e8f9f7 93 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 94 * @retval None
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 void HAL_PWR_DeInit(void)
<> 144:ef7eb2e8f9f7 97 {
<> 144:ef7eb2e8f9f7 98 __HAL_RCC_PWR_FORCE_RESET();
<> 144:ef7eb2e8f9f7 99 __HAL_RCC_PWR_RELEASE_RESET();
<> 144:ef7eb2e8f9f7 100 }
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /**
<> 144:ef7eb2e8f9f7 103 * @}
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @addtogroup PWR_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 107 * @brief Low Power modes configuration functions
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 @verbatim
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 ===============================================================================
<> 144:ef7eb2e8f9f7 112 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 113 ===============================================================================
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 *** Backup domain ***
<> 144:ef7eb2e8f9f7 116 =========================
<> 144:ef7eb2e8f9f7 117 [..]
<> 144:ef7eb2e8f9f7 118 After reset, the backup domain (RTC registers, RTC backup data
<> 144:ef7eb2e8f9f7 119 registers) is protected against possible unwanted
<> 144:ef7eb2e8f9f7 120 write accesses.
<> 144:ef7eb2e8f9f7 121 To enable access to the RTC Domain and RTC registers, proceed as follows:
<> 144:ef7eb2e8f9f7 122 (+) Enable the Power Controller (PWR) APB1 interface clock using the
<> 144:ef7eb2e8f9f7 123 __HAL_RCC_PWR_CLK_ENABLE() macro.
<> 144:ef7eb2e8f9f7 124 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 *** PVD configuration ***
<> 144:ef7eb2e8f9f7 127 =========================
<> 144:ef7eb2e8f9f7 128 [..]
<> 144:ef7eb2e8f9f7 129 (+) The PVD is used to monitor the VDD power supply by comparing it to a
<> 144:ef7eb2e8f9f7 130 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
<> 144:ef7eb2e8f9f7 131 (+) The PVD can use an external input analog voltage (PVD_IN) which is compared
<> 144:ef7eb2e8f9f7 132 internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
<> 144:ef7eb2e8f9f7 133 when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
<> 144:ef7eb2e8f9f7 136 than the PVD threshold. This event is internally connected to the EXTI
<> 144:ef7eb2e8f9f7 137 line16 and can generate an interrupt if enabled. This is done through
<> 144:ef7eb2e8f9f7 138 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
<> 144:ef7eb2e8f9f7 139 (+) The PVD is stopped in Standby mode.
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 *** WakeUp pin configuration ***
<> 144:ef7eb2e8f9f7 142 ================================
<> 144:ef7eb2e8f9f7 143 [..]
<> 144:ef7eb2e8f9f7 144 (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
<> 144:ef7eb2e8f9f7 145 forced in input pull-down configuration and is active on rising edges.
<> 144:ef7eb2e8f9f7 146 (+) There are two WakeUp pins:
<> 144:ef7eb2e8f9f7 147 WakeUp Pin 1 on PA.00.
<> 144:ef7eb2e8f9f7 148 WakeUp Pin 2 on PC.13.
<> 144:ef7eb2e8f9f7 149 WakeUp Pin 3 on PE.06 .
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 [..]
<> 144:ef7eb2e8f9f7 153 *** Main and Backup Regulators configuration ***
<> 144:ef7eb2e8f9f7 154 ================================================
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 (+) The main internal regulator can be configured to have a tradeoff between
<> 144:ef7eb2e8f9f7 157 performance and power consumption when the device does not operate at
<> 144:ef7eb2e8f9f7 158 the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
<> 144:ef7eb2e8f9f7 159 macro which configures the two VOS bits in PWR_CR register:
<> 144:ef7eb2e8f9f7 160 (++) PWR_REGULATOR_VOLTAGE_SCALE1 (VOS bits = 01), the regulator voltage output Scale 1 mode selected and
<> 144:ef7eb2e8f9f7 161 the System frequency can go up to 32 MHz.
<> 144:ef7eb2e8f9f7 162 (++) PWR_REGULATOR_VOLTAGE_SCALE2 (VOS bits = 10), the regulator voltage output Scale 2 mode selected and
<> 144:ef7eb2e8f9f7 163 the System frequency can go up to 16 MHz.
<> 144:ef7eb2e8f9f7 164 (++) PWR_REGULATOR_VOLTAGE_SCALE3 (VOS bits = 11), the regulator voltage output Scale 3 mode selected and
<> 144:ef7eb2e8f9f7 165 the System frequency can go up to 4.2 MHz.
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 Refer to the datasheets for more details.
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 *** Low Power modes configuration ***
<> 144:ef7eb2e8f9f7 170 =====================================
<> 144:ef7eb2e8f9f7 171 [..]
<> 144:ef7eb2e8f9f7 172 The device features 5 low-power modes:
<> 144:ef7eb2e8f9f7 173 (+) Low power run mode: regulator in low power mode, limited clock frequency,
<> 144:ef7eb2e8f9f7 174 limited number of peripherals running.
<> 144:ef7eb2e8f9f7 175 (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running.
<> 144:ef7eb2e8f9f7 176 (+) Low power sleep mode: Cortex-M0+ core stopped, limited clock frequency,
<> 144:ef7eb2e8f9f7 177 limited number of peripherals running, regulator in low power mode.
<> 144:ef7eb2e8f9f7 178 (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
<> 144:ef7eb2e8f9f7 179 (+) Standby mode: VCORE domain powered off
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 *** Low power run mode ***
<> 144:ef7eb2e8f9f7 182 =========================
<> 144:ef7eb2e8f9f7 183 [..]
<> 144:ef7eb2e8f9f7 184 To further reduce the consumption when the system is in Run mode, the regulator can be
<> 144:ef7eb2e8f9f7 185 configured in low power mode. In this mode, the system frequency should not exceed
<> 144:ef7eb2e8f9f7 186 MSI frequency range1.
<> 144:ef7eb2e8f9f7 187 In Low power run mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 (+) Entry:
<> 144:ef7eb2e8f9f7 190 (++) VCORE in range2
<> 144:ef7eb2e8f9f7 191 (++) Decrease the system frequency not to exceed the frequency of MSI frequency range1.
<> 144:ef7eb2e8f9f7 192 (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
<> 144:ef7eb2e8f9f7 193 function.
<> 144:ef7eb2e8f9f7 194 (+) Exit:
<> 144:ef7eb2e8f9f7 195 (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()
<> 144:ef7eb2e8f9f7 196 function.
<> 144:ef7eb2e8f9f7 197 (++) Increase the system frequency if needed.
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 *** Sleep mode ***
<> 144:ef7eb2e8f9f7 200 ==================
<> 144:ef7eb2e8f9f7 201 [..]
<> 144:ef7eb2e8f9f7 202 (+) Entry:
<> 144:ef7eb2e8f9f7 203 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
<> 144:ef7eb2e8f9f7 204 functions with
<> 144:ef7eb2e8f9f7 205 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
<> 144:ef7eb2e8f9f7 206 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 (+) Exit:
<> 144:ef7eb2e8f9f7 209 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
<> 144:ef7eb2e8f9f7 210 controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction was used to enter sleep mode,
<> 144:ef7eb2e8f9f7 211 the MCU exits Sleep mode as soon as an event occurs.
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 *** Low power sleep mode ***
<> 144:ef7eb2e8f9f7 214 ============================
<> 144:ef7eb2e8f9f7 215 [..]
<> 144:ef7eb2e8f9f7 216 (+) Entry:
<> 144:ef7eb2e8f9f7 217 The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)
<> 144:ef7eb2e8f9f7 218 functions with
<> 144:ef7eb2e8f9f7 219 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
<> 144:ef7eb2e8f9f7 220 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
<> 144:ef7eb2e8f9f7 221 (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register.
<> 144:ef7eb2e8f9f7 222 This reduces power consumption but increases the wake-up time.
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 (+) Exit:
<> 144:ef7eb2e8f9f7 225 (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
<> 144:ef7eb2e8f9f7 226 acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
<> 144:ef7eb2e8f9f7 227 from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,
<> 144:ef7eb2e8f9f7 228 the MCU exits Sleep mode as soon as an event occurs.
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 *** Stop mode ***
<> 144:ef7eb2e8f9f7 231 =================
<> 144:ef7eb2e8f9f7 232 [..]
<> 144:ef7eb2e8f9f7 233 The Stop mode is based on the Cortex-M0+ deepsleep mode combined with peripheral
<> 144:ef7eb2e8f9f7 234 clock gating. The voltage regulator can be configured either in normal or low-power mode.
<> 144:ef7eb2e8f9f7 235 In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
<> 144:ef7eb2e8f9f7 236 the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
<> 144:ef7eb2e8f9f7 237 To get the lowest consumption in Stop mode, the internal Flash memory also enters low
<> 144:ef7eb2e8f9f7 238 power mode. When the Flash memory is in power-down mode, an additional startup delay is
<> 144:ef7eb2e8f9f7 239 incurred when waking up from Stop mode.
<> 144:ef7eb2e8f9f7 240 To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
<> 144:ef7eb2e8f9f7 241 sensor can be switched off before entering Stop mode. They can be switched on again by
<> 144:ef7eb2e8f9f7 242 software after exiting Stop mode using the ULP bit in the PWR_CR register.
<> 144:ef7eb2e8f9f7 243 In Stop mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 (+) Entry:
<> 144:ef7eb2e8f9f7 246 The Stop mode is entered using the HAL_PWR_EnterSTOPMode
<> 144:ef7eb2e8f9f7 247 function with:
<> 144:ef7eb2e8f9f7 248 (++) Main regulator ON.
<> 144:ef7eb2e8f9f7 249 (++) Low Power regulator ON.
<> 144:ef7eb2e8f9f7 250 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
<> 144:ef7eb2e8f9f7 251 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
<> 144:ef7eb2e8f9f7 252 (+) Exit:
<> 144:ef7eb2e8f9f7 253 (++) By issuing an interrupt or a wakeup event, the MSI or HSI16 RC
<> 144:ef7eb2e8f9f7 254 oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR
<> 144:ef7eb2e8f9f7 255 register
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 *** Standby mode ***
<> 144:ef7eb2e8f9f7 258 ====================
<> 144:ef7eb2e8f9f7 259 [..]
<> 144:ef7eb2e8f9f7 260 The Standby mode allows to achieve the lowest power consumption. It is based on the
<> 144:ef7eb2e8f9f7 261 Cortex-M0+ deepsleep mode, with the voltage regulator disabled. The VCORE domain is
<> 144:ef7eb2e8f9f7 262 consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
<> 144:ef7eb2e8f9f7 263 also switched off. SRAM and register contents are lost except for the RTC registers, RTC
<> 144:ef7eb2e8f9f7 264 backup registers and Standby circuitry.
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
<> 144:ef7eb2e8f9f7 267 sensor can be switched off before entering the Standby mode. They can be switched
<> 144:ef7eb2e8f9f7 268 on again by software after exiting the Standby mode.
<> 144:ef7eb2e8f9f7 269 function.
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 (+) Entry:
<> 144:ef7eb2e8f9f7 272 (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
<> 144:ef7eb2e8f9f7 273 (+) Exit:
<> 144:ef7eb2e8f9f7 274 (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
<> 144:ef7eb2e8f9f7 275 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 *** Auto-wakeup (AWU) from low-power mode ***
<> 144:ef7eb2e8f9f7 278 =============================================
<> 144:ef7eb2e8f9f7 279 [..]
<> 144:ef7eb2e8f9f7 280 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
<> 144:ef7eb2e8f9f7 281 Wakeup event, a tamper event, a time-stamp event, or a comparator event,
<> 144:ef7eb2e8f9f7 282 without depending on an external interrupt (Auto-wakeup mode).
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 (+) RTC auto-wakeup (AWU) from the Stop mode
<> 144:ef7eb2e8f9f7 285 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
<> 144:ef7eb2e8f9f7 286 (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
<> 144:ef7eb2e8f9f7 287 or Event modes) using the EXTI_Init() function.
<> 144:ef7eb2e8f9f7 288 (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
<> 144:ef7eb2e8f9f7 289 (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
<> 144:ef7eb2e8f9f7 290 and RTC_AlarmCmd() functions.
<> 144:ef7eb2e8f9f7 291 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
<> 144:ef7eb2e8f9f7 292 is necessary to:
<> 144:ef7eb2e8f9f7 293 (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
<> 144:ef7eb2e8f9f7 294 or Event modes) using the EXTI_Init() function.
<> 144:ef7eb2e8f9f7 295 (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
<> 144:ef7eb2e8f9f7 296 function.
<> 144:ef7eb2e8f9f7 297 (+++) Configure the RTC to detect the tamper or time stamp event using the
<> 144:ef7eb2e8f9f7 298 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
<> 144:ef7eb2e8f9f7 299 functions.
<> 144:ef7eb2e8f9f7 300 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
<> 144:ef7eb2e8f9f7 301 (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt
<> 144:ef7eb2e8f9f7 302 or Event modes) using the EXTI_Init() function.
<> 144:ef7eb2e8f9f7 303 (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.
<> 144:ef7eb2e8f9f7 304 (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
<> 144:ef7eb2e8f9f7 305 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 (+) RTC auto-wakeup (AWU) from the Standby mode
<> 144:ef7eb2e8f9f7 308 (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
<> 144:ef7eb2e8f9f7 309 (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
<> 144:ef7eb2e8f9f7 310 (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
<> 144:ef7eb2e8f9f7 311 and RTC_AlarmCmd() functions.
<> 144:ef7eb2e8f9f7 312 (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
<> 144:ef7eb2e8f9f7 313 is necessary to:
<> 144:ef7eb2e8f9f7 314 (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
<> 144:ef7eb2e8f9f7 315 function.
<> 144:ef7eb2e8f9f7 316 (+++) Configure the RTC to detect the tamper or time stamp event using the
<> 144:ef7eb2e8f9f7 317 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
<> 144:ef7eb2e8f9f7 318 functions.
<> 144:ef7eb2e8f9f7 319 (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
<> 144:ef7eb2e8f9f7 320 (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
<> 144:ef7eb2e8f9f7 321 (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
<> 144:ef7eb2e8f9f7 322 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 (+) Comparator auto-wakeup (AWU) from the Stop mode
<> 144:ef7eb2e8f9f7 325 (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
<> 144:ef7eb2e8f9f7 326 event, it is necessary to:
<> 144:ef7eb2e8f9f7 327 (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
<> 144:ef7eb2e8f9f7 328 to be sensitive to to the selected edges (falling, rising or falling
<> 144:ef7eb2e8f9f7 329 and rising) (Interrupt or Event modes) using the EXTI_Init() function.
<> 144:ef7eb2e8f9f7 330 (+++) Configure the comparator to generate the event.
<> 144:ef7eb2e8f9f7 331 @endverbatim
<> 144:ef7eb2e8f9f7 332 * @{
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /**
<> 144:ef7eb2e8f9f7 336 * @brief Enables access to the backup domain (RTC registers, RTC
<> 144:ef7eb2e8f9f7 337 * backup data registers ).
<> 144:ef7eb2e8f9f7 338 * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
<> 144:ef7eb2e8f9f7 339 * Backup Domain Access should be kept enabled.
<> 144:ef7eb2e8f9f7 340 * @retval None
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342 void HAL_PWR_EnableBkUpAccess(void)
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 /* Enable access to RTC and backup registers */
<> 144:ef7eb2e8f9f7 345 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /**
<> 144:ef7eb2e8f9f7 349 * @brief Disables access to the backup domain
<> 144:ef7eb2e8f9f7 350 * @note Applies to RTC registers, RTC backup data registers.
<> 144:ef7eb2e8f9f7 351 * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
<> 144:ef7eb2e8f9f7 352 * Backup Domain Access should be kept enabled.
<> 144:ef7eb2e8f9f7 353 * @retval None
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 void HAL_PWR_DisableBkUpAccess(void)
<> 144:ef7eb2e8f9f7 356 {
<> 144:ef7eb2e8f9f7 357 /* Disable access to RTC and backup registers */
<> 144:ef7eb2e8f9f7 358 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 359 }
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
<> 144:ef7eb2e8f9f7 363 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
<> 144:ef7eb2e8f9f7 364 * information for the PVD.
<> 144:ef7eb2e8f9f7 365 * @note Refer to the electrical characteristics of your device datasheet for
<> 144:ef7eb2e8f9f7 366 * more details about the voltage threshold corresponding to each
<> 144:ef7eb2e8f9f7 367 * detection level.
<> 144:ef7eb2e8f9f7 368 * @retval None
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 /* Check the parameters */
<> 144:ef7eb2e8f9f7 373 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
<> 144:ef7eb2e8f9f7 374 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Set PLS[7:5] bits according to PVDLevel value */
<> 144:ef7eb2e8f9f7 377 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 380 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 381 __HAL_PWR_PVD_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 382 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 383 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 386 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 __HAL_PWR_PVD_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* Configure event mode */
<> 144:ef7eb2e8f9f7 392 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Configure the edge */
<> 144:ef7eb2e8f9f7 398 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 }
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /**
<> 144:ef7eb2e8f9f7 410 * @brief Enables the Power Voltage Detector(PVD).
<> 144:ef7eb2e8f9f7 411 * @retval None
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413 void HAL_PWR_EnablePVD(void)
<> 144:ef7eb2e8f9f7 414 {
<> 144:ef7eb2e8f9f7 415 /* Enable the power voltage detector */
<> 144:ef7eb2e8f9f7 416 SET_BIT(PWR->CR, PWR_CR_PVDE);
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /**
<> 144:ef7eb2e8f9f7 420 * @brief Disables the Power Voltage Detector(PVD).
<> 144:ef7eb2e8f9f7 421 * @retval None
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423 void HAL_PWR_DisablePVD(void)
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 /* Disable the power voltage detector */
<> 144:ef7eb2e8f9f7 426 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Enables the WakeUp PINx functionality.
<> 144:ef7eb2e8f9f7 431 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
<> 144:ef7eb2e8f9f7 432 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 433 * @arg PWR_WAKEUP_PIN1
<> 144:ef7eb2e8f9f7 434 * @arg PWR_WAKEUP_PIN2
<> 144:ef7eb2e8f9f7 435 * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
<> 144:ef7eb2e8f9f7 436 * @retval None
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 /* Check the parameter */
<> 144:ef7eb2e8f9f7 441 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
<> 144:ef7eb2e8f9f7 442 /* Enable the EWUPx pin */
<> 144:ef7eb2e8f9f7 443 SET_BIT(PWR->CSR, WakeUpPinx);
<> 144:ef7eb2e8f9f7 444 }
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /**
<> 144:ef7eb2e8f9f7 447 * @brief Disables the WakeUp PINx functionality.
<> 144:ef7eb2e8f9f7 448 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
<> 144:ef7eb2e8f9f7 449 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 450 * @arg PWR_WAKEUP_PIN1
<> 144:ef7eb2e8f9f7 451 * @arg PWR_WAKEUP_PIN2
<> 144:ef7eb2e8f9f7 452 * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
<> 144:ef7eb2e8f9f7 453 * @retval None
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 /* Check the parameter */
<> 144:ef7eb2e8f9f7 458 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
<> 144:ef7eb2e8f9f7 459 /* Disable the EWUPx pin */
<> 144:ef7eb2e8f9f7 460 CLEAR_BIT(PWR->CSR, WakeUpPinx);
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /**
<> 144:ef7eb2e8f9f7 464 * @brief Enters Sleep mode.
<> 144:ef7eb2e8f9f7 465 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 466 * @param Regulator: Specifies the regulator state in SLEEP mode.
<> 144:ef7eb2e8f9f7 467 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 468 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
<> 144:ef7eb2e8f9f7 469 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
<> 144:ef7eb2e8f9f7 470 * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 471 * When WFI entry is used, tick interrupt have to be disabled if not desired as
<> 144:ef7eb2e8f9f7 472 * the interrupt wake up source.
<> 144:ef7eb2e8f9f7 473 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 474 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
<> 144:ef7eb2e8f9f7 475 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
<> 144:ef7eb2e8f9f7 476 * @retval None
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
<> 144:ef7eb2e8f9f7 479 {
<> 151:5eaa88a5bcc7 480 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 481 /* Check the parameters */
<> 144:ef7eb2e8f9f7 482 assert_param(IS_PWR_REGULATOR(Regulator));
<> 144:ef7eb2e8f9f7 483 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /* Select the regulator state in Sleep mode ---------------------------------*/
<> 144:ef7eb2e8f9f7 486 tmpreg = PWR->CR;
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Clear PDDS and LPDS bits */
<> 144:ef7eb2e8f9f7 489 CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Set LPSDSR bit according to PWR_Regulator value */
<> 144:ef7eb2e8f9f7 492 SET_BIT(tmpreg, Regulator);
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Store the new value */
<> 144:ef7eb2e8f9f7 495 PWR->CR = tmpreg;
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Clear SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 498 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Select SLEEP mode entry -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 501 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 504 __WFI();
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506 else
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 509 __SEV();
<> 144:ef7eb2e8f9f7 510 __WFE();
<> 144:ef7eb2e8f9f7 511 __WFE();
<> 144:ef7eb2e8f9f7 512 }
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /**
<> 144:ef7eb2e8f9f7 516 * @brief Enters Stop mode.
<> 144:ef7eb2e8f9f7 517 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 518 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
<> 144:ef7eb2e8f9f7 519 * MSI or HSI16 RCoscillator is selected as system clock depending
<> 144:ef7eb2e8f9f7 520 * the bit STOPWUCK in the RCC_CFGR register.
<> 144:ef7eb2e8f9f7 521 * @note When the voltage regulator operates in low power mode, an additional
<> 144:ef7eb2e8f9f7 522 * startup delay is incurred when waking up from Stop mode.
<> 144:ef7eb2e8f9f7 523 * By keeping the internal regulator ON during Stop mode, the consumption
<> 144:ef7eb2e8f9f7 524 * is higher although the startup time is reduced.
<> 144:ef7eb2e8f9f7 525 * @note Before entering in this function, it is important to ensure that the WUF
<> 144:ef7eb2e8f9f7 526 * wakeup flag is cleared. To perform this action, it is possible to call the
<> 144:ef7eb2e8f9f7 527 * following macro : __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU)
<> 144:ef7eb2e8f9f7 528 *
<> 144:ef7eb2e8f9f7 529 * @param Regulator: Specifies the regulator state in Stop mode.
<> 144:ef7eb2e8f9f7 530 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 531 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
<> 144:ef7eb2e8f9f7 532 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
<> 144:ef7eb2e8f9f7 533 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 534 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 535 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
<> 144:ef7eb2e8f9f7 536 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
<> 144:ef7eb2e8f9f7 537 * @retval None
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 540 {
<> 151:5eaa88a5bcc7 541 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Check the parameters */
<> 144:ef7eb2e8f9f7 544 assert_param(IS_PWR_REGULATOR(Regulator));
<> 144:ef7eb2e8f9f7 545 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Select the regulator state in Stop mode ---------------------------------*/
<> 144:ef7eb2e8f9f7 548 tmpreg = PWR->CR;
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Clear PDDS and LPDS bits */
<> 144:ef7eb2e8f9f7 551 CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Set LPSDSR bit according to PWR_Regulator value */
<> 144:ef7eb2e8f9f7 554 SET_BIT(tmpreg, Regulator);
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* Store the new value */
<> 144:ef7eb2e8f9f7 557 PWR->CR = tmpreg;
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 560 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Select Stop mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 563 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 566 __WFI();
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568 else
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 571 __SEV();
<> 144:ef7eb2e8f9f7 572 __WFE();
<> 144:ef7eb2e8f9f7 573 __WFE();
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 577 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @brief Enters Standby mode.
<> 144:ef7eb2e8f9f7 583 * @note In Standby mode, all I/O pins are high impedance except for:
<> 144:ef7eb2e8f9f7 584 * - Reset pad (still available)
<> 144:ef7eb2e8f9f7 585 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
<> 144:ef7eb2e8f9f7 586 * Alarm out, or RTC clock calibration out.
<> 144:ef7eb2e8f9f7 587 * - RTC_AF2 pin (PC13) if configured for tamper.
<> 144:ef7eb2e8f9f7 588 * - WKUP pin 1 (PA00) if enabled.
<> 144:ef7eb2e8f9f7 589 * - WKUP pin 2 (PC13) if enabled.
<> 144:ef7eb2e8f9f7 590 * - WKUP pin 3 (PE06) if enabled, for stm32l07xxx and stm32l08xxx devices only.
<> 144:ef7eb2e8f9f7 591 * - WKUP pin 3 (PA02) if enabled, for stm32l031xx devices only.
<> 144:ef7eb2e8f9f7 592 * @retval None
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594 void HAL_PWR_EnterSTANDBYMode(void)
<> 144:ef7eb2e8f9f7 595 {
<> 144:ef7eb2e8f9f7 596 /* Select Standby mode */
<> 144:ef7eb2e8f9f7 597 SET_BIT(PWR->CR, PWR_CR_PDDS);
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 600 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* This option is used to ensure that store operations are completed */
<> 144:ef7eb2e8f9f7 603 #if defined ( __CC_ARM)
<> 144:ef7eb2e8f9f7 604 __force_stores();
<> 144:ef7eb2e8f9f7 605 #endif
<> 144:ef7eb2e8f9f7 606 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 607 __WFI();
<> 144:ef7eb2e8f9f7 608 }
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /**
<> 144:ef7eb2e8f9f7 611 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
<> 144:ef7eb2e8f9f7 612 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
<> 144:ef7eb2e8f9f7 613 * re-enters SLEEP mode when an interruption handling is over.
<> 144:ef7eb2e8f9f7 614 * Setting this bit is useful when the processor is expected to run only on
<> 144:ef7eb2e8f9f7 615 * interruptions handling.
<> 144:ef7eb2e8f9f7 616 * @retval None
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 void HAL_PWR_EnableSleepOnExit(void)
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 /* Set SLEEPONEXIT bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 621 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /**
<> 144:ef7eb2e8f9f7 626 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
<> 144:ef7eb2e8f9f7 627 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
<> 144:ef7eb2e8f9f7 628 * re-enters SLEEP mode when an interruption handling is over.
<> 144:ef7eb2e8f9f7 629 * @retval None
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631 void HAL_PWR_DisableSleepOnExit(void)
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 634 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /**
<> 144:ef7eb2e8f9f7 639 * @brief Enables CORTEX M0+ SEVONPEND bit.
<> 144:ef7eb2e8f9f7 640 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
<> 144:ef7eb2e8f9f7 641 * WFE to wake up when an interrupt moves from inactive to pended.
<> 144:ef7eb2e8f9f7 642 * @retval None
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644 void HAL_PWR_EnableSEVOnPend(void)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 /* Set SEVONPEND bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 647 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 144:ef7eb2e8f9f7 648 }
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /**
<> 144:ef7eb2e8f9f7 652 * @brief Disables CORTEX M0+ SEVONPEND bit.
<> 144:ef7eb2e8f9f7 653 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
<> 144:ef7eb2e8f9f7 654 * WFE to wake up when an interrupt moves from inactive to pended.
<> 144:ef7eb2e8f9f7 655 * @retval None
<> 144:ef7eb2e8f9f7 656 */
<> 144:ef7eb2e8f9f7 657 void HAL_PWR_DisableSEVOnPend(void)
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 /* Clear SEVONPEND bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 660 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /**
<> 144:ef7eb2e8f9f7 664 * @brief This function handles the PWR PVD interrupt request.
<> 144:ef7eb2e8f9f7 665 * @note This API should be called under the PVD_IRQHandler().
<> 144:ef7eb2e8f9f7 666 * @retval None
<> 144:ef7eb2e8f9f7 667 */
<> 144:ef7eb2e8f9f7 668 void HAL_PWR_PVD_IRQHandler(void)
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 /* Check PWR exti flag */
<> 144:ef7eb2e8f9f7 671 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 /* PWR PVD interrupt user callback */
<> 144:ef7eb2e8f9f7 674 HAL_PWR_PVDCallback();
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Clear PWR Exti pending bit */
<> 144:ef7eb2e8f9f7 677 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 678 }
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @brief PWR PVD interrupt callback
<> 144:ef7eb2e8f9f7 683 * @retval None
<> 144:ef7eb2e8f9f7 684 */
<> 144:ef7eb2e8f9f7 685 __weak void HAL_PWR_PVDCallback(void)
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 688 the HAL_PWR_PVDCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 689 */
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /**
<> 144:ef7eb2e8f9f7 693 * @}
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @}
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 #endif /* HAL_PWR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 701 /**
<> 144:ef7eb2e8f9f7 702 * @}
<> 144:ef7eb2e8f9f7 703 */
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /**
<> 144:ef7eb2e8f9f7 706 * @}
<> 144:ef7eb2e8f9f7 707 */
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 710