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targets/TARGET_Maxim/TARGET_MAX32620/device/spib_regs.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_Maxim/TARGET_MAX32620/spib_regs.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_SPIB_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_SPIB_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*
<> 144:ef7eb2e8f9f7 44 If types are not defined elsewhere (CMSIS) define them here
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46 #ifndef __IO
<> 144:ef7eb2e8f9f7 47 #define __IO volatile
<> 144:ef7eb2e8f9f7 48 #endif
<> 144:ef7eb2e8f9f7 49 #ifndef __I
<> 144:ef7eb2e8f9f7 50 #define __I volatile const
<> 144:ef7eb2e8f9f7 51 #endif
<> 144:ef7eb2e8f9f7 52 #ifndef __O
<> 144:ef7eb2e8f9f7 53 #define __O volatile
<> 144:ef7eb2e8f9f7 54 #endif
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*
<> 144:ef7eb2e8f9f7 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 144:ef7eb2e8f9f7 59 access to each register in module.
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Offset Register Description
<> 144:ef7eb2e8f9f7 63 ============= ============================================================================ */
<> 144:ef7eb2e8f9f7 64 typedef struct {
<> 144:ef7eb2e8f9f7 65 __IO uint32_t master_cfg; /* 0x0000 SPIB Master Configuration */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t oob_ctrl; /* 0x0004 SPIB OOB Control */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t intfl; /* 0x0008 SPIB Interrupt Flags */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t inten; /* 0x000C SPIB Interrupt Enables */
<> 144:ef7eb2e8f9f7 69 __IO uint32_t slave_reg; /* 0x0010 SPIB Slave Register Access */
<> 144:ef7eb2e8f9f7 70 } mxc_spib_regs_t;
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /*
<> 144:ef7eb2e8f9f7 74 Register offsets for module SPIB.
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #define MXC_R_SPIB_OFFS_MASTER_CFG ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 78 #define MXC_R_SPIB_OFFS_OOB_CTRL ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 79 #define MXC_R_SPIB_OFFS_INTFL ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 80 #define MXC_R_SPIB_OFFS_INTEN ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 81 #define MXC_R_SPIB_OFFS_SLAVE_REG ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /*
<> 144:ef7eb2e8f9f7 85 Field positions and masks for module SPIB.
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #define MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS 0
<> 144:ef7eb2e8f9f7 89 #define MXC_F_SPIB_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
<> 144:ef7eb2e8f9f7 90 #define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS 2
<> 144:ef7eb2e8f9f7 91 #define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
<> 144:ef7eb2e8f9f7 92 #define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS 8
<> 144:ef7eb2e8f9f7 93 #define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS))
<> 144:ef7eb2e8f9f7 94 #define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS 12
<> 144:ef7eb2e8f9f7 95 #define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS))
<> 144:ef7eb2e8f9f7 96 #define MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS 16
<> 144:ef7eb2e8f9f7 97 #define MXC_F_SPIB_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 98 #define MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS 18
<> 144:ef7eb2e8f9f7 99 #define MXC_F_SPIB_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS 0
<> 144:ef7eb2e8f9f7 102 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
<> 144:ef7eb2e8f9f7 103 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS 1
<> 144:ef7eb2e8f9f7 104 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
<> 144:ef7eb2e8f9f7 105 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS 2
<> 144:ef7eb2e8f9f7 106 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 #define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS 0
<> 144:ef7eb2e8f9f7 109 #define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
<> 144:ef7eb2e8f9f7 110 #define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS 1
<> 144:ef7eb2e8f9f7 111 #define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
<> 144:ef7eb2e8f9f7 112 #define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS 2
<> 144:ef7eb2e8f9f7 113 #define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 #define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS 0
<> 144:ef7eb2e8f9f7 116 #define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
<> 144:ef7eb2e8f9f7 117 #define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS 1
<> 144:ef7eb2e8f9f7 118 #define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
<> 144:ef7eb2e8f9f7 119 #define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS 2
<> 144:ef7eb2e8f9f7 120 #define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS 0
<> 144:ef7eb2e8f9f7 123 #define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS))
<> 144:ef7eb2e8f9f7 124 #define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS 1
<> 144:ef7eb2e8f9f7 125 #define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS))
<> 144:ef7eb2e8f9f7 126 #define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS 2
<> 144:ef7eb2e8f9f7 127 #define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
<> 144:ef7eb2e8f9f7 128 #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS 8
<> 144:ef7eb2e8f9f7 129 #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS))
<> 144:ef7eb2e8f9f7 130 #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS 16
<> 144:ef7eb2e8f9f7 131 #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS))
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /*
<> 144:ef7eb2e8f9f7 136 Field values and shifted values for module SPIB.
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 140 #define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 #define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
<> 144:ef7eb2e8f9f7 143 #define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 #define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 146 #define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
<> 144:ef7eb2e8f9f7 149 #define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 152 #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 153 #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 154 #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 157 #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 158 #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 159 #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 162 #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 163 #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 164 #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 167 #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 168 #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 169 #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 172 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
<> 144:ef7eb2e8f9f7 175 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 178 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
<> 144:ef7eb2e8f9f7 181 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 184 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
<> 144:ef7eb2e8f9f7 187 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 #define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 190 #define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
<> 144:ef7eb2e8f9f7 193 #define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 #define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 196 #define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 #define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
<> 144:ef7eb2e8f9f7 199 #define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 #define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 202 #define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 #define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
<> 144:ef7eb2e8f9f7 205 #define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 #define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 208 #define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 #define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
<> 144:ef7eb2e8f9f7 211 #define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 #define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 214 #define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 #define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
<> 144:ef7eb2e8f9f7 217 #define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 #define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 220 #define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 #define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
<> 144:ef7eb2e8f9f7 223 #define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 #define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 226 #define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 #define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
<> 144:ef7eb2e8f9f7 229 #define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235 #endif
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #endif /* _MXC_SPIB_REGS_H_ */
<> 144:ef7eb2e8f9f7 238