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targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
Parent:
149:156823d33999
Child:
161:2cc1468da177
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_i2c.h
<> 144:ef7eb2e8f9f7 3 * @brief Inter-intergrated circuit (I2C) peripheral API
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 144:ef7eb2e8f9f7 5 *******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 *******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 21 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 22 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 23 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 24 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 25 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 28 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 29 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 ******************************************************************************/
<> 144:ef7eb2e8f9f7 32
<> 150:02e0a0aed4ec 33 #ifndef EM_I2C_H
<> 150:02e0a0aed4ec 34 #define EM_I2C_H
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #include "em_device.h"
<> 144:ef7eb2e8f9f7 37 #if defined(I2C_COUNT) && (I2C_COUNT > 0)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #include <stdbool.h>
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 42 extern "C" {
<> 144:ef7eb2e8f9f7 43 #endif
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /***************************************************************************//**
<> 150:02e0a0aed4ec 46 * @addtogroup emlib
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 ******************************************************************************/
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 51 * @addtogroup I2C
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 ******************************************************************************/
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*******************************************************************************
<> 144:ef7eb2e8f9f7 56 ******************************* DEFINES ***********************************
<> 144:ef7eb2e8f9f7 57 ******************************************************************************/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /**
<> 144:ef7eb2e8f9f7 60 * @brief
<> 144:ef7eb2e8f9f7 61 * Standard mode max frequency assuming using 4:4 ratio for Nlow:Nhigh.
<> 144:ef7eb2e8f9f7 62 * @details
<> 144:ef7eb2e8f9f7 63 * From I2C specification: Min Tlow = 4.7us, min Thigh = 4.0us,
<> 144:ef7eb2e8f9f7 64 * max Trise=1.0us, max Tfall=0.3us. Since ratio is 4:4, have to use
<> 144:ef7eb2e8f9f7 65 * worst case value of Tlow or Thigh as base.
<> 144:ef7eb2e8f9f7 66 *
<> 144:ef7eb2e8f9f7 67 * 1/(Tlow + Thigh + 1us + 0.3us) = 1/(4.7 + 4.7 + 1.3)us = 93458Hz
<> 144:ef7eb2e8f9f7 68 * @note
<> 144:ef7eb2e8f9f7 69 * Due to chip characteristics, the max value is somewhat reduced.
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71 #if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_TINY_FAMILY) \
<> 144:ef7eb2e8f9f7 72 || defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY)
<> 144:ef7eb2e8f9f7 73 #define I2C_FREQ_STANDARD_MAX 93000
<> 144:ef7eb2e8f9f7 74 #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 75 #define I2C_FREQ_STANDARD_MAX 92000
<> 144:ef7eb2e8f9f7 76 #elif defined(_SILICON_LABS_32B_PLATFORM_2)
<> 144:ef7eb2e8f9f7 77 // None of the chips on this platform has been characterized on this parameter.
<> 144:ef7eb2e8f9f7 78 // Use same value as on Wonder until further notice.
<> 144:ef7eb2e8f9f7 79 #define I2C_FREQ_STANDARD_MAX 92000
<> 144:ef7eb2e8f9f7 80 #else
<> 144:ef7eb2e8f9f7 81 #error "Unknown device family."
<> 144:ef7eb2e8f9f7 82 #endif
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /**
<> 144:ef7eb2e8f9f7 85 * @brief
<> 144:ef7eb2e8f9f7 86 * Fast mode max frequency assuming using 6:3 ratio for Nlow:Nhigh.
<> 144:ef7eb2e8f9f7 87 * @details
<> 144:ef7eb2e8f9f7 88 * From I2C specification: Min Tlow = 1.3us, min Thigh = 0.6us,
<> 144:ef7eb2e8f9f7 89 * max Trise=0.3us, max Tfall=0.3us. Since ratio is 6:3, have to use
<> 144:ef7eb2e8f9f7 90 * worst case value of Tlow or 2xThigh as base.
<> 144:ef7eb2e8f9f7 91 *
<> 144:ef7eb2e8f9f7 92 * 1/(Tlow + Thigh + 0.3us + 0.3us) = 1/(1.3 + 0.65 + 0.6)us = 392157Hz
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94 #define I2C_FREQ_FAST_MAX 392157
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /**
<> 144:ef7eb2e8f9f7 98 * @brief
<> 144:ef7eb2e8f9f7 99 * Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh.
<> 144:ef7eb2e8f9f7 100 * @details
<> 144:ef7eb2e8f9f7 101 * From I2C specification: Min Tlow = 0.5us, min Thigh = 0.26us,
<> 144:ef7eb2e8f9f7 102 * max Trise=0.12us, max Tfall=0.12us. Since ratio is 11:6, have to use
<> 144:ef7eb2e8f9f7 103 * worst case value of Tlow or (11/6)xThigh as base.
<> 144:ef7eb2e8f9f7 104 *
<> 144:ef7eb2e8f9f7 105 * 1/(Tlow + Thigh + 0.12us + 0.12us) = 1/(0.5 + 0.273 + 0.24)us = 987167Hz
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 #define I2C_FREQ_FASTPLUS_MAX 987167
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /**
<> 144:ef7eb2e8f9f7 111 * @brief
<> 144:ef7eb2e8f9f7 112 * Indicate plain write sequence: S+ADDR(W)+DATA0+P.
<> 144:ef7eb2e8f9f7 113 * @details
<> 144:ef7eb2e8f9f7 114 * @li S - Start
<> 144:ef7eb2e8f9f7 115 * @li ADDR(W) - address with W/R bit cleared
<> 144:ef7eb2e8f9f7 116 * @li DATA0 - Data taken from buffer with index 0
<> 144:ef7eb2e8f9f7 117 * @li P - Stop
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 #define I2C_FLAG_WRITE 0x0001
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @brief
<> 144:ef7eb2e8f9f7 123 * Indicate plain read sequence: S+ADDR(R)+DATA0+P.
<> 144:ef7eb2e8f9f7 124 * @details
<> 144:ef7eb2e8f9f7 125 * @li S - Start
<> 144:ef7eb2e8f9f7 126 * @li ADDR(R) - address with W/R bit set
<> 144:ef7eb2e8f9f7 127 * @li DATA0 - Data read into buffer with index 0
<> 144:ef7eb2e8f9f7 128 * @li P - Stop
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 #define I2C_FLAG_READ 0x0002
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @brief
<> 144:ef7eb2e8f9f7 134 * Indicate combined write/read sequence: S+ADDR(W)+DATA0+Sr+ADDR(R)+DATA1+P.
<> 144:ef7eb2e8f9f7 135 * @details
<> 144:ef7eb2e8f9f7 136 * @li S - Start
<> 144:ef7eb2e8f9f7 137 * @li Sr - Repeated start
<> 144:ef7eb2e8f9f7 138 * @li ADDR(W) - address with W/R bit cleared
<> 144:ef7eb2e8f9f7 139 * @li ADDR(R) - address with W/R bit set
<> 144:ef7eb2e8f9f7 140 * @li DATAn - Data written from/read into buffer with index n
<> 144:ef7eb2e8f9f7 141 * @li P - Stop
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143 #define I2C_FLAG_WRITE_READ 0x0004
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /**
<> 144:ef7eb2e8f9f7 146 * @brief
<> 144:ef7eb2e8f9f7 147 * Indicate write sequence using two buffers: S+ADDR(W)+DATA0+DATA1+P.
<> 144:ef7eb2e8f9f7 148 * @details
<> 144:ef7eb2e8f9f7 149 * @li S - Start
<> 144:ef7eb2e8f9f7 150 * @li ADDR(W) - address with W/R bit cleared
<> 144:ef7eb2e8f9f7 151 * @li DATAn - Data written from buffer with index n
<> 144:ef7eb2e8f9f7 152 * @li P - Stop
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 #define I2C_FLAG_WRITE_WRITE 0x0008
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /** Use 10 bit address. */
<> 144:ef7eb2e8f9f7 157 #define I2C_FLAG_10BIT_ADDR 0x0010
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /*******************************************************************************
<> 144:ef7eb2e8f9f7 161 ******************************** ENUMS ************************************
<> 144:ef7eb2e8f9f7 162 ******************************************************************************/
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /** Clock low to high ratio settings. */
<> 144:ef7eb2e8f9f7 165 typedef enum
<> 144:ef7eb2e8f9f7 166 {
<> 144:ef7eb2e8f9f7 167 i2cClockHLRStandard = _I2C_CTRL_CLHR_STANDARD, /**< Ratio is 4:4 */
<> 144:ef7eb2e8f9f7 168 i2cClockHLRAsymetric = _I2C_CTRL_CLHR_ASYMMETRIC, /**< Ratio is 6:3 */
<> 144:ef7eb2e8f9f7 169 i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */
<> 144:ef7eb2e8f9f7 170 } I2C_ClockHLR_TypeDef;
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /** Return codes for single master mode transfer function. */
<> 144:ef7eb2e8f9f7 174 typedef enum
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 /* In progress code (>0) */
<> 144:ef7eb2e8f9f7 177 i2cTransferInProgress = 1, /**< Transfer in progress. */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Complete code (=0) */
<> 144:ef7eb2e8f9f7 180 i2cTransferDone = 0, /**< Transfer completed successfully. */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Transfer error codes (<0) */
<> 144:ef7eb2e8f9f7 183 i2cTransferNack = -1, /**< NACK received during transfer. */
<> 144:ef7eb2e8f9f7 184 i2cTransferBusErr = -2, /**< Bus error during transfer (misplaced START/STOP). */
<> 144:ef7eb2e8f9f7 185 i2cTransferArbLost = -3, /**< Arbitration lost during transfer. */
<> 144:ef7eb2e8f9f7 186 i2cTransferUsageFault = -4, /**< Usage fault. */
<> 144:ef7eb2e8f9f7 187 i2cTransferSwFault = -5 /**< SW fault. */
<> 144:ef7eb2e8f9f7 188 } I2C_TransferReturn_TypeDef;
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /*******************************************************************************
<> 144:ef7eb2e8f9f7 192 ******************************* STRUCTS ***********************************
<> 144:ef7eb2e8f9f7 193 ******************************************************************************/
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /** I2C initialization structure. */
<> 144:ef7eb2e8f9f7 196 typedef struct
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 /** Enable I2C peripheral when init completed. */
<> 144:ef7eb2e8f9f7 199 bool enable;
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /** Set to master (true) or slave (false) mode */
<> 144:ef7eb2e8f9f7 202 bool master;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * I2C reference clock assumed when configuring bus frequency setup.
<> 144:ef7eb2e8f9f7 206 * Set it to 0 if currently configurated reference clock shall be used
<> 144:ef7eb2e8f9f7 207 * This parameter is only applicable if operating in master mode.
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 uint32_t refFreq;
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * (Max) I2C bus frequency to use. This parameter is only applicable
<> 144:ef7eb2e8f9f7 213 * if operating in master mode.
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 uint32_t freq;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /** Clock low/high ratio control. */
<> 144:ef7eb2e8f9f7 218 I2C_ClockHLR_TypeDef clhr;
<> 144:ef7eb2e8f9f7 219 } I2C_Init_TypeDef;
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** Suggested default config for I2C init structure. */
<> 144:ef7eb2e8f9f7 222 #define I2C_INIT_DEFAULT \
<> 144:ef7eb2e8f9f7 223 { \
<> 144:ef7eb2e8f9f7 224 true, /* Enable when init done */ \
<> 144:ef7eb2e8f9f7 225 true, /* Set to master mode */ \
<> 144:ef7eb2e8f9f7 226 0, /* Use currently configured reference clock */ \
<> 144:ef7eb2e8f9f7 227 I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \
<> 144:ef7eb2e8f9f7 228 /* within I2C spec */ \
<> 144:ef7eb2e8f9f7 229 i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle */ \
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @brief
<> 144:ef7eb2e8f9f7 235 * Master mode transfer message structure used to define a complete
<> 144:ef7eb2e8f9f7 236 * I2C transfer sequence (from start to stop).
<> 144:ef7eb2e8f9f7 237 * @details
<> 144:ef7eb2e8f9f7 238 * The structure allows for defining the following types of sequences,
<> 144:ef7eb2e8f9f7 239 * please refer to defines for sequence details.
<> 144:ef7eb2e8f9f7 240 * @li #I2C_FLAG_READ - data read into buf[0].data
<> 144:ef7eb2e8f9f7 241 * @li #I2C_FLAG_WRITE - data written from buf[0].data
<> 144:ef7eb2e8f9f7 242 * @li #I2C_FLAG_WRITE_READ - data written from buf[0].data and read
<> 144:ef7eb2e8f9f7 243 * into buf[1].data
<> 144:ef7eb2e8f9f7 244 * @li #I2C_FLAG_WRITE_WRITE - data written from buf[0].data and
<> 144:ef7eb2e8f9f7 245 * buf[1].data
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247 typedef struct
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @brief
<> 144:ef7eb2e8f9f7 251 * Address to use after (repeated) start.
<> 144:ef7eb2e8f9f7 252 * @details
<> 144:ef7eb2e8f9f7 253 * Layout details, A = address bit, X = don't care bit (set to 0):
<> 144:ef7eb2e8f9f7 254 * @li 7 bit address - use format AAAA AAAX.
<> 144:ef7eb2e8f9f7 255 * @li 10 bit address - use format XXXX XAAX AAAA AAAA
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 uint16_t addr;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** Flags defining sequence type and details, see I2C_FLAG_... defines. */
<> 144:ef7eb2e8f9f7 260 uint16_t flags;
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * Buffers used to hold data to send from or receive into depending
<> 144:ef7eb2e8f9f7 264 * on sequence type.
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 struct
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 /** Buffer used for data to transmit/receive, must be @p len long. */
<> 144:ef7eb2e8f9f7 269 uint8_t *data;
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /**
<> 144:ef7eb2e8f9f7 272 * Number of bytes in @p data to send or receive. Notice that when
<> 144:ef7eb2e8f9f7 273 * receiving data to this buffer, at least 1 byte must be received.
<> 144:ef7eb2e8f9f7 274 * Setting @p len to 0 in the receive case is considered a usage fault.
<> 144:ef7eb2e8f9f7 275 * Transmitting 0 bytes is legal, in which case only the address
<> 144:ef7eb2e8f9f7 276 * is transmitted after the start condition.
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 uint16_t len;
<> 144:ef7eb2e8f9f7 279 } buf[2];
<> 144:ef7eb2e8f9f7 280 } I2C_TransferSeq_TypeDef;
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /*******************************************************************************
<> 144:ef7eb2e8f9f7 284 ***************************** PROTOTYPES **********************************
<> 144:ef7eb2e8f9f7 285 ******************************************************************************/
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c);
<> 144:ef7eb2e8f9f7 288 void I2C_BusFreqSet(I2C_TypeDef *i2c,
<> 144:ef7eb2e8f9f7 289 uint32_t freqRef,
<> 144:ef7eb2e8f9f7 290 uint32_t freqScl,
<> 144:ef7eb2e8f9f7 291 I2C_ClockHLR_TypeDef i2cMode);
<> 144:ef7eb2e8f9f7 292 void I2C_Enable(I2C_TypeDef *i2c, bool enable);
<> 144:ef7eb2e8f9f7 293 void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init);
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 296 * @brief
<> 144:ef7eb2e8f9f7 297 * Clear one or more pending I2C interrupts.
<> 144:ef7eb2e8f9f7 298 *
<> 144:ef7eb2e8f9f7 299 * @param[in] i2c
<> 144:ef7eb2e8f9f7 300 * Pointer to I2C peripheral register block.
<> 144:ef7eb2e8f9f7 301 *
<> 144:ef7eb2e8f9f7 302 * @param[in] flags
<> 144:ef7eb2e8f9f7 303 * Pending I2C interrupt source to clear. Use a bitwse logic OR combination of
<> 144:ef7eb2e8f9f7 304 * valid interrupt flags for the I2C module (I2C_IF_nnn).
<> 144:ef7eb2e8f9f7 305 ******************************************************************************/
<> 144:ef7eb2e8f9f7 306 __STATIC_INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags)
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 i2c->IFC = flags;
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 313 * @brief
<> 144:ef7eb2e8f9f7 314 * Disable one or more I2C interrupts.
<> 144:ef7eb2e8f9f7 315 *
<> 144:ef7eb2e8f9f7 316 * @param[in] i2c
<> 144:ef7eb2e8f9f7 317 * Pointer to I2C peripheral register block.
<> 144:ef7eb2e8f9f7 318 *
<> 144:ef7eb2e8f9f7 319 * @param[in] flags
<> 144:ef7eb2e8f9f7 320 * I2C interrupt sources to disable. Use a bitwise logic OR combination of
<> 144:ef7eb2e8f9f7 321 * valid interrupt flags for the I2C module (I2C_IF_nnn).
<> 144:ef7eb2e8f9f7 322 ******************************************************************************/
<> 144:ef7eb2e8f9f7 323 __STATIC_INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 i2c->IEN &= ~(flags);
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 330 * @brief
<> 144:ef7eb2e8f9f7 331 * Enable one or more I2C interrupts.
<> 144:ef7eb2e8f9f7 332 *
<> 144:ef7eb2e8f9f7 333 * @note
<> 144:ef7eb2e8f9f7 334 * Depending on the use, a pending interrupt may already be set prior to
<> 144:ef7eb2e8f9f7 335 * enabling the interrupt. Consider using I2C_IntClear() prior to enabling
<> 144:ef7eb2e8f9f7 336 * if such a pending interrupt should be ignored.
<> 144:ef7eb2e8f9f7 337 *
<> 144:ef7eb2e8f9f7 338 * @param[in] i2c
<> 144:ef7eb2e8f9f7 339 * Pointer to I2C peripheral register block.
<> 144:ef7eb2e8f9f7 340 *
<> 144:ef7eb2e8f9f7 341 * @param[in] flags
<> 144:ef7eb2e8f9f7 342 * I2C interrupt sources to enable. Use a bitwise logic OR combination of
<> 144:ef7eb2e8f9f7 343 * valid interrupt flags for the I2C module (I2C_IF_nnn).
<> 144:ef7eb2e8f9f7 344 ******************************************************************************/
<> 144:ef7eb2e8f9f7 345 __STATIC_INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags)
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 i2c->IEN |= flags;
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 352 * @brief
<> 144:ef7eb2e8f9f7 353 * Get pending I2C interrupt flags.
<> 144:ef7eb2e8f9f7 354 *
<> 144:ef7eb2e8f9f7 355 * @note
<> 144:ef7eb2e8f9f7 356 * The event bits are not cleared by the use of this function.
<> 144:ef7eb2e8f9f7 357 *
<> 144:ef7eb2e8f9f7 358 * @param[in] i2c
<> 144:ef7eb2e8f9f7 359 * Pointer to I2C peripheral register block.
<> 144:ef7eb2e8f9f7 360 *
<> 144:ef7eb2e8f9f7 361 * @return
<> 144:ef7eb2e8f9f7 362 * I2C interrupt sources pending. A bitwise logic OR combination of valid
<> 144:ef7eb2e8f9f7 363 * interrupt flags for the I2C module (I2C_IF_nnn).
<> 144:ef7eb2e8f9f7 364 ******************************************************************************/
<> 144:ef7eb2e8f9f7 365 __STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c)
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 return i2c->IF;
<> 144:ef7eb2e8f9f7 368 }
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 372 * @brief
<> 144:ef7eb2e8f9f7 373 * Get enabled and pending I2C interrupt flags.
<> 144:ef7eb2e8f9f7 374 * Useful for handling more interrupt sources in the same interrupt handler.
<> 144:ef7eb2e8f9f7 375 *
<> 144:ef7eb2e8f9f7 376 * @note
<> 144:ef7eb2e8f9f7 377 * Interrupt flags are not cleared by the use of this function.
<> 144:ef7eb2e8f9f7 378 *
<> 144:ef7eb2e8f9f7 379 * @param[in] i2c
<> 144:ef7eb2e8f9f7 380 * Pointer to I2C peripheral register block.
<> 144:ef7eb2e8f9f7 381 *
<> 144:ef7eb2e8f9f7 382 * @return
<> 144:ef7eb2e8f9f7 383 * Pending and enabled I2C interrupt sources
<> 144:ef7eb2e8f9f7 384 * The return value is the bitwise AND of
<> 144:ef7eb2e8f9f7 385 * - the enabled interrupt sources in I2Cn_IEN and
<> 144:ef7eb2e8f9f7 386 * - the pending interrupt flags I2Cn_IF
<> 144:ef7eb2e8f9f7 387 ******************************************************************************/
<> 144:ef7eb2e8f9f7 388 __STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c)
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 uint32_t ien;
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 ien = i2c->IEN;
<> 144:ef7eb2e8f9f7 393 return i2c->IF & ien;
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 398 * @brief
<> 144:ef7eb2e8f9f7 399 * Set one or more pending I2C interrupts from SW.
<> 144:ef7eb2e8f9f7 400 *
<> 144:ef7eb2e8f9f7 401 * @param[in] i2c
<> 144:ef7eb2e8f9f7 402 * Pointer to I2C peripheral register block.
<> 144:ef7eb2e8f9f7 403 *
<> 144:ef7eb2e8f9f7 404 * @param[in] flags
<> 144:ef7eb2e8f9f7 405 * I2C interrupt sources to set to pending. Use a bitwise logic OR combination
<> 144:ef7eb2e8f9f7 406 * of valid interrupt flags for the I2C module (I2C_IF_nnn).
<> 144:ef7eb2e8f9f7 407 ******************************************************************************/
<> 144:ef7eb2e8f9f7 408 __STATIC_INLINE void I2C_IntSet(I2C_TypeDef *i2c, uint32_t flags)
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 i2c->IFS = flags;
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 void I2C_Reset(I2C_TypeDef *i2c);
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 416 * @brief
<> 144:ef7eb2e8f9f7 417 * Get slave address used for I2C peripheral (when operating in slave mode).
<> 144:ef7eb2e8f9f7 418 *
<> 144:ef7eb2e8f9f7 419 * @details
<> 144:ef7eb2e8f9f7 420 * For 10 bit addressing mode, the address is split in two bytes, and only
<> 144:ef7eb2e8f9f7 421 * the first byte setting is fetched, effectively only controlling the 2 most
<> 144:ef7eb2e8f9f7 422 * significant bits of the 10 bit address. Full handling of 10 bit addressing
<> 144:ef7eb2e8f9f7 423 * in slave mode requires additional SW handling.
<> 144:ef7eb2e8f9f7 424 *
<> 144:ef7eb2e8f9f7 425 * @param[in] i2c
<> 144:ef7eb2e8f9f7 426 * Pointer to I2C peripheral register block.
<> 144:ef7eb2e8f9f7 427 *
<> 144:ef7eb2e8f9f7 428 * @return
<> 144:ef7eb2e8f9f7 429 * I2C slave address in use. The 7 most significant bits define the actual
<> 144:ef7eb2e8f9f7 430 * address, the least significant bit is reserved and always returned as 0.
<> 144:ef7eb2e8f9f7 431 ******************************************************************************/
<> 144:ef7eb2e8f9f7 432 __STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c)
<> 144:ef7eb2e8f9f7 433 {
<> 144:ef7eb2e8f9f7 434 return ((uint8_t)(i2c->SADDR));
<> 144:ef7eb2e8f9f7 435 }
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 439 * @brief
<> 144:ef7eb2e8f9f7 440 * Set slave address to use for I2C peripheral (when operating in slave mode).
<> 144:ef7eb2e8f9f7 441 *
<> 144:ef7eb2e8f9f7 442 * @details
<> 144:ef7eb2e8f9f7 443 * For 10 bit addressing mode, the address is split in two bytes, and only
<> 144:ef7eb2e8f9f7 444 * the first byte is set, effectively only controlling the 2 most significant
<> 144:ef7eb2e8f9f7 445 * bits of the 10 bit address. Full handling of 10 bit addressing in slave
<> 144:ef7eb2e8f9f7 446 * mode requires additional SW handling.
<> 144:ef7eb2e8f9f7 447 *
<> 144:ef7eb2e8f9f7 448 * @param[in] i2c
<> 144:ef7eb2e8f9f7 449 * Pointer to I2C peripheral register block.
<> 144:ef7eb2e8f9f7 450 *
<> 144:ef7eb2e8f9f7 451 * @param[in] addr
<> 144:ef7eb2e8f9f7 452 * I2C slave address to use. The 7 most significant bits define the actual
<> 144:ef7eb2e8f9f7 453 * address, the least significant bit is reserved and always set to 0.
<> 144:ef7eb2e8f9f7 454 ******************************************************************************/
<> 144:ef7eb2e8f9f7 455 __STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 i2c->SADDR = (uint32_t)addr & 0xfe;
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 462 * @brief
<> 144:ef7eb2e8f9f7 463 * Get slave address mask used for I2C peripheral (when operating in slave
<> 144:ef7eb2e8f9f7 464 * mode).
<> 144:ef7eb2e8f9f7 465 *
<> 144:ef7eb2e8f9f7 466 * @details
<> 144:ef7eb2e8f9f7 467 * The address mask defines how the comparator works. A bit position with
<> 144:ef7eb2e8f9f7 468 * value 0 means that the corresponding slave address bit is ignored during
<> 144:ef7eb2e8f9f7 469 * comparison (don't care). A bit position with value 1 means that the
<> 144:ef7eb2e8f9f7 470 * corresponding slave address bit must match.
<> 144:ef7eb2e8f9f7 471 *
<> 144:ef7eb2e8f9f7 472 * For 10 bit addressing mode, the address is split in two bytes, and only
<> 144:ef7eb2e8f9f7 473 * the mask for the first address byte is fetched, effectively only
<> 144:ef7eb2e8f9f7 474 * controlling the 2 most significant bits of the 10 bit address.
<> 144:ef7eb2e8f9f7 475 *
<> 144:ef7eb2e8f9f7 476 * @param[in] i2c
<> 144:ef7eb2e8f9f7 477 * Pointer to I2C peripheral register block.
<> 144:ef7eb2e8f9f7 478 *
<> 144:ef7eb2e8f9f7 479 * @return
<> 144:ef7eb2e8f9f7 480 * I2C slave address mask in use. The 7 most significant bits define the
<> 144:ef7eb2e8f9f7 481 * actual address mask, the least significant bit is reserved and always
<> 144:ef7eb2e8f9f7 482 * returned as 0.
<> 144:ef7eb2e8f9f7 483 ******************************************************************************/
<> 144:ef7eb2e8f9f7 484 __STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 return ((uint8_t)(i2c->SADDRMASK));
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 491 * @brief
<> 144:ef7eb2e8f9f7 492 * Set slave address mask used for I2C peripheral (when operating in slave
<> 144:ef7eb2e8f9f7 493 * mode).
<> 144:ef7eb2e8f9f7 494 *
<> 144:ef7eb2e8f9f7 495 * @details
<> 144:ef7eb2e8f9f7 496 * The address mask defines how the comparator works. A bit position with
<> 144:ef7eb2e8f9f7 497 * value 0 means that the corresponding slave address bit is ignored during
<> 144:ef7eb2e8f9f7 498 * comparison (don't care). A bit position with value 1 means that the
<> 144:ef7eb2e8f9f7 499 * corresponding slave address bit must match.
<> 144:ef7eb2e8f9f7 500 *
<> 144:ef7eb2e8f9f7 501 * For 10 bit addressing mode, the address is split in two bytes, and only
<> 144:ef7eb2e8f9f7 502 * the mask for the first address byte is set, effectively only controlling
<> 144:ef7eb2e8f9f7 503 * the 2 most significant bits of the 10 bit address.
<> 144:ef7eb2e8f9f7 504 *
<> 144:ef7eb2e8f9f7 505 * @param[in] i2c
<> 144:ef7eb2e8f9f7 506 * Pointer to I2C peripheral register block.
<> 144:ef7eb2e8f9f7 507 *
<> 144:ef7eb2e8f9f7 508 * @param[in] mask
<> 144:ef7eb2e8f9f7 509 * I2C slave address mask to use. The 7 most significant bits define the
<> 144:ef7eb2e8f9f7 510 * actual address mask, the least significant bit is reserved and should
<> 144:ef7eb2e8f9f7 511 * be 0.
<> 144:ef7eb2e8f9f7 512 ******************************************************************************/
<> 144:ef7eb2e8f9f7 513 __STATIC_INLINE void I2C_SlaveAddressMaskSet(I2C_TypeDef *i2c, uint8_t mask)
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 i2c->SADDRMASK = (uint32_t)mask & 0xfe;
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c);
<> 144:ef7eb2e8f9f7 520 I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
<> 144:ef7eb2e8f9f7 521 I2C_TransferSeq_TypeDef *seq);
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /** @} (end addtogroup I2C) */
<> 150:02e0a0aed4ec 524 /** @} (end addtogroup emlib) */
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528 #endif
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 #endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */
<> 150:02e0a0aed4ec 531 #endif /* EM_I2C_H */