d7a_1x_fs.h

00001 /// ======================================================================
00002 ///
00003 /// Copyright (C) 20XX WizziLab
00004 /// All Rights Reserved
00005 ///
00006 /// =======================================================================
00007 ///
00008 /// @file           d7a_fs_1x.h
00009 /// @brief          D7A 1.x File System definitions
00010 /// @defgroup D7A   D7A 1.x File System definitions
00011 /// @{
00012 /// =======================================================================
00013 
00014 #ifndef __D7A_1X_FS_H__
00015 #define __D7A_1X_FS_H__
00016 
00017 #include "d7a_1x.h"
00018 
00019 // =======================================================================
00020 // d7a_fs_id_t
00021 // -----------------------------------------------------------------------
00022 /// D7A 1.x File System Identifiers (need to be defs for auto linker generation)
00023 // =======================================================================
00024 #define D7A_FID_UID                    0
00025 #define D7A_FID_FACTORY_SETTINGS       1
00026 #define D7A_FID_FIRMWARE_VERSION       2
00027 #define D7A_FID_DEVICE_CAPACITY        3
00028 #define D7A_FID_DEVICE_STATUS          4
00029 #define D7A_FID_ENG                    5
00030 #define D7A_FID_VID                    6
00031 #define D7A_FID_RFU_07                 7
00032 #define D7A_FID_PHY_CFG                8
00033 #define D7A_FID_PHY_STATUS             9
00034 #define D7A_FID_DLL_CFG               10
00035 #define D7A_FID_DLL_STATUS            11
00036 #define D7A_FID_RFU_12                12
00037 #define D7A_FID_NWL_SECURITY          13
00038 #define D7A_FID_NWL_KEY               14
00039 #define D7A_FID_NWL_SSR               15
00040 #define D7A_FID_NWL_STATUS            16
00041 #define D7A_FID_TRL_STATUS            17
00042 #define D7A_FID_SEL_CFG               18
00043 #define D7A_FID_SEL_STATUS            19
00044 #define D7A_FID_RFU_20                20
00045 #define D7A_FID_RFU_21                21
00046 #define D7A_FID_RFU_22                22
00047 #define D7A_FID_LOCATION_DATA         23
00048 #define D7A_FID_ROOT_KEY              24
00049 #define D7A_FID_USER_KEY              25
00050 #define D7A_FID_CHALLENGE             26
00051 #define D7A_FID_SENSOR_DESCRIPTION    27
00052 #define D7A_FID_RTC                   28
00053 #define D7A_FID_TIME_STAMP            29
00054 #define D7A_FID_RFU_30                30
00055 #define D7A_FID_RFU_31                31
00056 #define D7A_FID_ACCESS_PROFILE_0      32
00057 #define D7A_FID_ACCESS_PROFILE_1      33
00058 #define D7A_FID_ACCESS_PROFILE_2      34
00059 #define D7A_FID_ACCESS_PROFILE_3      35
00060 #define D7A_FID_ACCESS_PROFILE_4      36
00061 #define D7A_FID_ACCESS_PROFILE_5      37
00062 #define D7A_FID_ACCESS_PROFILE_6      38
00063 #define D7A_FID_ACCESS_PROFILE_7      39
00064 #define D7A_FID_ACCESS_PROFILE_8      40
00065 #define D7A_FID_ACCESS_PROFILE_9      41
00066 #define D7A_FID_ACCESS_PROFILE_A      42
00067 #define D7A_FID_ACCESS_PROFILE_B      43
00068 #define D7A_FID_ACCESS_PROFILE_C      44
00069 #define D7A_FID_ACCESS_PROFILE_D      45
00070 #define D7A_FID_ACCESS_PROFILE_E      46
00071 #define D7A_FID_ACCESS_PROFILE_F      47
00072 #define D7A_FID_RFU_48                48
00073 #define D7A_FID_RFU_49                49
00074 #define D7A_FID_RFU_50                50
00075 #define D7A_FID_RFU_51                51
00076 #define D7A_FID_RFU_52                52
00077 #define D7A_FID_RFU_53                53
00078 #define D7A_FID_RFU_54                54
00079 #define D7A_FID_RFU_55                55
00080 #define D7A_FID_RFU_56                56
00081 #define D7A_FID_RFU_57                57
00082 #define D7A_FID_RFU_58                58
00083 #define D7A_FID_RFU_59                59
00084 #define D7A_FID_RFU_60                60
00085 #define D7A_FID_RFU_61                61
00086 #define D7A_FID_RFU_62                62
00087 #define D7A_FID_RFU_63                63
00088 
00089 
00090 // =======================================================================
00091 /// Fixed file sizes
00092 // =======================================================================
00093 #define D7A_FS_ROOT_KEY_SIZE            16
00094 #define D7A_FS_USER_KEY_SIZE            16
00095 
00096 // =======================================================================
00097 /// FILE ACCESS TYPES
00098 // =======================================================================
00099 #define D7A_FS_OPENBAR                  0b11110110
00100 #define D7A_FS_STANDARD                 0b11110100
00101 #define D7A_FS_READ_ONLY                0b11100100
00102 #define D7A_FS_USER_RO                  0b11100000
00103 #define D7A_FS_ROOT                     0b11000000
00104 #define D7A_FS_ROOT_RO                  0b10000000
00105 #define D7A_FS_ROOT_WO                  0b01000000
00106 
00107 /// =======================================================================
00108 /// =======================================================================
00109 ///
00110 /// 0. UID
00111 ///
00112 /// =======================================================================
00113 /// =======================================================================
00114 
00115 // =======================================================================
00116 // d7a_uid_t
00117 // -----------------------------------------------------------------------
00118 /// UID File structure
00119 // =======================================================================
00120 TYPEDEF_STRUCT_PACKED
00121 {
00122     /// UID is a u64 in big endian
00123     u8 uid[D7A_UID_LEN];
00124 
00125 } d7a_uid_t;
00126 #define D7A_FS_UID_SIZE                 sizeof(d7a_uid_t)
00127 
00128 /// =======================================================================
00129 /// =======================================================================
00130 ///
00131 /// 1. FACTORY SETTINGS
00132 ///
00133 /// =======================================================================
00134 /// =======================================================================
00135 
00136 // =======================================================================
00137 // d7a_factory_settings_t
00138 // -----------------------------------------------------------------------
00139 /// Factory Settingd File structure
00140 // =======================================================================
00141 TYPEDEF_STRUCT_PACKED
00142 {
00143     /// Calibrated frequency offset to be applied on the central frequency
00144     s16 fof;
00145     /// Reception Insertion Loss (dB)
00146     s8  iloss_rx;
00147     /// Transmission Insertion Loss (dB)
00148     s8  iloss_tx;
00149     /// Power supply voltage in V * 10
00150     u8  vdd;
00151 
00152 } d7a_factory_settings_t;
00153 #define D7A_FS_FACTORY_SETTINGS_SIZE        sizeof(d7a_factory_settings_t)
00154 
00155 /// =======================================================================
00156 /// =======================================================================
00157 ///
00158 /// 3. DEVICE CAPACITY
00159 ///
00160 /// =======================================================================
00161 /// =======================================================================
00162 
00163 // =======================================================================
00164 // d7a_device_t
00165 // -----------------------------------------------------------------------
00166 /// Enumerator of the device types
00167 // =======================================================================
00168 typedef enum
00169 {
00170     /// Endpoint
00171     D7A_DEVICE_EP = 0,
00172     /// Subcontroller
00173     D7A_DEVICE_SC,
00174     /// Gateway
00175     D7A_DEVICE_GW,
00176     /// Quantity
00177     D7A_DEVICE_QTY,
00178 
00179 } d7a_device_t;
00180 
00181 #define D7A_FS_BMP(b)                   (1 << (b))
00182 // =======================================================================
00183 // d7a_device_capacity_t
00184 // -----------------------------------------------------------------------
00185 /// Device Capacity File structure
00186 // =======================================================================
00187 TYPEDEF_STRUCT_PACKED
00188 {
00189     /// Supported ISM bands bitmap
00190     u8  ism_bands_bmp;
00191     /// Supported Channel Classes and Coding Schemes bitmap
00192     u8  ch_class_cs_bmp;
00193     /// Device type
00194     u8  device_type;
00195     /// Supported Network Layer Security Methods
00196     u16 nls_supported;
00197     /// Deprecated : Active Network Layer Security Methods
00198     u16 rfu;
00199     /// Min supported EIRP of the device in dBm
00200     s8  eirp_min;
00201     /// Max supported EIRP of the device in dBm
00202     s8  eirp_max;
00203     /// Total D7A File System Volatile memory
00204     u32 ram_total;
00205     /// Total D7A File System Permanent memory
00206     u32 flash_total;
00207     /// Maximum number of PHY inputs (>= 1)
00208     u16 miso_nb_max;
00209 
00210 } d7a_device_capacity_t;
00211 #define D7A_FS_DEVICE_CAPACITY_SIZE     sizeof(d7a_device_capacity_t)
00212 
00213 /// =======================================================================
00214 /// =======================================================================
00215 ///
00216 /// 4. DEVICE STATUS
00217 ///
00218 /// =======================================================================
00219 /// =======================================================================
00220 
00221 // =======================================================================
00222 // d7a_device_status_t
00223 // -----------------------------------------------------------------------
00224 /// Device Status File structure
00225 // =======================================================================
00226 TYPEDEF_STRUCT_PACKED
00227 {
00228     /// Error Code Bitmap
00229     u8 error_code_bmp;
00230     /// Available D7A File System Volatile memory
00231     u32 ram_available;
00232     /// Available D7A File System Permanent memory
00233     u32 flash_available;
00234 
00235 } d7a_device_status_t;
00236 #define D7A_FS_DEVICE_STATUS_SIZE       sizeof(d7a_device_status_t)
00237 
00238 /// =======================================================================
00239 /// =======================================================================
00240 ///
00241 /// 5. ENG
00242 ///
00243 /// =======================================================================
00244 /// =======================================================================
00245 
00246 // =======================================================================
00247 // d7a_eng_mode_t
00248 // -----------------------------------------------------------------------
00249 /// Enumerator of the Engineering modes
00250 // =======================================================================
00251 typedef enum
00252 {
00253     /// Normal Mode
00254     /// param : not used
00255     D7A_ENG_MODE_NORMAL         = 0,
00256     /// Spectrum Control Protocol flooding
00257     /// param[0] : access class
00258     /// param[1] : flooding duration in seconds (CTF)
00259     D7A_ENG_MODE_SCP            = 2,
00260     /// Beacon Test Mode. Discard duty and CSMA-CA
00261     /// param : not used
00262     D7A_ENG_MODE_BEACON         = 3,
00263     /// Sensitivity Test Mode. Fixed NF/ECCAO sensotivity is set according to the parameters
00264     /// param[0] : Noise Floor / or ECCAO
00265     /// param[1] : param[0] is, when O = NF, when 1 = ECCAO
00266     D7A_ENG_MODE_SENSITIVITY    = 4,
00267 } d7a_eng_mode_t;
00268 
00269 // =======================================================================
00270 // d7a_eng_t
00271 // -----------------------------------------------------------------------
00272 /// Engineering File structure
00273 // =======================================================================
00274 TYPEDEF_STRUCT_PACKED
00275 {
00276     /// Run/Running
00277     u8 run;
00278     /// Engineering Mode
00279     u8 mode;
00280     /// Parameter, depends on the mode (see enumerator)
00281     u8 param[2];
00282 
00283 } d7a_eng_t;
00284 #define D7A_FS_ENG_SIZE       sizeof(d7a_eng_t)
00285 
00286 /// =======================================================================
00287 /// =======================================================================
00288 ///
00289 /// 6. VID
00290 ///
00291 /// =======================================================================
00292 /// =======================================================================
00293 
00294 //======================================================================
00295 /// VID Control
00296 //======================================================================
00297 typedef union
00298 {
00299     struct {
00300         /// BTAG is a 6-bit address tag passed in the background broadcast frames
00301         u8 btag     : 6;
00302         /// Btag acceptance condition (0 : differ, 1 : equal)
00303         u8 bteq     : 1;
00304         /// Declare myself using VID instead of UID
00305         u8 en      :  1;
00306     } bf;
00307 
00308     /// byte access
00309     u8 byte;
00310 
00311 } d7a_vid_ctrl_t;
00312 
00313 // =======================================================================
00314 // d7a_vid_t
00315 // -----------------------------------------------------------------------
00316 /// VID File structure
00317 // =======================================================================
00318 TYPEDEF_STRUCT_PACKED
00319 {
00320     /// VID is a u16 in big endian
00321     u8 vid[D7A_VID_LEN];
00322     /// VID control fields
00323     d7a_vid_ctrl_t ctrl;
00324 
00325 } d7a_vid_t;
00326 #define D7A_FS_VID_SIZE                 sizeof(d7a_vid_t)
00327 
00328 /// =======================================================================
00329 /// =======================================================================
00330 ///
00331 /// 8. PHY CONFIGURATION
00332 ///
00333 /// =======================================================================
00334 /// =======================================================================
00335 
00336 // =======================================================================
00337 // d7a_ext_t
00338 // -----------------------------------------------------------------------
00339 /// Enumerator of the PHY channel extensions
00340 // =======================================================================
00341 typedef enum
00342 {
00343     /// Nominal D7A channels (FSK modulation)
00344     D7A_EXT_FSK = 0,
00345     /// Other D7A channels
00346     D7A_EXT_OTHER = 1,
00347 
00348 } d7a_ext_t;
00349 
00350 // =======================================================================
00351 // d7a_class_t
00352 // -----------------------------------------------------------------------
00353 /// Enumerator of the nominal PHY channel classes
00354 // =======================================================================
00355 typedef enum
00356 {
00357     /// Lo-Rate, 9.6 kbps, 4.8 kHz deviation
00358     D7A_CLASS_LO = 0,
00359     /// Reserved
00360     D7A_CLASS_RFU,
00361     /// Normal-Rate, 55.555 kbps, 50 kHz deviation
00362     D7A_CLASS_NORMAL,
00363     /// Hi-Rate, 166.667 kbps, 41.667 kHz deviation
00364     D7A_CLASS_HI,
00365     /// Quantity
00366     D7A_CLASS_QTY,
00367 
00368 } d7a_class_t;
00369 
00370 // =======================================================================
00371 // d7a_class_ext_t
00372 // -----------------------------------------------------------------------
00373 /// Enumerator of the Extended channel classes
00374 // =======================================================================
00375 typedef enum
00376 {
00377     /// LoRa modulation
00378     D7A_CLASS_EXT_LORA = 0,
00379     /// Reserved
00380     D7A_CLASS_EXT_RFU_1,
00381     /// Sigfox / UNB modulation
00382     D7A_CLASS_EXT_UNB,
00383     /// Decawave / UWB modulation (PHY 802.15.4a)
00384     D7A_CLASS_EXT_UWB,
00385     /// Quantity
00386     D7A_CLASS_EXT_QTY,
00387 
00388 } d7a_class_ext_t;
00389 
00390 // =======================================================================
00391 // d7a_band_t
00392 // -----------------------------------------------------------------------
00393 /// Enumerator of the PHY channel bands
00394 // =======================================================================
00395 typedef enum
00396 {
00397     /// Universal Band 0.0 to 1684 MHz
00398     D7A_BAND_000    = 0,
00399     /// RFU (band 315 MHz ?)
00400     D7A_BAND_RFU_1  = 1,
00401     /// Band 433.060 to 434.785 MHz
00402     D7A_BAND_433    = 2,
00403     /// Band 863.000 to 870.000 MHz
00404     D7A_BAND_868    = 3,
00405     /// Band 902.000 to 928.000 MHz
00406     D7A_BAND_915    = 4,
00407     /// RFU
00408     D7A_BAND_RFU_5  = 5,
00409     /// Band 2400.000 to 2480.000 MHz
00410     D7A_BAND_2400   = 6,
00411     /// Band 3.1 to 10.6 GHz exclusively for UWB usage
00412     D7A_BAND_UWB    = 7,
00413     /// Quantity
00414     D7A_BAND_QTY
00415 
00416 } d7a_band_t;
00417 
00418 // =======================================================================
00419 // d7a_cs_t
00420 // -----------------------------------------------------------------------
00421 /// Enumerator of the PHY channel coding schemes
00422 // =======================================================================
00423 typedef enum
00424 {
00425     /// Nominal - PN9 encoding
00426     /// Extension LoRa - LoRaWAN mode 0 (BW = 125 KHz, SF = 12, FEC 4/5)
00427     /// Extension UNB - TBD
00428     /// Extension UWB - rate 110 kbps
00429     D7A_CS_0 = 0,
00430     /// Nominal - 1/2 FEC + punc 1/4 + PN9 encoding
00431     /// Extension LoRa - LoRaWAN mode 1 (BW = 125 KHz, SF = 11, FEC 4/5)
00432     /// Extension UNB - TBD
00433     /// Extension UWB - rate 850 kbps
00434     D7A_CS_1,
00435     /// Nominal - 1/2 FEC + PN9 encoding
00436     /// Extension LoRa - LoRaWAN mode 2 (BW = 125 KHz, SF = 10, FEC 4/5)
00437     /// Extension UNB - TBD
00438     /// Extension UWB - rate 6.8 Mbps
00439     D7A_CS_2,
00440     /// Nominal - RFU
00441     /// Extension LoRa - LoRaWAN mode 3 (BW = 125 KHz, SF =  8, FEC 4/5)
00442     /// Extension UNB - TBD
00443     /// Extension UWB - TBD
00444     D7A_CS_3,
00445     /// Quantity
00446     D7A_CS_QTY,
00447 
00448 } d7a_cs_t;
00449 
00450 #define D7A_CLASS(a)        (a+4)
00451 
00452 //======================================================================
00453 /// PHY Duty configuration
00454 //======================================================================
00455 typedef union
00456 {
00457     struct {
00458         /// Window type (1: sliding, 0 : fixed)
00459         u8 sliding  : 1;
00460         /// RFU
00461         u8 rfu      : 3;
00462         /// When the widow type is sliding, number of sub-windows.
00463         /// This parameter is used to manage properly the duty
00464         /// limit without having to record every unitary TX event.
00465         /// Instead the duty is always limited to (sub_nb-1)/sub_nb
00466         /// and the duty credit never exceeds 1/sub_nb of the maximum
00467         /// available duty over the window (sliding sub-window).
00468         /// The bigger is sub_nb, the closer the credited duty is to
00469         /// the duty limit, but the smaller is the immediate available
00470         /// credit. For regular transmission of small packets, sub_nb
00471         /// can be kept high (> 10). For rare transmissions of long
00472         /// packets, sub_nb shall be kept small (< 5).
00473         u8 sub_nb   : 4;
00474     } bf;
00475 
00476     /// word access
00477     u8 word;
00478 
00479 } d7a_phy_duty_cfg_t;
00480 
00481 // =======================================================================
00482 // d7a_phy_cfg_t
00483 // -----------------------------------------------------------------------
00484 /// PHY Configuration File structure
00485 // =======================================================================
00486 TYPEDEF_STRUCT_PACKED
00487 {
00488     /// Preamble length depending on channel class
00489     u8 preamble[D7A_CLASS_QTY];
00490     /// Maximum authorized EIRP (dBm)
00491     s8 eirp_limit;
00492     /// TX duty cycle window in 1/10 of sec
00493     d7a_ctf_t duty_win;
00494     /// Duty management configuration
00495     d7a_phy_duty_cfg_t duty_cfg;
00496     /// TX Duty cycle limit in 1/1024 (full scale is 1024)
00497     u16 duty_limit;
00498 
00499 } d7a_phy_cfg_t;
00500 #define D7A_FS_PHY_CFG_SIZE             sizeof(d7a_phy_cfg_t)
00501 
00502 /// =======================================================================
00503 /// =======================================================================
00504 ///
00505 /// 9. PHY STATUS
00506 ///
00507 /// =======================================================================
00508 /// =======================================================================
00509 
00510 /// Maximum number of monitored channels
00511 #define D7A_PHY_MONITORED_CHANNELS              (32)
00512 
00513 //======================================================================
00514 /// PHY Channel Status Identifier
00515 //======================================================================
00516 typedef union
00517 {
00518     struct {
00519         /// Channel index (maximum 1039 indexes for ISM 915, use 11 bits)
00520         u16 idx   : 11;
00521         /// duty limit (0 : duty limit applies, 1 : no duty limit)
00522         u16 duty  :  1;
00523         /// Channel bandwidth (1 : 25 kHz, 0 : 200 kHz)
00524         u16 lo    :  1;
00525         /// Band
00526         u16 band  :  3;
00527     } bf;
00528 
00529     /// word access
00530     u16 word;
00531 
00532 } d7a_phy_status_ch_id_t;
00533 
00534 //======================================================================
00535 /// PHY Channel Monitoring Status
00536 //======================================================================
00537 TYPEDEF_STRUCT_PACKED
00538 {
00539     // Identifier
00540     d7a_phy_status_ch_id_t id;
00541     /// Noise floor in -dBm
00542     u8 nf;
00543 
00544 } d7a_phy_status_ch_t;
00545 
00546 // =======================================================================
00547 // d7a_phy_status_t
00548 // -----------------------------------------------------------------------
00549 /// PHY Status File structure
00550 // =======================================================================
00551 TYPEDEF_STRUCT_PACKED
00552 {
00553     /// Time since power on in seconds
00554     u32 up_time;
00555     /// RX time since power on in seconds
00556     u32 rx_time;
00557     /// TX time since power on in seconds
00558     u32 tx_time;
00559     /// TX Duty cycle in 1/1024 (full scale is 1024)
00560     u16 tx_duty;
00561     /// Number of monitored channels
00562     u8  ch_nb;
00563     /// Channel Status List
00564     d7a_phy_status_ch_t ch[D7A_PHY_MONITORED_CHANNELS];
00565     /// Channel duty credit in compressed format (Ti)
00566     d7a_ctf_t ch_credit[D7A_PHY_MONITORED_CHANNELS];
00567     /// Channel duty
00568     d7a_ctf_t ch_duty[D7A_PHY_MONITORED_CHANNELS];
00569 
00570 } d7a_phy_status_t;
00571 
00572 #define D7A_FS_PHY_STATUS_SIZE          sizeof(d7a_phy_status_t)
00573 
00574 /// =======================================================================
00575 /// =======================================================================
00576 ///
00577 /// 10. DLL CONFIGURATION
00578 ///
00579 /// =======================================================================
00580 /// =======================================================================
00581 
00582 // =======================================================================
00583 // d7a_nf_auto_t
00584 // -----------------------------------------------------------------------
00585 /// DLL Noise Floor Autoscaling
00586 // =======================================================================
00587 typedef enum
00588 {
00589     /// No Autoscaling (default).
00590     /// Always use the Noise Floor and Noise Floor Variance defined in the Access Profile
00591     D7A_NF_AUTO_NO = 0,
00592     /// Slow RSSI Variation.
00593     /// Noise Floor and Noise Floor variance are computed based on regular RSSI measurements
00594     /// with a forget factor defined by the associated parameter
00595     D7A_NF_AUTO_SLOW  = 1,
00596     // Max number of methods
00597     D7A_NF_QTY  = 4,
00598 
00599 } d7a_nf_auto_t;
00600 
00601 // =======================================================================
00602 // d7a_area_t
00603 // -----------------------------------------------------------------------
00604 /// DLL Area Enumerator
00605 // =======================================================================
00606 typedef enum
00607 {
00608     // Unclassified (the Moon, Mars...)
00609     // Reserved for application specific configurations
00610     D7A_AREA_REGION_0   = 0x00,
00611 
00612     // Region 1 (Europe, Russia, Middle East)
00613     D7A_AREA_REGION_1   = 0x10,
00614     // Default area governed by ECC / CEPT / ITU regulations
00615     // European Union, Norway (?), UK (?), Switzerland (?)
00616     D7A_AREA_ECC        = D7A_AREA_REGION_1,
00617     // Russia
00618     D7A_AREA_RUSSIA,
00619     // United Arab Emirates
00620     D7A_AREA_UAE,
00621 
00622     // 0x18 to 0x1F Reserved for application specific configurations
00623 
00624     // Region 2 (Americas)
00625     D7A_AREA_REGION_2   = 0x20,
00626     // Default area governed by FCC regulations
00627     // US, Canada, Chile, Argentina, Columbia,...
00628     D7A_AREA_FCC        = D7A_AREA_REGION_2,
00629     // Brazil
00630     D7A_AREA_BRAZIL,
00631 
00632     // 0x28 to 0x2F Reserved for application specific configurations
00633 
00634     // Region 3 (Asia Pacific)
00635     D7A_AREA_REGION_3   = 0x30,
00636     // Default area governed by Asia-Pacific regulations (seems does not exist yet)
00637     D7A_AREA_ASIA       = D7A_AREA_REGION_3,
00638     // Australia and New Zealand
00639     D7A_AREA_AU_NZ,
00640     // India
00641     D7A_AREA_INDIA,
00642     // Pakistan
00643     D7A_AREA_PAKISTAN,
00644     // Korea
00645     D7A_AREA_KOREA,
00646     // Japan
00647     D7A_AREA_JAPAN,
00648     // China
00649     D7A_AREA_CHINA,
00650     // Hong Kong
00651     D7A_AREA_HK,
00652     // Singapore
00653     D7A_AREA_SINGAPORE,
00654     // Malaysia
00655     D7A_AREA_MALAYSIA,
00656     // Indonesia
00657     D7A_AREA_INDONESIA,
00658 
00659     // Area enumerator mask
00660     D7A_AREA_MASK   = 0x3f,
00661 
00662 } d7a_area_t;
00663 
00664 // =======================================================================
00665 // d7a_cond_t
00666 // -----------------------------------------------------------------------
00667 /// D7A comparison conditions
00668 // =======================================================================
00669 typedef enum
00670 {
00671     /// <, =, > (always true)
00672     D7A_COND_ANY                       = 0,
00673     /// <, >
00674     D7A_COND_NE                        = 1,
00675     /// =
00676     D7A_COND_EQ                        = 2,
00677     /// <
00678     D7A_COND_LT                        = 3,
00679     /// <, =
00680     D7A_COND_LTE                       = 4,
00681     /// >
00682     D7A_COND_GT                        = 5,
00683     /// >, =
00684     D7A_COND_GTE                       = 6,
00685 } d7a_cond_t;
00686 // =======================================================================
00687 // d7a_dll_cfg_flags_t
00688 // -----------------------------------------------------------------------
00689 /// DLL control flags structure
00690 // =======================================================================
00691 typedef union
00692 {
00693     // bit access fields
00694     struct {
00695         // NF method
00696         u8 nf               :2;
00697         // btag filter condition (0 = disable)
00698         u8 btag_cond        :3;
00699         // 5.x - 6.x timout compatibility (REMOVEME)
00700         u8 comp_5x          :1;
00701         // RFU
00702         u8 rfu              :2;
00703     } bf;
00704     // byte access
00705     u8 byte;
00706 } d7a_dll_cfg_flags_t;
00707 // =======================================================================
00708 // d7a_dll_cfg_flags2_t
00709 // -----------------------------------------------------------------------
00710 /// DLL control flags2 structure
00711 // =======================================================================
00712 typedef union
00713 {
00714     // bit access fields
00715     struct {
00716         // Restart scheduler on TX done (main XCL)
00717         u8 on_tx_0          :1;
00718         // Restart scheduler on RX done (main XCL)
00719         u8 on_rx_0          :1;
00720         // Restart scheduler on TX done (1st secondary XCL)
00721         u8 on_tx_1          :1;
00722         // Restart scheduler on RX done (1st secondary XCL)
00723         u8 on_rx_1          :1;
00724         // Restart scheduler on TX done (2nd secondary XCL)
00725         u8 on_tx_2          :1;
00726         // Restart scheduler on RX done (2nd secondary XCL)
00727         u8 on_rx_2          :1;
00728         // Restart scheduler on TX done (3rd secondary XCL)
00729         u8 on_tx_3          :1;
00730         // Restart scheduler on RX done (3rd secondary XCL)
00731         u8 on_rx_3          :1;
00732     } bf;
00733     // byte access
00734     u8 byte;
00735 } d7a_dll_cfg_flags2_t;
00736 #define D7A_DLL_SCAN_XCL_NB     4
00737 //======================================================================
00738 /// DLL active access class scan structure
00739 //======================================================================
00740 TYPEDEF_STRUCT_PACKED
00741 {
00742     /// Active scan access class
00743     d7a_xcl_t xcl;
00744     /// Scan timeout
00745     d7a_ctf_t scan_to;
00746 } d7a_xcl_cfg_t;
00747 // =======================================================================
00748 // d7a_dll_cfg_t
00749 // -----------------------------------------------------------------------
00750 /// DLL Configuration File structure
00751 // =======================================================================
00752 TYPEDEF_STRUCT_PACKED
00753 {
00754     /// Main active scan access class
00755     d7a_xcl_t xcl;
00756     /// Main active access class scan timeout
00757     d7a_ctf_t scan_to;
00758     /// Area identifier.
00759     u8  area;
00760     /// Control (Bis) bitfield
00761     d7a_dll_cfg_flags2_t ctrl2;
00762     /// Noise Floor Computation Method Control Bitfield
00763     d7a_dll_cfg_flags_t ctrl;
00764     /// Noise Floor Method Parameter (depends on Method ID)
00765     u8  nf_param;
00766     /// Secondary active scan access classes
00767     d7a_xcl_cfg_t xtra[D7A_DLL_SCAN_XCL_NB-1];
00768 } d7a_dll_cfg_t;
00769 #define D7A_FS_DLL_CFG_SIZE             sizeof(d7a_dll_cfg_t)
00770 
00771 /// =======================================================================
00772 /// =======================================================================
00773 ///
00774 /// 11. DLL STATUS
00775 ///
00776 /// =======================================================================
00777 /// =======================================================================
00778 
00779 // =======================================================================
00780 // d7a_dll_status_t
00781 // -----------------------------------------------------------------------
00782 /// DLL status File structure
00783 // =======================================================================
00784 TYPEDEF_STRUCT_PACKED
00785 {
00786     /// Last RX level [-dBm]
00787     u8  rxlev_last;
00788     /// Last link budget [dB]
00789     u8  lb_last;
00790     /// Measured noise floor [-dBm]
00791     u8  nf;
00792     /// Last RX channel header
00793     d7a_ch_header_t ch_header;
00794     /// Last RX channel index
00795     u16 ch_idx;
00796     /// scan timeout ratio in 1/1024th
00797     u16 scan_ratio;
00798     /// scan count since boot
00799     u32 scan_cnt;
00800     /// scan timeout count since boot (timeout on detected channel acivity)
00801     u32 scan_to_cnt;
00802 
00803 } d7a_dll_status_t;
00804 #define D7A_FS_DLL_STATUS_SIZE          sizeof(d7a_dll_status_t)
00805 
00806 /// =======================================================================
00807 /// =======================================================================
00808 ///
00809 /// 12. NWL ROUTING
00810 ///
00811 /// =======================================================================
00812 /// =======================================================================
00813 
00814 // =======================================================================
00815 // d7a_nwl_routing_mode_t
00816 // -----------------------------------------------------------------------
00817 /// NWL routing modes
00818 // =======================================================================
00819 typedef enum
00820 {
00821     /// Default routing type
00822     D7A_NWL_ROUTING_MODE_DEFAULT = 0,
00823     /// Qty
00824     D7A_NWL_ROUTING_MODE_QTY
00825 
00826 } d7a_nwl_routing_mode_t;
00827 
00828 // =======================================================================
00829 // d7a_nwl_routing_entry_t
00830 // -----------------------------------------------------------------------
00831 /// NWL Single Routing entry
00832 // =======================================================================
00833 TYPEDEF_STRUCT_PACKED
00834 {
00835     /// Destination node to be reached
00836     d7a_addressee_t dst;
00837     /// Intermediary node to use
00838     d7a_addressee_t itm;
00839 
00840 } d7a_nwl_routing_entry_t;
00841 
00842 // =======================================================================
00843 // d7a_fs_nwl_routing_t
00844 // -----------------------------------------------------------------------
00845 /// NWL Routing File structure
00846 // =======================================================================
00847 #define D7A_FS_NWL_ROUTING_SIZE(n)          (sizeof(u8) + (n) * sizeof(d7a_nwl_routing_entry_t))
00848 #define d7a_nwl_routing_t(n) \
00849 struct __attribute__((packed)) \
00850 { \
00851     u8 routing;\
00852     d7a_nwl_routing_entry_t entry[(n)];\
00853 }
00854 
00855 /// =======================================================================
00856 /// =======================================================================
00857 ///
00858 /// 13. NWL SECURITY
00859 ///
00860 /// =======================================================================
00861 /// =======================================================================
00862 // =======================================================================
00863 // d7a_nwl_nls_status_bmp_t
00864 // -----------------------------------------------------------------------
00865 /// NWL Security status bitmap
00866 // =======================================================================
00867 typedef union
00868 {
00869     // bit access fields
00870     struct {
00871         /// SSR filter enable
00872         u8 ssr_en   : 1;
00873         /// SSR filter overflow
00874         u8 ssr_ovf  : 1;
00875         /// RFU
00876         u8 rfu      : 6;
00877     } bf;
00878 
00879     // byte access
00880     u8 byte;
00881 
00882 } d7a_nls_status_bmp_t;
00883 
00884 // =======================================================================
00885 // d7a_nwl_fs_security_t
00886 // -----------------------------------------------------------------------
00887 /// NWL Securty fil definition
00888 // =======================================================================
00889 TYPEDEF_STRUCT_PACKED
00890 {
00891     /// Security state
00892     d7a_nwl_security_t sec;
00893     /// Keyring ID
00894     u8 ringid[4];
00895     /// NLS status flags
00896     d7a_nls_status_bmp_t bmp;
00897 
00898 } d7a_nwl_fs_security_t;
00899 
00900 #define D7A_FS_NWL_SECURITY_ALLOC_SIZE  sizeof(d7a_nwl_fs_security_t)
00901 #define D7A_FS_NWL_SECURITY_SIZE        (D7A_FS_NWL_SECURITY_ALLOC_SIZE)
00902 
00903 /// =======================================================================
00904 /// =======================================================================
00905 ///
00906 /// 14. NWL SECURITY KEY
00907 ///
00908 /// =======================================================================
00909 /// =======================================================================
00910 
00911 // =======================================================================
00912 // d7a_nwl_key_t
00913 // -----------------------------------------------------------------------
00914 /// NWL AES-128 key File structure
00915 // =======================================================================
00916 TYPEDEF_STRUCT_PACKED
00917 {
00918     /// NWL Security key
00919     u8  val[16];
00920     /// Counter associated to the key (key id)
00921     u8  keyid;
00922     /// Keyring identifier
00923     u8  ringid[4];
00924 
00925 } d7a_nwl_key_t;
00926 #define D7A_FS_NWL_KEY_SIZE             sizeof(d7a_nwl_key_t)
00927 
00928 /// =======================================================================
00929 /// =======================================================================
00930 ///
00931 /// 14. NWL SECURITY STATE REGISTER
00932 ///
00933 /// =======================================================================
00934 /// =======================================================================
00935 
00936 // =======================================================================
00937 // d7a_nwl_ssr_filter_t
00938 // -----------------------------------------------------------------------
00939 /// NWL SSR filter
00940 // =======================================================================
00941 typedef union
00942 {
00943     // bit access fields
00944     struct {
00945         /// SSR filter enable
00946         u8 en       : 1;
00947         /// Consider only initial requests
00948         u8 req_only : 1;
00949         /// RFU
00950         u8 rfu      : 6;
00951     } bf;
00952 
00953     // byte access
00954     u8 byte;
00955 
00956 } d7a_nwl_ssr_filter_t;
00957 
00958 // =======================================================================
00959 // d7a_nwl_cfg_t
00960 // -----------------------------------------------------------------------
00961 /// NWL Security Configuration structure
00962 // =======================================================================
00963 TYPEDEF_STRUCT_PACKED
00964 {
00965     // NLS filter
00966     u16 nls_filter;
00967     // SSR filter
00968     d7a_nwl_ssr_filter_t ssr_filter;
00969     // Number of SSR entries
00970     u8 ssr_len;
00971 
00972 } d7a_nwl_cfg_t;
00973 
00974 // =======================================================================
00975 // d7a_nwl_ssr_entry_t
00976 // -----------------------------------------------------------------------
00977 /// NWL Single SSR entry
00978 // =======================================================================
00979 TYPEDEF_STRUCT_PACKED
00980 {
00981     /// Security state
00982     d7a_nwl_security_t sec;
00983     /// distant UID
00984     u8 uid[D7A_UID_LEN];
00985 
00986 } d7a_nwl_ssr_entry_t;
00987 
00988 // =======================================================================
00989 // d7a_nwl_ssr_t
00990 // -----------------------------------------------------------------------
00991 /// NWL Security State Register File structure
00992 // =======================================================================
00993 #define D7A_FS_NWL_SSR_SIZE(n)              (sizeof(d7a_nwl_cfg_t) + (n) * sizeof(d7a_nwl_ssr_entry_t))
00994 #define d7a_nwl_ssr_t(n) \
00995 struct __attribute__((packed)) \
00996 { \
00997     d7a_nwl_cfg_t cfg;\
00998     d7a_nwl_ssr_entry_t entry[(n)];\
00999 }
01000 
01001 /// =======================================================================
01002 /// =======================================================================
01003 ///
01004 /// 16. NWL STATUS
01005 ///
01006 /// =======================================================================
01007 /// =======================================================================
01008 
01009 
01010 // =======================================================================
01011 // d7a_nwl_status_t
01012 // -----------------------------------------------------------------------
01013 /// NWL status File structure
01014 // =======================================================================
01015 TYPEDEF_STRUCT_PACKED
01016 {
01017     /// Number of received valid BG frames
01018     u32 rx_bg_cnt;
01019     /// Number of received valid FG frames (D7AAdvP)
01020     u32 rx_fg_adv_cnt;
01021     /// Number of received valid FG frames (D7ANP)
01022     u32 rx_fg_cnt;
01023     /// Number of transmitted frames
01024     u32 tx_cnt;
01025     /// Number of tx failures
01026     u32 tx_fails;
01027 
01028 } d7a_nwl_status_t;
01029 
01030 #define D7A_FS_NWL_STATUS_SIZE          sizeof(d7a_nwl_status_t)
01031 
01032 /// =======================================================================
01033 /// =======================================================================
01034 ///
01035 /// 17. TRL STATUS
01036 ///
01037 /// =======================================================================
01038 /// =======================================================================
01039 
01040 // =======================================================================
01041 // d7a_tp_ack_status_zip_t
01042 // -----------------------------------------------------------------------
01043 /// Structure of the D7ATP ACK Template (compressed ACK record)
01044 // =======================================================================
01045 typedef struct
01046 {
01047     /// Length of the bitmap
01048     u8  len;
01049     /// First non-received ID, before which all IDs are receive.
01050     u8  start_id;
01051     /// Last received ID
01052     u8  end_id;
01053     /// Reception status bitmap
01054     u8  bitmap[32];
01055 
01056 } d7a_tp_ack_status_zip_t;
01057 
01058 // =======================================================================
01059 // d7a_trl_status_t
01060 // -----------------------------------------------------------------------
01061 /// Transport Layer Status File structure
01062 // =======================================================================
01063 TYPEDEF_STRUCT_PACKED
01064 {
01065     /// Real length of the whole record.
01066     u8 len;
01067     // Token of the recorded zip
01068     u8 token;
01069     /// At least room for one full zip
01070     d7a_tp_ack_status_zip_t zip;
01071 
01072 } d7a_trl_status_t;
01073 #define D7A_FS_TRL_STATUS_SIZE       sizeof(d7a_trl_status_t)
01074 
01075 /// =======================================================================
01076 /// =======================================================================
01077 ///
01078 /// 18. SEL CONFIGURATION
01079 ///
01080 /// =======================================================================
01081 /// =======================================================================
01082 
01083 // =======================================================================
01084 // d7a_agc_ctrl_t
01085 // -----------------------------------------------------------------------
01086 /// AGC control structure
01087 // =======================================================================
01088 typedef union
01089 {
01090     // bit access fields
01091     struct {
01092         /// AGC on
01093         /// When the field is not set, all Requesters and all Responders
01094         /// set their transmission power to the maximum authorized level.
01095         /// When the field is set, all Requesters, upon failure to receive
01096         /// an acknowledgement, reset their transmission power as defined
01097         /// by the TOGGLE field. Unicast transmissions (unicast requests
01098         /// and all responses) adjust the transmission power so that the
01099         /// expected reception RXLEV at the receiving party equals the
01100         /// last valid target RXLEV provided by that party, or when not
01101         /// provided, -80 dBm.
01102         u8 on       : 1;
01103         /// Enable target RXLEV reporting
01104         /// When set, the target RXLEV is provided by the transmitting
01105         /// party in the DLL header. The target RXLEV is computed based
01106         /// on local noise floor, channel class and device sensitivity
01107         u8 rxlev    : 1;
01108         /// Toggle between min and max
01109         /// On a first failure or when the field is not set, the transmission
01110         /// power is set to the maximum authorized level. When the field is
01111         /// set, on a subsequent failure, the transmission power is toggled
01112         /// between the minimum possible level and the maximum authorized
01113         /// levels.
01114         u8 toggle   : 1;
01115         // RFU
01116         u8 rfu      : 5;
01117     } bf;
01118 
01119     // byte access
01120     u8 byte;
01121 
01122 } d7a_agc_ctrl_t;
01123 
01124 // =======================================================================
01125 // d7a_sel_filter_t
01126 // -----------------------------------------------------------------------
01127 /// SEL segment filter options structure
01128 // =======================================================================
01129 typedef union
01130 {
01131     // bit access fields
01132     struct {
01133         /// Filter segments marked with retry if no response is expected
01134         u8 retry        : 1;
01135         /// Do not count TX CSMA-CA errors as ACK failures
01136         u8 csma_err     : 1;
01137         /// Do not count TX duty errors as ACK failures
01138         u8 duty_err     : 1;
01139         // RFU
01140         u8 rfu          : 5;
01141     } bf;
01142 
01143     // byte access
01144     u8 byte;
01145 
01146 } d7a_sel_filter_t;
01147 
01148 // =======================================================================
01149 // d7a_sel_cfg_t
01150 // -----------------------------------------------------------------------
01151 /// SEL configuration file structure
01152 // =======================================================================
01153 TYPEDEF_STRUCT_PACKED
01154 {
01155     /// AGC mode
01156     d7a_agc_ctrl_t agc_ctrl;
01157     /// AGC parameter
01158     u8  agc_param;
01159     /// retry (valid in all RESP modes)
01160     u8  retry;
01161     /// repeat (valid in RESP_NO_RPT)
01162     u8  repeat;
01163     /// maximum acknowledgement window
01164     u8  ack_win;
01165     /// segment filter options
01166     d7a_sel_filter_t filter;
01167     /// request timeout in seconds for non-persistent FIFOs (conpressed format)
01168     d7a_ctf_t to;
01169 
01170 } d7a_sel_cfg_t;
01171 #define D7A_FS_SEL_CFG_SIZE  sizeof(d7a_sel_cfg_t)
01172 
01173 /// =======================================================================
01174 /// =======================================================================
01175 ///
01176 /// 19. SEL STATUS
01177 ///
01178 /// =======================================================================
01179 /// =======================================================================
01180 
01181 // =======================================================================
01182 // d7a_sel_status_t
01183 // -----------------------------------------------------------------------
01184 /// Structure of the SEL Protocol status
01185 // =======================================================================
01186 TYPEDEF_STRUCT_PACKED
01187 {
01188     /// UID of the device issuing the FCP
01189     u8  uid[D7A_UID_LEN];
01190     /// Frequency offset in Hz
01191     s16 fof;
01192 
01193 } d7a_sel_status_t;
01194 #define D7A_FS_SEL_STATUS_SIZE      sizeof(d7a_sel_status_t)
01195 
01196 /// =======================================================================
01197 /// =======================================================================
01198 ///
01199 /// 26. CHALLENGE
01200 ///
01201 /// =======================================================================
01202 /// =======================================================================
01203 #define D7A_CHALLENGE_SIZE      32
01204 #define D7A_FS_CHALLENGE_SIZE   sizeof(d7a_chal_t)
01205 TYPEDEF_STRUCT_PACKED
01206 {
01207     /// Challenge validity in Minutes
01208     u8  validity;
01209     /// Challenge
01210     u8  chal[D7A_CHALLENGE_SIZE];
01211 
01212 } d7a_chal_t;
01213 
01214 /// =======================================================================
01215 /// =======================================================================
01216 ///
01217 /// 29. TIME STAMP
01218 ///
01219 /// =======================================================================
01220 /// =======================================================================
01221 
01222 // =======================================================================
01223 // d7a_time_stamp_t
01224 // -----------------------------------------------------------------------
01225 /// Structure of the Time stamp status
01226 // =======================================================================
01227 TYPEDEF_STRUCT_PACKED
01228 {
01229     /// Ping stamp (aka roundtrip time) in x100 picosec
01230     /// This is a RX timestamp relative to the last TX timestamp
01231     u32 rx;
01232     /// Pong stamp (aka reply time) in x100 picosec
01233     /// This is a TX timestamp relative to the last RX timestamp
01234     u32 tx;
01235 
01236 } d7a_time_stamp_t;
01237 #define D7A_FS_TIME_STAMP_SIZE      sizeof(d7a_time_stamp_t)
01238 
01239 /// =======================================================================
01240 /// =======================================================================
01241 ///
01242 /// 32-47. ACCESS PROFILES
01243 ///
01244 /// =======================================================================
01245 /// =======================================================================
01246 
01247 // =======================================================================
01248 // d7a_subprofile_t
01249 // -----------------------------------------------------------------------
01250 /// Sub-profile structure
01251 // =======================================================================
01252 TYPEDEF_STRUCT_PACKED
01253 {
01254     /// Subband select bitmap
01255     u8 bmp;
01256     /// Scheduler period
01257     d7a_ctf_t tsched;
01258 
01259 } d7a_subprofile_t;
01260 
01261 // =======================================================================
01262 // d7a_cca_cfg_t
01263 // -----------------------------------------------------------------------
01264 /// Clear Channel Assessment Configuration structure
01265 // =======================================================================
01266 typedef union
01267 {
01268     // bit access fields
01269     struct {
01270         /// Default CCA Threshold (-dBm)
01271         u8 val : 7;
01272         /// CCA not required flag
01273         u8 opt : 1;
01274     } bf;
01275 
01276     // byte access
01277     u8 byte;
01278 
01279 } d7a_cca_cfg_t;
01280 
01281 // =======================================================================
01282 // d7a_subband_t
01283 // -----------------------------------------------------------------------
01284 /// Subband structure
01285 // =======================================================================
01286 TYPEDEF_STRUCT_PACKED
01287 {
01288     /// Start channel index
01289     u16 start_idx;
01290     /// End channel index
01291     u16 end_idx;
01292     /// Transmission EIRP (dBm)
01293     s8  eirp;
01294     /// Clear channel assessment configuration (-dBm)
01295     d7a_cca_cfg_t cca;
01296     /// Maximum per-channel transmission duty cycle in per-mil in CTF
01297     d7a_ctf_t duty;
01298 
01299 } d7a_subband_t;
01300 
01301 // =======================================================================
01302 // d7a_access_profile_t
01303 // -----------------------------------------------------------------------
01304 /// DLL Access Profile structure
01305 // =======================================================================
01306 TYPEDEF_STRUCT_PACKED
01307 {
01308     /// Channel header
01309     d7a_ch_header_t header;
01310     /// Access control
01311     d7a_subprofile_t sp[4];
01312     /// Subbands
01313     d7a_subband_t sb[8];
01314 
01315 } d7a_access_profile_t;
01316 #define D7A_FS_AP_SIZE                  sizeof(d7a_access_profile_t)
01317 
01318 #endif // __D7A_1X_FS_H__