w5500.h

00001 //*****************************************************************************
00002 //
00003 //! \file w5500.h
00004 //! \brief W5500 HAL Header File.
00005 //! \version 1.0.0
00006 //! \date 2013/10/01
00007 //! \par  Revision history
00008 //!       <2013/10/01> 1st Release
00009 //! \author MidnightCow
00010 //! \copyright
00011 //!
00012 //! Copyright (c)  2013, WIZnet Co., LTD.
00013 //! All rights reserved.
00014 //! 
00015 //! Redistribution and use in source and binary forms, with or without 
00016 //! modification, are permitted provided that the following conditions 
00017 //! are met: 
00018 //! 
00019 //!     * Redistributions of source code must retain the above copyright 
00020 //! notice, this list of conditions and the following disclaimer. 
00021 //!     * Redistributions in binary form must reproduce the above copyright
00022 //! notice, this list of conditions and the following disclaimer in the
00023 //! documentation and/or other materials provided with the distribution. 
00024 //!     * Neither the name of the <ORGANIZATION> nor the names of its 
00025 //! contributors may be used to endorse or promote products derived 
00026 //! from this software without specific prior written permission. 
00027 //! 
00028 //! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029 //! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
00030 //! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00031 //! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
00032 //! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
00033 //! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
00034 //! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00035 //! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
00036 //! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00037 //! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 
00038 //! THE POSSIBILITY OF SUCH DAMAGE.
00039 //
00040 //*****************************************************************************
00041 
00042 #ifndef  _W5500_H_
00043 #define  _W5500_H_
00044 
00045 #include <stdint.h>
00046 #include "Ethernet/wizchip_conf.h"
00047 
00048 #define _W5500_IO_BASE_              0x00000000
00049 
00050 #define _W5500_SPI_READ_               (0x00 << 2) //< SPI interface Read operation in Control Phase
00051 #define _W5500_SPI_WRITE_              (0x01 << 2) //< SPI interface Write operation in Control Phase
00052 
00053 #define WIZCHIP_CREG_BLOCK          0x00    //< Common register block
00054 #define WIZCHIP_SREG_BLOCK(N)       (1+4*N) //< Socket N register block
00055 #define WIZCHIP_TXBUF_BLOCK(N)      (2+4*N) //< Socket N Tx buffer address block
00056 #define WIZCHIP_RXBUF_BLOCK(N)      (3+4*N) //< Socket N Rx buffer address block
00057 
00058 #define WIZCHIP_OFFSET_INC(ADDR, N)    (ADDR + (N<<8)) //< Increase offset address
00059 
00060 
00061 
00062 //////////////////////////////
00063 //--------------------------  defgroup ---------------------------------
00064 /**
00065  * @defgroup W5500 W5500
00066  *
00067  * @brief WHIZCHIP register defines and I/O functions of @b W5500.
00068  *
00069  * - @ref WIZCHIP_register : @ref Common_register_group and @ref Socket_register_group
00070  * - @ref WIZCHIP_IO_Functions : @ref Basic_IO_function, @ref Common_register_access_function and @ref Socket_register_access_function
00071  */
00072  
00073  
00074 /**
00075  * @defgroup WIZCHIP_register WIZCHIP register
00076  * @ingroup W5500
00077  *
00078  * @brief WHIZCHIP register defines register group of @b W5500.
00079  *
00080  * - @ref Common_register_group : Common register group
00081  * - @ref Socket_register_group : \c SOCKET n register group
00082  */
00083 
00084 
00085 /**
00086  * @defgroup WIZCHIP_IO_Functions WIZCHIP I/O functions
00087  * @ingroup W5500
00088  *
00089  * @brief This supports the basic I/O functions for @ref WIZCHIP_register.
00090  *
00091  * - <b> Basic I/O function </b> \n
00092  *   WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() \n\n
00093  *
00094  * - @ref Common_register_group <b>access functions</b> \n
00095  *  -# @b Mode \n
00096  *    getMR(), setMR()
00097  *  -# @b Interrupt \n
00098  *    getIR(), setIR(), getIMR(), setIMR(), getSIR(), setSIR(), getSIMR(), setSIMR(), getINTLEVEL(), setINTLEVEL()
00099  *  -# <b> Network Information </b> \n
00100  *    getSHAR(), setSHAR(), getGAR(), setGAR(), getSUBR(), setSUBR(), getSIPR(), setSIPR()
00101  *  -# @b Retransmission \n
00102  *    getRCR(), setRCR(), getRTR(), setRTR()
00103  *  -# @b PPPoE \n
00104  *    getPTIMER(), setPTIMER(), getPMAGIC(), getPMAGIC(), getPSID(), setPSID(), getPHAR(), setPHAR(), getPMRU(), setPMRU()
00105  *  -# <b> ICMP packet </b>\n
00106  *    getUIPR(), getUPORTR()
00107  *  -# @b etc. \n
00108  *    getPHYCFGR(), setPHYCFGR(), getVERSIONR() \n\n
00109  *
00110  * - \ref Socket_register_group <b>access functions</b> \n
00111  *   -# <b> SOCKET control</b> \n
00112  *      getSn_MR(), setSn_MR(), getSn_CR(), setSn_CR(), getSn_IMR(), setSn_IMR(), getSn_IR(), setSn_IR()
00113  *   -# <b> SOCKET information</b> \n
00114  *      getSn_SR(), getSn_DHAR(), setSn_DHAR(), getSn_PORT(), setSn_PORT(), getSn_DIPR(), setSn_DIPR(), getSn_DPORT(), setSn_DPORT()
00115  *      getSn_MSSR(), setSn_MSSR()
00116  *   -# <b> SOCKET communication </b> \n
00117  *      getSn_RXBUF_SIZE(), setSn_RXBUF_SIZE(), getSn_TXBUF_SIZE(), setSn_TXBUF_SIZE() \n
00118  *      getSn_TX_RD(), getSn_TX_WR(), setSn_TX_WR() \n
00119  *      getSn_RX_RD(), setSn_RX_RD(), getSn_RX_WR() \n
00120  *      getSn_TX_FSR(), getSn_RX_RSR(), getSn_KPALVTR(), setSn_KPALVTR()
00121  *   -# <b> IP header field </b> \n
00122  *      getSn_FRAG(), setSn_FRAG(),  getSn_TOS(), setSn_TOS() \n
00123  *      getSn_TTL(), setSn_TTL()
00124  */
00125 
00126 
00127 
00128 /**
00129  * @defgroup Common_register_group Common register
00130  * @ingroup WIZCHIP_register
00131  *
00132  * @brief Common register group\n
00133  * It set the basic for the networking\n
00134  * It set the configuration such as interrupt, network information, ICMP, etc.
00135  * @details
00136  * @sa MR : Mode register.
00137  * @sa GAR, SUBR, SHAR, SIPR
00138  * @sa INTLEVEL, IR, IMR, SIR, SIMR : Interrupt.
00139  * @sa RTR, RCR : Data retransmission.
00140  * @sa PTIMER, PMAGIC, PHAR, PSID, PMRU : PPPoE.
00141  * @sa UIPR, UPORTR : ICMP message.
00142  * @sa PHYCFGR, VERSIONR : etc.
00143  */
00144  
00145   
00146  
00147 /**
00148  * @defgroup Socket_register_group Socket register
00149  * @ingroup WIZCHIP_register
00150  *
00151  * @brief Socket register group.\n
00152  * Socket register configures and control SOCKETn which is necessary to data communication.
00153  * @details
00154  * @sa Sn_MR, Sn_CR, Sn_IR, Sn_IMR : SOCKETn Control
00155  * @sa Sn_SR, Sn_PORT, Sn_DHAR, Sn_DIPR, Sn_DPORT : SOCKETn Information
00156  * @sa Sn_MSSR, Sn_TOS, Sn_TTL, Sn_KPALVTR, Sn_FRAG : Internet protocol.
00157  * @sa Sn_RXBUF_SIZE, Sn_TXBUF_SIZE, Sn_TX_FSR, Sn_TX_RD, Sn_TX_WR, Sn_RX_RSR, Sn_RX_RD, Sn_RX_WR : Data communication
00158  */
00159  
00160  
00161  
00162  /**
00163  * @defgroup Basic_IO_function Basic I/O function
00164  * @ingroup WIZCHIP_IO_Functions
00165  * @brief These are basic input/output functions to read values from register or write values to register.
00166  */
00167 
00168 /**
00169  * @defgroup Common_register_access_function Common register access functions
00170  * @ingroup WIZCHIP_IO_Functions
00171  * @brief These are functions to access <b>common registers</b>.
00172  */
00173 
00174 /**
00175  * @defgroup Socket_register_access_function Socket register access functions
00176  * @ingroup WIZCHIP_IO_Functions
00177  * @brief These are functions to access <b>socket registers</b>.
00178  */
00179  
00180 //------------------------------- defgroup end --------------------------------------------
00181 //----------------------------- W5500 Common Registers IOMAP -----------------------------
00182 /**
00183  * @ingroup Common_register_group
00184  * @brief Mode Register address(R/W)\n
00185  * @ref MR is used for S/W reset, ping block mode, PPPoE mode and etc.
00186  * @details Each bit of @ref MR defined as follows.
00187  * <table>
00188  *      <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
00189  *      <tr>  <td>RST</td> <td>Reserved</td> <td>WOL</td> <td>PB</td> <td>PPPoE</td> <td>Reserved</td> <td>FARP</td> <td>Reserved</td> </tr>
00190  * </table>
00191  * - \ref MR_RST            : Reset
00192  * - \ref MR_WOL            : Wake on LAN
00193  * - \ref MR_PB             : Ping block
00194  * - \ref MR_PPPOE          : PPPoE mode
00195  * - \ref MR_FARP           : Force ARP mode
00196  */
00197 #define MR                 (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00198 
00199 /**
00200  * @ingroup Common_register_group
00201  * @brief Gateway IP Register address(R/W)
00202  * @details @ref GAR configures the default gateway address.
00203  */
00204 #define GAR                (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00205 
00206 /**
00207  * @ingroup Common_register_group
00208  * @brief Subnet mask Register address(R/W)
00209  * @details @ref SUBR configures the subnet mask address.
00210  */
00211 #define SUBR               (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00212 
00213 /**
00214  * @ingroup Common_register_group
00215  * @brief Source MAC Register address(R/W)
00216  * @details @ref SHAR configures the source hardware address.
00217  */
00218 #define SHAR               (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00219 
00220 /**
00221  * @ingroup Common_register_group
00222  * @brief Source IP Register address(R/W)
00223  * @details @ref SIPR configures the source IP address.
00224  */
00225 #define SIPR               (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
00226 
00227 /**
00228  * @ingroup Common_register_group
00229  * @brief Set Interrupt low level timer register address(R/W)
00230  * @details @ref INTLEVEL configures the Interrupt Assert Time.
00231  */
00232 #define INTLEVEL           (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00233 
00234 /**
00235  * @ingroup Common_register_group
00236  * @brief Interrupt Register(R/W)
00237  * @details @ref IR indicates the interrupt status. Each bit of @ref IR will be still until the bit will be written to by the host.
00238  * If @ref IR is not equal to x00 INTn PIN is asserted to low until it is x00\n\n
00239  * Each bit of @ref IR defined as follows.
00240  * <table>
00241  *      <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
00242  *      <tr>  <td>CONFLICT</td> <td>UNREACH</td> <td>PPPoE</td> <td>MP</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr>
00243  * </table>
00244  * - \ref IR_CONFLICT : IP conflict
00245  * - \ref IR_UNREACH  : Destination unreachable
00246  * - \ref IR_PPPoE    : PPPoE connection close
00247  * - \ref IR_MP       : Magic packet
00248  */
00249 #define IR                 (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00250 
00251 /**
00252  * @ingroup Common_register_group
00253  * @brief Interrupt mask register(R/W)
00254  * @details @ref IMR is used to mask interrupts. Each bit of @ref IMR corresponds to each bit of @ref IR.
00255  * When a bit of @ref IMR is and the corresponding bit of @ref IR is  an interrupt will be issued. In other words,
00256  * if a bit of @ref IMR is  an interrupt will not be issued even if the corresponding bit of @ref IR is \n\n
00257  * Each bit of @ref IMR defined as the following.
00258  * <table>
00259  *      <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
00260  *      <tr>  <td>IM_IR7</td> <td>IM_IR6</td> <td>IM_IR5</td> <td>IM_IR4</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr>
00261  * </table>
00262  * - \ref IM_IR7 : IP Conflict Interrupt Mask
00263  * - \ref IM_IR6 : Destination unreachable Interrupt Mask
00264  * - \ref IM_IR5 : PPPoE Close Interrupt Mask
00265  * - \ref IM_IR4 : Magic Packet Interrupt Mask
00266  */
00267 #define IMR                (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00268 
00269 /**
00270  * @ingroup Common_register_group
00271  * @brief Socket Interrupt Register(R/W)
00272  * @details @ref SIR indicates the interrupt status of Socket.\n
00273  * Each bit of @ref SIR be still until @ref Sn_IR is cleared by the host.\n
00274  * If @ref Sn_IR is not equal to x00 the n-th bit of @ref SIR is and INTn PIN is asserted until @ref SIR is x00 */
00275 #define SIR                (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00276 
00277 /**
00278  * @ingroup Common_register_group
00279  * @brief Socket Interrupt Mask Register(R/W)
00280  * @details Each bit of @ref SIMR corresponds to each bit of @ref SIR.
00281  * When a bit of @ref SIMR is and the corresponding bit of @ref SIR is  Interrupt will be issued.
00282  * In other words, if a bit of @ref SIMR is  an interrupt will be not issued even if the corresponding bit of @ref SIR is 
00283  */
00284 #define SIMR               (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00285 
00286 /**
00287  * @ingroup Common_register_group
00288  * @brief Timeout register address( 1 is 100us )(R/W)
00289  * @details @ref RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of @ref RTR is x07D0or 000
00290  * And so the default timeout period is 200ms(100us X 2000). During the time configured by @ref RTR, W5500 waits for the peer response
00291  * to the packet that is transmitted by \ref Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command).
00292  * If the peer does not respond within the @ref RTR time, W5500 retransmits the packet or issues timeout.
00293  */
00294 #define RTR                (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00295 
00296 /**
00297  * @ingroup Common_register_group
00298  * @brief Retry count register(R/W)
00299  * @details @ref RCR configures the number of time of retransmission.
00300  * When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (@ref Sn_IR[TIMEOUT] = .
00301  */
00302 #define RCR                (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
00303 
00304 /**
00305  * @ingroup Common_register_group
00306  * @brief PPP LCP Request Timer register  in PPPoE mode(R/W)
00307  * @details @ref PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.
00308  */
00309 #define PTIMER             (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
00310 
00311 /**
00312  * @ingroup Common_register_group
00313  * @brief PPP LCP Magic number register  in PPPoE mode(R/W)
00314  * @details @ref PMAGIC configures the 4bytes magic number to be used in LCP negotiation.
00315  */
00316 #define PMAGIC             (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
00317 
00318 /**
00319  * @ingroup Common_register_group
00320  * @brief PPP Destination MAC Register address(R/W)
00321  * @details @ref PHAR configures the PPPoE server hardware address that is acquired during PPPoE connection process.
00322  */
00323 #define PHAR                (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
00324 
00325 /**
00326  * @ingroup Common_register_group
00327  * @brief PPP Session Identification Register(R/W)
00328  * @details @ref PSID configures the PPPoE sever session ID acquired during PPPoE connection process.
00329  */
00330 #define PSID               (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00331 
00332 /**
00333  * @ingroup Common_register_group
00334  * @brief PPP Maximum Segment Size(MSS) register(R/W)
00335  * @details @ref PMRU configures the maximum receive unit of PPPoE.
00336  */
00337 #define PMRU               (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00338 
00339 /**
00340  * @ingroup Common_register_group
00341  * @brief Unreachable IP register address in UDP mode(R)
00342  * @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number
00343  * which socket is not open and @ref UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR indicates
00344  * the destination IP address & port number respectively.
00345  */
00346 #define UIPR               (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00347 
00348 /**
00349  * @ingroup Common_register_group
00350  * @brief Unreachable Port register address in UDP mode(R)
00351  * @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number
00352  * which socket is not open and @ref UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR
00353  * indicates the destination IP address & port number respectively.
00354  */
00355 #define UPORTR              (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
00356 
00357 /**
00358  * @ingroup Common_register_group
00359  * @brief PHY Status Register(R/W)
00360  * @details @ref PHYCFGR configures PHY operation mode and resets PHY. In addition, @ref PHYCFGR indicates the status of PHY such as duplex, Speed, Link.
00361  */
00362 #define PHYCFGR            (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
00363 
00364 // Reserved                  (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_CREG_BLOCK << 3))
00365 // Reserved                  (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00366 // Reserved                  (_W5500_IO_BASE_ + (0x0031 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00367 // Reserved                  (_W5500_IO_BASE_ + (0x0032 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00368 // Reserved                  (_W5500_IO_BASE_ + (0x0033 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00369 // Reserved                  (_W5500_IO_BASE_ + (0x0034 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00370 // Reserved                  (_W5500_IO_BASE_ + (0x0035 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00371 // Reserved                  (_W5500_IO_BASE_ + (0x0036 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00372 // Reserved                  (_W5500_IO_BASE_ + (0x0037 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00373 // Reserved                  (_W5500_IO_BASE_ + (0x0038 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00374 
00375 /**
00376  * @ingroup Common_register_group
00377  * @brief chip version register address(R)
00378  * @details @ref VERSIONR always indicates the W5500 version as @b 0x04.
00379  */
00380 #define VERSIONR           (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
00381 
00382 
00383 //----------------------------- W5500 Socket Registers IOMAP -----------------------------
00384 /**
00385  * @ingroup Socket_register_group
00386  * @brief socket Mode register(R/W)
00387  * @details @ref Sn_MR configures the option or protocol type of Socket n.\n\n
00388  * Each bit of @ref Sn_MR defined as the following.
00389  * <table>
00390  *      <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
00391  *      <tr>  <td>MULTI/MFEN</td> <td>BCASTB</td> <td>ND/MC/MMB</td> <td>UCASTB/MIP6B</td> <td>Protocol[3]</td> <td>Protocol[2]</td> <td>Protocol[1]</td> <td>Protocol[0]</td> </tr>
00392  * </table>
00393  * - @ref Sn_MR_MULTI   : Support UDP Multicasting
00394  * - @ref Sn_MR_BCASTB  : Broadcast block <b>in UDP Multicasting</b>
00395  * - @ref Sn_MR_ND      : No Delayed Ack(TCP) flag
00396  * - @ref Sn_MR_MC      : IGMP version used <b>in UDP mulitcasting</b>
00397  * - @ref Sn_MR_MMB     : Multicast Blocking <b>in @ref Sn_MR_MACRAW mode</b>
00398  * - @ref Sn_MR_UCASTB  : Unicast Block <b>in UDP Multicating</b>
00399  * - @ref Sn_MR_MIP6B   : IPv6 packet Blocking <b>in @ref Sn_MR_MACRAW mode</b>
00400  * - <b>Protocol</b>
00401  * <table>
00402  *      <tr>   <td><b>Protocol[3]</b></td> <td><b>Protocol[2]</b></td> <td><b>Protocol[1]</b></td> <td><b>Protocol[0]</b></td> <td>@b Meaning</td>   </tr>
00403  *      <tr>   <td>0</td> <td>0</td> <td>0</td> <td>0</td> <td>Closed</td>   </tr>
00404  *      <tr>   <td>0</td> <td>0</td> <td>0</td> <td>1</td> <td>TCP</td>   </tr>
00405  *      <tr>   <td>0</td> <td>0</td> <td>1</td> <td>0</td> <td>UDP</td>   </tr>
00406  *      <tr>   <td>0</td> <td>1</td> <td>0</td> <td>0</td> <td>MACRAW</td>   </tr>
00407  * </table>
00408  *  - @ref Sn_MR_MACRAW : MAC LAYER RAW SOCK \n
00409  *  - @ref Sn_MR_UDP        : UDP
00410  *  - @ref Sn_MR_TCP        : TCP
00411  *  - @ref Sn_MR_CLOSE  : Unused socket
00412  *  @note MACRAW mode should be only used in Socket 0.
00413  */
00414 #define Sn_MR(N)           (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00415 
00416 /**
00417  * @ingroup Socket_register_group
00418  * @brief Socket command register(R/W)
00419  * @details This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE.\n
00420  * After W5500 accepts the command, the @ref Sn_CR register is automatically cleared to 0x00.
00421  * Even though @ref Sn_CR is cleared to 0x00, the command is still being processed.\n
00422  * To check whether the command is completed or not, please check the @ref Sn_IR or @ref Sn_SR.
00423  * - @ref Sn_CR_OPEN        : Initialize or open socket.
00424  * - @ref Sn_CR_LISTEN      : Wait connection request in TCP mode(<b>Server mode</b>)
00425  * - @ref Sn_CR_CONNECT     : Send connection request in TCP mode(<b>Client mode</b>)
00426  * - @ref Sn_CR_DISCON      : Send closing request in TCP mode.
00427  * - @ref Sn_CR_CLOSE       : Close socket.
00428  * - @ref Sn_CR_SEND        : Update TX buffer pointer and send data.
00429  * - @ref Sn_CR_SEND_MAC    : Send data with MAC address, so without ARP process.
00430  * - @ref Sn_CR_SEND_KEEP   : Send keep alive message.
00431  * - @ref Sn_CR_RECV        : Update RX buffer pointer and receive data.
00432  */
00433 #define Sn_CR(N)           (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00434 
00435 /**
00436  * @ingroup Socket_register_group
00437  * @brief Socket interrupt register(R)
00438  * @details @ref Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving data, timeout).\n
00439  * When an interrupt occurs and the corresponding bit of @ref Sn_IMR is  the corresponding bit of @ref Sn_IR becomes \n
00440  * In order to clear the @ref Sn_IR bit, the host should write the bit to \n
00441  * <table>
00442  *      <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
00443  *      <tr>  <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>SEND_OK</td> <td>TIMEOUT</td> <td>RECV</td> <td>DISCON</td> <td>CON</td> </tr>
00444  * </table>
00445  * - \ref Sn_IR_SENDOK : <b>SEND_OK Interrupt</b>
00446  * - \ref Sn_IR_TIMEOUT : <b>TIMEOUT Interrupt</b>
00447  * - \ref Sn_IR_RECV : <b>RECV Interrupt</b>
00448  * - \ref Sn_IR_DISCON : <b>DISCON Interrupt</b>
00449  * - \ref Sn_IR_CON : <b>CON Interrupt</b>
00450  */
00451 #define Sn_IR(N)           (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00452 
00453 /**
00454  * @ingroup Socket_register_group
00455  * @brief Socket status register(R)
00456  * @details @ref Sn_SR indicates the status of Socket n.\n
00457  * The status of Socket n is changed by @ref Sn_CR or some special control packet as SYN, FIN packet in TCP.
00458  * @par Normal status
00459  * - @ref SOCK_CLOSED       : Closed
00460  * - @ref SOCK_INIT         : Initiate state
00461  * - @ref SOCK_LISTEN       : Listen state
00462  * - @ref SOCK_ESTABLISHED  : Success to connect
00463  * - @ref SOCK_CLOSE_WAIT   : Closing state
00464  * - @ref SOCK_UDP          : UDP socket
00465  * - @ref SOCK_MACRAW       : MAC raw mode socket
00466  *@par Temporary status during changing the status of Socket n.
00467  * - @ref SOCK_SYNSENT      : This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
00468  * - @ref SOCK_SYNRECV      : It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
00469  * - @ref SOCK_FIN_WAIT     : Connection state
00470  * - @ref SOCK_CLOSING      : Closing state
00471  * - @ref SOCK_TIME_WAIT    : Closing state
00472  * - @ref SOCK_LAST_ACK     : Closing state
00473  */
00474 #define Sn_SR(N)           (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00475 
00476 /**
00477  * @ingroup Socket_register_group
00478  * @brief source port register(R/W)
00479  * @details @ref Sn_PORT configures the source port number of Socket n.
00480  * It is valid when Socket n is used in TCP/UPD mode. It should be set before OPEN command is ordered.
00481  */
00482 #define Sn_PORT(N)         (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00483 
00484 /**
00485  * @ingroup Socket_register_group
00486  * @brief Peer MAC register address(R/W)
00487  * @details @ref Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or
00488  * it indicates that it is acquired in ARP-process by CONNECT/SEND command.
00489  */
00490 #define Sn_DHAR(N)         (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00491 
00492 /**
00493  * @ingroup Socket_register_group
00494  * @brief Peer IP register address(R/W)
00495  * @details @ref Sn_DIPR configures or indicates the destination IP address of Socket n. It is valid when Socket n is used in TCP/UDP mode.
00496  * In TCP client mode, it configures an IP address of �TCP serverbefore CONNECT command.
00497  * In TCP server mode, it indicates an IP address of �TCP clientafter successfully establishing connection.
00498  * In UDP mode, it configures an IP address of peer to be received the UDP packet by SEND or SEND_MAC command.
00499  */
00500 #define Sn_DIPR(N)         (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00501 
00502 /**
00503  * @ingroup Socket_register_group
00504  * @brief Peer port register address(R/W)
00505  * @details @ref Sn_DPORT configures or indicates the destination port number of Socket n. It is valid when Socket n is used in TCP/UDP mode.
00506  * In �TCP clientmode, it configures the listen port number of �TCP serverbefore CONNECT command.
00507  * In �TCP Servermode, it indicates the port number of TCP client after successfully establishing connection.
00508  * In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command.
00509  */
00510 #define Sn_DPORT(N)        (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00511 
00512 /**
00513  * @ingroup Socket_register_group
00514  * @brief Maximum Segment Size(Sn_MSSR0) register address(R/W)
00515  * @details @ref Sn_MSSR configures or indicates the MTU(Maximum Transfer Unit) of Socket n.
00516  */
00517 #define Sn_MSSR(N)         (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00518 
00519 // Reserved                  (_W5500_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00520 
00521 /**
00522  * @ingroup Socket_register_group
00523  * @brief IP Type of Service(TOS) Register(R/W)
00524  * @details @ref Sn_TOS configures the TOS(Type Of Service field in IP Header) of Socket n.
00525  * It is set before OPEN command.
00526  */
00527 #define Sn_TOS(N)          (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00528 /**
00529  * @ingroup Socket_register_group
00530  * @brief IP Time to live(TTL) Register(R/W)
00531  * @details @ref Sn_TTL configures the TTL(Time To Live field in IP header) of Socket n.
00532  * It is set before OPEN command.
00533  */
00534 #define Sn_TTL(N)          (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00535 // Reserved                  (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00536 // Reserved                  (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) 
00537 // Reserved                  (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00538 // Reserved                  (_W5500_IO_BASE_ + (0x001A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00539 // Reserved                  (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00540 // Reserved                  (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00541 // Reserved                  (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00542 
00543 /**
00544  * @ingroup Socket_register_group
00545  * @brief Receive memory size register(R/W)
00546  * @details @ref Sn_RXBUF_SIZE configures the RX buffer block size of Socket n.
00547  * Socket n RX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes.
00548  * If a different size is configured, the data cannot be normally received from a peer.
00549  * Although Socket n RX Buffer Block size is initially configured to 2Kbytes,
00550  * user can re-configure its size using @ref Sn_RXBUF_SIZE. The total sum of @ref Sn_RXBUF_SIZE can not be exceed 16Kbytes.
00551  * When exceeded, the data reception error is occurred.
00552  */
00553 #define Sn_RXBUF_SIZE(N)   (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00554 
00555 /**
00556  * @ingroup Socket_register_group
00557  * @brief Transmit memory size register(R/W)
00558  * @details @ref Sn_TXBUF_SIZE configures the TX buffer block size of Socket n. Socket n TX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes.
00559  * If a different size is configured, the data can�t be normally transmitted to a peer.
00560  * Although Socket n TX Buffer Block size is initially configured to 2Kbytes,
00561  * user can be re-configure its size using @ref Sn_TXBUF_SIZE. The total sum of @ref Sn_TXBUF_SIZE can not be exceed 16Kbytes.
00562  * When exceeded, the data transmission error is occurred.
00563  */
00564 #define Sn_TXBUF_SIZE(N)   (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00565 
00566 /**
00567  * @ingroup Socket_register_group
00568  * @brief Transmit free memory size register(R)
00569  * @details @ref Sn_TX_FSR indicates the free size of Socket n TX Buffer Block. It is initialized to the configured size by @ref Sn_TXBUF_SIZE.
00570  * Data bigger than @ref Sn_TX_FSR should not be saved in the Socket n TX Buffer because the bigger data overwrites the previous saved data not yet sent.
00571  * Therefore, check before saving the data to the Socket n TX Buffer, and if data is equal or smaller than its checked size,
00572  * transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size,
00573  * transmit the data after dividing into the checked size and saving in the Socket n TX buffer.
00574  */
00575 #define Sn_TX_FSR(N)       (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00576 
00577 /**
00578  * @ingroup Socket_register_group
00579  * @brief Transmit memory read pointer register address(R)
00580  * @details @ref Sn_TX_RD is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP.
00581  * After its initialization, it is auto-increased by SEND command.
00582  * SEND command transmits the saved data from the current @ref Sn_TX_RD to the @ref Sn_TX_WR in the Socket n TX Buffer.
00583  * After transmitting the saved data, the SEND command increases the @ref Sn_TX_RD as same as the @ref Sn_TX_WR.
00584  * If its increment value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs),
00585  * then the carry bit is ignored and will automatically update with the lower 16bits value.
00586  */
00587 #define Sn_TX_RD(N)        (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00588 
00589 /**
00590  * @ingroup Socket_register_group
00591  * @brief Transmit memory write pointer register address(R/W)
00592  * @details @ref Sn_TX_WR is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP.\n
00593  * It should be read or be updated like as follows.\n
00594  * 1. Read the starting address for saving the transmitting data.\n
00595  * 2. Save the transmitting data from the starting address of Socket n TX buffer.\n
00596  * 3. After saving the transmitting data, update @ref Sn_TX_WR to the increased value as many as transmitting data size.
00597  * If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs),
00598  * then the carry bit is ignored and will automatically update with the lower 16bits value.\n
00599  * 4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command
00600  */
00601 #define Sn_TX_WR(N)        (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00602 
00603 /**
00604  * @ingroup Socket_register_group
00605  * @brief Received data size register(R)
00606  * @details @ref Sn_RX_RSR indicates the data size received and saved in Socket n RX Buffer.
00607  * @ref Sn_RX_RSR does not exceed the @ref Sn_RXBUF_SIZE and is calculated as the difference between
00608  * �Socket n RX Write Pointer (@ref Sn_RX_WR)and �Socket n RX Read Pointer (@ref Sn_RX_RD)
00609  */
00610 #define Sn_RX_RSR(N)       (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00611 
00612 /**
00613  * @ingroup Socket_register_group
00614  * @brief Read point of Receive memory(R/W)
00615  * @details @ref Sn_RX_RD is initialized by OPEN command. Make sure to be read or updated as follows.\n
00616  * 1. Read the starting save address of the received data.\n
00617  * 2. Read data from the starting address of Socket n RX Buffer.\n
00618  * 3. After reading the received data, Update @ref Sn_RX_RD to the increased value as many as the reading size.
00619  * If the increment value exceeds the maximum value 0xFFFF, that is, is greater than 0x10000 and the carry bit occurs,
00620  * update with the lower 16bits value ignored the carry bit.\n
00621  * 4. Order RECV command is for notifying the updated @ref Sn_RX_RD to W5500.
00622  */
00623 #define Sn_RX_RD(N)        (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00624 
00625 /**
00626  * @ingroup Socket_register_group
00627  * @brief Write point of Receive memory(R)
00628  * @details @ref Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception.
00629  * If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs),
00630  * then the carry bit is ignored and will automatically update with the lower 16bits value.
00631  */
00632 #define Sn_RX_WR(N)        (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00633 
00634 /**
00635  * @ingroup Socket_register_group
00636  * @brief socket interrupt mask register(R)
00637  * @details @ref Sn_IMR masks the interrupt of Socket n.
00638  * Each bit corresponds to each bit of @ref Sn_IR. When a Socket n Interrupt is occurred and the corresponding bit of @ref Sn_IMR is 
00639  * the corresponding bit of @ref Sn_IR becomes  When both the corresponding bit of @ref Sn_IMR and @ref Sn_IR are and the n-th bit of @ref IR is 
00640  * Host is interrupted by asserted INTn PIN to low.
00641  */
00642 #define Sn_IMR(N)          (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00643 
00644 /**
00645  * @ingroup Socket_register_group
00646  * @brief Fragment field value in IP header register(R/W)
00647  * @details @ref Sn_FRAG configures the FRAG(Fragment field in IP header).
00648  */
00649 #define Sn_FRAG(N)         (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00650 
00651 /**
00652  * @ingroup Socket_register_group
00653  * @brief Keep Alive Timer register(R/W)
00654  * @details @ref Sn_KPALVTR configures the transmitting timer of �KEEP ALIVE(KA)packet of SOCKETn. It is valid only in TCP mode,
00655  * and ignored in other modes. The time unit is 5s.
00656  * KA packet is transmittable after @ref Sn_SR is changed to SOCK_ESTABLISHED and after the data is transmitted or received to/from a peer at least once.
00657  * In case of '@ref Sn_KPALVTR > 0', W5500 automatically transmits KA packet after time-period for checking the TCP connection (Auto-keepalive-process).
00658  * In case of '@ref Sn_KPALVTR = 0', Auto-keep-alive-process will not operate,
00659  * and KA packet can be transmitted by SEND_KEEP command by the host (Manual-keep-alive-process).
00660  * Manual-keep-alive-process is ignored in case of '@ref Sn_KPALVTR > 0'.
00661  */
00662 #define Sn_KPALVTR(N)      (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00663 
00664 //#define Sn_TSR(N)          (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
00665 
00666 
00667 //----------------------------- W5500 Register values  -----------------------------
00668 
00669 /* MODE register values */
00670 /**
00671  * @brief Reset
00672  * @details If this bit is  All internal registers will be initialized. It will be automatically cleared as after S/W reset.
00673  */
00674 #define MR_RST                       0x80
00675 
00676 /**
00677  * @brief Wake on LAN
00678  * @details 0 : Disable WOL mode\n
00679  * 1 : Enable WOL mode\n
00680  * If WOL mode is enabled and the received magic packet over UDP has been normally processed, the Interrupt PIN (INTn) asserts to low.
00681  * When using WOL mode, the UDP Socket should be opened with any source port number. (Refer to Socket n Mode Register (@ref Sn_MR) for opening Socket.)
00682  * @note The magic packet over UDP supported by W5500 consists of 6 bytes synchronization stream (xFFFFFFFFFFFF and
00683  * 16 times Target MAC address stream in UDP payload. The options such like password are ignored. You can use any UDP source port number for WOL mode.
00684  */
00685 #define MR_WOL                       0x20
00686 
00687 /**
00688  * @brief Ping block
00689  * @details 0 : Disable Ping block\n
00690  * 1 : Enable Ping block\n
00691  * If the bit is  it blocks the response to a ping request.
00692  */
00693 #define MR_PB                        0x10
00694 
00695 /**
00696  * @brief Enable PPPoE
00697  * @details 0 : DisablePPPoE mode\n
00698  * 1 : EnablePPPoE mode\n
00699  * If you use ADSL, this bit should be 
00700  */
00701 #define MR_PPPOE                     0x08
00702 
00703 /**
00704  * @brief Enable UDP_FORCE_ARP CHECHK
00705  * @details 0 : Disable Force ARP mode\n
00706  * 1 : Enable Force ARP mode\n
00707  * In Force ARP mode, It forces on sending ARP Request whenever data is sent.
00708  */
00709 #define MR_FARP                      0x02
00710 
00711 /* IR register values */
00712 /**
00713  * @brief Check IP conflict.
00714  * @details Bit is set as when own source IP address is same with the sender IP address in the received ARP request.
00715  */
00716 #define IR_CONFLICT                  0x80
00717 
00718 /**
00719  * @brief Get the destination unreachable message in UDP sending.
00720  * @details When receiving the ICMP (Destination port unreachable) packet, this bit is set as 
00721  * When this bit is  Destination Information such as IP address and Port number may be checked with the corresponding @ref UIPR & @ref UPORTR.
00722  */
00723 #define IR_UNREACH                   0x40
00724 
00725 /**
00726  * @brief Get the PPPoE close message.
00727  * @details When PPPoE is disconnected during PPPoE mode, this bit is set.
00728  */
00729 #define IR_PPPoE                     0x20
00730 
00731 /**
00732  * @brief Get the magic packet interrupt.
00733  * @details When WOL mode is enabled and receives the magic packet over UDP, this bit is set.
00734  */
00735 #define IR_MP                        0x10
00736 
00737 
00738 /* PHYCFGR register value */
00739 #define PHYCFGR_RST                  ~(1<<7)  //< For PHY reset, must operate AND mask.
00740 #define PHYCFGR_OPMD                 (1<<6)   // Configre PHY with OPMDC value
00741 #define PHYCFGR_OPMDC_ALLA           (7<<3)
00742 #define PHYCFGR_OPMDC_PDOWN          (6<<3)
00743 #define PHYCFGR_OPMDC_NA             (5<<3)
00744 #define PHYCFGR_OPMDC_100FA          (4<<3)
00745 #define PHYCFGR_OPMDC_100F           (3<<3)
00746 #define PHYCFGR_OPMDC_100H           (2<<3)
00747 #define PHYCFGR_OPMDC_10F            (1<<3)
00748 #define PHYCFGR_OPMDC_10H            (0<<3)           
00749 #define PHYCFGR_DPX_FULL             (1<<2)
00750 #define PHYCFGR_DPX_HALF             (0<<2)
00751 #define PHYCFGR_SPD_100              (1<<1)
00752 #define PHYCFGR_SPD_10               (0<<1)
00753 #define PHYCFGR_LNK_ON               (1<<0)
00754 #define PHYCFGR_LNK_OFF              (0<<0)
00755 
00756 /* IMR register values */
00757 /**
00758  * @brief IP Conflict Interrupt Mask.
00759  * @details 0: Disable IP Conflict Interrupt\n
00760  * 1: Enable IP Conflict Interrupt
00761  */
00762 #define IM_IR7                       0x80
00763 
00764 /**
00765  * @brief Destination unreachable Interrupt Mask.
00766  * @details 0: Disable Destination unreachable Interrupt\n
00767  * 1: Enable Destination unreachable Interrupt
00768  */
00769 #define IM_IR6                       0x40
00770 
00771 /**
00772  * @brief PPPoE Close Interrupt Mask.
00773  * @details 0: Disable PPPoE Close Interrupt\n
00774  * 1: Enable PPPoE Close Interrupt
00775  */
00776 #define IM_IR5                       0x20
00777 
00778 /**
00779  * @brief Magic Packet Interrupt Mask.
00780  * @details 0: Disable Magic Packet Interrupt\n
00781  * 1: Enable Magic Packet Interrupt
00782  */
00783 #define IM_IR4                       0x10
00784 
00785 /* Sn_MR Default values */
00786 /**
00787  * @brief Support UDP Multicasting
00788  * @details 0 : disable Multicasting\n
00789  * 1 : enable Multicasting\n
00790  * This bit is applied only during UDP mode(P[3:0] = 010.\n
00791  * To use multicasting, @ref Sn_DIPR & @ref Sn_DPORT should be respectively configured with the multicast group IP address & port number
00792  * before Socket n is opened by OPEN command of @ref Sn_CR.
00793  */
00794 #define Sn_MR_MULTI                  0x80
00795 
00796 /**
00797  * @brief Broadcast block in UDP Multicasting.
00798  * @details 0 : disable Broadcast Blocking\n
00799  * 1 : enable Broadcast Blocking\n
00800  * This bit blocks to receive broadcasting packet during UDP mode(P[3:0] = 010.\m
00801  * In addition, This bit does when MACRAW mode(P[3:0] = 100
00802  */
00803 #define Sn_MR_BCASTB                 0x40
00804 
00805 /**
00806  * @brief No Delayed Ack(TCP), Multicast flag
00807  * @details 0 : Disable No Delayed ACK option\n
00808  * 1 : Enable No Delayed ACK option\n
00809  * This bit is applied only during TCP mode (P[3:0] = 001.\n
00810  * When this bit is  It sends the ACK packet without delay as soon as a Data packet is received from a peer.\n
00811  * When this bit is  It sends the ACK packet after waiting for the timeout time configured by @ref RTR.
00812  */
00813 #define Sn_MR_ND                     0x20
00814 
00815 /**
00816  * @brief Unicast Block in UDP Multicasting
00817  * @details 0 : disable Unicast Blocking\n
00818  * 1 : enable Unicast Blocking\n
00819  * This bit blocks receiving the unicast packet during UDP mode(P[3:0] = 010 and MULTI = 
00820  */
00821 #define Sn_MR_UCASTB                 0x10
00822 
00823 /**
00824  * @brief MAC LAYER RAW SOCK
00825  * @details This configures the protocol mode of Socket n.
00826  * @note MACRAW mode should be only used in Socket 0.
00827  */
00828 #define Sn_MR_MACRAW                 0x04
00829 
00830 //#define Sn_MR_IPRAW                  0x03     /**< IP LAYER RAW SOCK */
00831 
00832 /**
00833  * @brief UDP
00834  * @details This configures the protocol mode of Socket n.
00835  */
00836 #define Sn_MR_UDP                    0x02
00837 
00838 /**
00839  * @brief TCP
00840  * @details This configures the protocol mode of Socket n.
00841  */
00842 #define Sn_MR_TCP                    0x01
00843 
00844 /**
00845  * @brief Unused socket
00846  * @details This configures the protocol mode of Socket n.
00847  */
00848 #define Sn_MR_CLOSE                  0x00
00849 
00850 /* Sn_MR values used with Sn_MR_MACRAW */
00851 /**
00852  * @brief MAC filter enable in @ref Sn_MR_MACRAW mode
00853  * @details 0 : disable MAC Filtering\n
00854  * 1 : enable MAC Filtering\n
00855  * This bit is applied only during MACRAW mode(P[3:0] = 100.\n
00856  * When set as  W5500 can only receive broadcasting packet or packet sent to itself.
00857  * When this bit is  W5500 can receive all packets on Ethernet.
00858  * If user wants to implement Hybrid TCP/IP stack,
00859  * it is recommended that this bit is set as for reducing host overhead to process the all received packets.
00860  */
00861 #define Sn_MR_MFEN                   Sn_MR_MULTI
00862 
00863 /**
00864  * @brief Multicast Blocking in @ref Sn_MR_MACRAW mode
00865  * @details 0 : using IGMP version 2\n
00866  * 1 : using IGMP version 1\n
00867  * This bit is applied only during UDP mode(P[3:0] = 010 and MULTI = 
00868  * It configures the version for IGMP messages (Join/Leave/Report).
00869  */
00870 #define Sn_MR_MMB                    Sn_MR_ND
00871 
00872 /**
00873  * @brief IPv6 packet Blocking in @ref Sn_MR_MACRAW mode
00874  * @details 0 : disable IPv6 Blocking\n
00875  * 1 : enable IPv6 Blocking\n
00876  * This bit is applied only during MACRAW mode (P[3:0] = 100. It blocks to receiving the IPv6 packet.
00877  */
00878 #define Sn_MR_MIP6B                  Sn_MR_UCASTB
00879 
00880 /* Sn_MR value used with Sn_MR_UDP & Sn_MR_MULTI */
00881 /**
00882  * @brief IGMP version used in UDP mulitcasting
00883  * @details 0 : disable Multicast Blocking\n
00884  * 1 : enable Multicast Blocking\n
00885  * This bit is applied only when MACRAW mode(P[3:0] = 100. It blocks to receive the packet with multicast MAC address.
00886  */
00887 #define Sn_MR_MC                     Sn_MR_ND
00888 
00889 /* Sn_MR alternate values */
00890 /**
00891  * @brief For Berkeley Socket API
00892  */
00893 #define SOCK_STREAM                  Sn_MR_TCP
00894 
00895 /**
00896  * @brief For Berkeley Socket API
00897  */
00898 #define SOCK_DGRAM                   Sn_MR_UDP
00899 
00900 
00901 /* Sn_CR values */
00902 /**
00903  * @brief Initialize or open socket
00904  * @details Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0).
00905  * The table below shows the value of @ref Sn_SR corresponding to @ref Sn_MR.\n
00906  * <table>
00907  *   <tr>  <td>\b Sn_MR (P[3:0])</td> <td>\b Sn_SR</td>                  </tr>
00908  *   <tr>  <td>Sn_MR_CLOSE  (000</td> <td></td>                      </tr>
00909  *   <tr>  <td>Sn_MR_TCP  (001</td> <td>SOCK_INIT (0x13)</td>        </tr>
00910  *   <tr>  <td>Sn_MR_UDP  (010</td>  <td>SOCK_UDP (0x22)</td>        </tr>
00911  *   <tr>  <td>S0_MR_MACRAW  (100</td>  <td>SOCK_MACRAW (0x02)</td>  </tr>
00912  * </table>
00913  */
00914 #define Sn_CR_OPEN                   0x01
00915 
00916 /**
00917  * @brief Wait connection request in TCP mode(Server mode)
00918  * @details This is valid only in TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP).
00919  * In this mode, Socket n operates as a �TCP serverand waits for  connection-request (SYN packet) from any �TCP client
00920  * The @ref Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN.
00921  * When a �TCP clientconnection request is successfully established,
00922  * the @ref Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the Sn_IR(0) becomes 
00923  * But when a �TCP clientconnection request is failed, Sn_IR(3) becomes and the status of @ref Sn_SR changes to SOCK_CLOSED.
00924  */
00925 #define Sn_CR_LISTEN                 0x02
00926 
00927 /**
00928  * @brief Send connection request in TCP mode(Client mode)
00929  * @details  To connect, a connect-request (SYN packet) is sent to b>TCP server</b>configured by @ref Sn_DIPR & Sn_DPORT(destination address & port).
00930  * If the connect-request is successful, the @ref Sn_SR is changed to @ref SOCK_ESTABLISHED and the Sn_IR(0) becomes \n\n
00931  * The connect-request fails in the following three cases.\n
00932  * 1. When a @b ARPTO occurs (@ref Sn_IR[3] =  ) because destination hardware address is not acquired through the ARP-process.\n
00933  * 2. When a @b SYN/ACK packet is not received and @b TCPTO (Sn_IR(3) =  )\n
00934  * 3. When a @b RST packet is received instead of a @b SYN/ACK packet. In these cases, @ref Sn_SR is changed to @ref SOCK_CLOSED.
00935  * @note This is valid only in TCP mode and operates when Socket n acts as b>TCP client</b>
00936  */
00937 #define Sn_CR_CONNECT                0x04
00938 
00939 /**
00940  * @brief Send closing request in TCP mode
00941  * @details Regardless of b>TCP server</b>or b>TCP client</b> the DISCON command processes the disconnect-process (b>Active close</b>or b>Passive close</b>.\n
00942  * @par Active close
00943  * it transmits disconnect-request(FIN packet) to the connected peer\n
00944  * @par Passive close
00945  * When FIN packet is received from peer, a FIN packet is replied back to the peer.\n
00946  * @details When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), @ref Sn_SR is changed to @ref SOCK_CLOSED.\n
00947  * Otherwise, TCPTO occurs (Sn_IR(3)=)= and then @ref Sn_SR is changed to @ref SOCK_CLOSED.
00948  * @note Valid only in TCP mode.
00949  */
00950 #define Sn_CR_DISCON                 0x08
00951 
00952 /**
00953  * @brief Close socket
00954  * @details Sn_SR is changed to @ref SOCK_CLOSED.
00955  */
00956 #define Sn_CR_CLOSE                  0x10
00957 
00958 /**
00959  * @brief Update TX buffer pointer and send data
00960  * @details SEND transmits all the data in the Socket n TX buffer.\n
00961  * For more details, please refer to Socket n TX Free Size Register (@ref Sn_TX_FSR), Socket n,
00962  * TX Write Pointer Register(@ref Sn_TX_WR), and Socket n TX Read Pointer Register(@ref Sn_TX_RD).
00963  */
00964 #define Sn_CR_SEND                   0x20
00965 
00966 /**
00967  * @brief Send data with MAC address, so without ARP process
00968  * @details The basic operation is same as SEND.\n
00969  * Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).\n
00970  * But SEND_MAC transmits data without the automatic ARP-process.\n
00971  * In this case, the destination hardware address is acquired from @ref Sn_DHAR configured by host, instead of APR-process.
00972  * @note Valid only in UDP mode.
00973  */
00974 #define Sn_CR_SEND_MAC               0x21
00975 
00976 /**
00977  * @brief Send keep alive message
00978  * @details It checks the connection status by sending 1byte keep-alive packet.\n
00979  * If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur.
00980  * @note Valid only in TCP mode.
00981  */
00982 #define Sn_CR_SEND_KEEP              0x22
00983 
00984 /**
00985  * @brief Update RX buffer pointer and receive data
00986  * @details RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (@ref Sn_RX_RD).\n
00987  * For more details, refer to Socket n RX Received Size Register (@ref Sn_RX_RSR), Socket n RX Write Pointer Register (@ref Sn_RX_WR),
00988  * and Socket n RX Read Pointer Register (@ref Sn_RX_RD).
00989  */
00990 #define Sn_CR_RECV                   0x40
00991 
00992 /* Sn_IR values */
00993 /**
00994  * @brief SEND_OK Interrupt
00995  * @details This is issued when SEND command is completed.
00996  */
00997 #define Sn_IR_SENDOK                 0x10
00998 
00999 /**
01000  * @brief TIMEOUT Interrupt
01001  * @details This is issued when ARPTO or TCPTO occurs.
01002  */
01003 #define Sn_IR_TIMEOUT                0x08
01004 
01005 /**
01006  * @brief RECV Interrupt
01007  * @details This is issued whenever data is received from a peer.
01008  */
01009 #define Sn_IR_RECV                   0x04
01010 
01011 /**
01012  * @brief DISCON Interrupt
01013  * @details This is issued when FIN or FIN/ACK packet is received from a peer.
01014  */
01015 #define Sn_IR_DISCON                 0x02
01016 
01017 /**
01018  * @brief CON Interrupt
01019  * @details This is issued one time when the connection with peer is successful and then @ref Sn_SR is changed to @ref SOCK_ESTABLISHED.
01020  */
01021 #define Sn_IR_CON                    0x01
01022 
01023 /* Sn_SR values */
01024 /**
01025  * @brief Closed
01026  * @details This indicates that Socket n is released.\N
01027  * When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to @ref SOCK_CLOSED regardless of previous status.
01028  */
01029 #define SOCK_CLOSED                  0x00
01030 
01031 /**
01032  * @brief Initiate state
01033  * @details This indicates Socket n is opened with TCP mode.\N
01034  * It is changed to @ref SOCK_INIT when Sn_MR(P[3:0]) = 001and OPEN command is ordered.\N
01035  * After @ref SOCK_INIT, user can use LISTEN /CONNECT command.
01036  */
01037 #define SOCK_INIT                    0x13
01038 
01039 /**
01040  * @brief Listen state
01041  * @details This indicates Socket n is operating as b>TCP server</b>mode and waiting for connection-request (SYN packet) from a peer (b>TCP client</b>.\n
01042  * It will change to @ref SOCK_ESTALBLISHED when the connection-request is successfully accepted.\n
01043  * Otherwise it will change to @ref SOCK_CLOSED after TCPTO occurred (Sn_IR(TIMEOUT) = .
01044  */
01045 #define SOCK_LISTEN                  0x14
01046 
01047 /**
01048  * @brief Connection state
01049  * @details This indicates Socket n sent the connect-request packet (SYN packet) to a peer.\n
01050  * It is temporarily shown when @ref Sn_SR is changed from @ref SOCK_INIT to @ref SOCK_ESTABLISHED by CONNECT command.\n
01051  * If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to @ref SOCK_ESTABLISHED.\n
01052  * Otherwise, it changes to @ref SOCK_CLOSED after TCPTO (@ref Sn_IR[TIMEOUT] =  is occurred.
01053  */
01054 #define SOCK_SYNSENT                 0x15
01055 
01056 /**
01057  * @brief Connection state
01058  * @details It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.\n
01059  * If socket n sends the response (SYN/ACK  packet) to the peer successfully,  it changes to @ref SOCK_ESTABLISHED. \n
01060  * If not, it changes to @ref SOCK_CLOSED after timeout occurs (@ref Sn_IR[TIMEOUT] = .
01061  */
01062 #define SOCK_SYNRECV                 0x16
01063 
01064 /**
01065  * @brief Success to connect
01066  * @details This indicates the status of the connection of Socket n.\n
01067  * It changes to @ref SOCK_ESTABLISHED when the b>TCP SERVER</b>processed the SYN packet from the b>TCP CLIENT</b>during @ref SOCK_LISTEN, or
01068  * when the CONNECT command is successful.\n
01069  * During @ref SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command.
01070  */
01071 #define SOCK_ESTABLISHED             0x17
01072 
01073 /**
01074  * @brief Closing state
01075  * @details These indicate Socket n is closing.\n
01076  * These are shown in disconnect-process such as active-close and passive-close.\n
01077  * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED.
01078  */
01079 #define SOCK_FIN_WAIT                0x18
01080 
01081 /**
01082  * @brief Closing state
01083  * @details These indicate Socket n is closing.\n
01084  * These are shown in disconnect-process such as active-close and passive-close.\n
01085  * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED.
01086  */
01087 #define SOCK_CLOSING                 0x1A
01088 
01089 /**
01090  * @brief Closing state
01091  * @details These indicate Socket n is closing.\n
01092  * These are shown in disconnect-process such as active-close and passive-close.\n
01093  * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED.
01094  */
01095 #define SOCK_TIME_WAIT               0x1B
01096 
01097 /**
01098  * @brief Closing state
01099  * @details This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.\n
01100  * This is half-closing status, and data can be transferred.\n
01101  * For full-closing, DISCON command is used. But For just-closing, CLOSE command is used.
01102  */
01103 #define SOCK_CLOSE_WAIT              0x1C
01104 
01105 /**
01106  * @brief Closing state
01107  * @details This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.\n
01108  * It changes to @ref SOCK_CLOSED when Socket n received the response successfully, or when timeout occurs  (@ref Sn_IR[TIMEOUT] = .
01109  */
01110 #define SOCK_LAST_ACK                0x1D
01111 
01112 /**
01113  * @brief UDP socket
01114  * @details This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0]) = 010.\n
01115  * It changes to SOCK_UPD when Sn_MR(P[3:0]) = 010 and OPEN command is ordered.\n
01116  * Unlike TCP mode, data can be transfered without the connection-process.
01117  */
01118 #define SOCK_UDP                     0x22
01119 
01120 //#define SOCK_IPRAW                   0x32     /**< IP raw mode socket */
01121 
01122 /**
01123  * @brief MAC raw mode socket
01124  * @details This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = 100and is valid only in Socket 0.\n
01125  * It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100and OPEN command is ordered.\n
01126  * Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process.
01127  */
01128 #define SOCK_MACRAW                  0x42
01129 
01130 //#define SOCK_PPPOE                   0x5F
01131 
01132 /* IP PROTOCOL */
01133 #define IPPROTO_IP                   0        //< Dummy for IP 
01134 #define IPPROTO_ICMP                 1        //< Control message protocol
01135 #define IPPROTO_IGMP                 2        //< Internet group management protocol
01136 #define IPPROTO_GGP                  3        //< Gateway^2 (deprecated)
01137 #define IPPROTO_TCP                  6        //< TCP
01138 #define IPPROTO_PUP                  12       //< PUP
01139 #define IPPROTO_UDP                  17       //< UDP
01140 #define IPPROTO_IDP                  22       //< XNS idp
01141 #define IPPROTO_ND                   77       //< UNOFFICIAL net disk protocol
01142 #define IPPROTO_RAW                  255      //< Raw IP packet
01143 
01144 
01145 /**
01146  * @brief Enter a critical section
01147  *
01148  * @details It is provided to protect your shared code which are executed without distribution. \n \n
01149  *
01150  * In non-OS environment, It can be just implemented by disabling whole interrupt.\n
01151  * In OS environment, You can replace it to critical section api supported by OS.
01152  *
01153  * \sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
01154  * \sa WIZCHIP_CRITICAL_EXIT()
01155  */
01156 #define WIZCHIP_CRITICAL_ENTER()    WIZCHIP.CRIS._enter()
01157 
01158 /**
01159  * @brief Exit a critical section
01160  *
01161  * @details It is provided to protect your shared code which are executed without distribution. \n\n
01162  *
01163  * In non-OS environment, It can be just implemented by disabling whole interrupt. \n
01164  * In OS environment, You can replace it to critical section api supported by OS.
01165  *
01166  * @sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
01167  * @sa WIZCHIP_CRITICAL_ENTER()
01168  */
01169 #define WIZCHIP_CRITICAL_EXIT()     WIZCHIP.CRIS._exit()
01170 
01171 
01172 
01173 ////////////////////////
01174 // Basic I/O Function //
01175 ////////////////////////
01176 
01177 /**
01178  * @ingroup Basic_IO_function
01179  * @brief It reads 1 byte value from a register.
01180  * @param AddrSel Register address
01181  * @return The value of register
01182  */
01183 uint8_t  WIZCHIP_READ (uint32_t AddrSel);
01184 
01185 /**
01186  * @ingroup Basic_IO_function
01187  * @brief It writes 1 byte value to a register.
01188  * @param AddrSel Register address
01189  * @param wb Write data
01190  * @return void
01191  */
01192 void     WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
01193 
01194 /**
01195  * @ingroup Basic_IO_function
01196  * @brief It reads sequence data from registers.
01197  * @param AddrSel Register address
01198  * @param pBuf Pointer buffer to read data
01199  * @param len Data length
01200  */
01201 void     WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
01202 
01203 /**
01204  * @ingroup Basic_IO_function
01205  * @brief It writes sequence data to registers.
01206  * @param AddrSel Register address
01207  * @param pBuf Pointer buffer to write data
01208  * @param len Data length
01209  */
01210 void     WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
01211 
01212 /////////////////////////////////
01213 // Common Register I/O function //
01214 /////////////////////////////////
01215 /**
01216  * @ingroup Common_register_access_function
01217  * @brief Set Mode Register
01218  * @param (uint8_t)mr The value to be set.
01219  * @sa getMR()
01220  */
01221 #define setMR(mr) \
01222     WIZCHIP_WRITE(MR,mr)
01223 
01224 
01225 /**
01226  * @ingroup Common_register_access_function
01227  * @brief Get Mode Register
01228  * @return uint8_t. The value of Mode register.
01229  * @sa setMR()
01230  */
01231 #define getMR() \
01232         WIZCHIP_READ(MR)
01233 
01234 /**
01235  * @ingroup Common_register_access_function
01236  * @brief Set gateway IP address
01237  * @param (uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes.
01238  * @sa getGAR()
01239  */
01240 #define setGAR(gar) \
01241         WIZCHIP_WRITE_BUF(GAR,gar,4)
01242 
01243 /**
01244  * @ingroup Common_register_access_function
01245  * @brief Get gateway IP address
01246  * @param (uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes.
01247  * @sa setGAR()
01248  */
01249 #define getGAR(gar) \
01250         WIZCHIP_READ_BUF(GAR,gar,4)
01251 
01252 /**
01253  * @ingroup Common_register_access_function
01254  * @brief Set subnet mask address
01255  * @param (uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes.
01256  * @sa getSUBR()
01257  */
01258 #define setSUBR(subr) \
01259         WIZCHIP_WRITE_BUF(SUBR, subr,4)
01260 
01261 
01262 /**
01263  * @ingroup Common_register_access_function
01264  * @brief Get subnet mask address
01265  * @param (uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes.
01266  * @sa setSUBR()
01267  */
01268 #define getSUBR(subr) \
01269         WIZCHIP_READ_BUF(SUBR, subr, 4)
01270 
01271 /**
01272  * @ingroup Common_register_access_function
01273  * @brief Set local MAC address
01274  * @param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes.
01275  * @sa getSHAR()
01276  */
01277 #define setSHAR(shar) \
01278         WIZCHIP_WRITE_BUF(SHAR, shar, 6)
01279 
01280 /**
01281  * @ingroup Common_register_access_function
01282  * @brief Get local MAC address
01283  * @param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes.
01284  * @sa setSHAR()
01285  */
01286 #define getSHAR(shar) \
01287         WIZCHIP_READ_BUF(SHAR, shar, 6)
01288 
01289 /**
01290  * @ingroup Common_register_access_function
01291  * @brief Set local IP address
01292  * @param (uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes.
01293  * @sa getSIPR()
01294  */
01295 #define setSIPR(sipr) \
01296         WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
01297 
01298 /**
01299  * @ingroup Common_register_access_function
01300  * @brief Get local IP address
01301  * @param (uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes.
01302  * @sa setSIPR()
01303  */
01304 #define getSIPR(sipr) \
01305         WIZCHIP_READ_BUF(SIPR, sipr, 4)
01306 
01307 /**
01308  * @ingroup Common_register_access_function
01309  * @brief Set INTLEVEL register
01310  * @param (uint16_t)intlevel Value to set @ref INTLEVEL register.
01311  * @sa getINTLEVEL()
01312  */
01313 #define setINTLEVEL(intlevel)  {\
01314         WIZCHIP_WRITE(INTLEVEL,   (uint8_t)(intlevel >> 8)); \
01315         WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
01316     }
01317 
01318 
01319 /**
01320  * @ingroup Common_register_access_function
01321  * @brief Get INTLEVEL register
01322  * @return uint16_t. Value of @ref INTLEVEL register.
01323  * @sa setINTLEVEL()
01324  */
01325 #define getINTLEVEL() \
01326         ((WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
01327 
01328 /**
01329  * @ingroup Common_register_access_function
01330  * @brief Set @ref IR register
01331  * @param (uint8_t)ir Value to set @ref IR register.
01332  * @sa getIR()
01333  */
01334 #define setIR(ir) \
01335         WIZCHIP_WRITE(IR, (ir & 0xF0))
01336 
01337 /**
01338  * @ingroup Common_register_access_function
01339  * @brief Get @ref IR register
01340  * @return uint8_t. Value of @ref IR register.
01341  * @sa setIR()
01342  */
01343 #define getIR() \
01344         (WIZCHIP_READ(IR) & 0xF0)
01345 /**
01346  * @ingroup Common_register_access_function
01347  * @brief Set @ref IMR register
01348  * @param (uint8_t)imr Value to set @ref IMR register.
01349  * @sa getIMR()
01350  */
01351 #define setIMR(imr) \
01352         WIZCHIP_WRITE(IMR, imr)
01353 
01354 /**
01355  * @ingroup Common_register_access_function
01356  * @brief Get @ref IMR register
01357  * @return uint8_t. Value of @ref IMR register.
01358  * @sa setIMR()
01359  */
01360 #define getIMR() \
01361         WIZCHIP_READ(IMR)
01362 
01363 
01364 /**
01365  * @ingroup Common_register_access_function
01366  * @brief Set @ref SIR register
01367  * @param (uint8_t)sir Value to set @ref SIR register.
01368  * @sa getSIR()
01369  */
01370 #define setSIR(sir) \
01371         WIZCHIP_WRITE(SIR, sir)
01372 
01373 /**
01374  * @ingroup Common_register_access_function
01375  * @brief Get @ref SIR register
01376  * @return uint8_t. Value of @ref SIR register.
01377  * @sa setSIR()
01378  */
01379 #define getSIR() \
01380         WIZCHIP_READ(SIR)
01381 /**
01382  * @ingroup Common_register_access_function
01383  * @brief Set @ref SIMR register
01384  * @param (uint8_t)simr Value to set @ref SIMR register.
01385  * @sa getSIMR()
01386  */
01387 #define setSIMR(simr) \
01388         WIZCHIP_WRITE(SIMR, simr)
01389 
01390 /**
01391  * @ingroup Common_register_access_function
01392  * @brief Get @ref SIMR register
01393  * @return uint8_t. Value of @ref SIMR register.
01394  * @sa setSIMR()
01395  */
01396 #define getSIMR() \
01397         WIZCHIP_READ(SIMR)
01398 
01399 /**
01400  * @ingroup Common_register_access_function
01401  * @brief Set @ref RTR register
01402  * @param (uint16_t)rtr Value to set @ref RTR register.
01403  * @sa getRTR()
01404  */
01405 #define setRTR(rtr)   {\
01406         WIZCHIP_WRITE(RTR,   (uint8_t)(rtr >> 8)); \
01407         WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(RTR,1), (uint8_t) rtr); \
01408     }
01409 
01410 /**
01411  * @ingroup Common_register_access_function
01412  * @brief Get @ref RTR register
01413  * @return uint16_t. Value of @ref RTR register.
01414  * @sa setRTR()
01415  */
01416 #define getRTR() \
01417         ((WIZCHIP_READ(RTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(RTR,1)))
01418 
01419 /**
01420  * @ingroup Common_register_access_function
01421  * @brief Set @ref RCR register
01422  * @param (uint8_t)rcr Value to set @ref RCR register.
01423  * @sa getRCR()
01424  */
01425 #define setRCR(rcr) \
01426         WIZCHIP_WRITE(RCR, rcr)
01427 
01428 /**
01429  * @ingroup Common_register_access_function
01430  * @brief Get @ref RCR register
01431  * @return uint8_t. Value of @ref RCR register.
01432  * @sa setRCR()
01433  */
01434 #define getRCR() \
01435         WIZCHIP_READ(RCR)
01436 
01437 //================================================== test done ===========================================================
01438 
01439 /**
01440  * @ingroup Common_register_access_function
01441  * @brief Set @ref PTIMER register
01442  * @param (uint8_t)ptimer Value to set @ref PTIMER register.
01443  * @sa getPTIMER()
01444  */
01445 #define setPTIMER(ptimer) \
01446         WIZCHIP_WRITE(PTIMER, ptimer)
01447 
01448 /**
01449  * @ingroup Common_register_access_function
01450  * @brief Get @ref PTIMER register
01451  * @return uint8_t. Value of @ref PTIMER register.
01452  * @sa setPTIMER()
01453  */
01454 #define getPTIMER() \
01455         WIZCHIP_READ(PTIMER)
01456 
01457 /**
01458  * @ingroup Common_register_access_function
01459  * @brief Set @ref PMAGIC register
01460  * @param (uint8_t)pmagic Value to set @ref PMAGIC register.
01461  * @sa getPMAGIC()
01462  */
01463 #define setPMAGIC(pmagic) \
01464         WIZCHIP_WRITE(PMAGIC, pmagic)
01465 
01466 /**
01467  * @ingroup Common_register_access_function
01468  * @brief Get @ref PMAGIC register
01469  * @return uint8_t. Value of @ref PMAGIC register.
01470  * @sa setPMAGIC()
01471  */
01472 #define getPMAGIC() \
01473         WIZCHIP_READ(PMAGIC)
01474 
01475 /**
01476  * @ingroup Common_register_access_function
01477  * @brief Set PHAR address
01478  * @param (uint8_t*)phar Pointer variable to set PPP destination MAC register address. It should be allocated 6 bytes.
01479  * @sa getPHAR()
01480  */
01481 #define setPHAR(phar) \
01482         WIZCHIP_WRITE_BUF(PHAR, phar, 6)
01483 
01484 /**
01485  * @ingroup Common_register_access_function
01486  * @brief Get local IP address
01487  * @param (uint8_t*)phar Pointer variable to PPP destination MAC register address. It should be allocated 6 bytes.
01488  * @sa setPHAR()
01489  */
01490 #define getPHAR(phar) \
01491         WIZCHIP_READ_BUF(PHAR, phar, 6)
01492 
01493 /**
01494  * @ingroup Common_register_access_function
01495  * @brief Set @ref PSID register
01496  * @param (uint16_t)psid Value to set @ref PSID register.
01497  * @sa getPSID()
01498  */
01499 #define setPSID(psid)  {\
01500         WIZCHIP_WRITE(PSID,   (uint8_t)(psid >> 8)); \
01501         WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \
01502     }
01503 
01504 /**
01505  * @ingroup Common_register_access_function
01506  * @brief Get @ref PSID register
01507  * @return uint16_t. Value of @ref PSID register.
01508  * @sa setPSID()
01509  */
01510 //uint16_t getPSID(void);
01511 #define getPSID() \
01512         ((WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
01513 
01514 /**
01515  * @ingroup Common_register_access_function
01516  * @brief Set @ref PMRU register
01517  * @param (uint16_t)pmru Value to set @ref PMRU register.
01518  * @sa getPMRU()
01519  */
01520 #define setPMRU(pmru) { \
01521         WIZCHIP_WRITE(PMRU,   (uint8_t)(pmru>>8)); \
01522         WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \
01523     }
01524 
01525 /**
01526  * @ingroup Common_register_access_function
01527  * @brief Get @ref PMRU register
01528  * @return uint16_t. Value of @ref PMRU register.
01529  * @sa setPMRU()
01530  */
01531 #define getPMRU() \
01532         ((WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
01533 
01534 /**
01535  * @ingroup Common_register_access_function
01536  * @brief Get unreachable IP address
01537  * @param (uint8_t*)uipr Pointer variable to get unreachable IP address. It should be allocated 4 bytes.
01538  */
01539 #define getUIPR(uipr) \
01540         WIZCHIP_READ_BUF(UIPR,uipr,6)
01541 
01542 /**
01543  * @ingroup Common_register_access_function
01544  * @brief Get @ref UPORTR register
01545  * @return uint16_t. Value of @ref UPORTR register.
01546  */
01547 #define getUPORTR() \
01548     ((WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
01549 
01550 /**
01551  * @ingroup Common_register_access_function
01552  * @brief Set @ref PHYCFGR register
01553  * @param (uint8_t)phycfgr Value to set @ref PHYCFGR register.
01554  * @sa getPHYCFGR()
01555  */
01556 #define setPHYCFGR(phycfgr) \
01557         WIZCHIP_WRITE(PHYCFGR, phycfgr)
01558 
01559 /**
01560  * @ingroup Common_register_access_function
01561  * @brief Get @ref PHYCFGR register
01562  * @return uint8_t. Value of @ref PHYCFGR register.
01563  * @sa setPHYCFGR()
01564  */
01565 #define getPHYCFGR() \
01566         WIZCHIP_READ(PHYCFGR)
01567 
01568 /**
01569  * @ingroup Common_register_access_function
01570  * @brief Get @ref VERSIONR register
01571  * @return uint8_t. Value of @ref VERSIONR register.
01572  */
01573 #define getVERSIONR() \
01574         WIZCHIP_READ(VERSIONR)
01575 
01576 /////////////////////////////////////
01577 
01578 ///////////////////////////////////
01579 // Socket N register I/O function //
01580 ///////////////////////////////////
01581 /**
01582  * @ingroup Socket_register_access_function
01583  * @brief Set @ref Sn_MR register
01584  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01585  * @param (uint8_t)mr Value to set @ref Sn_MR
01586  * @sa getSn_MR()
01587  */
01588 #define setSn_MR(sn, mr) \
01589         WIZCHIP_WRITE(Sn_MR(sn),mr)
01590 
01591 /**
01592  * @ingroup Socket_register_access_function
01593  * @brief Get @ref Sn_MR register
01594  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01595  * @return uint8_t. Value of @ref Sn_MR.
01596  * @sa setSn_MR()
01597  */
01598 #define getSn_MR(sn) \
01599     WIZCHIP_READ(Sn_MR(sn))
01600 
01601 /**
01602  * @ingroup Socket_register_access_function
01603  * @brief Set @ref Sn_CR register
01604  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01605  * @param (uint8_t)cr Value to set @ref Sn_CR
01606  * @sa getSn_CR()
01607  */
01608 #define setSn_CR(sn, cr) \
01609         WIZCHIP_WRITE(Sn_CR(sn), cr)
01610 
01611 /**
01612  * @ingroup Socket_register_access_function
01613  * @brief Get @ref Sn_CR register
01614  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01615  * @return uint8_t. Value of @ref Sn_CR.
01616  * @sa setSn_CR()
01617  */
01618 #define getSn_CR(sn) \
01619         WIZCHIP_READ(Sn_CR(sn))
01620 
01621 /**
01622  * @ingroup Socket_register_access_function
01623  * @brief Set @ref Sn_IR register
01624  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01625  * @param (uint8_t)ir Value to set @ref Sn_IR
01626  * @sa getSn_IR()
01627  */
01628 #define setSn_IR(sn, ir) \
01629         WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))
01630 
01631 /**
01632  * @ingroup Socket_register_access_function
01633  * @brief Get @ref Sn_IR register
01634  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01635  * @return uint8_t. Value of @ref Sn_IR.
01636  * @sa setSn_IR()
01637  */
01638 #define getSn_IR(sn) \
01639         (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)
01640 
01641 /**
01642  * @ingroup Socket_register_access_function
01643  * @brief Set @ref Sn_IMR register
01644  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01645  * @param (uint8_t)imr Value to set @ref Sn_IMR
01646  * @sa getSn_IMR()
01647  */
01648 #define setSn_IMR(sn, imr) \
01649         WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))
01650 
01651 /**
01652  * @ingroup Socket_register_access_function
01653  * @brief Get @ref Sn_IMR register
01654  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01655  * @return uint8_t. Value of @ref Sn_IMR.
01656  * @sa setSn_IMR()
01657  */
01658 #define getSn_IMR(sn) \
01659         (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)
01660 
01661 /**
01662  * @ingroup Socket_register_access_function
01663  * @brief Get @ref Sn_SR register
01664  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01665  * @return uint8_t. Value of @ref Sn_SR.
01666  */
01667 #define getSn_SR(sn) \
01668         WIZCHIP_READ(Sn_SR(sn))
01669 
01670 /**
01671  * @ingroup Socket_register_access_function
01672  * @brief Set @ref Sn_PORT register
01673  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01674  * @param (uint16_t)port Value to set @ref Sn_PORT.
01675  * @sa getSn_PORT()
01676  */
01677 #define setSn_PORT(sn, port)  { \
01678         WIZCHIP_WRITE(Sn_PORT(sn),   (uint8_t)(port >> 8)); \
01679         WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
01680     }
01681 
01682 /**
01683  * @ingroup Socket_register_access_function
01684  * @brief Get @ref Sn_PORT register
01685  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01686  * @return uint16_t. Value of @ref Sn_PORT.
01687  * @sa setSn_PORT()
01688  */
01689 #define getSn_PORT(sn) \
01690         ((WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
01691 
01692 /**
01693  * @ingroup Socket_register_access_function
01694  * @brief Set @ref Sn_DHAR register
01695  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01696  * @param (uint8_t*)dhar Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes.
01697  * @sa getSn_DHAR()
01698  */
01699 #define setSn_DHAR(sn, dhar) \
01700         WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
01701 
01702 /**
01703  * @ingroup Socket_register_access_function
01704  * @brief Get @ref Sn_MR register
01705  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01706  * @param (uint8_t*)dhar Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes.
01707  * @sa setSn_DHAR()
01708  */
01709 #define getSn_DHAR(sn, dhar) \
01710         WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
01711 
01712 /**
01713  * @ingroup Socket_register_access_function
01714  * @brief Set @ref Sn_DIPR register
01715  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01716  * @param (uint8_t*)dipr Pointer variable to set socket n destination IP address. It should be allocated 4 bytes.
01717  * @sa getSn_DIPR()
01718  */
01719 #define setSn_DIPR(sn, dipr) \
01720         WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
01721 
01722 /**
01723  * @ingroup Socket_register_access_function
01724  * @brief Get @ref Sn_DIPR register
01725  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01726  * @param (uint8_t*)dipr Pointer variable to get socket n destination IP address. It should be allocated 4 bytes.
01727  * @sa SetSn_DIPR()
01728  */
01729 #define getSn_DIPR(sn, dipr) \
01730         WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
01731 
01732 /**
01733  * @ingroup Socket_register_access_function
01734  * @brief Set @ref Sn_DPORT register
01735  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01736  * @param (uint16_t)dport Value to set @ref Sn_DPORT
01737  * @sa getSn_DPORT()
01738  */
01739 #define setSn_DPORT(sn, dport) { \
01740         WIZCHIP_WRITE(Sn_DPORT(sn),   (uint8_t) (dport>>8)); \
01741         WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t)  dport); \
01742     }
01743 
01744 /**
01745  * @ingroup Socket_register_access_function
01746  * @brief Get @ref Sn_DPORT register
01747  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01748  * @return uint16_t. Value of @ref Sn_DPORT.
01749  * @sa setSn_DPORT()
01750  */
01751 #define getSn_DPORT(sn) \
01752         ((WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
01753 
01754 /**
01755  * @ingroup Socket_register_access_function
01756  * @brief Set @ref Sn_MSSR register
01757  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01758  * @param (uint16_t)mss Value to set @ref Sn_MSSR
01759  * @sa setSn_MSSR()
01760  */
01761 #define setSn_MSSR(sn, mss) { \
01762         WIZCHIP_WRITE(Sn_MSSR(sn),   (uint8_t)(mss>>8)); \
01763         WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
01764     }
01765 
01766 /**
01767  * @ingroup Socket_register_access_function
01768  * @brief Get @ref Sn_MSSR register
01769  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01770  * @return uint16_t. Value of @ref Sn_MSSR.
01771  * @sa setSn_MSSR()
01772  */
01773 #define getSn_MSSR(sn) \
01774         ((WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
01775 
01776 /**
01777  * @ingroup Socket_register_access_function
01778  * @brief Set @ref Sn_TOS register
01779  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01780  * @param (uint8_t)tos Value to set @ref Sn_TOS
01781  * @sa getSn_TOS()
01782  */
01783 #define setSn_TOS(sn, tos) \
01784         WIZCHIP_WRITE(Sn_TOS(sn), tos)
01785 
01786 /**
01787  * @ingroup Socket_register_access_function
01788  * @brief Get @ref Sn_TOS register
01789  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01790  * @return uint8_t. Value of Sn_TOS.
01791  * @sa setSn_TOS()
01792  */
01793 #define getSn_TOS(sn) \
01794         WIZCHIP_READ(Sn_TOS(sn))
01795 
01796 /**
01797  * @ingroup Socket_register_access_function
01798  * @brief Set @ref Sn_TTL register
01799  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01800  * @param (uint8_t)ttl Value to set @ref Sn_TTL
01801  * @sa getSn_TTL()
01802  */
01803 #define setSn_TTL(sn, ttl) \
01804         WIZCHIP_WRITE(Sn_TTL(sn), ttl)
01805 
01806 
01807 /**
01808  * @ingroup Socket_register_access_function
01809  * @brief Get @ref Sn_TTL register
01810  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01811  * @return uint8_t. Value of @ref Sn_TTL.
01812  * @sa setSn_TTL()
01813  */
01814 #define getSn_TTL(sn) \
01815         WIZCHIP_READ(Sn_TTL(sn))
01816 
01817 
01818 /**
01819  * @ingroup Socket_register_access_function
01820  * @brief Set @ref Sn_RXBUF_SIZE register
01821  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01822  * @param (uint8_t)rxbufsize Value to set @ref Sn_RXBUF_SIZE
01823  * @sa getSn_RXBUF_SIZE()
01824  */
01825 #define setSn_RXBUF_SIZE(sn, rxbufsize) \
01826         WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)
01827 
01828 
01829 /**
01830  * @ingroup Socket_register_access_function
01831  * @brief Get @ref Sn_RXBUF_SIZE register
01832  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01833  * @return uint8_t. Value of @ref Sn_RXBUF_SIZE.
01834  * @sa setSn_RXBUF_SIZE()
01835  */
01836 #define getSn_RXBUF_SIZE(sn) \
01837         WIZCHIP_READ(Sn_RXBUF_SIZE(sn))
01838 
01839 /**
01840  * @ingroup Socket_register_access_function
01841  * @brief Set @ref Sn_TXBUF_SIZE register
01842  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01843  * @param (uint8_t)txbufsize Value to set @ref Sn_TXBUF_SIZE
01844  * @sa getSn_TXBUF_SIZE()
01845  */
01846 #define setSn_TXBUF_SIZE(sn, txbufsize) \
01847         WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)
01848 
01849 /**
01850  * @ingroup Socket_register_access_function
01851  * @brief Get @ref Sn_TXBUF_SIZE register
01852  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01853  * @return uint8_t. Value of @ref Sn_TXBUF_SIZE.
01854  * @sa setSn_TXBUF_SIZE()
01855  */
01856 #define getSn_TXBUF_SIZE(sn) \
01857         WIZCHIP_READ(Sn_TXBUF_SIZE(sn))
01858 
01859 /**
01860  * @ingroup Socket_register_access_function
01861  * @brief Get @ref Sn_TX_FSR register
01862  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01863  * @return uint16_t. Value of @ref Sn_TX_FSR.
01864  */
01865 uint16_t getSn_TX_FSR(uint8_t sn);
01866 
01867 /**
01868  * @ingroup Socket_register_access_function
01869  * @brief Get @ref Sn_TX_RD register
01870  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01871  * @return uint16_t. Value of @ref Sn_TX_RD.
01872  */
01873 #define getSn_TX_RD(sn) \
01874         ((WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
01875 
01876 /**
01877  * @ingroup Socket_register_access_function
01878  * @brief Set @ref Sn_TX_WR register
01879  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01880  * @param (uint16_t)txwr Value to set @ref Sn_TX_WR
01881  * @sa GetSn_TX_WR()
01882  */
01883 #define setSn_TX_WR(sn, txwr) { \
01884         WIZCHIP_WRITE(Sn_TX_WR(sn),   (uint8_t)(txwr>>8)); \
01885         WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
01886         }
01887 
01888 /**
01889  * @ingroup Socket_register_access_function
01890  * @brief Get @ref Sn_TX_WR register
01891  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01892  * @return uint16_t. Value of @ref Sn_TX_WR.
01893  * @sa setSn_TX_WR()
01894  */
01895 #define getSn_TX_WR(sn) \
01896         ((WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
01897 
01898 
01899 /**
01900  * @ingroup Socket_register_access_function
01901  * @brief Get @ref Sn_RX_RSR register
01902  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01903  * @return uint16_t. Value of @ref Sn_RX_RSR.
01904  */
01905 uint16_t getSn_RX_RSR(uint8_t sn);
01906 
01907 
01908 /**
01909  * @ingroup Socket_register_access_function
01910  * @brief Set @ref Sn_RX_RD register
01911  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01912  * @param (uint16_t)rxrd Value to set @ref Sn_RX_RD
01913  * @sa getSn_RX_RD()
01914  */
01915 #define setSn_RX_RD(sn, rxrd) { \
01916         WIZCHIP_WRITE(Sn_RX_RD(sn),   (uint8_t)(rxrd>>8)); \
01917         WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
01918     }
01919 
01920 /**
01921  * @ingroup Socket_register_access_function
01922  * @brief Get @ref Sn_RX_RD register
01923  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01924  * @regurn uint16_t. Value of @ref Sn_RX_RD.
01925  * @sa setSn_RX_RD()
01926  */
01927 #define getSn_RX_RD(sn) \
01928         ((WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
01929 
01930 /**
01931  * @ingroup Socket_register_access_function
01932  * @brief Get @ref Sn_RX_WR register
01933  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01934  * @return uint16_t. Value of @ref Sn_RX_WR.
01935  */
01936 #define getSn_RX_WR(sn) \
01937         ((WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
01938 
01939 
01940 /**
01941  * @ingroup Socket_register_access_function
01942  * @brief Set @ref Sn_FRAG register
01943  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01944  * @param (uint16_t)frag Value to set @ref Sn_FRAG
01945  * @sa getSn_FRAD()
01946  */
01947 #define setSn_FRAG(sn, frag) { \
01948         WIZCHIP_WRITE(Sn_FRAG(sn),  (uint8_t)(frag >>8)); \
01949         WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
01950     }
01951 
01952 /**
01953  * @ingroup Socket_register_access_function
01954  * @brief Get @ref Sn_FRAG register
01955  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01956  * @return uint16_t. Value of @ref Sn_FRAG.
01957  * @sa setSn_FRAG()
01958  */
01959 #define getSn_FRAG(sn) \
01960         ((WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
01961 
01962 /**
01963  * @ingroup Socket_register_access_function
01964  * @brief Set @ref Sn_KPALVTR register
01965  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01966  * @param (uint8_t)kpalvt Value to set @ref Sn_KPALVTR
01967  * @sa getSn_KPALVTR()
01968  */
01969 #define setSn_KPALVTR(sn, kpalvt) \
01970         WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)
01971 
01972 /**
01973  * @ingroup Socket_register_access_function
01974  * @brief Get @ref Sn_KPALVTR register
01975  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01976  * @return uint8_t. Value of @ref Sn_KPALVTR.
01977  * @sa setSn_KPALVTR()
01978  */
01979 #define getSn_KPALVTR(sn) \
01980         WIZCHIP_READ(Sn_KPALVTR(sn))
01981 
01982 //////////////////////////////////////
01983 
01984 /////////////////////////////////////
01985 // Sn_TXBUF & Sn_RXBUF IO function //
01986 /////////////////////////////////////
01987 /**  
01988  * @brief Gets the max buffer size of socket sn passed as parameter.
01989  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01990  * @return uint16_t. Value of Socket n RX max buffer size.
01991  */
01992 #define getSn_RxMAX(sn) \
01993         (getSn_RXBUF_SIZE(sn) << 10)
01994 
01995 /**  
01996  * @brief Gets the max buffer size of socket sn passed as parameters.
01997  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
01998  * @return uint16_t. Value of Socket n TX max buffer size.
01999  */
02000 //uint16_t getSn_TxMAX(uint8_t sn);
02001 #define getSn_TxMAX(sn) \
02002         (getSn_TXBUF_SIZE(sn) << 10)
02003 
02004 /**
02005  * @ingroup Basic_IO_function
02006  * @brief It copies data to internal TX memory
02007  *
02008  * @details This function reads the Tx write pointer register and after that,
02009  * it copies the <i>wizdata(pointer buffer)</i> of the length of <i>len(variable)</i> bytes to internal TX memory
02010  * and updates the Tx write pointer register.
02011  * This function is being called by send() and sendto() function also.
02012  *
02013  * @note User should read upper byte first and lower byte later to get proper value.
02014  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
02015  * @param wizdata Pointer buffer to write data
02016  * @param len Data length
02017  * @sa wiz_recv_data()
02018  */
02019 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
02020 
02021 /**
02022  * @ingroup Basic_IO_function
02023  * @brief It copies data to your buffer from internal RX memory
02024  *
02025  * @details This function read the Rx read pointer register and after that,
02026  * it copies the received data from internal RX memory
02027  * to <i>wizdata(pointer variable)</i> of the length of <i>len(variable)</i> bytes.
02028  * This function is being called by recv() also.
02029  *
02030  * @note User should read upper byte first and lower byte later to get proper value.
02031  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
02032  * @param wizdata Pointer buffer to read data
02033  * @param len Data length
02034  * @sa wiz_send_data()
02035  */
02036 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
02037 
02038 /**
02039  * @ingroup Basic_IO_function
02040  * @brief It discard the received data in RX memory.
02041  * @details It discards the data of the length of <i>len(variable)</i> bytes in internal RX memory.
02042  * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>.
02043  * @param len Data length
02044  */
02045 void wiz_recv_ignore(uint8_t sn, uint16_t len);
02046 
02047 #endif   // _W5500_H_