Vekatech / Touch

Touch driver for companion boards (VKLCD50RTA & VKLCD70RT)

stmpe811iic.h@0:0383b9f88d72, 2017-11-03 (annotated)

Committer:
tvendov
Date:
Fri Nov 03 08:52:07 2017 +0000
Revision:
0:0383b9f88d72
Touch panel driver initial release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tvendov 0:0383b9f88d72 1 /*******************************************************************************
tvendov 0:0383b9f88d72 2
tvendov 0:0383b9f88d72 3 *******************************************************************************/
tvendov 0:0383b9f88d72 4 /******************************************************************************
tvendov 0:0383b9f88d72 5 * File Name : tpiic.h
tvendov 0:0383b9f88d72 6 * Description : TPIIC header
tvendov 0:0383b9f88d72 7 ******************************************************************************/
tvendov 0:0383b9f88d72 8 #ifndef STMPE811IIC_H
tvendov 0:0383b9f88d72 9 #define STMPE811IIC_H
tvendov 0:0383b9f88d72 10
tvendov 0:0383b9f88d72 11 #ifdef LCD_PANEL_H
tvendov 0:0383b9f88d72 12 #include "lcd_panel.h"
tvendov 0:0383b9f88d72 13 #else
tvendov 0:0383b9f88d72 14 /* TOUCH panels: */
tvendov 0:0383b9f88d72 15 #define LCD_CH0_PANEL_VKLCD50RTA (1) /* 16bitRGB(565) [HVGA 480x272] */
tvendov 0:0383b9f88d72 16 #define LCD_CH0_PANEL_VKLCD70RT (2) /* LVDS [WSVGA 1024x600] */
tvendov 0:0383b9f88d72 17
tvendov 0:0383b9f88d72 18 #define LCD_VDC5_CH0_PANEL LCD_CH0_PANEL_VKLCD70RT
tvendov 0:0383b9f88d72 19 #endif
tvendov 0:0383b9f88d72 20
tvendov 0:0383b9f88d72 21 /******************************************************************************
tvendov 0:0383b9f88d72 22 Includes <System Includes> , "Project Includes"
tvendov 0:0383b9f88d72 23 ******************************************************************************/
tvendov 0:0383b9f88d72 24
tvendov 0:0383b9f88d72 25 #define __USE_DEFAULT_CALIBRATION_DATA__
tvendov 0:0383b9f88d72 26
tvendov 0:0383b9f88d72 27 #define STMPE811_DEVICE_ADDR (0x82)
tvendov 0:0383b9f88d72 28 //#define STMPE811_DEVICE_ADDR (0x88)
tvendov 0:0383b9f88d72 29 //#define EE_LPC11U35_DEVICE_ADDR (0xA0)
tvendov 0:0383b9f88d72 30
tvendov 0:0383b9f88d72 31 #define TPIIC_CH 3
tvendov 0:0383b9f88d72 32 #define TPIIC_SCL P1_6
tvendov 0:0383b9f88d72 33 #define TPIIC_SDA P1_7
tvendov 0:0383b9f88d72 34
tvendov 0:0383b9f88d72 35 #if (LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_VKLCD70RT)
tvendov 0:0383b9f88d72 36 #define TPIRQ_CH 1
tvendov 0:0383b9f88d72 37 #define TPIRQ_PIN P7_8
tvendov 0:0383b9f88d72 38
tvendov 0:0383b9f88d72 39 #define EEIIC_CH 3
tvendov 0:0383b9f88d72 40 #define EEIIC_SCL P1_6
tvendov 0:0383b9f88d72 41 #define EEIIC_SDA P1_7
tvendov 0:0383b9f88d72 42 #define EE_CALIB_DEVICE_ADDR 0xA8
tvendov 0:0383b9f88d72 43
tvendov 0:0383b9f88d72 44 #define TPCALIBRATION_DATA 0x38,0x00,0x00,0x00,0x01,0x00,0x00,0x00,\
tvendov 0:0383b9f88d72 45 0x50,0xb4,0x52,0x38,0xec,0x97,0xd0,0x3f,0xd7,0xfe,0x58,0xc5,0x10,0xb2,0x52,0x3f,\
tvendov 0:0383b9f88d72 46 0xde,0x09,0xc6,0x87,0xaa,0x7d,0xbb,0x3e,0x65,0xaa,0xb4,0xd2,0x56,0x04,0xc5,0xbf,\
tvendov 0:0383b9f88d72 47 0x02,0xb3,0x33,0x61,0x9b,0x1e,0x34,0xc0,0x88,0x87,0xc3,0x39,0x38,0x7d,0x83,0x40
tvendov 0:0383b9f88d72 48 #else
tvendov 0:0383b9f88d72 49 #define TPIRQ_CH 2
tvendov 0:0383b9f88d72 50 #define TPIRQ_PIN P1_2
tvendov 0:0383b9f88d72 51
tvendov 0:0383b9f88d72 52 #define EEIIC_CH 0
tvendov 0:0383b9f88d72 53 #define EEIIC_SCL P1_0
tvendov 0:0383b9f88d72 54 #define EEIIC_SDA P1_1
tvendov 0:0383b9f88d72 55 #define EE_CALIB_DEVICE_ADDR 0xA8
tvendov 0:0383b9f88d72 56
tvendov 0:0383b9f88d72 57 #define TPCALIBRATION_DATA 0x38,0x00,0x00,0x00,0x01,0x00,0x00,0x00,\
tvendov 0:0383b9f88d72 58 0x66,0x44,0x6c,0xe9,0x11,0xa1,0xbf,0xbf,0x70,0x8f,0x61,0x1c,0x3f,0x5e,0x20,0x3f,\
tvendov 0:0383b9f88d72 59 0xad,0x80,0xca,0x76,0x62,0xb9,0x8a,0x3e,0xae,0x95,0xef,0x7e,0xa7,0x8d,0xb2,0xbf,\
tvendov 0:0383b9f88d72 60 0x24,0x37,0x82,0x68,0xe6,0xc1,0x7e,0x40,0xf4,0xb6,0xa8,0xe8,0x88,0xa3,0x71,0x40
tvendov 0:0383b9f88d72 61 #endif
tvendov 0:0383b9f88d72 62
tvendov 0:0383b9f88d72 63 #define FIFO_DEPTH 128 // packets, which means 12bit x + 12bit y +8bit = 32bit for 1 data packet
tvendov 0:0383b9f88d72 64
tvendov 0:0383b9f88d72 65 //sys regs
tvendov 0:0383b9f88d72 66 #define CHIP_ID 0x00 // 16 R 0x0811 Device identification
tvendov 0:0383b9f88d72 67 #define ID_VER 0x02 // 8 R 0x01 Revision number 0x01 for engineering sample for final silicon
tvendov 0:0383b9f88d72 68 #define SYS_CTRL1 0x03 // 8 R/W 0x00 Reset control
tvendov 0:0383b9f88d72 69 #define SYS_CTRL2 0x04 // 8 R/W 0x0F Clock control
tvendov 0:0383b9f88d72 70 #define SPI_CFG 0x08 // 8 R/W 0x01 SPI interface configuration
tvendov 0:0383b9f88d72 71 #define INT_CTRL 0x09 // 8 R/W 0x00 Interrupt control register
tvendov 0:0383b9f88d72 72 #define INT_EN 0x0A // 8 R/W 0x00 Interrupt enable register
tvendov 0:0383b9f88d72 73 #define INT_STA 0x0B // 8 R 0x10 interrupt status register
tvendov 0:0383b9f88d72 74 #define GPIO_EN 0x0C // 8 R/W 0x00 GPIO interrupt enable register
tvendov 0:0383b9f88d72 75 #define GPIO_INT_STA 0x0D // 8 R 0x00 GPIO interrupt status register
tvendov 0:0383b9f88d72 76 #define ADC_INT_EN 0x0E // 8 R/W 0x00 ADC interrupt enable register
tvendov 0:0383b9f88d72 77 #define ADC_INT_STA 0x0F // 8 R 0x00 ADC interrupt status register
tvendov 0:0383b9f88d72 78 #define GPIO_SET_PIN 0x10 // 8 R/W 0x00 GPIO set pin register
tvendov 0:0383b9f88d72 79 #define GPIO_CLR_PIN 0x11 // 8 R/W 0x00 GPIO clear pin register
tvendov 0:0383b9f88d72 80 #define GPIO_MP_STA 0x12 // 8 R/W 0x00 GPIO monitor pin state register
tvendov 0:0383b9f88d72 81 #define GPIO_DIR 0x13 // 8 R/W 0x00 GPIO direction register
tvendov 0:0383b9f88d72 82 #define GPIO_ED 0x14 // 8 R/W 0x00 GPIO edge detect register
tvendov 0:0383b9f88d72 83 #define GPIO_RE 0x15 // 8 R/W 0x00 GPIO rising edge register
tvendov 0:0383b9f88d72 84 #define GPIO_FE 0x16 // 8 R/W 0x00 GPIO falling edge register
tvendov 0:0383b9f88d72 85 #define GPIO_AF 0x17 // 8 R/W 0x00 Alternate function register
tvendov 0:0383b9f88d72 86
tvendov 0:0383b9f88d72 87 //ADC regs
tvendov 0:0383b9f88d72 88 #define ADC_CTRL1 0x20 // 8 R/W 0x9C ADC control
tvendov 0:0383b9f88d72 89 #define ADC_CTRL2 0x21 // 8 R/W 0x01 ADC control
tvendov 0:0383b9f88d72 90 #define ADC_CAPT 0x22 // 8 R/W 0xFF To initiate ADC data acquisition
tvendov 0:0383b9f88d72 91 #define ADC_DATA_CH0 0x30 // 16 R 0x0000 ADC channel 0
tvendov 0:0383b9f88d72 92 #define ADC_DATA_CH1 0x32 // 16 R 0x0000 ADC channel 1
tvendov 0:0383b9f88d72 93 #define ADC_DATA_CH2 0x34 // 16 R 0x0000 ADC channel 2
tvendov 0:0383b9f88d72 94 #define ADC_DATA_CH3 0x36 // 16 R 0x0000 ADC channel 3
tvendov 0:0383b9f88d72 95 #define ADC_DATA_CH4 0x38 // 16 R 0x0000 ADC channel 4
tvendov 0:0383b9f88d72 96 #define ADC_DATA_CH5 0x3A // 16 R 0x0000 ADC channel 5
tvendov 0:0383b9f88d72 97 #define ADC_DATA_CH6 0x3C // 16 R 0x0000 ADC channel 6
tvendov 0:0383b9f88d72 98 #define ADC_DATA_CH7 0x3E // 16 R 0x0000 ADC channel 7
tvendov 0:0383b9f88d72 99
tvendov 0:0383b9f88d72 100 //touch regs
tvendov 0:0383b9f88d72 101 #define TSC_CTRL 0x40 // 8 R/W 0x90 4-wire touchscreen controller setup
tvendov 0:0383b9f88d72 102 #define TSC_CFG 0x41 // 8 R/W 0x00 Touchscreen controller configuration
tvendov 0:0383b9f88d72 103 #define WDW_TR_X 0x42 // 16 R/W 0x0FFF Window setup for top right X
tvendov 0:0383b9f88d72 104 #define WDW_TR_Y 0x44 // 16 R/W 0x0FFF Window setup for top right Y
tvendov 0:0383b9f88d72 105 #define WDW_BL_X 0x46 // 16 R/W 0x0000 Window setup for bottom left X
tvendov 0:0383b9f88d72 106 #define WDW_BL_Y 0x48 // 16 R/W 0x0000 Window setup for bottom left Y
tvendov 0:0383b9f88d72 107 #define FIFO_TH 0x4A // 8 R/W 0x00 FIFO level to generate interrupt
tvendov 0:0383b9f88d72 108 #define FIFO_STA 0x4B // 8 R/W 0x20 Current status of FIFO
tvendov 0:0383b9f88d72 109 #define FIFO_SIZE 0x4C // 8 R 0x00 Current filled level of FIFO
tvendov 0:0383b9f88d72 110 #define TSC_DATA_X 0x4D // 16 R 0x0000 Data port for touchscreen controller data access
tvendov 0:0383b9f88d72 111 #define TSC_DATA_Y 0x4F // 16 R 0x0000 Data port for touchscreen controller data access
tvendov 0:0383b9f88d72 112 #define TSC_DATA_Z 0x51 // 8 R 0x0000 Data port for touchscreen controller data access
tvendov 0:0383b9f88d72 113 #define TSC_DATA_XYZ 0x52 // 32 R 0x00000000 Data port for touchscreen controller data access
tvendov 0:0383b9f88d72 114 #define TSC_FRACT_Z 0x56 // 8 0x00
tvendov 0:0383b9f88d72 115 #define TSC_DATA_AI 0x57 // 8 R 0x00 Data port for touchscreen controller data access AUTO_INCREMENT
tvendov 0:0383b9f88d72 116 #define TSC_DATA_NAI 0x07 // 8 R 0x00 Data port for touchscreen controller data access NONE_AUTO_INCREMENT
tvendov 0:0383b9f88d72 117 #define TSC_DATA_FIFO 0xD7 //
tvendov 0:0383b9f88d72 118 #define TSC_I_DRIVE 0x58 // 8 R/W 0x00
tvendov 0:0383b9f88d72 119 #define TSC_SHIELD 0x59 // 8 R/W 0x00
tvendov 0:0383b9f88d72 120
tvendov 0:0383b9f88d72 121 //temperature regs
tvendov 0:0383b9f88d72 122 #define TEMP_CTRL 0x60 // 8 R/W 0x00 Temperature sensor setup
tvendov 0:0383b9f88d72 123 #define TEMP_DATA 0x61 // 8 R 0x00 Temperature data access port
tvendov 0:0383b9f88d72 124 #define TEMP_TH 0x62 // 8 R/W 0x00 Threshold for temperature controlled interrupt
tvendov 0:0383b9f88d72 125
tvendov 0:0383b9f88d72 126 //interrupt status & enable bits
tvendov 0:0383b9f88d72 127 #define INT_GPIO 0x80
tvendov 0:0383b9f88d72 128 #define INT_ADC 0x40
tvendov 0:0383b9f88d72 129 #define INT_TEMP_SENS 0x20
tvendov 0:0383b9f88d72 130 #define INT_FIFO_EMPTY 0x10
tvendov 0:0383b9f88d72 131 #define INT_FIFO_FULL 0x08
tvendov 0:0383b9f88d72 132 #define INT_FIFO_OFLOW 0x04
tvendov 0:0383b9f88d72 133 #define INT_FIFO_TH 0x02
tvendov 0:0383b9f88d72 134 #define INT_TOUCH_DET 0x01
tvendov 0:0383b9f88d72 135
tvendov 0:0383b9f88d72 136 //other bits
tvendov 0:0383b9f88d72 137 #define TSC_STA 0x80
tvendov 0:0383b9f88d72 138
tvendov 0:0383b9f88d72 139 //Z axis accuracy
tvendov 0:0383b9f88d72 140 #define _8_0 0x00
tvendov 0:0383b9f88d72 141 #define _7_1 0x01
tvendov 0:0383b9f88d72 142 #define _6_2 0x02
tvendov 0:0383b9f88d72 143 #define _5_3 0x03
tvendov 0:0383b9f88d72 144 #define _4_4 0x04
tvendov 0:0383b9f88d72 145 #define _3_5 0x05
tvendov 0:0383b9f88d72 146 #define _2_6 0x06
tvendov 0:0383b9f88d72 147 #define _1_7 0x07
tvendov 0:0383b9f88d72 148
tvendov 0:0383b9f88d72 149 #define INIT_DATA /* {register, value}, ... */ \
tvendov 0:0383b9f88d72 150 {SYS_CTRL1, 0x02}, /* 0. Reset touchscreen controller */ \
tvendov 0:0383b9f88d72 151 {SYS_CTRL2, 0x0C}, /* 1. Disable the clock gating for the touchscreen controller and ADC in the SYS_CFG2 register*/ \
tvendov 0:0383b9f88d72 152 {INT_EN, (INT_FIFO_OFLOW | INT_FIFO_TH | INT_TOUCH_DET)}, /* 2. Configure which interrupts to be outputed */ \
tvendov 0:0383b9f88d72 153 {ADC_CTRL1, 0x49}, /* 3. Write: register Add = 0x20 ADC_CTRL1, data = 0x49 delay, 2mS */ \
tvendov 0:0383b9f88d72 154 {ADC_CTRL2, 0x01}, /* 4. Write: register Add = 0x21 ADC_CTRL2, data = 0x01 */ \
tvendov 0:0383b9f88d72 155 {GPIO_AF, 0x00}, /* 5. Write: register Add = 0x17 GPIO_AF, data = 0x00 */ \
tvendov 0:0383b9f88d72 156 {TSC_CFG, 0x6C}, /* 6. 5ms panel voltage setting time, 1ms touch detection delay, averaging on every 2-nd sample */ \
tvendov 0:0383b9f88d72 157 {FIFO_TH, 0x05}, /* 7. Group points reading (if more than 4 points collected generate interrupt) */ \
tvendov 0:0383b9f88d72 158 {FIFO_STA, 0x01}, /* 8a. Clear FIFO */ \
tvendov 0:0383b9f88d72 159 {FIFO_STA, 0x00}, /* 8b. Reset FIFO */ \
tvendov 0:0383b9f88d72 160 {TSC_FRACT_Z, _8_0}, /* 9. Choose the appropriate accurency of the measured pressure of the touch 7 fractional bits & 1 int */ \
tvendov 0:0383b9f88d72 161 {TSC_I_DRIVE, 0x00}, /* 10. Write: register Add = 0x58 TSC_I_DRIVE, data = 0x01 */ \
tvendov 0:0383b9f88d72 162 {TSC_CTRL, 0x01}, /* 11. Configure the operating mode and the window tracking index, start touch detection & data acquisition*/\
tvendov 0:0383b9f88d72 163 {INT_STA, 0xFF}, /* 12. Clear Interrupt register*/ \
tvendov 0:0383b9f88d72 164 {INT_CTRL, 0x03}, /* 13. Configure the interrupt signal and enable the interrupts //int-> Edge interrupt -> falling edge*/
tvendov 0:0383b9f88d72 165
tvendov 0:0383b9f88d72 166 /******************************************************************************
tvendov 0:0383b9f88d72 167 Variable Externs
tvendov 0:0383b9f88d72 168 ******************************************************************************/
tvendov 0:0383b9f88d72 169
tvendov 0:0383b9f88d72 170 typedef union __CALIB {
tvendov 0:0383b9f88d72 171 struct __DATA
tvendov 0:0383b9f88d72 172 {
tvendov 0:0383b9f88d72 173 unsigned long len;
tvendov 0:0383b9f88d72 174 unsigned long flag;
tvendov 0:0383b9f88d72 175 double KX1, KY1, KX2, KY2, KX3, KY3;
tvendov 0:0383b9f88d72 176 }data;
tvendov 0:0383b9f88d72 177 unsigned char KX08[sizeof(struct __DATA)];
tvendov 0:0383b9f88d72 178 }touch_calib_data_t;
tvendov 0:0383b9f88d72 179
tvendov 0:0383b9f88d72 180 typedef union RAW_SAMPLE__ {
tvendov 0:0383b9f88d72 181 struct AXIS__
tvendov 0:0383b9f88d72 182 {
tvendov 0:0383b9f88d72 183 unsigned short x;
tvendov 0:0383b9f88d72 184 unsigned short y;
tvendov 0:0383b9f88d72 185 unsigned long z;
tvendov 0:0383b9f88d72 186 }axis;
tvendov 0:0383b9f88d72 187 unsigned long long dot;
tvendov 0:0383b9f88d72 188 }touch_raw_data_t;
tvendov 0:0383b9f88d72 189
tvendov 0:0383b9f88d72 190 typedef union SCREEN_SAMPLE__ {
tvendov 0:0383b9f88d72 191 struct AXIS_
tvendov 0:0383b9f88d72 192 {
tvendov 0:0383b9f88d72 193 short x;
tvendov 0:0383b9f88d72 194 short y;
tvendov 0:0383b9f88d72 195 float z;
tvendov 0:0383b9f88d72 196 }axis;
tvendov 0:0383b9f88d72 197 unsigned long long dot;
tvendov 0:0383b9f88d72 198 }touch_screen_data_t;
tvendov 0:0383b9f88d72 199
tvendov 0:0383b9f88d72 200 #endif /* STMPE811IIC_H */