FT_Gpu_Hal.cpp

00001 /* mbed Library for FTDI FT800  Enbedded Video Engine "EVE"
00002  * based on Original Code Sample from FTDI
00003  * ported to mbed by Peter Drescher, DC2PD 2014
00004  * Released under the MIT License: http://mbed.org/license/mit 
00005  * 19.09.14 changed to shorter function names  
00006  * FTDI was using very long names. 
00007  * Ft_App_Flush_Co_Buffer -> Flush_Co_Buffer ...  */
00008 
00009 #include "FT_Platform.h"
00010 #include "mbed.h"
00011 #include "FT_LCD_Type.h"
00012 Serial pc(USBTX, USBRX);
00013 
00014 FT800::FT800(PinName mosi,
00015             PinName miso,
00016             PinName sck,
00017             PinName ss,
00018             PinName intr,
00019             PinName pd)
00020     :
00021      _spi(mosi, miso, sck),
00022      _ss(ss),
00023      _pd(pd),
00024      _f800_isr(InterruptIn(intr))
00025      {
00026          _spi.format(8,0);                  // 8 bit spi mode 0
00027          _spi.frequency(1000000);          // start with 10 Mhz SPI clock
00028          _ss = 1;                           // cs high
00029          _pd = 1;                           // PD high
00030          Bootup();
00031      }
00032 
00033 
00034 ft_bool_t FT800::Bootup(void){
00035     Open();
00036     BootupConfig();
00037 
00038     return(1);
00039     }
00040 
00041 
00042 ft_void_t FT800::BootupConfig(void){
00043     ft_uint8_t chipid;
00044     /* Do a power cycle for safer side */
00045     Powercycle( FT_TRUE);
00046     /*
00047     7/8/16: Curt added the sleep delay below...
00048     */
00049 //  Sleep(30);
00050     
00051     /* Set the clk to external clock */
00052     HostCommand( FT_GPU_EXTERNAL_OSC);
00053     Sleep(10);
00054     
00055     /* Access address 0 to wake up the FT800 */
00056     HostCommand( FT_GPU_ACTIVE_M);
00057     Sleep(500);
00058 
00059     /* Switch PLL output to 48MHz */
00060 //  HostCommand( FT_GPU_PLL_48M);
00061     Sleep(10);
00062 
00063     /* Do a core reset for safer side */
00064     HostCommand( FT_GPU_CORE_RESET);
00065     Sleep(500);
00066     //Read Register ID to check if FT800 is ready.
00067     chipid = Rd8(  REG_ID);
00068 //  chipid = Rd8(0x0C0000);
00069     pc.printf("ID%08X\n", chipid);
00070     while(chipid != 0x7C)
00071 
00072 
00073     // Speed up
00074     _spi.frequency(20000000);           // 20 Mhz SPI clock DC
00075 //  _spi.frequency(12000000);           // 12 Mhz SPI clock
00076     /* Configuration of LCD display */
00077     DispHCycle = my_DispHCycle;
00078     Wr16(  REG_HCYCLE, DispHCycle);
00079     DispHOffset = my_DispHOffset;
00080     Wr16(  REG_HOFFSET, DispHOffset);
00081     DispWidth = my_DispWidth;
00082     Wr16(  REG_HSIZE, DispWidth);
00083     DispHSync0 = my_DispHSync0;
00084     Wr16(  REG_HSYNC0, DispHSync0);
00085     DispHSync1 = my_DispHSync1;
00086     Wr16(  REG_HSYNC1, DispHSync1);
00087     DispVCycle = my_DispVCycle;
00088     Wr16(  REG_VCYCLE, DispVCycle);
00089     DispVOffset = my_DispVOffset;
00090     Wr16(  REG_VOFFSET, DispVOffset);
00091     DispHeight = my_DispHeight;
00092     Wr16(  REG_VSIZE, DispHeight);
00093     DispVSync0 = my_DispVSync0;
00094     Wr16(  REG_VSYNC0, DispVSync0);
00095     DispVSync1 = my_DispVSync1;
00096     Wr16(  REG_VSYNC1, DispVSync1);
00097     DispSwizzle = my_DispSwizzle;
00098     Wr8(  REG_SWIZZLE, DispSwizzle);
00099     DispPCLKPol = my_DispPCLKPol;
00100     Wr8(  REG_PCLK_POL, DispPCLKPol);
00101     Wr8(  REG_CSPREAD, 0);
00102     DispPCLK = my_DispPCLK;
00103     Wr8(  REG_PCLK, DispPCLK);//after this display is visible on the LCD
00104 
00105     Wr16(  REG_PWM_HZ, 10000);
00106 
00107 #ifdef Inv_Backlite               // turn on backlite
00108     Wr16(  REG_PWM_DUTY, 0);
00109 #else
00110     Wr16(  REG_PWM_DUTY, 100);
00111 #endif
00112 
00113     Wr8(  REG_GPIO_DIR,0x82);  //| Rd8( REG_GPIO_DIR));
00114     Wr8(  REG_GPIO,0x080);     //| Rd8( REG_GPIO));
00115 
00116     Wr32(  RAM_DL, CLEAR(1,1,1));
00117     Wr32(  RAM_DL+4, DISPLAY());
00118     Wr32(  REG_DLSWAP,1);
00119 
00120     Wr16(  REG_PCLK, DispPCLK);
00121 
00122     /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
00123     Wr16(  REG_TOUCH_RZTHRESH,2400);
00124 
00125 }
00126 
00127 
00128 
00129 /* API to initialize the SPI interface */
00130 ft_bool_t  FT800::Init()
00131 {
00132     // is done in constructor
00133     return 1;
00134 }
00135 
00136 
00137 ft_bool_t  FT800::Open()
00138 {
00139     cmd_fifo_wp = dl_buff_wp = 0;
00140     status = OPENED;
00141     return 1;
00142 }
00143 
00144 ft_void_t  FT800::Close( )
00145 {
00146     status = CLOSED;
00147 }
00148 
00149 ft_void_t FT800::DeInit()
00150 {
00151 
00152 }
00153 
00154 /*The APIs for reading/writing transfer continuously only with small buffer system*/
00155 ft_void_t  FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
00156 {
00157     if (FT_GPU_READ == rw){
00158         _ss = 0;       // cs low
00159         _spi.write(addr >> 16);
00160         _spi.write(addr >> 8);
00161         _spi.write(addr & 0xff);
00162         _spi.write(0); //Dummy Read Byte
00163         status = READING;
00164     }else{
00165         _ss = 0;       // cs low
00166         _spi.write(0x80 | (addr >> 16));
00167         _spi.write(addr >> 8);
00168         _spi.write(addr & 0xff);
00169         status = WRITING;
00170     }
00171 }
00172 
00173 
00174 /*The APIs for writing transfer continuously only*/
00175 ft_void_t  FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
00176 {
00177     StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
00178 }
00179 
00180 ft_uint8_t  FT800::TransferString( const ft_char8_t *string)
00181 {
00182     ft_uint16_t length = strlen(string);
00183     while(length --){
00184        Transfer8( *string);
00185        string ++;
00186     }
00187     //Append one null as ending flag
00188     Transfer8( 0);
00189     return(1);
00190 }
00191 
00192 
00193 ft_uint8_t  FT800::Transfer8( ft_uint8_t value)
00194 {
00195         return _spi.write(value);
00196 }
00197 
00198 
00199 ft_uint16_t  FT800::Transfer16( ft_uint16_t value)
00200 {
00201     ft_uint16_t retVal = 0;
00202 
00203         if (status == WRITING){
00204         Transfer8( value & 0xFF);//LSB first
00205         Transfer8( (value >> 8) & 0xFF);
00206     }else{
00207         retVal = Transfer8( 0);
00208         retVal |= (ft_uint16_t)Transfer8( 0) << 8;
00209     }
00210 
00211     return retVal;
00212 }
00213 
00214 ft_uint32_t  FT800::Transfer32( ft_uint32_t value)
00215 {
00216     ft_uint32_t retVal = 0;
00217     if (status == WRITING){
00218         Transfer16( value & 0xFFFF);//LSB first
00219         Transfer16( (value >> 16) & 0xFFFF);
00220     }else{
00221         retVal = Transfer16( 0);
00222         retVal |= (ft_uint32_t)Transfer16( 0) << 16;
00223     }
00224     return retVal;
00225 }
00226 
00227 ft_void_t   FT800::EndTransfer( )
00228 {
00229     _ss = 1;
00230     status = OPENED;
00231 }
00232 
00233 
00234 ft_uint8_t  FT800::Rd8( ft_uint32_t addr)
00235 {
00236     ft_uint8_t value;
00237     StartTransfer( FT_GPU_READ,addr);
00238     value = Transfer8( 0);
00239     EndTransfer( );
00240     return value;
00241 }
00242 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
00243 {
00244     ft_uint16_t value;
00245     StartTransfer( FT_GPU_READ,addr);
00246     value = Transfer16( 0);
00247     EndTransfer( );
00248     return value;
00249 }
00250 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
00251 {
00252     ft_uint32_t value;
00253     StartTransfer( FT_GPU_READ,addr);
00254     value = Transfer32( 0);
00255     EndTransfer( );
00256     return value;
00257 }
00258 
00259 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
00260 {
00261     StartTransfer( FT_GPU_WRITE,addr);
00262     Transfer8( v);
00263     EndTransfer( );
00264 }
00265 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
00266 {
00267     StartTransfer( FT_GPU_WRITE,addr);
00268     Transfer16( v);
00269     EndTransfer( );
00270 }
00271 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
00272 {
00273     StartTransfer( FT_GPU_WRITE,addr);
00274     Transfer32( v);
00275     EndTransfer( );
00276 }
00277 
00278 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
00279 {
00280   _ss = 0;
00281   _spi.write(cmd);
00282   _spi.write(0);
00283   _spi.write(0);
00284   _ss = 1;
00285 }
00286 
00287 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
00288 {
00289    HostCommand( pllsource);
00290 }
00291 
00292 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
00293 {
00294    HostCommand( freq);
00295 }
00296 
00297 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
00298 {
00299    HostCommand( pwrmode);
00300 }
00301 
00302 ft_void_t FT800::CoreReset( )
00303 {
00304    HostCommand( 0x68);
00305 }
00306 
00307 
00308 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
00309 {
00310      cmd_fifo_wp  = ( cmd_fifo_wp + count) & 4095;
00311     //4 byte alignment
00312      cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
00313     Wr16( REG_CMD_WRITE, cmd_fifo_wp);
00314 }
00315 
00316 
00317 ft_uint16_t FT800::fifo_Freespace( )
00318 {
00319     ft_uint16_t fullness,retval;
00320 
00321     fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
00322     retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
00323     return (retval);
00324 }
00325 
00326 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
00327 {
00328     ft_uint32_t length =0, SizeTransfered = 0;
00329 
00330 #define MAX_CMD_FIFO_TRANSFER   fifo_Freespace( )
00331     do {
00332         length = count;
00333         if (length > MAX_CMD_FIFO_TRANSFER){
00334             length = MAX_CMD_FIFO_TRANSFER;
00335         }
00336                 CheckCmdBuffer( length);
00337 
00338                 StartCmdTransfer( FT_GPU_WRITE,length);
00339 
00340                 SizeTransfered = 0;
00341         while (length--) {
00342                     Transfer8( *buffer);
00343                     buffer++;
00344                     SizeTransfered ++;
00345         }
00346                 length = SizeTransfered;
00347 
00348         EndTransfer( );
00349         Updatecmdfifo( length);
00350 
00351         WaitCmdfifo_empty( );
00352 
00353         count -= length;
00354     }while (count > 0);
00355 }
00356 
00357 
00358 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
00359 {
00360     ft_uint32_t length =0, SizeTransfered = 0;
00361 
00362 #define MAX_CMD_FIFO_TRANSFER   fifo_Freespace( )
00363     do {
00364         length = count;
00365         if (length > MAX_CMD_FIFO_TRANSFER){
00366             length = MAX_CMD_FIFO_TRANSFER;
00367         }
00368                 CheckCmdBuffer( length);
00369 
00370                 StartCmdTransfer( FT_GPU_WRITE,length);
00371 
00372 
00373                 SizeTransfered = 0;
00374         while (length--) {
00375                     Transfer8( ft_pgm_read_byte_near(buffer));
00376             buffer++;
00377                     SizeTransfered ++;
00378         }
00379                 length = SizeTransfered;
00380 
00381                 EndTransfer( );
00382         Updatecmdfifo( length);
00383 
00384         WaitCmdfifo_empty( );
00385 
00386         count -= length;
00387     }while (count > 0);
00388 }
00389 
00390 
00391 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
00392 {
00393    ft_uint16_t getfreespace;
00394    do{
00395         getfreespace = fifo_Freespace( );
00396    }while(getfreespace < count);
00397 }
00398 
00399 ft_void_t FT800::WaitCmdfifo_empty( )
00400 {
00401    while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
00402 
00403     cmd_fifo_wp = Rd16( REG_CMD_WRITE);
00404 }
00405 
00406 ft_void_t FT800::WaitLogo_Finish( )
00407 {
00408     ft_int16_t cmdrdptr,cmdwrptr;
00409 
00410     do{
00411          cmdrdptr = Rd16( REG_CMD_READ);
00412          cmdwrptr = Rd16( REG_CMD_WRITE);
00413     }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
00414      cmd_fifo_wp = 0;
00415 }
00416 
00417 
00418 ft_void_t FT800::ResetCmdFifo( )
00419 {
00420     cmd_fifo_wp = 0;
00421 }
00422 
00423 
00424 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
00425 {
00426          CheckCmdBuffer( sizeof(cmd));
00427 
00428          Wr32( RAM_CMD +  cmd_fifo_wp,cmd);
00429 
00430          Updatecmdfifo( sizeof(cmd));
00431 }
00432 
00433 
00434 ft_void_t FT800::ResetDLBuffer( )
00435 {
00436             dl_buff_wp = 0;
00437 }
00438 
00439 /* Toggle PD_N pin of FT800 board for a power cycle*/
00440 ft_void_t FT800::Powercycle(  ft_bool_t up)
00441 {
00442     if (up)
00443     {
00444              //Toggle PD_N from low to high for power up switch
00445             _pd = 0;
00446             Sleep(20);
00447 
00448             _pd = 1;
00449             Sleep(20);
00450     }else
00451     {
00452              //Toggle PD_N from high to low for power down switch
00453             _pd = 1;
00454             Sleep(20);
00455 
00456             _pd = 0;
00457             Sleep(20);
00458     }
00459 }
00460 
00461 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
00462 {
00463     //ft_uint32_t SizeTransfered = 0;
00464 
00465     StartTransfer( FT_GPU_WRITE,addr);
00466 
00467     while (length--) {
00468             Transfer8( ft_pgm_read_byte_near(buffer));
00469         buffer++;
00470     }
00471 
00472     EndTransfer( );
00473 }
00474 
00475 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
00476 {
00477     //ft_uint32_t SizeTransfered = 0;
00478 
00479     StartTransfer( FT_GPU_WRITE,addr);
00480 
00481     while (length--) {
00482             Transfer8( *buffer);
00483         buffer++;
00484     }
00485 
00486     EndTransfer( );
00487 }
00488 
00489 
00490 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
00491 {
00492     //ft_uint32_t SizeTransfered = 0;
00493 
00494     StartTransfer( FT_GPU_READ,addr);
00495 
00496     while (length--) {
00497        *buffer = Transfer8( 0);
00498        buffer++;
00499     }
00500 
00501     EndTransfer( );
00502 }
00503 
00504 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
00505 {
00506     ft_int16_t Length;
00507     ft_char8_t *pdst,charval;
00508     ft_int32_t CurrVal = value,tmpval,i;
00509     ft_char8_t tmparray[16],idx = 0;
00510 
00511     Length = strlen(pSrc);
00512     pdst = pSrc + Length;
00513 
00514     if(0 == value)
00515     {
00516         *pdst++ = '0';
00517         *pdst++ = '\0';
00518         return 0;
00519     }
00520 
00521     if(CurrVal < 0)
00522     {
00523         *pdst++ = '-';
00524         CurrVal = - CurrVal;
00525     }
00526     /* insert the value */
00527     while(CurrVal > 0){
00528         tmpval = CurrVal;
00529         CurrVal /= 10;
00530         tmpval = tmpval - CurrVal*10;
00531         charval = '0' + tmpval;
00532         tmparray[idx++] = charval;
00533     }
00534 
00535     for(i=0;i<idx;i++)
00536     {
00537         *pdst++ = tmparray[idx - i - 1];
00538     }
00539     *pdst++ = '\0';
00540 
00541     return 0;
00542 }
00543 
00544 
00545 ft_void_t FT800::Sleep(ft_uint16_t ms)
00546 {
00547     wait_ms(ms);
00548 }
00549 
00550 ft_void_t FT800::Sound_ON(){
00551      Wr8(  REG_GPIO, 0x02 | Rd8( REG_GPIO));
00552 }
00553 
00554 ft_void_t FT800::Sound_OFF(){
00555      Wr8(  REG_GPIO, 0xFD & Rd8( REG_GPIO));
00556 }
00557 
00558 
00559 
00560