TeamGyro / mbed-rtos

OS2

Dependents:   GYRO_MPU6050 Bluetooth_Powered_Multimeter_Using_STM32F429_and_RTOS fyp

rtx/TARGET_CORTEX_M/rt_HAL_CM.h@0:a7c449cd2d5a, 2020-02-03 (annotated)

Committer:
guilhemMBED
Date:
Mon Feb 03 13:41:14 2020 +0000
Revision:
0:a7c449cd2d5a
previous version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
guilhemMBED 0:a7c449cd2d5a 1
guilhemMBED 0:a7c449cd2d5a 2 /** \addtogroup rtos */
guilhemMBED 0:a7c449cd2d5a 3 /** @{*/
guilhemMBED 0:a7c449cd2d5a 4 /*----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 5 * CMSIS-RTOS - RTX
guilhemMBED 0:a7c449cd2d5a 6 *----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 7 * Name: RT_HAL_CM.H
guilhemMBED 0:a7c449cd2d5a 8 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
guilhemMBED 0:a7c449cd2d5a 9 * Rev.: V4.79
guilhemMBED 0:a7c449cd2d5a 10 *----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 11 *
guilhemMBED 0:a7c449cd2d5a 12 * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
guilhemMBED 0:a7c449cd2d5a 13 * All rights reserved.
guilhemMBED 0:a7c449cd2d5a 14 * Redistribution and use in source and binary forms, with or without
guilhemMBED 0:a7c449cd2d5a 15 * modification, are permitted provided that the following conditions are met:
guilhemMBED 0:a7c449cd2d5a 16 * - Redistributions of source code must retain the above copyright
guilhemMBED 0:a7c449cd2d5a 17 * notice, this list of conditions and the following disclaimer.
guilhemMBED 0:a7c449cd2d5a 18 * - Redistributions in binary form must reproduce the above copyright
guilhemMBED 0:a7c449cd2d5a 19 * notice, this list of conditions and the following disclaimer in the
guilhemMBED 0:a7c449cd2d5a 20 * documentation and/or other materials provided with the distribution.
guilhemMBED 0:a7c449cd2d5a 21 * - Neither the name of ARM nor the names of its contributors may be used
guilhemMBED 0:a7c449cd2d5a 22 * to endorse or promote products derived from this software without
guilhemMBED 0:a7c449cd2d5a 23 * specific prior written permission.
guilhemMBED 0:a7c449cd2d5a 24 *
guilhemMBED 0:a7c449cd2d5a 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
guilhemMBED 0:a7c449cd2d5a 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
guilhemMBED 0:a7c449cd2d5a 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
guilhemMBED 0:a7c449cd2d5a 28 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
guilhemMBED 0:a7c449cd2d5a 29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
guilhemMBED 0:a7c449cd2d5a 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
guilhemMBED 0:a7c449cd2d5a 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
guilhemMBED 0:a7c449cd2d5a 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
guilhemMBED 0:a7c449cd2d5a 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
guilhemMBED 0:a7c449cd2d5a 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
guilhemMBED 0:a7c449cd2d5a 35 * POSSIBILITY OF SUCH DAMAGE.
guilhemMBED 0:a7c449cd2d5a 36 *---------------------------------------------------------------------------*/
guilhemMBED 0:a7c449cd2d5a 37
guilhemMBED 0:a7c449cd2d5a 38 /* Definitions */
guilhemMBED 0:a7c449cd2d5a 39 #define INITIAL_xPSR 0x01000000U
guilhemMBED 0:a7c449cd2d5a 40 #define DEMCR_TRCENA 0x01000000U
guilhemMBED 0:a7c449cd2d5a 41 #define ITM_ITMENA 0x00000001U
guilhemMBED 0:a7c449cd2d5a 42 #define MAGIC_WORD 0xE25A2EA5U
guilhemMBED 0:a7c449cd2d5a 43 #define MAGIC_PATTERN 0xCCCCCCCCU
guilhemMBED 0:a7c449cd2d5a 44
guilhemMBED 0:a7c449cd2d5a 45 #if defined (__CC_ARM) /* ARM Compiler */
guilhemMBED 0:a7c449cd2d5a 46
guilhemMBED 0:a7c449cd2d5a 47 #if ((defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) && !defined(NO_EXCLUSIVE_ACCESS))
guilhemMBED 0:a7c449cd2d5a 48 #define __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 49 #else
guilhemMBED 0:a7c449cd2d5a 50 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 51 #endif
guilhemMBED 0:a7c449cd2d5a 52
guilhemMBED 0:a7c449cd2d5a 53 /* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
guilhemMBED 0:a7c449cd2d5a 54 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 55 #pragma diag_suppress 3731
guilhemMBED 0:a7c449cd2d5a 56 #endif
guilhemMBED 0:a7c449cd2d5a 57
guilhemMBED 0:a7c449cd2d5a 58 #ifndef __CMSIS_GENERIC
guilhemMBED 0:a7c449cd2d5a 59
guilhemMBED 0:a7c449cd2d5a 60 __attribute__((always_inline)) static inline U32 __get_PRIMASK(void)
guilhemMBED 0:a7c449cd2d5a 61 {
guilhemMBED 0:a7c449cd2d5a 62 register U32 primask __asm("primask");
guilhemMBED 0:a7c449cd2d5a 63 return primask;
guilhemMBED 0:a7c449cd2d5a 64 }
guilhemMBED 0:a7c449cd2d5a 65
guilhemMBED 0:a7c449cd2d5a 66 #define __DMB() do {\
guilhemMBED 0:a7c449cd2d5a 67 __schedule_barrier();\
guilhemMBED 0:a7c449cd2d5a 68 __dmb(0xF);\
guilhemMBED 0:a7c449cd2d5a 69 __schedule_barrier();\
guilhemMBED 0:a7c449cd2d5a 70 } while (0)
guilhemMBED 0:a7c449cd2d5a 71
guilhemMBED 0:a7c449cd2d5a 72 #endif
guilhemMBED 0:a7c449cd2d5a 73
guilhemMBED 0:a7c449cd2d5a 74 #elif defined (__GNUC__) /* GNU Compiler */
guilhemMBED 0:a7c449cd2d5a 75
guilhemMBED 0:a7c449cd2d5a 76 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 77
guilhemMBED 0:a7c449cd2d5a 78 #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
guilhemMBED 0:a7c449cd2d5a 79 #define __TARGET_ARCH_6S_M
guilhemMBED 0:a7c449cd2d5a 80 #endif
guilhemMBED 0:a7c449cd2d5a 81
guilhemMBED 0:a7c449cd2d5a 82 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
guilhemMBED 0:a7c449cd2d5a 83 #define __TARGET_FPU_VFP
guilhemMBED 0:a7c449cd2d5a 84 #endif
guilhemMBED 0:a7c449cd2d5a 85
guilhemMBED 0:a7c449cd2d5a 86 #define __inline inline
guilhemMBED 0:a7c449cd2d5a 87 #define __weak __attribute__((weak))
guilhemMBED 0:a7c449cd2d5a 88
guilhemMBED 0:a7c449cd2d5a 89 #ifndef __CMSIS_GENERIC
guilhemMBED 0:a7c449cd2d5a 90
guilhemMBED 0:a7c449cd2d5a 91 __attribute__((always_inline)) static inline U32 __get_PRIMASK(void)
guilhemMBED 0:a7c449cd2d5a 92 {
guilhemMBED 0:a7c449cd2d5a 93 U32 result;
guilhemMBED 0:a7c449cd2d5a 94
guilhemMBED 0:a7c449cd2d5a 95 __asm volatile ("mrs %0, primask" : "=r" (result));
guilhemMBED 0:a7c449cd2d5a 96 return result;
guilhemMBED 0:a7c449cd2d5a 97 }
guilhemMBED 0:a7c449cd2d5a 98
guilhemMBED 0:a7c449cd2d5a 99 __attribute__((always_inline)) static inline void __enable_irq(void)
guilhemMBED 0:a7c449cd2d5a 100 {
guilhemMBED 0:a7c449cd2d5a 101 __asm volatile ("cpsie i");
guilhemMBED 0:a7c449cd2d5a 102 }
guilhemMBED 0:a7c449cd2d5a 103
guilhemMBED 0:a7c449cd2d5a 104 __attribute__((always_inline)) static inline U32 __disable_irq(void)
guilhemMBED 0:a7c449cd2d5a 105 {
guilhemMBED 0:a7c449cd2d5a 106 U32 result;
guilhemMBED 0:a7c449cd2d5a 107
guilhemMBED 0:a7c449cd2d5a 108 __asm volatile ("mrs %0, primask" : "=r" (result));
guilhemMBED 0:a7c449cd2d5a 109 __asm volatile ("cpsid i");
guilhemMBED 0:a7c449cd2d5a 110 return(result & 1);
guilhemMBED 0:a7c449cd2d5a 111 }
guilhemMBED 0:a7c449cd2d5a 112
guilhemMBED 0:a7c449cd2d5a 113 __attribute__((always_inline)) static inline void __DMB(void)
guilhemMBED 0:a7c449cd2d5a 114 {
guilhemMBED 0:a7c449cd2d5a 115 __asm volatile ("dmb 0xF":::"memory");
guilhemMBED 0:a7c449cd2d5a 116 }
guilhemMBED 0:a7c449cd2d5a 117
guilhemMBED 0:a7c449cd2d5a 118 #endif
guilhemMBED 0:a7c449cd2d5a 119
guilhemMBED 0:a7c449cd2d5a 120 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
guilhemMBED 0:a7c449cd2d5a 121 {
guilhemMBED 0:a7c449cd2d5a 122 U8 result;
guilhemMBED 0:a7c449cd2d5a 123
guilhemMBED 0:a7c449cd2d5a 124 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
guilhemMBED 0:a7c449cd2d5a 125 return(result);
guilhemMBED 0:a7c449cd2d5a 126 }
guilhemMBED 0:a7c449cd2d5a 127
guilhemMBED 0:a7c449cd2d5a 128 #elif defined (__ICCARM__) /* IAR Compiler */
guilhemMBED 0:a7c449cd2d5a 129
guilhemMBED 0:a7c449cd2d5a 130 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 131
guilhemMBED 0:a7c449cd2d5a 132 #if (__CORE__ == __ARM6M__)
guilhemMBED 0:a7c449cd2d5a 133 #define __TARGET_ARCH_6S_M 1
guilhemMBED 0:a7c449cd2d5a 134 #endif
guilhemMBED 0:a7c449cd2d5a 135
guilhemMBED 0:a7c449cd2d5a 136 #if defined __ARMVFP__
guilhemMBED 0:a7c449cd2d5a 137 #define __TARGET_FPU_VFP 1
guilhemMBED 0:a7c449cd2d5a 138 #endif
guilhemMBED 0:a7c449cd2d5a 139
guilhemMBED 0:a7c449cd2d5a 140 #define __inline inline
guilhemMBED 0:a7c449cd2d5a 141
guilhemMBED 0:a7c449cd2d5a 142 #ifndef __CMSIS_GENERIC
guilhemMBED 0:a7c449cd2d5a 143
guilhemMBED 0:a7c449cd2d5a 144 static inline U32 __get_PRIMASK(void)
guilhemMBED 0:a7c449cd2d5a 145 {
guilhemMBED 0:a7c449cd2d5a 146 U32 result;
guilhemMBED 0:a7c449cd2d5a 147
guilhemMBED 0:a7c449cd2d5a 148 __asm volatile ("mrs %0, primask" : "=r" (result));
guilhemMBED 0:a7c449cd2d5a 149 return result;
guilhemMBED 0:a7c449cd2d5a 150 }
guilhemMBED 0:a7c449cd2d5a 151
guilhemMBED 0:a7c449cd2d5a 152 static inline void __enable_irq(void)
guilhemMBED 0:a7c449cd2d5a 153 {
guilhemMBED 0:a7c449cd2d5a 154 __asm volatile ("cpsie i");
guilhemMBED 0:a7c449cd2d5a 155 }
guilhemMBED 0:a7c449cd2d5a 156
guilhemMBED 0:a7c449cd2d5a 157 static inline U32 __disable_irq(void)
guilhemMBED 0:a7c449cd2d5a 158 {
guilhemMBED 0:a7c449cd2d5a 159 U32 result;
guilhemMBED 0:a7c449cd2d5a 160
guilhemMBED 0:a7c449cd2d5a 161 __asm volatile ("mrs %0, primask" : "=r" (result));
guilhemMBED 0:a7c449cd2d5a 162 __asm volatile ("cpsid i");
guilhemMBED 0:a7c449cd2d5a 163 return(result & 1);
guilhemMBED 0:a7c449cd2d5a 164 }
guilhemMBED 0:a7c449cd2d5a 165
guilhemMBED 0:a7c449cd2d5a 166 #endif
guilhemMBED 0:a7c449cd2d5a 167
guilhemMBED 0:a7c449cd2d5a 168 static inline U8 __clz(U32 value)
guilhemMBED 0:a7c449cd2d5a 169 {
guilhemMBED 0:a7c449cd2d5a 170 U8 result;
guilhemMBED 0:a7c449cd2d5a 171
guilhemMBED 0:a7c449cd2d5a 172 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
guilhemMBED 0:a7c449cd2d5a 173 return(result);
guilhemMBED 0:a7c449cd2d5a 174 }
guilhemMBED 0:a7c449cd2d5a 175
guilhemMBED 0:a7c449cd2d5a 176 #endif
guilhemMBED 0:a7c449cd2d5a 177
guilhemMBED 0:a7c449cd2d5a 178 /* NVIC registers */
guilhemMBED 0:a7c449cd2d5a 179 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010U))
guilhemMBED 0:a7c449cd2d5a 180 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014U))
guilhemMBED 0:a7c449cd2d5a 181 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018U))
guilhemMBED 0:a7c449cd2d5a 182 #define NVIC_ISER ((volatile U32 *)0xE000E100U)
guilhemMBED 0:a7c449cd2d5a 183 #define NVIC_ICER ((volatile U32 *)0xE000E180U)
guilhemMBED 0:a7c449cd2d5a 184 #if defined(__TARGET_ARCH_6S_M)
guilhemMBED 0:a7c449cd2d5a 185 #define NVIC_IP ((volatile U32 *)0xE000E400U)
guilhemMBED 0:a7c449cd2d5a 186 #else
guilhemMBED 0:a7c449cd2d5a 187 #define NVIC_IP ((volatile U8 *)0xE000E400U)
guilhemMBED 0:a7c449cd2d5a 188 #endif
guilhemMBED 0:a7c449cd2d5a 189 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04U))
guilhemMBED 0:a7c449cd2d5a 190 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0CU))
guilhemMBED 0:a7c449cd2d5a 191 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1CU))
guilhemMBED 0:a7c449cd2d5a 192 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20U))
guilhemMBED 0:a7c449cd2d5a 193
guilhemMBED 0:a7c449cd2d5a 194 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1UL<<28)
guilhemMBED 0:a7c449cd2d5a 195 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & 5U)
guilhemMBED 0:a7c449cd2d5a 196 #define OS_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_PENDING) << 25
guilhemMBED 0:a7c449cd2d5a 197 #define OS_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | (U8)(p<<2)) << 26
guilhemMBED 0:a7c449cd2d5a 198 #define OS_LOCK() NVIC_ST_CTRL = 0x0005U
guilhemMBED 0:a7c449cd2d5a 199 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007U
guilhemMBED 0:a7c449cd2d5a 200
guilhemMBED 0:a7c449cd2d5a 201 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1U)
guilhemMBED 0:a7c449cd2d5a 202 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_X_PENDING) << 27
guilhemMBED 0:a7c449cd2d5a 203 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | p) << 28
guilhemMBED 0:a7c449cd2d5a 204 #if defined(__TARGET_ARCH_6S_M)
guilhemMBED 0:a7c449cd2d5a 205 #define OS_X_INIT(n) NVIC_IP[n>>2] |= (U32)0xFFU << ((n & 0x03U) << 3); \
guilhemMBED 0:a7c449cd2d5a 206 NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
guilhemMBED 0:a7c449cd2d5a 207 #else
guilhemMBED 0:a7c449cd2d5a 208 #define OS_X_INIT(n) NVIC_IP[n] = 0xFFU; \
guilhemMBED 0:a7c449cd2d5a 209 NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
guilhemMBED 0:a7c449cd2d5a 210 #endif
guilhemMBED 0:a7c449cd2d5a 211 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = (U32)1U << (n & 0x1FU)
guilhemMBED 0:a7c449cd2d5a 212 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
guilhemMBED 0:a7c449cd2d5a 213
guilhemMBED 0:a7c449cd2d5a 214 /* Core Debug registers */
guilhemMBED 0:a7c449cd2d5a 215 #define DEMCR (*((volatile U32 *)0xE000EDFCU))
guilhemMBED 0:a7c449cd2d5a 216
guilhemMBED 0:a7c449cd2d5a 217 /* ITM registers */
guilhemMBED 0:a7c449cd2d5a 218 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80U))
guilhemMBED 0:a7c449cd2d5a 219 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00U))
guilhemMBED 0:a7c449cd2d5a 220 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078U))
guilhemMBED 0:a7c449cd2d5a 221 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007CU))
guilhemMBED 0:a7c449cd2d5a 222 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007CU))
guilhemMBED 0:a7c449cd2d5a 223 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007CU))
guilhemMBED 0:a7c449cd2d5a 224
guilhemMBED 0:a7c449cd2d5a 225 /* Variables */
guilhemMBED 0:a7c449cd2d5a 226 extern BIT dbg_msg;
guilhemMBED 0:a7c449cd2d5a 227
guilhemMBED 0:a7c449cd2d5a 228 /* Functions */
guilhemMBED 0:a7c449cd2d5a 229 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 230 #define rt_inc(p) while(__strex((__ldrex(p)+1U),p))
guilhemMBED 0:a7c449cd2d5a 231 #define rt_dec(p) while(__strex((__ldrex(p)-1U),p))
guilhemMBED 0:a7c449cd2d5a 232 #else
guilhemMBED 0:a7c449cd2d5a 233 #define rt_inc(p) do {\
guilhemMBED 0:a7c449cd2d5a 234 U32 primask = __get_PRIMASK();\
guilhemMBED 0:a7c449cd2d5a 235 __disable_irq();\
guilhemMBED 0:a7c449cd2d5a 236 (*p)++;\
guilhemMBED 0:a7c449cd2d5a 237 if (!primask) {\
guilhemMBED 0:a7c449cd2d5a 238 __enable_irq();\
guilhemMBED 0:a7c449cd2d5a 239 }\
guilhemMBED 0:a7c449cd2d5a 240 } while (0)
guilhemMBED 0:a7c449cd2d5a 241 #define rt_dec(p) do {\
guilhemMBED 0:a7c449cd2d5a 242 U32 primask = __get_PRIMASK();\
guilhemMBED 0:a7c449cd2d5a 243 __disable_irq();\
guilhemMBED 0:a7c449cd2d5a 244 (*p)--;\
guilhemMBED 0:a7c449cd2d5a 245 if (!primask) {\
guilhemMBED 0:a7c449cd2d5a 246 __enable_irq();\
guilhemMBED 0:a7c449cd2d5a 247 }\
guilhemMBED 0:a7c449cd2d5a 248 } while (0)
guilhemMBED 0:a7c449cd2d5a 249 #endif
guilhemMBED 0:a7c449cd2d5a 250
guilhemMBED 0:a7c449cd2d5a 251 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
guilhemMBED 0:a7c449cd2d5a 252 U32 cnt,c2;
guilhemMBED 0:a7c449cd2d5a 253 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 254 do {
guilhemMBED 0:a7c449cd2d5a 255 if ((cnt = __ldrex(count)) == size) {
guilhemMBED 0:a7c449cd2d5a 256 __clrex();
guilhemMBED 0:a7c449cd2d5a 257 return (cnt); }
guilhemMBED 0:a7c449cd2d5a 258 } while (__strex(cnt+1U, count));
guilhemMBED 0:a7c449cd2d5a 259 do {
guilhemMBED 0:a7c449cd2d5a 260 c2 = (cnt = __ldrex(first)) + 1U;
guilhemMBED 0:a7c449cd2d5a 261 if (c2 == size) { c2 = 0U; }
guilhemMBED 0:a7c449cd2d5a 262 } while (__strex(c2, first));
guilhemMBED 0:a7c449cd2d5a 263 #else
guilhemMBED 0:a7c449cd2d5a 264 U32 primask = __get_PRIMASK();
guilhemMBED 0:a7c449cd2d5a 265 __disable_irq();
guilhemMBED 0:a7c449cd2d5a 266 if ((cnt = *count) < size) {
guilhemMBED 0:a7c449cd2d5a 267 *count = (U8)(cnt+1U);
guilhemMBED 0:a7c449cd2d5a 268 c2 = (cnt = *first) + 1U;
guilhemMBED 0:a7c449cd2d5a 269 if (c2 == size) { c2 = 0U; }
guilhemMBED 0:a7c449cd2d5a 270 *first = (U8)c2;
guilhemMBED 0:a7c449cd2d5a 271 }
guilhemMBED 0:a7c449cd2d5a 272 if (!primask) {
guilhemMBED 0:a7c449cd2d5a 273 __enable_irq ();
guilhemMBED 0:a7c449cd2d5a 274 }
guilhemMBED 0:a7c449cd2d5a 275 #endif
guilhemMBED 0:a7c449cd2d5a 276 return (cnt);
guilhemMBED 0:a7c449cd2d5a 277 }
guilhemMBED 0:a7c449cd2d5a 278
guilhemMBED 0:a7c449cd2d5a 279 __inline static void rt_systick_init (void) {
guilhemMBED 0:a7c449cd2d5a 280 NVIC_ST_RELOAD = os_trv;
guilhemMBED 0:a7c449cd2d5a 281 NVIC_ST_CURRENT = 0U;
guilhemMBED 0:a7c449cd2d5a 282 NVIC_ST_CTRL = 0x0007U;
guilhemMBED 0:a7c449cd2d5a 283 NVIC_SYS_PRI3 |= 0xFF000000U;
guilhemMBED 0:a7c449cd2d5a 284 }
guilhemMBED 0:a7c449cd2d5a 285
guilhemMBED 0:a7c449cd2d5a 286 __inline static U32 rt_systick_val (void) {
guilhemMBED 0:a7c449cd2d5a 287 return (os_trv - NVIC_ST_CURRENT);
guilhemMBED 0:a7c449cd2d5a 288 }
guilhemMBED 0:a7c449cd2d5a 289
guilhemMBED 0:a7c449cd2d5a 290 __inline static U32 rt_systick_ovf (void) {
guilhemMBED 0:a7c449cd2d5a 291 return ((NVIC_INT_CTRL >> 26) & 1U);
guilhemMBED 0:a7c449cd2d5a 292 }
guilhemMBED 0:a7c449cd2d5a 293
guilhemMBED 0:a7c449cd2d5a 294 __inline static void rt_svc_init (void) {
guilhemMBED 0:a7c449cd2d5a 295 #if !defined(__TARGET_ARCH_6S_M)
guilhemMBED 0:a7c449cd2d5a 296 U32 sh,prigroup;
guilhemMBED 0:a7c449cd2d5a 297 #endif
guilhemMBED 0:a7c449cd2d5a 298 NVIC_SYS_PRI3 |= 0x00FF0000U;
guilhemMBED 0:a7c449cd2d5a 299 #if defined(__TARGET_ARCH_6S_M)
guilhemMBED 0:a7c449cd2d5a 300 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000U;
guilhemMBED 0:a7c449cd2d5a 301 #else
guilhemMBED 0:a7c449cd2d5a 302 sh = 8U - __clz(~((NVIC_SYS_PRI3 << 8) & 0xFF000000U));
guilhemMBED 0:a7c449cd2d5a 303 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07U);
guilhemMBED 0:a7c449cd2d5a 304 if (prigroup >= sh) {
guilhemMBED 0:a7c449cd2d5a 305 sh = prigroup + 1U;
guilhemMBED 0:a7c449cd2d5a 306 }
guilhemMBED 0:a7c449cd2d5a 307
guilhemMBED 0:a7c449cd2d5a 308 /* Only change the SVCall priority if uVisor is not present. */
guilhemMBED 0:a7c449cd2d5a 309 #if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
guilhemMBED 0:a7c449cd2d5a 310 NVIC_SYS_PRI2 = ((0xFEFFFFFFU << sh) & 0xFF000000U) | (NVIC_SYS_PRI2 & 0x00FFFFFFU);
guilhemMBED 0:a7c449cd2d5a 311 #endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
guilhemMBED 0:a7c449cd2d5a 312 #endif
guilhemMBED 0:a7c449cd2d5a 313 }
guilhemMBED 0:a7c449cd2d5a 314
guilhemMBED 0:a7c449cd2d5a 315 extern void rt_set_PSP (U32 stack);
guilhemMBED 0:a7c449cd2d5a 316 extern U32 rt_get_PSP (void);
guilhemMBED 0:a7c449cd2d5a 317 extern void os_set_env (void);
guilhemMBED 0:a7c449cd2d5a 318 extern void *_alloc_box (void *box_mem);
guilhemMBED 0:a7c449cd2d5a 319 extern U32 _free_box (void *box_mem, void *box);
guilhemMBED 0:a7c449cd2d5a 320
guilhemMBED 0:a7c449cd2d5a 321 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
guilhemMBED 0:a7c449cd2d5a 322 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
guilhemMBED 0:a7c449cd2d5a 323 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
guilhemMBED 0:a7c449cd2d5a 324
guilhemMBED 0:a7c449cd2d5a 325 extern void dbg_init (void);
guilhemMBED 0:a7c449cd2d5a 326 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
guilhemMBED 0:a7c449cd2d5a 327 extern void dbg_task_switch (U32 task_id);
guilhemMBED 0:a7c449cd2d5a 328
guilhemMBED 0:a7c449cd2d5a 329 #ifdef DBG_MSG
guilhemMBED 0:a7c449cd2d5a 330 #define DBG_INIT() dbg_init()
guilhemMBED 0:a7c449cd2d5a 331 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
guilhemMBED 0:a7c449cd2d5a 332 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk!=os_tsk.run)) \
guilhemMBED 0:a7c449cd2d5a 333 dbg_task_switch(task_id)
guilhemMBED 0:a7c449cd2d5a 334 #else
guilhemMBED 0:a7c449cd2d5a 335 #define DBG_INIT()
guilhemMBED 0:a7c449cd2d5a 336 #define DBG_TASK_NOTIFY(p_tcb,create)
guilhemMBED 0:a7c449cd2d5a 337 #define DBG_TASK_SWITCH(task_id)
guilhemMBED 0:a7c449cd2d5a 338 #endif
guilhemMBED 0:a7c449cd2d5a 339
guilhemMBED 0:a7c449cd2d5a 340 /*----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 341 * end of file
guilhemMBED 0:a7c449cd2d5a 342 *---------------------------------------------------------------------------*/
guilhemMBED 0:a7c449cd2d5a 343
guilhemMBED 0:a7c449cd2d5a 344 /** @}*/