TeamGyro / mbed-rtos

OS2

Dependents:   GYRO_MPU6050 Bluetooth_Powered_Multimeter_Using_STM32F429_and_RTOS fyp

rtx/TARGET_CORTEX_A/rt_HAL_CM.h@0:a7c449cd2d5a, 2020-02-03 (annotated)

Committer:
guilhemMBED
Date:
Mon Feb 03 13:41:14 2020 +0000
Revision:
0:a7c449cd2d5a
previous version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
guilhemMBED 0:a7c449cd2d5a 1 /*----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 2 * RL-ARM - RTX
guilhemMBED 0:a7c449cd2d5a 3 *----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 4 * Name: RT_HAL_CM.H
guilhemMBED 0:a7c449cd2d5a 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
guilhemMBED 0:a7c449cd2d5a 6 * Rev.: V4.70
guilhemMBED 0:a7c449cd2d5a 7 *----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 8 *
guilhemMBED 0:a7c449cd2d5a 9 * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
guilhemMBED 0:a7c449cd2d5a 10 * All rights reserved.
guilhemMBED 0:a7c449cd2d5a 11 * Redistribution and use in source and binary forms, with or without
guilhemMBED 0:a7c449cd2d5a 12 * modification, are permitted provided that the following conditions are met:
guilhemMBED 0:a7c449cd2d5a 13 * - Redistributions of source code must retain the above copyright
guilhemMBED 0:a7c449cd2d5a 14 * notice, this list of conditions and the following disclaimer.
guilhemMBED 0:a7c449cd2d5a 15 * - Redistributions in binary form must reproduce the above copyright
guilhemMBED 0:a7c449cd2d5a 16 * notice, this list of conditions and the following disclaimer in the
guilhemMBED 0:a7c449cd2d5a 17 * documentation and/or other materials provided with the distribution.
guilhemMBED 0:a7c449cd2d5a 18 * - Neither the name of ARM nor the names of its contributors may be used
guilhemMBED 0:a7c449cd2d5a 19 * to endorse or promote products derived from this software without
guilhemMBED 0:a7c449cd2d5a 20 * specific prior written permission.
guilhemMBED 0:a7c449cd2d5a 21 *
guilhemMBED 0:a7c449cd2d5a 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
guilhemMBED 0:a7c449cd2d5a 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
guilhemMBED 0:a7c449cd2d5a 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
guilhemMBED 0:a7c449cd2d5a 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
guilhemMBED 0:a7c449cd2d5a 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
guilhemMBED 0:a7c449cd2d5a 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
guilhemMBED 0:a7c449cd2d5a 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
guilhemMBED 0:a7c449cd2d5a 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
guilhemMBED 0:a7c449cd2d5a 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
guilhemMBED 0:a7c449cd2d5a 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
guilhemMBED 0:a7c449cd2d5a 32 * POSSIBILITY OF SUCH DAMAGE.
guilhemMBED 0:a7c449cd2d5a 33 *---------------------------------------------------------------------------*/
guilhemMBED 0:a7c449cd2d5a 34
guilhemMBED 0:a7c449cd2d5a 35 /* Definitions */
guilhemMBED 0:a7c449cd2d5a 36 #define INITIAL_xPSR 0x01000000
guilhemMBED 0:a7c449cd2d5a 37 #define DEMCR_TRCENA 0x01000000
guilhemMBED 0:a7c449cd2d5a 38 #define ITM_ITMENA 0x00000001
guilhemMBED 0:a7c449cd2d5a 39 #define MAGIC_WORD 0xE25A2EA5
guilhemMBED 0:a7c449cd2d5a 40
guilhemMBED 0:a7c449cd2d5a 41 #if defined (__CC_ARM) /* ARM Compiler */
guilhemMBED 0:a7c449cd2d5a 42
guilhemMBED 0:a7c449cd2d5a 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !defined(NO_EXCLUSIVE_ACCESS))
guilhemMBED 0:a7c449cd2d5a 44 #define __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 45 #else
guilhemMBED 0:a7c449cd2d5a 46 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 47 #endif
guilhemMBED 0:a7c449cd2d5a 48
guilhemMBED 0:a7c449cd2d5a 49 /* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
guilhemMBED 0:a7c449cd2d5a 50 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 51 #pragma diag_suppress 3731
guilhemMBED 0:a7c449cd2d5a 52 #endif
guilhemMBED 0:a7c449cd2d5a 53
guilhemMBED 0:a7c449cd2d5a 54 #elif defined (__GNUC__) /* GNU Compiler */
guilhemMBED 0:a7c449cd2d5a 55
guilhemMBED 0:a7c449cd2d5a 56 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 57
guilhemMBED 0:a7c449cd2d5a 58 #if defined (__CORTEX_M0)
guilhemMBED 0:a7c449cd2d5a 59 #define __TARGET_ARCH_6S_M 1
guilhemMBED 0:a7c449cd2d5a 60 #else
guilhemMBED 0:a7c449cd2d5a 61 #define __TARGET_ARCH_6S_M 0
guilhemMBED 0:a7c449cd2d5a 62 #endif
guilhemMBED 0:a7c449cd2d5a 63
guilhemMBED 0:a7c449cd2d5a 64 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
guilhemMBED 0:a7c449cd2d5a 65 #define __TARGET_FPU_VFP 1
guilhemMBED 0:a7c449cd2d5a 66 #else
guilhemMBED 0:a7c449cd2d5a 67 #define __TARGET_FPU_VFP 0
guilhemMBED 0:a7c449cd2d5a 68 #endif
guilhemMBED 0:a7c449cd2d5a 69
guilhemMBED 0:a7c449cd2d5a 70 #define __inline inline
guilhemMBED 0:a7c449cd2d5a 71 #define __weak __attribute__((weak))
guilhemMBED 0:a7c449cd2d5a 72
guilhemMBED 0:a7c449cd2d5a 73 #ifndef __CMSIS_GENERIC
guilhemMBED 0:a7c449cd2d5a 74
guilhemMBED 0:a7c449cd2d5a 75 __attribute__((always_inline)) static inline void __enable_irq(void)
guilhemMBED 0:a7c449cd2d5a 76 {
guilhemMBED 0:a7c449cd2d5a 77 __asm volatile ("cpsie i");
guilhemMBED 0:a7c449cd2d5a 78 }
guilhemMBED 0:a7c449cd2d5a 79
guilhemMBED 0:a7c449cd2d5a 80 __attribute__((always_inline)) static inline U32 __disable_irq(void)
guilhemMBED 0:a7c449cd2d5a 81 {
guilhemMBED 0:a7c449cd2d5a 82 U32 result;
guilhemMBED 0:a7c449cd2d5a 83
guilhemMBED 0:a7c449cd2d5a 84 __asm volatile ("mrs %0, primask" : "=r" (result));
guilhemMBED 0:a7c449cd2d5a 85 __asm volatile ("cpsid i");
guilhemMBED 0:a7c449cd2d5a 86 return(result & 1);
guilhemMBED 0:a7c449cd2d5a 87 }
guilhemMBED 0:a7c449cd2d5a 88
guilhemMBED 0:a7c449cd2d5a 89 #endif
guilhemMBED 0:a7c449cd2d5a 90
guilhemMBED 0:a7c449cd2d5a 91 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
guilhemMBED 0:a7c449cd2d5a 92 {
guilhemMBED 0:a7c449cd2d5a 93 U8 result;
guilhemMBED 0:a7c449cd2d5a 94
guilhemMBED 0:a7c449cd2d5a 95 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
guilhemMBED 0:a7c449cd2d5a 96 return(result);
guilhemMBED 0:a7c449cd2d5a 97 }
guilhemMBED 0:a7c449cd2d5a 98
guilhemMBED 0:a7c449cd2d5a 99 #elif defined (__ICCARM__) /* IAR Compiler */
guilhemMBED 0:a7c449cd2d5a 100
guilhemMBED 0:a7c449cd2d5a 101 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 102
guilhemMBED 0:a7c449cd2d5a 103 #if (__CORE__ == __ARM6M__)
guilhemMBED 0:a7c449cd2d5a 104 #define __TARGET_ARCH_6S_M 1
guilhemMBED 0:a7c449cd2d5a 105 #else
guilhemMBED 0:a7c449cd2d5a 106 #define __TARGET_ARCH_6S_M 0
guilhemMBED 0:a7c449cd2d5a 107 #endif
guilhemMBED 0:a7c449cd2d5a 108
guilhemMBED 0:a7c449cd2d5a 109 #if defined __ARMVFP__
guilhemMBED 0:a7c449cd2d5a 110 #define __TARGET_FPU_VFP 1
guilhemMBED 0:a7c449cd2d5a 111 #else
guilhemMBED 0:a7c449cd2d5a 112 #define __TARGET_FPU_VFP 0
guilhemMBED 0:a7c449cd2d5a 113 #endif
guilhemMBED 0:a7c449cd2d5a 114
guilhemMBED 0:a7c449cd2d5a 115 #define __inline inline
guilhemMBED 0:a7c449cd2d5a 116
guilhemMBED 0:a7c449cd2d5a 117 #ifndef __CMSIS_GENERIC
guilhemMBED 0:a7c449cd2d5a 118
guilhemMBED 0:a7c449cd2d5a 119 static inline void __enable_irq(void)
guilhemMBED 0:a7c449cd2d5a 120 {
guilhemMBED 0:a7c449cd2d5a 121 __asm volatile ("cpsie i");
guilhemMBED 0:a7c449cd2d5a 122 }
guilhemMBED 0:a7c449cd2d5a 123
guilhemMBED 0:a7c449cd2d5a 124 static inline U32 __disable_irq(void)
guilhemMBED 0:a7c449cd2d5a 125 {
guilhemMBED 0:a7c449cd2d5a 126 U32 result;
guilhemMBED 0:a7c449cd2d5a 127
guilhemMBED 0:a7c449cd2d5a 128 __asm volatile ("mrs %0, primask" : "=r" (result));
guilhemMBED 0:a7c449cd2d5a 129 __asm volatile ("cpsid i");
guilhemMBED 0:a7c449cd2d5a 130 return(result & 1);
guilhemMBED 0:a7c449cd2d5a 131 }
guilhemMBED 0:a7c449cd2d5a 132
guilhemMBED 0:a7c449cd2d5a 133 #endif
guilhemMBED 0:a7c449cd2d5a 134
guilhemMBED 0:a7c449cd2d5a 135 static inline U8 __clz(U32 value)
guilhemMBED 0:a7c449cd2d5a 136 {
guilhemMBED 0:a7c449cd2d5a 137 U8 result;
guilhemMBED 0:a7c449cd2d5a 138
guilhemMBED 0:a7c449cd2d5a 139 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
guilhemMBED 0:a7c449cd2d5a 140 return(result);
guilhemMBED 0:a7c449cd2d5a 141 }
guilhemMBED 0:a7c449cd2d5a 142
guilhemMBED 0:a7c449cd2d5a 143 #endif
guilhemMBED 0:a7c449cd2d5a 144
guilhemMBED 0:a7c449cd2d5a 145 /* NVIC registers */
guilhemMBED 0:a7c449cd2d5a 146 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
guilhemMBED 0:a7c449cd2d5a 147 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
guilhemMBED 0:a7c449cd2d5a 148 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
guilhemMBED 0:a7c449cd2d5a 149 #define NVIC_ISER ((volatile U32 *)0xE000E100)
guilhemMBED 0:a7c449cd2d5a 150 #define NVIC_ICER ((volatile U32 *)0xE000E180)
guilhemMBED 0:a7c449cd2d5a 151 #if (__TARGET_ARCH_6S_M)
guilhemMBED 0:a7c449cd2d5a 152 #define NVIC_IP ((volatile U32 *)0xE000E400)
guilhemMBED 0:a7c449cd2d5a 153 #else
guilhemMBED 0:a7c449cd2d5a 154 #define NVIC_IP ((volatile U8 *)0xE000E400)
guilhemMBED 0:a7c449cd2d5a 155 #endif
guilhemMBED 0:a7c449cd2d5a 156 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
guilhemMBED 0:a7c449cd2d5a 157 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
guilhemMBED 0:a7c449cd2d5a 158 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
guilhemMBED 0:a7c449cd2d5a 159 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
guilhemMBED 0:a7c449cd2d5a 160
guilhemMBED 0:a7c449cd2d5a 161 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
guilhemMBED 0:a7c449cd2d5a 162 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
guilhemMBED 0:a7c449cd2d5a 163 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
guilhemMBED 0:a7c449cd2d5a 164 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
guilhemMBED 0:a7c449cd2d5a 165 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
guilhemMBED 0:a7c449cd2d5a 166 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
guilhemMBED 0:a7c449cd2d5a 167
guilhemMBED 0:a7c449cd2d5a 168 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
guilhemMBED 0:a7c449cd2d5a 169 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
guilhemMBED 0:a7c449cd2d5a 170 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
guilhemMBED 0:a7c449cd2d5a 171 #if (__TARGET_ARCH_6S_M)
guilhemMBED 0:a7c449cd2d5a 172 #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
guilhemMBED 0:a7c449cd2d5a 173 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
guilhemMBED 0:a7c449cd2d5a 174 #else
guilhemMBED 0:a7c449cd2d5a 175 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
guilhemMBED 0:a7c449cd2d5a 176 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
guilhemMBED 0:a7c449cd2d5a 177 #endif
guilhemMBED 0:a7c449cd2d5a 178 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
guilhemMBED 0:a7c449cd2d5a 179 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
guilhemMBED 0:a7c449cd2d5a 180
guilhemMBED 0:a7c449cd2d5a 181 /* Core Debug registers */
guilhemMBED 0:a7c449cd2d5a 182 #define DEMCR (*((volatile U32 *)0xE000EDFC))
guilhemMBED 0:a7c449cd2d5a 183
guilhemMBED 0:a7c449cd2d5a 184 /* ITM registers */
guilhemMBED 0:a7c449cd2d5a 185 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
guilhemMBED 0:a7c449cd2d5a 186 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
guilhemMBED 0:a7c449cd2d5a 187 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
guilhemMBED 0:a7c449cd2d5a 188 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
guilhemMBED 0:a7c449cd2d5a 189 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
guilhemMBED 0:a7c449cd2d5a 190 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
guilhemMBED 0:a7c449cd2d5a 191
guilhemMBED 0:a7c449cd2d5a 192 /* Variables */
guilhemMBED 0:a7c449cd2d5a 193 extern BIT dbg_msg;
guilhemMBED 0:a7c449cd2d5a 194
guilhemMBED 0:a7c449cd2d5a 195 /* Functions */
guilhemMBED 0:a7c449cd2d5a 196 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 197 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
guilhemMBED 0:a7c449cd2d5a 198 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
guilhemMBED 0:a7c449cd2d5a 199 #else
guilhemMBED 0:a7c449cd2d5a 200 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
guilhemMBED 0:a7c449cd2d5a 201 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
guilhemMBED 0:a7c449cd2d5a 202 #endif
guilhemMBED 0:a7c449cd2d5a 203
guilhemMBED 0:a7c449cd2d5a 204 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
guilhemMBED 0:a7c449cd2d5a 205 U32 cnt,c2;
guilhemMBED 0:a7c449cd2d5a 206 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 207 do {
guilhemMBED 0:a7c449cd2d5a 208 if ((cnt = __ldrex(count)) == size) {
guilhemMBED 0:a7c449cd2d5a 209 __clrex();
guilhemMBED 0:a7c449cd2d5a 210 return (cnt); }
guilhemMBED 0:a7c449cd2d5a 211 } while (__strex(cnt+1, count));
guilhemMBED 0:a7c449cd2d5a 212 do {
guilhemMBED 0:a7c449cd2d5a 213 c2 = (cnt = __ldrex(first)) + 1;
guilhemMBED 0:a7c449cd2d5a 214 if (c2 == size) c2 = 0;
guilhemMBED 0:a7c449cd2d5a 215 } while (__strex(c2, first));
guilhemMBED 0:a7c449cd2d5a 216 #else
guilhemMBED 0:a7c449cd2d5a 217 __disable_irq();
guilhemMBED 0:a7c449cd2d5a 218 if ((cnt = *count) < size) {
guilhemMBED 0:a7c449cd2d5a 219 *count = cnt+1;
guilhemMBED 0:a7c449cd2d5a 220 c2 = (cnt = *first) + 1;
guilhemMBED 0:a7c449cd2d5a 221 if (c2 == size) c2 = 0;
guilhemMBED 0:a7c449cd2d5a 222 *first = c2;
guilhemMBED 0:a7c449cd2d5a 223 }
guilhemMBED 0:a7c449cd2d5a 224 __enable_irq ();
guilhemMBED 0:a7c449cd2d5a 225 #endif
guilhemMBED 0:a7c449cd2d5a 226 return (cnt);
guilhemMBED 0:a7c449cd2d5a 227 }
guilhemMBED 0:a7c449cd2d5a 228
guilhemMBED 0:a7c449cd2d5a 229 __inline static void rt_systick_init (void) {
guilhemMBED 0:a7c449cd2d5a 230 NVIC_ST_RELOAD = os_trv;
guilhemMBED 0:a7c449cd2d5a 231 NVIC_ST_CURRENT = 0;
guilhemMBED 0:a7c449cd2d5a 232 NVIC_ST_CTRL = 0x0007;
guilhemMBED 0:a7c449cd2d5a 233 NVIC_SYS_PRI3 |= 0xFF000000;
guilhemMBED 0:a7c449cd2d5a 234 }
guilhemMBED 0:a7c449cd2d5a 235
guilhemMBED 0:a7c449cd2d5a 236 __inline static U32 rt_systick_val (void) {
guilhemMBED 0:a7c449cd2d5a 237 return (os_trv - NVIC_ST_CURRENT);
guilhemMBED 0:a7c449cd2d5a 238 }
guilhemMBED 0:a7c449cd2d5a 239
guilhemMBED 0:a7c449cd2d5a 240 __inline static U32 rt_systick_ovf (void) {
guilhemMBED 0:a7c449cd2d5a 241 return ((NVIC_INT_CTRL >> 26) & 1);
guilhemMBED 0:a7c449cd2d5a 242 }
guilhemMBED 0:a7c449cd2d5a 243
guilhemMBED 0:a7c449cd2d5a 244 __inline static void rt_svc_init (void) {
guilhemMBED 0:a7c449cd2d5a 245 #if !(__TARGET_ARCH_6S_M)
guilhemMBED 0:a7c449cd2d5a 246 int sh,prigroup;
guilhemMBED 0:a7c449cd2d5a 247 #endif
guilhemMBED 0:a7c449cd2d5a 248 NVIC_SYS_PRI3 |= 0x00FF0000;
guilhemMBED 0:a7c449cd2d5a 249 #if (__TARGET_ARCH_6S_M)
guilhemMBED 0:a7c449cd2d5a 250 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
guilhemMBED 0:a7c449cd2d5a 251 #else
guilhemMBED 0:a7c449cd2d5a 252 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
guilhemMBED 0:a7c449cd2d5a 253 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
guilhemMBED 0:a7c449cd2d5a 254 if (prigroup >= sh) {
guilhemMBED 0:a7c449cd2d5a 255 sh = prigroup + 1;
guilhemMBED 0:a7c449cd2d5a 256 }
guilhemMBED 0:a7c449cd2d5a 257 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
guilhemMBED 0:a7c449cd2d5a 258 #endif
guilhemMBED 0:a7c449cd2d5a 259 }
guilhemMBED 0:a7c449cd2d5a 260
guilhemMBED 0:a7c449cd2d5a 261 extern void rt_set_PSP (U32 stack);
guilhemMBED 0:a7c449cd2d5a 262 extern U32 rt_get_PSP (void);
guilhemMBED 0:a7c449cd2d5a 263 extern void os_set_env (void);
guilhemMBED 0:a7c449cd2d5a 264 extern void *_alloc_box (void *box_mem);
guilhemMBED 0:a7c449cd2d5a 265 extern int _free_box (void *box_mem, void *box);
guilhemMBED 0:a7c449cd2d5a 266
guilhemMBED 0:a7c449cd2d5a 267 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
guilhemMBED 0:a7c449cd2d5a 268 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
guilhemMBED 0:a7c449cd2d5a 269 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
guilhemMBED 0:a7c449cd2d5a 270
guilhemMBED 0:a7c449cd2d5a 271 extern void dbg_init (void);
guilhemMBED 0:a7c449cd2d5a 272 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
guilhemMBED 0:a7c449cd2d5a 273 extern void dbg_task_switch (U32 task_id);
guilhemMBED 0:a7c449cd2d5a 274
guilhemMBED 0:a7c449cd2d5a 275 #ifdef DBG_MSG
guilhemMBED 0:a7c449cd2d5a 276 #define DBG_INIT() dbg_init()
guilhemMBED 0:a7c449cd2d5a 277 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
guilhemMBED 0:a7c449cd2d5a 278 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk!=os_tsk.run)) \
guilhemMBED 0:a7c449cd2d5a 279 dbg_task_switch(task_id)
guilhemMBED 0:a7c449cd2d5a 280 #else
guilhemMBED 0:a7c449cd2d5a 281 #define DBG_INIT()
guilhemMBED 0:a7c449cd2d5a 282 #define DBG_TASK_NOTIFY(p_tcb,create)
guilhemMBED 0:a7c449cd2d5a 283 #define DBG_TASK_SWITCH(task_id)
guilhemMBED 0:a7c449cd2d5a 284 #endif
guilhemMBED 0:a7c449cd2d5a 285
guilhemMBED 0:a7c449cd2d5a 286 /*----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 287 * end of file
guilhemMBED 0:a7c449cd2d5a 288 *---------------------------------------------------------------------------*/
guilhemMBED 0:a7c449cd2d5a 289