TeamGyro / mbed-rtos

OS2

Dependents:   GYRO_MPU6050 Bluetooth_Powered_Multimeter_Using_STM32F429_and_RTOS fyp

rtx/TARGET_CORTEX_A/rt_HAL_CA.h@0:a7c449cd2d5a, 2020-02-03 (annotated)

Committer:
guilhemMBED
Date:
Mon Feb 03 13:41:14 2020 +0000
Revision:
0:a7c449cd2d5a
previous version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
guilhemMBED 0:a7c449cd2d5a 1 /*----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 2 * RL-ARM - RTX
guilhemMBED 0:a7c449cd2d5a 3 *----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 4 * Name: RT_HAL_CA.H
guilhemMBED 0:a7c449cd2d5a 5 * Purpose: Hardware Abstraction Layer for Cortex-A definitions
guilhemMBED 0:a7c449cd2d5a 6 * Rev.: 14th Jan 2014
guilhemMBED 0:a7c449cd2d5a 7 *----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 8 *
guilhemMBED 0:a7c449cd2d5a 9 * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
guilhemMBED 0:a7c449cd2d5a 10 * All rights reserved.
guilhemMBED 0:a7c449cd2d5a 11 * Redistribution and use in source and binary forms, with or without
guilhemMBED 0:a7c449cd2d5a 12 * modification, are permitted provided that the following conditions are met:
guilhemMBED 0:a7c449cd2d5a 13 * - Redistributions of source code must retain the above copyright
guilhemMBED 0:a7c449cd2d5a 14 * notice, this list of conditions and the following disclaimer.
guilhemMBED 0:a7c449cd2d5a 15 * - Redistributions in binary form must reproduce the above copyright
guilhemMBED 0:a7c449cd2d5a 16 * notice, this list of conditions and the following disclaimer in the
guilhemMBED 0:a7c449cd2d5a 17 * documentation and/or other materials provided with the distribution.
guilhemMBED 0:a7c449cd2d5a 18 * - Neither the name of ARM nor the names of its contributors may be used
guilhemMBED 0:a7c449cd2d5a 19 * to endorse or promote products derived from this software without
guilhemMBED 0:a7c449cd2d5a 20 * specific prior written permission.
guilhemMBED 0:a7c449cd2d5a 21 *
guilhemMBED 0:a7c449cd2d5a 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
guilhemMBED 0:a7c449cd2d5a 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
guilhemMBED 0:a7c449cd2d5a 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
guilhemMBED 0:a7c449cd2d5a 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
guilhemMBED 0:a7c449cd2d5a 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
guilhemMBED 0:a7c449cd2d5a 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
guilhemMBED 0:a7c449cd2d5a 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
guilhemMBED 0:a7c449cd2d5a 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
guilhemMBED 0:a7c449cd2d5a 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
guilhemMBED 0:a7c449cd2d5a 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
guilhemMBED 0:a7c449cd2d5a 32 * POSSIBILITY OF SUCH DAMAGE.
guilhemMBED 0:a7c449cd2d5a 33 *---------------------------------------------------------------------------*/
guilhemMBED 0:a7c449cd2d5a 34
guilhemMBED 0:a7c449cd2d5a 35 /* Definitions */
guilhemMBED 0:a7c449cd2d5a 36 #define INIT_CPSR_SYS 0x4000001F
guilhemMBED 0:a7c449cd2d5a 37 #define INIT_CPSR_USER 0x40000010
guilhemMBED 0:a7c449cd2d5a 38
guilhemMBED 0:a7c449cd2d5a 39 #define CPSR_T_BIT 0x20
guilhemMBED 0:a7c449cd2d5a 40 #define CPSR_I_BIT 0x80
guilhemMBED 0:a7c449cd2d5a 41 #define CPSR_F_BIT 0x40
guilhemMBED 0:a7c449cd2d5a 42
guilhemMBED 0:a7c449cd2d5a 43 #define MODE_USR 0x10
guilhemMBED 0:a7c449cd2d5a 44 #define MODE_FIQ 0x11
guilhemMBED 0:a7c449cd2d5a 45 #define MODE_IRQ 0x12
guilhemMBED 0:a7c449cd2d5a 46 #define MODE_SVC 0x13
guilhemMBED 0:a7c449cd2d5a 47 #define MODE_ABT 0x17
guilhemMBED 0:a7c449cd2d5a 48 #define MODE_UND 0x1B
guilhemMBED 0:a7c449cd2d5a 49 #define MODE_SYS 0x1F
guilhemMBED 0:a7c449cd2d5a 50
guilhemMBED 0:a7c449cd2d5a 51 #define MAGIC_WORD 0xE25A2EA5
guilhemMBED 0:a7c449cd2d5a 52
guilhemMBED 0:a7c449cd2d5a 53 #include "core_ca9.h"
guilhemMBED 0:a7c449cd2d5a 54
guilhemMBED 0:a7c449cd2d5a 55 #if defined (__CC_ARM) /* ARM Compiler */
guilhemMBED 0:a7c449cd2d5a 56
guilhemMBED 0:a7c449cd2d5a 57 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !defined(NO_EXCLUSIVE_ACCESS))
guilhemMBED 0:a7c449cd2d5a 58 #define __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 59 #else
guilhemMBED 0:a7c449cd2d5a 60 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 61 #endif
guilhemMBED 0:a7c449cd2d5a 62
guilhemMBED 0:a7c449cd2d5a 63 /* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
guilhemMBED 0:a7c449cd2d5a 64 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 65 #pragma diag_suppress 3731
guilhemMBED 0:a7c449cd2d5a 66 #endif
guilhemMBED 0:a7c449cd2d5a 67
guilhemMBED 0:a7c449cd2d5a 68 #elif defined (__GNUC__) /* GNU Compiler */
guilhemMBED 0:a7c449cd2d5a 69
guilhemMBED 0:a7c449cd2d5a 70 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 71
guilhemMBED 0:a7c449cd2d5a 72 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
guilhemMBED 0:a7c449cd2d5a 73 #define __TARGET_FPU_VFP 1
guilhemMBED 0:a7c449cd2d5a 74 #else
guilhemMBED 0:a7c449cd2d5a 75 #define __TARGET_FPU_VFP 0
guilhemMBED 0:a7c449cd2d5a 76 #endif
guilhemMBED 0:a7c449cd2d5a 77
guilhemMBED 0:a7c449cd2d5a 78 #define __inline inline
guilhemMBED 0:a7c449cd2d5a 79 #define __weak __attribute__((weak))
guilhemMBED 0:a7c449cd2d5a 80
guilhemMBED 0:a7c449cd2d5a 81 #elif defined (__ICCARM__) /* IAR Compiler */
guilhemMBED 0:a7c449cd2d5a 82
guilhemMBED 0:a7c449cd2d5a 83 #endif
guilhemMBED 0:a7c449cd2d5a 84
guilhemMBED 0:a7c449cd2d5a 85 static U8 priority = 0xff;
guilhemMBED 0:a7c449cd2d5a 86
guilhemMBED 0:a7c449cd2d5a 87 extern const U32 GICDistributor_BASE;
guilhemMBED 0:a7c449cd2d5a 88 extern const U32 GICInterface_BASE;
guilhemMBED 0:a7c449cd2d5a 89
guilhemMBED 0:a7c449cd2d5a 90 /* GIC registers - Distributor */
guilhemMBED 0:a7c449cd2d5a 91 #define GICD_ICDICER0 (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */
guilhemMBED 0:a7c449cd2d5a 92 #define GICD_ICDISER0 (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */
guilhemMBED 0:a7c449cd2d5a 93 #define GICD_ICDIPR0 (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */
guilhemMBED 0:a7c449cd2d5a 94 #define GICD_ICDSGIR (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */
guilhemMBED 0:a7c449cd2d5a 95 #define GICD_ICDICERx(irq) *(volatile U32 *)(&GICD_ICDICER0 + irq/32)
guilhemMBED 0:a7c449cd2d5a 96 #define GICD_ICDISERx(irq) *(volatile U32 *)(&GICD_ICDISER0 + irq/32)
guilhemMBED 0:a7c449cd2d5a 97
guilhemMBED 0:a7c449cd2d5a 98 /* GIC register - CPU Interface */
guilhemMBED 0:a7c449cd2d5a 99 #define GICI_ICCPMR (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */
guilhemMBED 0:a7c449cd2d5a 100
guilhemMBED 0:a7c449cd2d5a 101 #define SGI_PENDSV 0 /* SGI0 */
guilhemMBED 0:a7c449cd2d5a 102 #define SGI_PENDSV_BIT ((U32)(1 << (SGI_PENDSV & 0xf)))
guilhemMBED 0:a7c449cd2d5a 103
guilhemMBED 0:a7c449cd2d5a 104 //Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
guilhemMBED 0:a7c449cd2d5a 105 #if defined (__ICCARM__)
guilhemMBED 0:a7c449cd2d5a 106 #define OS_LOCK() int irq_dis = __disable_irq_iar();\
guilhemMBED 0:a7c449cd2d5a 107 priority = GICI_ICCPMR; \
guilhemMBED 0:a7c449cd2d5a 108 GICI_ICCPMR = 0xff; \
guilhemMBED 0:a7c449cd2d5a 109 GICI_ICCPMR = GICI_ICCPMR - 1; \
guilhemMBED 0:a7c449cd2d5a 110 __DSB();\
guilhemMBED 0:a7c449cd2d5a 111 if(!irq_dis) __enable_irq(); \
guilhemMBED 0:a7c449cd2d5a 112
guilhemMBED 0:a7c449cd2d5a 113 #else
guilhemMBED 0:a7c449cd2d5a 114 #define OS_LOCK() int irq_dis = __disable_irq();\
guilhemMBED 0:a7c449cd2d5a 115 priority = GICI_ICCPMR; \
guilhemMBED 0:a7c449cd2d5a 116 GICI_ICCPMR = 0xff; \
guilhemMBED 0:a7c449cd2d5a 117 GICI_ICCPMR = GICI_ICCPMR - 1; \
guilhemMBED 0:a7c449cd2d5a 118 __DSB();\
guilhemMBED 0:a7c449cd2d5a 119 if(!irq_dis) __enable_irq(); \
guilhemMBED 0:a7c449cd2d5a 120
guilhemMBED 0:a7c449cd2d5a 121 #endif
guilhemMBED 0:a7c449cd2d5a 122
guilhemMBED 0:a7c449cd2d5a 123 //Restore priority filter. Re-enable timer and PendSV signaling
guilhemMBED 0:a7c449cd2d5a 124 #define OS_UNLOCK() __DSB(); \
guilhemMBED 0:a7c449cd2d5a 125 GICI_ICCPMR = priority; \
guilhemMBED 0:a7c449cd2d5a 126
guilhemMBED 0:a7c449cd2d5a 127 #define OS_PEND_IRQ() GICD_ICDSGIR = 0x0010000 | SGI_PENDSV
guilhemMBED 0:a7c449cd2d5a 128 #define OS_PEND(fl,p) if(p) OS_PEND_IRQ();
guilhemMBED 0:a7c449cd2d5a 129 #define OS_UNPEND(fl)
guilhemMBED 0:a7c449cd2d5a 130
guilhemMBED 0:a7c449cd2d5a 131 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c-
guilhemMBED 0:a7c449cd2d5a 132 * OS_X_INIT enables the IRQ n in the GIC */
guilhemMBED 0:a7c449cd2d5a 133 #define OS_X_INIT(n) volatile char *reg; \
guilhemMBED 0:a7c449cd2d5a 134 reg = (char *)(&GICD_ICDIPR0 + n / 4); \
guilhemMBED 0:a7c449cd2d5a 135 reg += n % 4; \
guilhemMBED 0:a7c449cd2d5a 136 *reg = (char)0xff; \
guilhemMBED 0:a7c449cd2d5a 137 *reg = *reg - 1; \
guilhemMBED 0:a7c449cd2d5a 138 GICD_ICDISERx(n) = (U32)(1 << n % 32);
guilhemMBED 0:a7c449cd2d5a 139 #define OS_X_LOCK(n) OS_LOCK()
guilhemMBED 0:a7c449cd2d5a 140 #define OS_X_UNLOCK(n) OS_UNLOCK()
guilhemMBED 0:a7c449cd2d5a 141 #define OS_X_PEND_IRQ() OS_PEND_IRQ()
guilhemMBED 0:a7c449cd2d5a 142 #define OS_X_PEND(fl,p) if(p) OS_X_PEND_IRQ();
guilhemMBED 0:a7c449cd2d5a 143 #define OS_X_UNPEND(fl)
guilhemMBED 0:a7c449cd2d5a 144
guilhemMBED 0:a7c449cd2d5a 145
guilhemMBED 0:a7c449cd2d5a 146 /* Functions */
guilhemMBED 0:a7c449cd2d5a 147 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 148 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
guilhemMBED 0:a7c449cd2d5a 149 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
guilhemMBED 0:a7c449cd2d5a 150 #else
guilhemMBED 0:a7c449cd2d5a 151 #if defined (__ICCARM__)
guilhemMBED 0:a7c449cd2d5a 152 #define rt_inc(p) { int irq_dis = __disable_irq_iar();(*p)++;if(!irq_dis) __enable_irq(); }
guilhemMBED 0:a7c449cd2d5a 153 #define rt_dec(p) { int irq_dis = __disable_irq_iar();(*p)--;if(!irq_dis) __enable_irq(); }
guilhemMBED 0:a7c449cd2d5a 154 #else
guilhemMBED 0:a7c449cd2d5a 155 #define rt_inc(p) { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); }
guilhemMBED 0:a7c449cd2d5a 156 #define rt_dec(p) { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); }
guilhemMBED 0:a7c449cd2d5a 157 #endif /* __ICCARM__ */
guilhemMBED 0:a7c449cd2d5a 158 #endif /* __USE_EXCLUSIVE_ACCESS */
guilhemMBED 0:a7c449cd2d5a 159
guilhemMBED 0:a7c449cd2d5a 160 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
guilhemMBED 0:a7c449cd2d5a 161 U32 cnt,c2;
guilhemMBED 0:a7c449cd2d5a 162 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 163 do {
guilhemMBED 0:a7c449cd2d5a 164 if ((cnt = __ldrex(count)) == size) {
guilhemMBED 0:a7c449cd2d5a 165 __clrex();
guilhemMBED 0:a7c449cd2d5a 166 return (cnt); }
guilhemMBED 0:a7c449cd2d5a 167 } while (__strex(cnt+1, count));
guilhemMBED 0:a7c449cd2d5a 168 do {
guilhemMBED 0:a7c449cd2d5a 169 c2 = (cnt = __ldrex(first)) + 1;
guilhemMBED 0:a7c449cd2d5a 170 if (c2 == size) c2 = 0;
guilhemMBED 0:a7c449cd2d5a 171 } while (__strex(c2, first));
guilhemMBED 0:a7c449cd2d5a 172 #else
guilhemMBED 0:a7c449cd2d5a 173 int irq_dis;
guilhemMBED 0:a7c449cd2d5a 174 #if defined (__ICCARM__)
guilhemMBED 0:a7c449cd2d5a 175 irq_dis = __disable_irq_iar();
guilhemMBED 0:a7c449cd2d5a 176 #else
guilhemMBED 0:a7c449cd2d5a 177 irq_dis = __disable_irq();
guilhemMBED 0:a7c449cd2d5a 178 #endif /* __ICCARM__ */
guilhemMBED 0:a7c449cd2d5a 179 if ((cnt = *count) < size) {
guilhemMBED 0:a7c449cd2d5a 180 *count = cnt+1;
guilhemMBED 0:a7c449cd2d5a 181 c2 = (cnt = *first) + 1;
guilhemMBED 0:a7c449cd2d5a 182 if (c2 == size) c2 = 0;
guilhemMBED 0:a7c449cd2d5a 183 *first = c2;
guilhemMBED 0:a7c449cd2d5a 184 }
guilhemMBED 0:a7c449cd2d5a 185 if(!irq_dis) __enable_irq ();
guilhemMBED 0:a7c449cd2d5a 186 #endif
guilhemMBED 0:a7c449cd2d5a 187 return (cnt);
guilhemMBED 0:a7c449cd2d5a 188 }
guilhemMBED 0:a7c449cd2d5a 189
guilhemMBED 0:a7c449cd2d5a 190 __inline static void rt_systick_init (void) {
guilhemMBED 0:a7c449cd2d5a 191 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
guilhemMBED 0:a7c449cd2d5a 192 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
guilhemMBED 0:a7c449cd2d5a 193 }
guilhemMBED 0:a7c449cd2d5a 194
guilhemMBED 0:a7c449cd2d5a 195 __inline static U32 rt_systick_val (void) {
guilhemMBED 0:a7c449cd2d5a 196 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
guilhemMBED 0:a7c449cd2d5a 197 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
guilhemMBED 0:a7c449cd2d5a 198 return 0;
guilhemMBED 0:a7c449cd2d5a 199 }
guilhemMBED 0:a7c449cd2d5a 200
guilhemMBED 0:a7c449cd2d5a 201 __inline static U32 rt_systick_ovf (void) {
guilhemMBED 0:a7c449cd2d5a 202 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
guilhemMBED 0:a7c449cd2d5a 203 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
guilhemMBED 0:a7c449cd2d5a 204 return 0;
guilhemMBED 0:a7c449cd2d5a 205 }
guilhemMBED 0:a7c449cd2d5a 206
guilhemMBED 0:a7c449cd2d5a 207 __inline static void rt_svc_init (void) {
guilhemMBED 0:a7c449cd2d5a 208 /* Register pendSV - through SGI */
guilhemMBED 0:a7c449cd2d5a 209 volatile char *reg;
guilhemMBED 0:a7c449cd2d5a 210
guilhemMBED 0:a7c449cd2d5a 211 reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
guilhemMBED 0:a7c449cd2d5a 212 reg += SGI_PENDSV % 4;
guilhemMBED 0:a7c449cd2d5a 213 /* Write 0xff to read priority level */
guilhemMBED 0:a7c449cd2d5a 214 *reg = (char)0xff;
guilhemMBED 0:a7c449cd2d5a 215 /* Read priority level and set the lowest possible*/
guilhemMBED 0:a7c449cd2d5a 216 *reg = *reg - 1;
guilhemMBED 0:a7c449cd2d5a 217
guilhemMBED 0:a7c449cd2d5a 218 GICD_ICDISERx(SGI_PENDSV) = (U32)SGI_PENDSV_BIT;
guilhemMBED 0:a7c449cd2d5a 219 }
guilhemMBED 0:a7c449cd2d5a 220
guilhemMBED 0:a7c449cd2d5a 221 extern void rt_set_PSP (U32 stack);
guilhemMBED 0:a7c449cd2d5a 222 extern U32 rt_get_PSP (void);
guilhemMBED 0:a7c449cd2d5a 223 extern void os_set_env (P_TCB p_TCB);
guilhemMBED 0:a7c449cd2d5a 224 extern void *_alloc_box (void *box_mem);
guilhemMBED 0:a7c449cd2d5a 225 extern int _free_box (void *box_mem, void *box);
guilhemMBED 0:a7c449cd2d5a 226
guilhemMBED 0:a7c449cd2d5a 227 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
guilhemMBED 0:a7c449cd2d5a 228 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
guilhemMBED 0:a7c449cd2d5a 229 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
guilhemMBED 0:a7c449cd2d5a 230
guilhemMBED 0:a7c449cd2d5a 231 extern void dbg_init (void);
guilhemMBED 0:a7c449cd2d5a 232 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
guilhemMBED 0:a7c449cd2d5a 233 extern void dbg_task_switch (U32 task_id);
guilhemMBED 0:a7c449cd2d5a 234
guilhemMBED 0:a7c449cd2d5a 235 #define DBG_INIT()
guilhemMBED 0:a7c449cd2d5a 236 #define DBG_TASK_NOTIFY(p_tcb,create)
guilhemMBED 0:a7c449cd2d5a 237 #define DBG_TASK_SWITCH(task_id)
guilhemMBED 0:a7c449cd2d5a 238
guilhemMBED 0:a7c449cd2d5a 239 /*----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 240 * end of file
guilhemMBED 0:a7c449cd2d5a 241 *---------------------------------------------------------------------------*/
guilhemMBED 0:a7c449cd2d5a 242