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Dependents:   GYRO_MPU6050 Bluetooth_Powered_Multimeter_Using_STM32F429_and_RTOS fyp

rtx/TARGET_ARM7/rt_HAL_CM.h@0:a7c449cd2d5a, 2020-02-03 (annotated)

Committer:
guilhemMBED
Date:
Mon Feb 03 13:41:14 2020 +0000
Revision:
0:a7c449cd2d5a
previous version;

Who changed what in which revision?

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guilhemMBED 0:a7c449cd2d5a 1 /*----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 2 * RL-ARM - RTX
guilhemMBED 0:a7c449cd2d5a 3 *----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 4 * Name: RT_HAL_CM.H
guilhemMBED 0:a7c449cd2d5a 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
guilhemMBED 0:a7c449cd2d5a 6 * Rev.: V4.60
guilhemMBED 0:a7c449cd2d5a 7 *----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 8 *
guilhemMBED 0:a7c449cd2d5a 9 * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
guilhemMBED 0:a7c449cd2d5a 10 * All rights reserved.
guilhemMBED 0:a7c449cd2d5a 11 * Redistribution and use in source and binary forms, with or without
guilhemMBED 0:a7c449cd2d5a 12 * modification, are permitted provided that the following conditions are met:
guilhemMBED 0:a7c449cd2d5a 13 * - Redistributions of source code must retain the above copyright
guilhemMBED 0:a7c449cd2d5a 14 * notice, this list of conditions and the following disclaimer.
guilhemMBED 0:a7c449cd2d5a 15 * - Redistributions in binary form must reproduce the above copyright
guilhemMBED 0:a7c449cd2d5a 16 * notice, this list of conditions and the following disclaimer in the
guilhemMBED 0:a7c449cd2d5a 17 * documentation and/or other materials provided with the distribution.
guilhemMBED 0:a7c449cd2d5a 18 * - Neither the name of ARM nor the names of its contributors may be used
guilhemMBED 0:a7c449cd2d5a 19 * to endorse or promote products derived from this software without
guilhemMBED 0:a7c449cd2d5a 20 * specific prior written permission.
guilhemMBED 0:a7c449cd2d5a 21 *
guilhemMBED 0:a7c449cd2d5a 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
guilhemMBED 0:a7c449cd2d5a 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
guilhemMBED 0:a7c449cd2d5a 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
guilhemMBED 0:a7c449cd2d5a 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
guilhemMBED 0:a7c449cd2d5a 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
guilhemMBED 0:a7c449cd2d5a 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
guilhemMBED 0:a7c449cd2d5a 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
guilhemMBED 0:a7c449cd2d5a 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
guilhemMBED 0:a7c449cd2d5a 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
guilhemMBED 0:a7c449cd2d5a 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
guilhemMBED 0:a7c449cd2d5a 32 * POSSIBILITY OF SUCH DAMAGE.
guilhemMBED 0:a7c449cd2d5a 33 *---------------------------------------------------------------------------*/
guilhemMBED 0:a7c449cd2d5a 34
guilhemMBED 0:a7c449cd2d5a 35 #include "cmsis.h"
guilhemMBED 0:a7c449cd2d5a 36 /* Definitions */
guilhemMBED 0:a7c449cd2d5a 37 #define INITIAL_xPSR 0x10000000
guilhemMBED 0:a7c449cd2d5a 38 #define DEMCR_TRCENA 0x01000000
guilhemMBED 0:a7c449cd2d5a 39 #define ITM_ITMENA 0x00000001
guilhemMBED 0:a7c449cd2d5a 40 #define MAGIC_WORD 0xE25A2EA5
guilhemMBED 0:a7c449cd2d5a 41
guilhemMBED 0:a7c449cd2d5a 42 #define SYS_TICK_IRQn TIMER0_IRQn
guilhemMBED 0:a7c449cd2d5a 43
guilhemMBED 0:a7c449cd2d5a 44 extern void rt_set_PSP (U32 stack);
guilhemMBED 0:a7c449cd2d5a 45 extern U32 rt_get_PSP (void);
guilhemMBED 0:a7c449cd2d5a 46 extern void os_set_env (void);
guilhemMBED 0:a7c449cd2d5a 47 extern void SysTick_Handler (void);
guilhemMBED 0:a7c449cd2d5a 48 extern void *_alloc_box (void *box_mem);
guilhemMBED 0:a7c449cd2d5a 49 extern int _free_box (void *box_mem, void *box);
guilhemMBED 0:a7c449cd2d5a 50
guilhemMBED 0:a7c449cd2d5a 51 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
guilhemMBED 0:a7c449cd2d5a 52 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
guilhemMBED 0:a7c449cd2d5a 53 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
guilhemMBED 0:a7c449cd2d5a 54
guilhemMBED 0:a7c449cd2d5a 55 extern void dbg_init (void);
guilhemMBED 0:a7c449cd2d5a 56 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
guilhemMBED 0:a7c449cd2d5a 57 extern void dbg_task_switch (U32 task_id);
guilhemMBED 0:a7c449cd2d5a 58
guilhemMBED 0:a7c449cd2d5a 59
guilhemMBED 0:a7c449cd2d5a 60 #if defined (__CC_ARM) /* ARM Compiler */
guilhemMBED 0:a7c449cd2d5a 61
guilhemMBED 0:a7c449cd2d5a 62 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
guilhemMBED 0:a7c449cd2d5a 63 #define __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 64 #else
guilhemMBED 0:a7c449cd2d5a 65 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 66 #endif
guilhemMBED 0:a7c449cd2d5a 67
guilhemMBED 0:a7c449cd2d5a 68 #elif defined (__GNUC__) /* GNU Compiler */
guilhemMBED 0:a7c449cd2d5a 69
guilhemMBED 0:a7c449cd2d5a 70 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 71
guilhemMBED 0:a7c449cd2d5a 72 #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
guilhemMBED 0:a7c449cd2d5a 73 #define __TARGET_ARCH_6S_M 1
guilhemMBED 0:a7c449cd2d5a 74 #else
guilhemMBED 0:a7c449cd2d5a 75 #define __TARGET_ARCH_6S_M 0
guilhemMBED 0:a7c449cd2d5a 76 #endif
guilhemMBED 0:a7c449cd2d5a 77
guilhemMBED 0:a7c449cd2d5a 78 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
guilhemMBED 0:a7c449cd2d5a 79 #define __TARGET_FPU_VFP 1
guilhemMBED 0:a7c449cd2d5a 80 #else
guilhemMBED 0:a7c449cd2d5a 81 #define __TARGET_FPU_VFP 0
guilhemMBED 0:a7c449cd2d5a 82 #endif
guilhemMBED 0:a7c449cd2d5a 83
guilhemMBED 0:a7c449cd2d5a 84 #define __inline inline
guilhemMBED 0:a7c449cd2d5a 85 #define __weak __attribute__((weak))
guilhemMBED 0:a7c449cd2d5a 86
guilhemMBED 0:a7c449cd2d5a 87
guilhemMBED 0:a7c449cd2d5a 88 #elif defined (__ICCARM__) /* IAR Compiler */
guilhemMBED 0:a7c449cd2d5a 89
guilhemMBED 0:a7c449cd2d5a 90 #undef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 91
guilhemMBED 0:a7c449cd2d5a 92 #if (__CORE__ == __ARM6M__)
guilhemMBED 0:a7c449cd2d5a 93 #define __TARGET_ARCH_6S_M 1
guilhemMBED 0:a7c449cd2d5a 94 #else
guilhemMBED 0:a7c449cd2d5a 95 #define __TARGET_ARCH_6S_M 0
guilhemMBED 0:a7c449cd2d5a 96 #endif
guilhemMBED 0:a7c449cd2d5a 97
guilhemMBED 0:a7c449cd2d5a 98 #if defined __ARMVFP__
guilhemMBED 0:a7c449cd2d5a 99 #define __TARGET_FPU_VFP 1
guilhemMBED 0:a7c449cd2d5a 100 #else
guilhemMBED 0:a7c449cd2d5a 101 #define __TARGET_FPU_VFP 0
guilhemMBED 0:a7c449cd2d5a 102 #endif
guilhemMBED 0:a7c449cd2d5a 103
guilhemMBED 0:a7c449cd2d5a 104 #define __inline inline
guilhemMBED 0:a7c449cd2d5a 105
guilhemMBED 0:a7c449cd2d5a 106 #endif
guilhemMBED 0:a7c449cd2d5a 107
guilhemMBED 0:a7c449cd2d5a 108
guilhemMBED 0:a7c449cd2d5a 109 /* NVIC registers */
guilhemMBED 0:a7c449cd2d5a 110
guilhemMBED 0:a7c449cd2d5a 111 #define OS_PEND_IRQ() NVIC_PendIRQ(SYS_TICK_IRQn)
guilhemMBED 0:a7c449cd2d5a 112 #define OS_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn)
guilhemMBED 0:a7c449cd2d5a 113 #define OS_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn)
guilhemMBED 0:a7c449cd2d5a 114 #define OS_PEND(fl,p) NVIC_PendIRQ(SYS_TICK_IRQn)
guilhemMBED 0:a7c449cd2d5a 115 #define OS_LOCK() NVIC_DisableIRQ(SYS_TICK_IRQn)
guilhemMBED 0:a7c449cd2d5a 116 #define OS_UNLOCK() NVIC_EnableIRQ(SYS_TICK_IRQn)
guilhemMBED 0:a7c449cd2d5a 117
guilhemMBED 0:a7c449cd2d5a 118 #define OS_X_PENDING NVIC_PendingIRQ(SYS_TICK_IRQn)
guilhemMBED 0:a7c449cd2d5a 119 #define OS_X_UNPEND(fl) NVIC_UnpendIRQ(SYS_TICK_IRQn)
guilhemMBED 0:a7c449cd2d5a 120 #define OS_X_PEND(fl,p) NVIC_PendIRQ(SYS_TICK_IRQn)
guilhemMBED 0:a7c449cd2d5a 121
guilhemMBED 0:a7c449cd2d5a 122 #define OS_X_INIT(n) NVIC_EnableIRQ(n)
guilhemMBED 0:a7c449cd2d5a 123 #define OS_X_LOCK(n) NVIC_DisableIRQ(n)
guilhemMBED 0:a7c449cd2d5a 124 #define OS_X_UNLOCK(n) NVIC_EnableIRQ(n)
guilhemMBED 0:a7c449cd2d5a 125
guilhemMBED 0:a7c449cd2d5a 126 /* Variables */
guilhemMBED 0:a7c449cd2d5a 127 extern BIT dbg_msg;
guilhemMBED 0:a7c449cd2d5a 128
guilhemMBED 0:a7c449cd2d5a 129 /* Functions */
guilhemMBED 0:a7c449cd2d5a 130 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 131 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
guilhemMBED 0:a7c449cd2d5a 132 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
guilhemMBED 0:a7c449cd2d5a 133 #else
guilhemMBED 0:a7c449cd2d5a 134 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
guilhemMBED 0:a7c449cd2d5a 135 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
guilhemMBED 0:a7c449cd2d5a 136 #endif
guilhemMBED 0:a7c449cd2d5a 137
guilhemMBED 0:a7c449cd2d5a 138 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
guilhemMBED 0:a7c449cd2d5a 139 U32 cnt,c2;
guilhemMBED 0:a7c449cd2d5a 140 #ifdef __USE_EXCLUSIVE_ACCESS
guilhemMBED 0:a7c449cd2d5a 141 do {
guilhemMBED 0:a7c449cd2d5a 142 if ((cnt = __ldrex(count)) == size) {
guilhemMBED 0:a7c449cd2d5a 143 __clrex();
guilhemMBED 0:a7c449cd2d5a 144 return (cnt); }
guilhemMBED 0:a7c449cd2d5a 145 } while (__strex(cnt+1, count));
guilhemMBED 0:a7c449cd2d5a 146 do {
guilhemMBED 0:a7c449cd2d5a 147 c2 = (cnt = __ldrex(first)) + 1;
guilhemMBED 0:a7c449cd2d5a 148 if (c2 == size) c2 = 0;
guilhemMBED 0:a7c449cd2d5a 149 } while (__strex(c2, first));
guilhemMBED 0:a7c449cd2d5a 150 #else
guilhemMBED 0:a7c449cd2d5a 151 __disable_irq();
guilhemMBED 0:a7c449cd2d5a 152 if ((cnt = *count) < size) {
guilhemMBED 0:a7c449cd2d5a 153 *count = cnt+1;
guilhemMBED 0:a7c449cd2d5a 154 c2 = (cnt = *first) + 1;
guilhemMBED 0:a7c449cd2d5a 155 if (c2 == size) c2 = 0;
guilhemMBED 0:a7c449cd2d5a 156 *first = c2;
guilhemMBED 0:a7c449cd2d5a 157 }
guilhemMBED 0:a7c449cd2d5a 158 __enable_irq ();
guilhemMBED 0:a7c449cd2d5a 159 #endif
guilhemMBED 0:a7c449cd2d5a 160 return (cnt);
guilhemMBED 0:a7c449cd2d5a 161 }
guilhemMBED 0:a7c449cd2d5a 162
guilhemMBED 0:a7c449cd2d5a 163 __inline static void rt_systick_init (void) {
guilhemMBED 0:a7c449cd2d5a 164 #if SYS_TICK_IRQn == TIMER0_IRQn
guilhemMBED 0:a7c449cd2d5a 165 #define SYS_TICK_TIMER LPC_TIM0
guilhemMBED 0:a7c449cd2d5a 166 LPC_SC->PCONP |= (1 << PCTIM0);
guilhemMBED 0:a7c449cd2d5a 167 LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<3))) | (1<<2); //PCLK == CPUCLK
guilhemMBED 0:a7c449cd2d5a 168 #elif SYS_TICK_IRQn == TIMER1_IRQn
guilhemMBED 0:a7c449cd2d5a 169 #define SYS_TICK_TIMER LPC_TIM1
guilhemMBED 0:a7c449cd2d5a 170 LPC_SC->PCONP |= (1 << PCTIM1);
guilhemMBED 0:a7c449cd2d5a 171 LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(1<<5))) | (1<<4); //PCLK == CPUCLK
guilhemMBED 0:a7c449cd2d5a 172 #elif SYS_TICK_IRQn == TIMER2_IRQn
guilhemMBED 0:a7c449cd2d5a 173 #define SYS_TICK_TIMER LPC_TIM2
guilhemMBED 0:a7c449cd2d5a 174 LPC_SC->PCONP |= (1 << PCTIM2);
guilhemMBED 0:a7c449cd2d5a 175 LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<13))) | (1<<12); //PCLK == CPUCLK
guilhemMBED 0:a7c449cd2d5a 176 #else
guilhemMBED 0:a7c449cd2d5a 177 #define SYS_TICK_TIMER LPC_TIM3
guilhemMBED 0:a7c449cd2d5a 178 LPC_SC->PCONP |= (1 << PCTIM3);
guilhemMBED 0:a7c449cd2d5a 179 LPC_SC->PCLKSEL1 = (LPC_SC->PCLKSEL1 & (~(1<<15))) | (1<<14); //PCLK == CPUCLK
guilhemMBED 0:a7c449cd2d5a 180 #endif
guilhemMBED 0:a7c449cd2d5a 181
guilhemMBED 0:a7c449cd2d5a 182 // setup Timer to count forever
guilhemMBED 0:a7c449cd2d5a 183 //interrupt_reg
guilhemMBED 0:a7c449cd2d5a 184 SYS_TICK_TIMER->TCR = 2; // reset & disable timer 0
guilhemMBED 0:a7c449cd2d5a 185 SYS_TICK_TIMER->TC = os_trv;
guilhemMBED 0:a7c449cd2d5a 186 SYS_TICK_TIMER->PR = 0; // set the prescale divider
guilhemMBED 0:a7c449cd2d5a 187 //Reset of TC and Interrupt when MR3 MR2 matches TC
guilhemMBED 0:a7c449cd2d5a 188 SYS_TICK_TIMER->MCR = (1 << 9) |(1 << 10); //TMCR_MR3_R_Msk | TMCR_MR3_I_Msk
guilhemMBED 0:a7c449cd2d5a 189 SYS_TICK_TIMER->MR3 = os_trv; // match registers
guilhemMBED 0:a7c449cd2d5a 190 SYS_TICK_TIMER->CCR = 0; // disable compare registers
guilhemMBED 0:a7c449cd2d5a 191 SYS_TICK_TIMER->EMR = 0; // disable external match register
guilhemMBED 0:a7c449cd2d5a 192 // initialize the interrupt vector
guilhemMBED 0:a7c449cd2d5a 193 NVIC_SetVector(SYS_TICK_IRQn, (uint32_t)&SysTick_Handler);
guilhemMBED 0:a7c449cd2d5a 194 SYS_TICK_TIMER->TCR = 1; // enable timer 0
guilhemMBED 0:a7c449cd2d5a 195 }
guilhemMBED 0:a7c449cd2d5a 196
guilhemMBED 0:a7c449cd2d5a 197 __inline static void rt_svc_init (void) {
guilhemMBED 0:a7c449cd2d5a 198 // TODO: add svcInit
guilhemMBED 0:a7c449cd2d5a 199
guilhemMBED 0:a7c449cd2d5a 200 }
guilhemMBED 0:a7c449cd2d5a 201
guilhemMBED 0:a7c449cd2d5a 202 #ifdef DBG_MSG
guilhemMBED 0:a7c449cd2d5a 203 #define DBG_INIT() dbg_init()
guilhemMBED 0:a7c449cd2d5a 204 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
guilhemMBED 0:a7c449cd2d5a 205 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
guilhemMBED 0:a7c449cd2d5a 206 dbg_task_switch(task_id)
guilhemMBED 0:a7c449cd2d5a 207 #else
guilhemMBED 0:a7c449cd2d5a 208 #define DBG_INIT()
guilhemMBED 0:a7c449cd2d5a 209 #define DBG_TASK_NOTIFY(p_tcb,create)
guilhemMBED 0:a7c449cd2d5a 210 #define DBG_TASK_SWITCH(task_id)
guilhemMBED 0:a7c449cd2d5a 211 #endif
guilhemMBED 0:a7c449cd2d5a 212
guilhemMBED 0:a7c449cd2d5a 213 /*----------------------------------------------------------------------------
guilhemMBED 0:a7c449cd2d5a 214 * end of file
guilhemMBED 0:a7c449cd2d5a 215 *---------------------------------------------------------------------------*/
guilhemMBED 0:a7c449cd2d5a 216