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Dependents:   MX106-finaltest

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c@552:a1b9575155a3, 2015-05-27 (annotated)

Committer:
mbed_official
Date:
Wed May 27 13:30:08 2015 +0100
Revision:
552:a1b9575155a3
Parent:
445:3312ed629f01
Child:
620:49241b7c6da5
Synchronized with git revision a74a8f14fd8c4bf3dc09980c4bf9498ebcf4c207



Full URL: https://github.com/mbedmicro/mbed/commit/a74a8f14fd8c4bf3dc09980c4bf9498ebcf4c207/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 445:3312ed629f01 1 /* mbed Microcontroller Library
mbed_official 445:3312ed629f01 2 * Copyright (c) 2015 ARM Limited
mbed_official 445:3312ed629f01 3 *
mbed_official 445:3312ed629f01 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 445:3312ed629f01 5 * you may not use this file except in compliance with the License.
mbed_official 445:3312ed629f01 6 * You may obtain a copy of the License at
mbed_official 445:3312ed629f01 7 *
mbed_official 445:3312ed629f01 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 445:3312ed629f01 9 *
mbed_official 445:3312ed629f01 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 445:3312ed629f01 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 445:3312ed629f01 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 445:3312ed629f01 13 * See the License for the specific language governing permissions and
mbed_official 445:3312ed629f01 14 * limitations under the License.
mbed_official 445:3312ed629f01 15 */
mbed_official 445:3312ed629f01 16 #include "mbed_assert.h"
mbed_official 445:3312ed629f01 17 #include "spi_api.h"
mbed_official 445:3312ed629f01 18
mbed_official 445:3312ed629f01 19 #include <math.h>
mbed_official 445:3312ed629f01 20
mbed_official 445:3312ed629f01 21 #include "cmsis.h"
mbed_official 445:3312ed629f01 22 #include "pinmap.h"
mbed_official 445:3312ed629f01 23 #include "clk_freqs.h"
mbed_official 445:3312ed629f01 24 #include "PeripheralPins.h"
mbed_official 445:3312ed629f01 25
mbed_official 445:3312ed629f01 26 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
mbed_official 445:3312ed629f01 27 // determine the SPI to use
mbed_official 445:3312ed629f01 28 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
mbed_official 445:3312ed629f01 29 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
mbed_official 445:3312ed629f01 30 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
mbed_official 445:3312ed629f01 31 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
mbed_official 445:3312ed629f01 32 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
mbed_official 445:3312ed629f01 33 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
mbed_official 445:3312ed629f01 34
mbed_official 445:3312ed629f01 35 obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
mbed_official 445:3312ed629f01 36 MBED_ASSERT((int)obj->spi != NC);
mbed_official 445:3312ed629f01 37
mbed_official 445:3312ed629f01 38 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK;
mbed_official 445:3312ed629f01 39 SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
mbed_official 445:3312ed629f01 40
mbed_official 445:3312ed629f01 41 obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK);
mbed_official 445:3312ed629f01 42 //obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK;
mbed_official 445:3312ed629f01 43
mbed_official 445:3312ed629f01 44 // not halt in the debug mode
mbed_official 445:3312ed629f01 45 obj->spi->SR |= SPI_SR_EOQF_MASK;
mbed_official 445:3312ed629f01 46
mbed_official 445:3312ed629f01 47 // pin out the spi pins
mbed_official 445:3312ed629f01 48 pinmap_pinout(mosi, PinMap_SPI_MOSI);
mbed_official 445:3312ed629f01 49 pinmap_pinout(miso, PinMap_SPI_MISO);
mbed_official 445:3312ed629f01 50 pinmap_pinout(sclk, PinMap_SPI_SCLK);
mbed_official 445:3312ed629f01 51 if (ssel != NC) {
mbed_official 445:3312ed629f01 52 pinmap_pinout(ssel, PinMap_SPI_SSEL);
mbed_official 445:3312ed629f01 53 }
mbed_official 445:3312ed629f01 54 }
mbed_official 445:3312ed629f01 55
mbed_official 445:3312ed629f01 56 void spi_free(spi_t *obj) {
mbed_official 445:3312ed629f01 57 // [TODO]
mbed_official 445:3312ed629f01 58 }
mbed_official 445:3312ed629f01 59 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 445:3312ed629f01 60 MBED_ASSERT((bits > 4) || (bits < 16));
mbed_official 445:3312ed629f01 61 MBED_ASSERT((mode >= 0) && (mode <= 3));
mbed_official 445:3312ed629f01 62
mbed_official 445:3312ed629f01 63 uint32_t polarity = (mode & 0x2) ? 1 : 0;
mbed_official 445:3312ed629f01 64 uint32_t phase = (mode & 0x1) ? 1 : 0;
mbed_official 445:3312ed629f01 65
mbed_official 445:3312ed629f01 66 // set master/slave
mbed_official 445:3312ed629f01 67 obj->spi->MCR &= ~SPI_MCR_MSTR_MASK;
mbed_official 445:3312ed629f01 68 obj->spi->MCR |= ((!slave) << SPI_MCR_MSTR_SHIFT);
mbed_official 445:3312ed629f01 69
mbed_official 445:3312ed629f01 70 // CTAR0 is used
mbed_official 445:3312ed629f01 71 obj->spi->CTAR[0] &= ~(SPI_CTAR_CPHA_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_FMSZ_MASK);
mbed_official 445:3312ed629f01 72 obj->spi->CTAR[0] |= (polarity << SPI_CTAR_CPOL_SHIFT) | (phase << SPI_CTAR_CPHA_SHIFT) | ((bits - 1) << SPI_CTAR_FMSZ_SHIFT);
mbed_official 445:3312ed629f01 73 }
mbed_official 445:3312ed629f01 74
mbed_official 445:3312ed629f01 75 static const uint8_t baudrate_prescaler[] = {2,3,5,7};
mbed_official 445:3312ed629f01 76 static const uint16_t baudrate_scaler[] = {2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768};
mbed_official 445:3312ed629f01 77
mbed_official 445:3312ed629f01 78 void spi_frequency(spi_t *obj, int hz) {
mbed_official 445:3312ed629f01 79 uint32_t f_error = 0;
mbed_official 445:3312ed629f01 80 uint32_t p_error = 0xffffffff;
mbed_official 445:3312ed629f01 81 uint32_t ref = 0;
mbed_official 445:3312ed629f01 82 uint32_t br = 0;
mbed_official 445:3312ed629f01 83 uint32_t ref_spr = 0;
mbed_official 445:3312ed629f01 84 uint32_t ref_prescaler = 0;
mbed_official 445:3312ed629f01 85 uint32_t ref_dr = 0;
mbed_official 445:3312ed629f01 86
mbed_official 445:3312ed629f01 87 // bus clk
mbed_official 445:3312ed629f01 88 uint32_t PCLK = bus_frequency();
mbed_official 445:3312ed629f01 89
mbed_official 445:3312ed629f01 90 for (uint32_t i = 0; i < 4; i++) {
mbed_official 445:3312ed629f01 91 for (br = 0; br <= 15; br++) {
mbed_official 445:3312ed629f01 92 for (uint32_t dr = 0; dr < 2; dr++) {
mbed_official 445:3312ed629f01 93 ref = (PCLK * (1U + dr) / baudrate_prescaler[i]) / baudrate_scaler[br];
mbed_official 445:3312ed629f01 94 if (ref > (uint32_t)hz)
mbed_official 445:3312ed629f01 95 continue;
mbed_official 445:3312ed629f01 96 f_error = hz - ref;
mbed_official 445:3312ed629f01 97 if (f_error < p_error) {
mbed_official 445:3312ed629f01 98 ref_spr = br;
mbed_official 445:3312ed629f01 99 ref_prescaler = i;
mbed_official 445:3312ed629f01 100 ref_dr = dr;
mbed_official 445:3312ed629f01 101 p_error = f_error;
mbed_official 445:3312ed629f01 102 }
mbed_official 445:3312ed629f01 103 }
mbed_official 445:3312ed629f01 104 }
mbed_official 445:3312ed629f01 105 }
mbed_official 445:3312ed629f01 106
mbed_official 445:3312ed629f01 107 // set PBR and BR
mbed_official 445:3312ed629f01 108 obj->spi->CTAR[0] &= ~(SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK | SPI_CTAR_DBR_MASK);
mbed_official 445:3312ed629f01 109 obj->spi->CTAR[0] |= (ref_prescaler << SPI_CTAR_PBR_SHIFT) | (ref_spr << SPI_CTAR_BR_SHIFT) | (ref_dr << SPI_CTAR_DBR_SHIFT);
mbed_official 445:3312ed629f01 110 }
mbed_official 445:3312ed629f01 111
mbed_official 445:3312ed629f01 112 static inline int spi_writeable(spi_t *obj) {
mbed_official 445:3312ed629f01 113 return (obj->spi->SR & SPI_SR_TFFF_MASK) ? 1 : 0;
mbed_official 445:3312ed629f01 114 }
mbed_official 445:3312ed629f01 115
mbed_official 445:3312ed629f01 116 static inline int spi_readable(spi_t *obj) {
mbed_official 445:3312ed629f01 117 return (obj->spi->SR & SPI_SR_RFDF_MASK) ? 1 : 0;
mbed_official 445:3312ed629f01 118 }
mbed_official 445:3312ed629f01 119
mbed_official 445:3312ed629f01 120 int spi_master_write(spi_t *obj, int value) {
mbed_official 445:3312ed629f01 121 //clear RX buffer flag
mbed_official 445:3312ed629f01 122 obj->spi->SR |= SPI_SR_RFDF_MASK;
mbed_official 445:3312ed629f01 123 // wait tx buffer empty
mbed_official 445:3312ed629f01 124 while(!spi_writeable(obj));
mbed_official 445:3312ed629f01 125 obj->spi->PUSHR = SPI_PUSHR_TXDATA(value & 0xffff) /*| SPI_PUSHR_EOQ_MASK*/;
mbed_official 445:3312ed629f01 126
mbed_official 445:3312ed629f01 127 // wait rx buffer full
mbed_official 445:3312ed629f01 128 while (!spi_readable(obj));
mbed_official 445:3312ed629f01 129 return obj->spi->POPR;
mbed_official 445:3312ed629f01 130 }
mbed_official 445:3312ed629f01 131
mbed_official 445:3312ed629f01 132 int spi_slave_receive(spi_t *obj) {
mbed_official 445:3312ed629f01 133 return spi_readable(obj);
mbed_official 445:3312ed629f01 134 }
mbed_official 445:3312ed629f01 135
mbed_official 445:3312ed629f01 136 int spi_slave_read(spi_t *obj) {
mbed_official 445:3312ed629f01 137 obj->spi->SR |= SPI_SR_RFDF_MASK;
mbed_official 445:3312ed629f01 138 return obj->spi->POPR;
mbed_official 445:3312ed629f01 139 }
mbed_official 445:3312ed629f01 140
mbed_official 445:3312ed629f01 141 void spi_slave_write(spi_t *obj, int value) {
mbed_official 445:3312ed629f01 142 while (!spi_writeable(obj));
mbed_official 445:3312ed629f01 143 }