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targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c@520:7182721120da, 2015-04-23 (annotated)

Committer:
mbed_official
Date:
Thu Apr 23 08:00:08 2015 +0100
Revision:
520:7182721120da
Parent:
494:41cd0bfadcd0
Child:
531:47d2b67c511f
Synchronized with git revision b73059c798bfc528a56a32338beda95fafea4cdf



Full URL: https://github.com/mbedmicro/mbed/commit/b73059c798bfc528a56a32338beda95fafea4cdf/



STM32 - Fix HSE/HSI clk source detection

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 494:41cd0bfadcd0 1 /**
mbed_official 494:41cd0bfadcd0 2 ******************************************************************************
mbed_official 494:41cd0bfadcd0 3 * @file system_stm32l0xx.c
mbed_official 494:41cd0bfadcd0 4 * @author MCD Application Team
mbed_official 494:41cd0bfadcd0 5 * @version V1.2.0
mbed_official 494:41cd0bfadcd0 6 * @date 06-February-2015
mbed_official 494:41cd0bfadcd0 7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
mbed_official 494:41cd0bfadcd0 8 *
mbed_official 494:41cd0bfadcd0 9 * This file provides two functions and one global variable to be called from
mbed_official 494:41cd0bfadcd0 10 * user application:
mbed_official 494:41cd0bfadcd0 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 494:41cd0bfadcd0 12 * before branch to main program. This call is made inside
mbed_official 494:41cd0bfadcd0 13 * the "startup_stm32l0xx.s" file.
mbed_official 494:41cd0bfadcd0 14 *
mbed_official 494:41cd0bfadcd0 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 494:41cd0bfadcd0 16 * by the user application to setup the SysTick
mbed_official 494:41cd0bfadcd0 17 * timer or configure other parameters.
mbed_official 494:41cd0bfadcd0 18 *
mbed_official 494:41cd0bfadcd0 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 494:41cd0bfadcd0 20 * be called whenever the core clock is changed
mbed_official 494:41cd0bfadcd0 21 * during program execution.
mbed_official 494:41cd0bfadcd0 22 *
mbed_official 494:41cd0bfadcd0 23 * This file configures the system clock as follows:
mbed_official 494:41cd0bfadcd0 24 *-----------------------------------------------------------------------------
mbed_official 494:41cd0bfadcd0 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 494:41cd0bfadcd0 26 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 494:41cd0bfadcd0 27 * | 2- PLL_HSE_XTAL |
mbed_official 494:41cd0bfadcd0 28 * | (external 8 MHz xtal) |
mbed_official 494:41cd0bfadcd0 29 *-----------------------------------------------------------------------------
mbed_official 494:41cd0bfadcd0 30 * SYSCLK(MHz) | 32 | 32
mbed_official 494:41cd0bfadcd0 31 *-----------------------------------------------------------------------------
mbed_official 494:41cd0bfadcd0 32 * AHBCLK (MHz) | 32 | 32
mbed_official 494:41cd0bfadcd0 33 *-----------------------------------------------------------------------------
mbed_official 494:41cd0bfadcd0 34 * APB1CLK (MHz) | 32 | 32
mbed_official 494:41cd0bfadcd0 35 *-----------------------------------------------------------------------------
mbed_official 494:41cd0bfadcd0 36 * APB2CLK (MHz) | 32 | 32
mbed_official 494:41cd0bfadcd0 37 *-----------------------------------------------------------------------------
mbed_official 494:41cd0bfadcd0 38 * USB capable (48 MHz precise clock) | YES | YES
mbed_official 494:41cd0bfadcd0 39 *-----------------------------------------------------------------------------
mbed_official 494:41cd0bfadcd0 40 ******************************************************************************
mbed_official 494:41cd0bfadcd0 41 * @attention
mbed_official 494:41cd0bfadcd0 42 *
mbed_official 494:41cd0bfadcd0 43 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 494:41cd0bfadcd0 44 *
mbed_official 494:41cd0bfadcd0 45 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 494:41cd0bfadcd0 46 * are permitted provided that the following conditions are met:
mbed_official 494:41cd0bfadcd0 47 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 494:41cd0bfadcd0 48 * this list of conditions and the following disclaimer.
mbed_official 494:41cd0bfadcd0 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 494:41cd0bfadcd0 50 * this list of conditions and the following disclaimer in the documentation
mbed_official 494:41cd0bfadcd0 51 * and/or other materials provided with the distribution.
mbed_official 494:41cd0bfadcd0 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 494:41cd0bfadcd0 53 * may be used to endorse or promote products derived from this software
mbed_official 494:41cd0bfadcd0 54 * without specific prior written permission.
mbed_official 494:41cd0bfadcd0 55 *
mbed_official 494:41cd0bfadcd0 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 494:41cd0bfadcd0 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 494:41cd0bfadcd0 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 494:41cd0bfadcd0 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 494:41cd0bfadcd0 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 494:41cd0bfadcd0 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 494:41cd0bfadcd0 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 494:41cd0bfadcd0 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 494:41cd0bfadcd0 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 494:41cd0bfadcd0 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 494:41cd0bfadcd0 66 *
mbed_official 494:41cd0bfadcd0 67 ******************************************************************************
mbed_official 494:41cd0bfadcd0 68 */
mbed_official 494:41cd0bfadcd0 69
mbed_official 494:41cd0bfadcd0 70 /** @addtogroup CMSIS
mbed_official 494:41cd0bfadcd0 71 * @{
mbed_official 494:41cd0bfadcd0 72 */
mbed_official 494:41cd0bfadcd0 73
mbed_official 494:41cd0bfadcd0 74 /** @addtogroup stm32l0xx_system
mbed_official 494:41cd0bfadcd0 75 * @{
mbed_official 494:41cd0bfadcd0 76 */
mbed_official 494:41cd0bfadcd0 77
mbed_official 494:41cd0bfadcd0 78 /** @addtogroup STM32L0xx_System_Private_Includes
mbed_official 494:41cd0bfadcd0 79 * @{
mbed_official 494:41cd0bfadcd0 80 */
mbed_official 494:41cd0bfadcd0 81
mbed_official 494:41cd0bfadcd0 82 #include "stm32l0xx.h"
mbed_official 494:41cd0bfadcd0 83 #include "hal_tick.h"
mbed_official 494:41cd0bfadcd0 84
mbed_official 494:41cd0bfadcd0 85 #if !defined (HSE_VALUE)
mbed_official 494:41cd0bfadcd0 86 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
mbed_official 494:41cd0bfadcd0 87 #endif /* HSE_VALUE */
mbed_official 494:41cd0bfadcd0 88
mbed_official 494:41cd0bfadcd0 89 #if !defined (MSI_VALUE)
mbed_official 494:41cd0bfadcd0 90 #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 494:41cd0bfadcd0 91 #endif /* MSI_VALUE */
mbed_official 494:41cd0bfadcd0 92
mbed_official 494:41cd0bfadcd0 93 #if !defined (HSI_VALUE)
mbed_official 494:41cd0bfadcd0 94 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 494:41cd0bfadcd0 95 #endif /* HSI_VALUE */
mbed_official 494:41cd0bfadcd0 96
mbed_official 494:41cd0bfadcd0 97
mbed_official 494:41cd0bfadcd0 98 /**
mbed_official 494:41cd0bfadcd0 99 * @}
mbed_official 494:41cd0bfadcd0 100 */
mbed_official 494:41cd0bfadcd0 101
mbed_official 494:41cd0bfadcd0 102 /** @addtogroup STM32L0xx_System_Private_TypesDefinitions
mbed_official 494:41cd0bfadcd0 103 * @{
mbed_official 494:41cd0bfadcd0 104 */
mbed_official 494:41cd0bfadcd0 105
mbed_official 494:41cd0bfadcd0 106 /**
mbed_official 494:41cd0bfadcd0 107 * @}
mbed_official 494:41cd0bfadcd0 108 */
mbed_official 494:41cd0bfadcd0 109
mbed_official 494:41cd0bfadcd0 110 /** @addtogroup STM32L0xx_System_Private_Defines
mbed_official 494:41cd0bfadcd0 111 * @{
mbed_official 494:41cd0bfadcd0 112 */
mbed_official 494:41cd0bfadcd0 113 /************************* Miscellaneous Configuration ************************/
mbed_official 494:41cd0bfadcd0 114
mbed_official 494:41cd0bfadcd0 115 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 494:41cd0bfadcd0 116 Internal SRAM. */
mbed_official 494:41cd0bfadcd0 117 /* #define VECT_TAB_SRAM */
mbed_official 494:41cd0bfadcd0 118 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 494:41cd0bfadcd0 119 This value must be a multiple of 0x200. */
mbed_official 494:41cd0bfadcd0 120 /******************************************************************************/
mbed_official 494:41cd0bfadcd0 121 /**
mbed_official 494:41cd0bfadcd0 122 * @}
mbed_official 494:41cd0bfadcd0 123 */
mbed_official 494:41cd0bfadcd0 124
mbed_official 494:41cd0bfadcd0 125 /** @addtogroup STM32L0xx_System_Private_Macros
mbed_official 494:41cd0bfadcd0 126 * @{
mbed_official 494:41cd0bfadcd0 127 */
mbed_official 494:41cd0bfadcd0 128
mbed_official 494:41cd0bfadcd0 129 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 494:41cd0bfadcd0 130 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 494:41cd0bfadcd0 131 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 494:41cd0bfadcd0 132
mbed_official 494:41cd0bfadcd0 133 /**
mbed_official 494:41cd0bfadcd0 134 * @}
mbed_official 494:41cd0bfadcd0 135 */
mbed_official 494:41cd0bfadcd0 136
mbed_official 494:41cd0bfadcd0 137 /** @addtogroup STM32L0xx_System_Private_Variables
mbed_official 494:41cd0bfadcd0 138 * @{
mbed_official 494:41cd0bfadcd0 139 */
mbed_official 494:41cd0bfadcd0 140 /* This variable is updated in three ways:
mbed_official 494:41cd0bfadcd0 141 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 494:41cd0bfadcd0 142 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 494:41cd0bfadcd0 143 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 494:41cd0bfadcd0 144 Note: If you use this function to configure the system clock; then there
mbed_official 494:41cd0bfadcd0 145 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 494:41cd0bfadcd0 146 variable is updated automatically.
mbed_official 494:41cd0bfadcd0 147 */
mbed_official 520:7182721120da 148 uint32_t SystemCoreClock = 32000000;
mbed_official 520:7182721120da 149 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 520:7182721120da 150 const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
mbed_official 494:41cd0bfadcd0 151
mbed_official 494:41cd0bfadcd0 152 /**
mbed_official 494:41cd0bfadcd0 153 * @}
mbed_official 494:41cd0bfadcd0 154 */
mbed_official 494:41cd0bfadcd0 155
mbed_official 494:41cd0bfadcd0 156 /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
mbed_official 494:41cd0bfadcd0 157 * @{
mbed_official 494:41cd0bfadcd0 158 */
mbed_official 494:41cd0bfadcd0 159
mbed_official 494:41cd0bfadcd0 160 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 494:41cd0bfadcd0 161 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 494:41cd0bfadcd0 162 #endif
mbed_official 494:41cd0bfadcd0 163
mbed_official 494:41cd0bfadcd0 164 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 494:41cd0bfadcd0 165
mbed_official 494:41cd0bfadcd0 166 /**
mbed_official 494:41cd0bfadcd0 167 * @}
mbed_official 494:41cd0bfadcd0 168 */
mbed_official 494:41cd0bfadcd0 169
mbed_official 494:41cd0bfadcd0 170 /** @addtogroup STM32L0xx_System_Private_Functions
mbed_official 494:41cd0bfadcd0 171 * @{
mbed_official 494:41cd0bfadcd0 172 */
mbed_official 494:41cd0bfadcd0 173
mbed_official 494:41cd0bfadcd0 174 /**
mbed_official 494:41cd0bfadcd0 175 * @brief Setup the microcontroller system.
mbed_official 494:41cd0bfadcd0 176 * @param None
mbed_official 494:41cd0bfadcd0 177 * @retval None
mbed_official 494:41cd0bfadcd0 178 */
mbed_official 494:41cd0bfadcd0 179 void SystemInit (void)
mbed_official 494:41cd0bfadcd0 180 {
mbed_official 494:41cd0bfadcd0 181 /*!< Set MSION bit */
mbed_official 494:41cd0bfadcd0 182 RCC->CR |= (uint32_t)0x00000100;
mbed_official 494:41cd0bfadcd0 183
mbed_official 494:41cd0bfadcd0 184 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
mbed_official 494:41cd0bfadcd0 185 RCC->CFGR &= (uint32_t) 0x88FF400C;
mbed_official 494:41cd0bfadcd0 186
mbed_official 494:41cd0bfadcd0 187 /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
mbed_official 494:41cd0bfadcd0 188 RCC->CR &= (uint32_t)0xFEF6FFF6;
mbed_official 494:41cd0bfadcd0 189
mbed_official 494:41cd0bfadcd0 190 /*!< Reset HSI48ON bit */
mbed_official 494:41cd0bfadcd0 191 RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
mbed_official 494:41cd0bfadcd0 192
mbed_official 494:41cd0bfadcd0 193 /*!< Reset HSEBYP bit */
mbed_official 494:41cd0bfadcd0 194 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 494:41cd0bfadcd0 195
mbed_official 494:41cd0bfadcd0 196 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
mbed_official 494:41cd0bfadcd0 197 RCC->CFGR &= (uint32_t)0xFF02FFFF;
mbed_official 494:41cd0bfadcd0 198
mbed_official 494:41cd0bfadcd0 199 /*!< Disable all interrupts */
mbed_official 494:41cd0bfadcd0 200 RCC->CIER = 0x00000000;
mbed_official 494:41cd0bfadcd0 201
mbed_official 494:41cd0bfadcd0 202 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 494:41cd0bfadcd0 203 #ifdef VECT_TAB_SRAM
mbed_official 494:41cd0bfadcd0 204 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 494:41cd0bfadcd0 205 #else
mbed_official 494:41cd0bfadcd0 206 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 494:41cd0bfadcd0 207 #endif
mbed_official 494:41cd0bfadcd0 208
mbed_official 494:41cd0bfadcd0 209 /* Configure the Cube driver */
mbed_official 494:41cd0bfadcd0 210 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
mbed_official 494:41cd0bfadcd0 211 HAL_Init();
mbed_official 494:41cd0bfadcd0 212
mbed_official 494:41cd0bfadcd0 213 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 494:41cd0bfadcd0 214 AHB/APBx prescalers and Flash settings */
mbed_official 494:41cd0bfadcd0 215 SetSysClock();
mbed_official 494:41cd0bfadcd0 216
mbed_official 494:41cd0bfadcd0 217 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 494:41cd0bfadcd0 218 TIM_MST_RESET_ON;
mbed_official 494:41cd0bfadcd0 219 TIM_MST_RESET_OFF;
mbed_official 494:41cd0bfadcd0 220 }
mbed_official 494:41cd0bfadcd0 221
mbed_official 494:41cd0bfadcd0 222 /**
mbed_official 494:41cd0bfadcd0 223 * @brief Update SystemCoreClock according to Clock Register Values
mbed_official 494:41cd0bfadcd0 224 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 494:41cd0bfadcd0 225 * be used by the user application to setup the SysTick timer or configure
mbed_official 494:41cd0bfadcd0 226 * other parameters.
mbed_official 494:41cd0bfadcd0 227 *
mbed_official 494:41cd0bfadcd0 228 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 494:41cd0bfadcd0 229 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 494:41cd0bfadcd0 230 * based on this variable will be incorrect.
mbed_official 494:41cd0bfadcd0 231 *
mbed_official 494:41cd0bfadcd0 232 * @note - The system frequency computed by this function is not the real
mbed_official 494:41cd0bfadcd0 233 * frequency in the chip. It is calculated based on the predefined
mbed_official 494:41cd0bfadcd0 234 * constant and the selected clock source:
mbed_official 494:41cd0bfadcd0 235 *
mbed_official 494:41cd0bfadcd0 236 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
mbed_official 494:41cd0bfadcd0 237 * value as defined by the MSI range.
mbed_official 494:41cd0bfadcd0 238 *
mbed_official 494:41cd0bfadcd0 239 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 494:41cd0bfadcd0 240 *
mbed_official 494:41cd0bfadcd0 241 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 494:41cd0bfadcd0 242 *
mbed_official 494:41cd0bfadcd0 243 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 494:41cd0bfadcd0 244 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 494:41cd0bfadcd0 245 *
mbed_official 494:41cd0bfadcd0 246 * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
mbed_official 494:41cd0bfadcd0 247 * 16 MHz) but the real value may vary depending on the variations
mbed_official 494:41cd0bfadcd0 248 * in voltage and temperature.
mbed_official 494:41cd0bfadcd0 249 *
mbed_official 494:41cd0bfadcd0 250 * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
mbed_official 494:41cd0bfadcd0 251 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 494:41cd0bfadcd0 252 * frequency of the crystal used. Otherwise, this function may
mbed_official 494:41cd0bfadcd0 253 * have wrong result.
mbed_official 494:41cd0bfadcd0 254 *
mbed_official 494:41cd0bfadcd0 255 * - The result of this function could be not correct when using fractional
mbed_official 494:41cd0bfadcd0 256 * value for HSE crystal.
mbed_official 494:41cd0bfadcd0 257 * @param None
mbed_official 494:41cd0bfadcd0 258 * @retval None
mbed_official 494:41cd0bfadcd0 259 */
mbed_official 494:41cd0bfadcd0 260 void SystemCoreClockUpdate (void)
mbed_official 494:41cd0bfadcd0 261 {
mbed_official 494:41cd0bfadcd0 262 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
mbed_official 494:41cd0bfadcd0 263
mbed_official 494:41cd0bfadcd0 264 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 494:41cd0bfadcd0 265 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 494:41cd0bfadcd0 266
mbed_official 494:41cd0bfadcd0 267 switch (tmp)
mbed_official 494:41cd0bfadcd0 268 {
mbed_official 494:41cd0bfadcd0 269 case 0x00: /* MSI used as system clock */
mbed_official 494:41cd0bfadcd0 270 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official 494:41cd0bfadcd0 271 SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official 494:41cd0bfadcd0 272 break;
mbed_official 494:41cd0bfadcd0 273 case 0x04: /* HSI used as system clock */
mbed_official 494:41cd0bfadcd0 274 SystemCoreClock = HSI_VALUE;
mbed_official 494:41cd0bfadcd0 275 break;
mbed_official 494:41cd0bfadcd0 276 case 0x08: /* HSE used as system clock */
mbed_official 494:41cd0bfadcd0 277 SystemCoreClock = HSE_VALUE;
mbed_official 494:41cd0bfadcd0 278 break;
mbed_official 494:41cd0bfadcd0 279 case 0x0C: /* PLL used as system clock */
mbed_official 494:41cd0bfadcd0 280 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 494:41cd0bfadcd0 281 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 494:41cd0bfadcd0 282 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
mbed_official 494:41cd0bfadcd0 283 pllmul = PLLMulTable[(pllmul >> 18)];
mbed_official 494:41cd0bfadcd0 284 plldiv = (plldiv >> 22) + 1;
mbed_official 494:41cd0bfadcd0 285
mbed_official 494:41cd0bfadcd0 286 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 494:41cd0bfadcd0 287
mbed_official 494:41cd0bfadcd0 288 if (pllsource == 0x00)
mbed_official 494:41cd0bfadcd0 289 {
mbed_official 494:41cd0bfadcd0 290 /* HSI oscillator clock selected as PLL clock entry */
mbed_official 494:41cd0bfadcd0 291 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official 494:41cd0bfadcd0 292 }
mbed_official 494:41cd0bfadcd0 293 else
mbed_official 494:41cd0bfadcd0 294 {
mbed_official 494:41cd0bfadcd0 295 /* HSE selected as PLL clock entry */
mbed_official 494:41cd0bfadcd0 296 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official 494:41cd0bfadcd0 297 }
mbed_official 494:41cd0bfadcd0 298 break;
mbed_official 494:41cd0bfadcd0 299 default: /* MSI used as system clock */
mbed_official 494:41cd0bfadcd0 300 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official 494:41cd0bfadcd0 301 SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official 494:41cd0bfadcd0 302 break;
mbed_official 494:41cd0bfadcd0 303 }
mbed_official 494:41cd0bfadcd0 304 /* Compute HCLK clock frequency --------------------------------------------*/
mbed_official 494:41cd0bfadcd0 305 /* Get HCLK prescaler */
mbed_official 494:41cd0bfadcd0 306 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 494:41cd0bfadcd0 307 /* HCLK clock frequency */
mbed_official 494:41cd0bfadcd0 308 SystemCoreClock >>= tmp;
mbed_official 494:41cd0bfadcd0 309 }
mbed_official 494:41cd0bfadcd0 310
mbed_official 494:41cd0bfadcd0 311 /**
mbed_official 494:41cd0bfadcd0 312 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 494:41cd0bfadcd0 313 * AHB/APBx prescalers and Flash settings
mbed_official 494:41cd0bfadcd0 314 * @note This function should be called only once the RCC clock configuration
mbed_official 494:41cd0bfadcd0 315 * is reset to the default reset state (done in SystemInit() function).
mbed_official 494:41cd0bfadcd0 316 * @param None
mbed_official 494:41cd0bfadcd0 317 * @retval None
mbed_official 494:41cd0bfadcd0 318 */
mbed_official 494:41cd0bfadcd0 319 void SetSysClock(void)
mbed_official 494:41cd0bfadcd0 320 {
mbed_official 494:41cd0bfadcd0 321 /* 1- Try to start with HSE and external clock */
mbed_official 494:41cd0bfadcd0 322 #if USE_PLL_HSE_EXTC != 0
mbed_official 494:41cd0bfadcd0 323 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 494:41cd0bfadcd0 324 #endif
mbed_official 494:41cd0bfadcd0 325 {
mbed_official 494:41cd0bfadcd0 326 /* 2- If fail try to start with HSE and external xtal */
mbed_official 494:41cd0bfadcd0 327 #if USE_PLL_HSE_XTAL != 0
mbed_official 494:41cd0bfadcd0 328 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 494:41cd0bfadcd0 329 #endif
mbed_official 494:41cd0bfadcd0 330 {
mbed_official 494:41cd0bfadcd0 331 /* 3- If fail start with HSI clock */
mbed_official 494:41cd0bfadcd0 332 if (SetSysClock_PLL_HSI() == 0)
mbed_official 494:41cd0bfadcd0 333 {
mbed_official 494:41cd0bfadcd0 334 while(1)
mbed_official 494:41cd0bfadcd0 335 {
mbed_official 494:41cd0bfadcd0 336 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 494:41cd0bfadcd0 337 }
mbed_official 494:41cd0bfadcd0 338 }
mbed_official 494:41cd0bfadcd0 339 }
mbed_official 494:41cd0bfadcd0 340 }
mbed_official 494:41cd0bfadcd0 341
mbed_official 494:41cd0bfadcd0 342 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 494:41cd0bfadcd0 343 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
mbed_official 494:41cd0bfadcd0 344 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
mbed_official 494:41cd0bfadcd0 345 }
mbed_official 494:41cd0bfadcd0 346
mbed_official 494:41cd0bfadcd0 347 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 494:41cd0bfadcd0 348 /******************************************************************************/
mbed_official 494:41cd0bfadcd0 349 /* PLL (clocked by HSE) used as System clock source */
mbed_official 494:41cd0bfadcd0 350 /******************************************************************************/
mbed_official 494:41cd0bfadcd0 351 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 494:41cd0bfadcd0 352 {
mbed_official 494:41cd0bfadcd0 353 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 494:41cd0bfadcd0 354 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 494:41cd0bfadcd0 355
mbed_official 494:41cd0bfadcd0 356 /* Used to gain time after DeepSleep in case HSI is used */
mbed_official 494:41cd0bfadcd0 357 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official 494:41cd0bfadcd0 358 {
mbed_official 494:41cd0bfadcd0 359 return 0;
mbed_official 494:41cd0bfadcd0 360 }
mbed_official 494:41cd0bfadcd0 361
mbed_official 494:41cd0bfadcd0 362 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 494:41cd0bfadcd0 363 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 494:41cd0bfadcd0 364 regarding system frequency refer to product datasheet. */
mbed_official 494:41cd0bfadcd0 365 __PWR_CLK_ENABLE();
mbed_official 494:41cd0bfadcd0 366 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official 494:41cd0bfadcd0 367
mbed_official 494:41cd0bfadcd0 368 /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
mbed_official 494:41cd0bfadcd0 369 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
mbed_official 494:41cd0bfadcd0 370 if (bypass == 0)
mbed_official 494:41cd0bfadcd0 371 {
mbed_official 494:41cd0bfadcd0 372 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 494:41cd0bfadcd0 373 }
mbed_official 494:41cd0bfadcd0 374 else
mbed_official 494:41cd0bfadcd0 375 {
mbed_official 494:41cd0bfadcd0 376 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 494:41cd0bfadcd0 377 }
mbed_official 494:41cd0bfadcd0 378 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
mbed_official 494:41cd0bfadcd0 379 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
mbed_official 494:41cd0bfadcd0 380 // PLLCLK = (8 MHz * 8)/2 = 32 MHz
mbed_official 494:41cd0bfadcd0 381 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 494:41cd0bfadcd0 382 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 494:41cd0bfadcd0 383 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8;
mbed_official 494:41cd0bfadcd0 384 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
mbed_official 494:41cd0bfadcd0 385 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 494:41cd0bfadcd0 386 {
mbed_official 494:41cd0bfadcd0 387 return 0; // FAIL
mbed_official 494:41cd0bfadcd0 388 }
mbed_official 494:41cd0bfadcd0 389
mbed_official 494:41cd0bfadcd0 390 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 494:41cd0bfadcd0 391 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 494:41cd0bfadcd0 392 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official 494:41cd0bfadcd0 393 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official 494:41cd0bfadcd0 394 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 494:41cd0bfadcd0 395 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 494:41cd0bfadcd0 396 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official 494:41cd0bfadcd0 397 {
mbed_official 494:41cd0bfadcd0 398 return 0; // FAIL
mbed_official 494:41cd0bfadcd0 399 }
mbed_official 494:41cd0bfadcd0 400
mbed_official 494:41cd0bfadcd0 401 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 494:41cd0bfadcd0 402 //if (bypass == 0)
mbed_official 494:41cd0bfadcd0 403 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
mbed_official 494:41cd0bfadcd0 404 //else
mbed_official 494:41cd0bfadcd0 405 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
mbed_official 494:41cd0bfadcd0 406
mbed_official 494:41cd0bfadcd0 407 return 1; // OK
mbed_official 494:41cd0bfadcd0 408 }
mbed_official 494:41cd0bfadcd0 409 #endif
mbed_official 494:41cd0bfadcd0 410
mbed_official 494:41cd0bfadcd0 411 /******************************************************************************/
mbed_official 494:41cd0bfadcd0 412 /* PLL (clocked by HSI) used as System clock source */
mbed_official 494:41cd0bfadcd0 413 /******************************************************************************/
mbed_official 494:41cd0bfadcd0 414 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 494:41cd0bfadcd0 415 {
mbed_official 494:41cd0bfadcd0 416 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 494:41cd0bfadcd0 417 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 494:41cd0bfadcd0 418
mbed_official 494:41cd0bfadcd0 419 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 494:41cd0bfadcd0 420 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 494:41cd0bfadcd0 421 regarding system frequency refer to product datasheet. */
mbed_official 494:41cd0bfadcd0 422 __PWR_CLK_ENABLE();
mbed_official 494:41cd0bfadcd0 423 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official 494:41cd0bfadcd0 424
mbed_official 494:41cd0bfadcd0 425 /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
mbed_official 494:41cd0bfadcd0 426 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
mbed_official 494:41cd0bfadcd0 427 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 494:41cd0bfadcd0 428 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 494:41cd0bfadcd0 429 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
mbed_official 494:41cd0bfadcd0 430 // PLLCLK = (16 MHz * 4)/2 = 32 MHz
mbed_official 494:41cd0bfadcd0 431 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 494:41cd0bfadcd0 432 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 494:41cd0bfadcd0 433 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
mbed_official 494:41cd0bfadcd0 434 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
mbed_official 494:41cd0bfadcd0 435 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 494:41cd0bfadcd0 436 {
mbed_official 494:41cd0bfadcd0 437 return 0; // FAIL
mbed_official 494:41cd0bfadcd0 438 }
mbed_official 494:41cd0bfadcd0 439
mbed_official 494:41cd0bfadcd0 440 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 494:41cd0bfadcd0 441 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 494:41cd0bfadcd0 442 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official 494:41cd0bfadcd0 443 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official 494:41cd0bfadcd0 444 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 494:41cd0bfadcd0 445 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 494:41cd0bfadcd0 446 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official 494:41cd0bfadcd0 447 {
mbed_official 494:41cd0bfadcd0 448 return 0; // FAIL
mbed_official 494:41cd0bfadcd0 449 }
mbed_official 494:41cd0bfadcd0 450
mbed_official 494:41cd0bfadcd0 451 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 494:41cd0bfadcd0 452 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 494:41cd0bfadcd0 453
mbed_official 494:41cd0bfadcd0 454 return 1; // OK
mbed_official 494:41cd0bfadcd0 455 }
mbed_official 494:41cd0bfadcd0 456
mbed_official 494:41cd0bfadcd0 457 /**
mbed_official 494:41cd0bfadcd0 458 * @}
mbed_official 494:41cd0bfadcd0 459 */
mbed_official 494:41cd0bfadcd0 460
mbed_official 494:41cd0bfadcd0 461 /**
mbed_official 494:41cd0bfadcd0 462 * @}
mbed_official 494:41cd0bfadcd0 463 */
mbed_official 494:41cd0bfadcd0 464
mbed_official 494:41cd0bfadcd0 465 /**
mbed_official 494:41cd0bfadcd0 466 * @}
mbed_official 494:41cd0bfadcd0 467 */
mbed_official 494:41cd0bfadcd0 468
mbed_official 494:41cd0bfadcd0 469 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/