TUKS-COURSE-TIMER

TUKS MCU Introductory course » Code » TUKS-COURSE-TIMER

TUKS MCU Introductory course / TUKS-COURSE-TIMER

HAL_L476/stm32l4xx_hal_rcc.c@1:d0dfbce63a89, 2017-02-24 (annotated)

Committer:: elmot
Date:: Fri Feb 24 21:13:56 2017 +0000
Revision:: 1:d0dfbce63a89

Ready-to-copy

Who changed what in which revision?

User	Revision	Line number	New contents of line
elmot	1:d0dfbce63a89	1	/**
elmot	1:d0dfbce63a89	2	******************************************************************************
elmot	1:d0dfbce63a89	3	* @file stm32l4xx_hal_rcc.c
elmot	1:d0dfbce63a89	4	* @author MCD Application Team
elmot	1:d0dfbce63a89	5	* @version V1.5.1
elmot	1:d0dfbce63a89	6	* @date 31-May-2016
elmot	1:d0dfbce63a89	7	* @brief RCC HAL module driver.
elmot	1:d0dfbce63a89	8	* This file provides firmware functions to manage the following
elmot	1:d0dfbce63a89	9	* functionalities of the Reset and Clock Control (RCC) peripheral:
elmot	1:d0dfbce63a89	10	* + Initialization and de-initialization functions
elmot	1:d0dfbce63a89	11	* + Peripheral Control functions
elmot	1:d0dfbce63a89	12	*
elmot	1:d0dfbce63a89	13	@verbatim
elmot	1:d0dfbce63a89	14	==============================================================================
elmot	1:d0dfbce63a89	15	##### RCC specific features #####
elmot	1:d0dfbce63a89	16	==============================================================================
elmot	1:d0dfbce63a89	17	[..]
elmot	1:d0dfbce63a89	18	After reset the device is running from Multiple Speed Internal oscillator
elmot	1:d0dfbce63a89	19	(4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
elmot	1:d0dfbce63a89	20	and I-Cache are disabled, and all peripherals are off except internal
elmot	1:d0dfbce63a89	21	SRAM, Flash and JTAG.
elmot	1:d0dfbce63a89	22
elmot	1:d0dfbce63a89	23	(+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
elmot	1:d0dfbce63a89	24	all peripherals mapped on these busses are running at MSI speed.
elmot	1:d0dfbce63a89	25	(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
elmot	1:d0dfbce63a89	26	(+) All GPIOs are in analog mode, except the JTAG pins which
elmot	1:d0dfbce63a89	27	are assigned to be used for debug purpose.
elmot	1:d0dfbce63a89	28
elmot	1:d0dfbce63a89	29	[..]
elmot	1:d0dfbce63a89	30	Once the device started from reset, the user application has to:
elmot	1:d0dfbce63a89	31	(+) Configure the clock source to be used to drive the System clock
elmot	1:d0dfbce63a89	32	(if the application needs higher frequency/performance)
elmot	1:d0dfbce63a89	33	(+) Configure the System clock frequency and Flash settings
elmot	1:d0dfbce63a89	34	(+) Configure the AHB and APB busses prescalers
elmot	1:d0dfbce63a89	35	(+) Enable the clock for the peripheral(s) to be used
elmot	1:d0dfbce63a89	36	(+) Configure the clock source(s) for peripherals which clocks are not
elmot	1:d0dfbce63a89	37	derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG)
elmot	1:d0dfbce63a89	38
elmot	1:d0dfbce63a89	39	@endverbatim
elmot	1:d0dfbce63a89	40	******************************************************************************
elmot	1:d0dfbce63a89	41	* @attention
elmot	1:d0dfbce63a89	42	*
elmot	1:d0dfbce63a89	43	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot	1:d0dfbce63a89	44	*
elmot	1:d0dfbce63a89	45	* Redistribution and use in source and binary forms, with or without modification,
elmot	1:d0dfbce63a89	46	* are permitted provided that the following conditions are met:
elmot	1:d0dfbce63a89	47	* 1. Redistributions of source code must retain the above copyright notice,
elmot	1:d0dfbce63a89	48	* this list of conditions and the following disclaimer.
elmot	1:d0dfbce63a89	49	* 2. Redistributions in binary form must reproduce the above copyright notice,
elmot	1:d0dfbce63a89	50	* this list of conditions and the following disclaimer in the documentation
elmot	1:d0dfbce63a89	51	* and/or other materials provided with the distribution.
elmot	1:d0dfbce63a89	52	* 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot	1:d0dfbce63a89	53	* may be used to endorse or promote products derived from this software
elmot	1:d0dfbce63a89	54	* without specific prior written permission.
elmot	1:d0dfbce63a89	55	*
elmot	1:d0dfbce63a89	56	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot	1:d0dfbce63a89	57	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot	1:d0dfbce63a89	58	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot	1:d0dfbce63a89	59	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot	1:d0dfbce63a89	60	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot	1:d0dfbce63a89	61	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot	1:d0dfbce63a89	62	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot	1:d0dfbce63a89	63	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot	1:d0dfbce63a89	64	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot	1:d0dfbce63a89	65	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot	1:d0dfbce63a89	66	*
elmot	1:d0dfbce63a89	67	******************************************************************************
elmot	1:d0dfbce63a89	68	*/
elmot	1:d0dfbce63a89	69
elmot	1:d0dfbce63a89	70	/* Includes ------------------------------------------------------------------*/
elmot	1:d0dfbce63a89	71	#include "stm32l4xx_hal.h"
elmot	1:d0dfbce63a89	72
elmot	1:d0dfbce63a89	73	/** @addtogroup STM32L4xx_HAL_Driver
elmot	1:d0dfbce63a89	74	* @{
elmot	1:d0dfbce63a89	75	*/
elmot	1:d0dfbce63a89	76
elmot	1:d0dfbce63a89	77	/** @defgroup RCC RCC
elmot	1:d0dfbce63a89	78	* @brief RCC HAL module driver
elmot	1:d0dfbce63a89	79	* @{
elmot	1:d0dfbce63a89	80	*/
elmot	1:d0dfbce63a89	81
elmot	1:d0dfbce63a89	82	#ifdef HAL_RCC_MODULE_ENABLED
elmot	1:d0dfbce63a89	83
elmot	1:d0dfbce63a89	84	/* Private typedef -----------------------------------------------------------*/
elmot	1:d0dfbce63a89	85	/* Private define ------------------------------------------------------------*/
elmot	1:d0dfbce63a89	86	/** @defgroup RCC_Private_Constants RCC Private Constants
elmot	1:d0dfbce63a89	87	* @{
elmot	1:d0dfbce63a89	88	*/
elmot	1:d0dfbce63a89	89	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
elmot	1:d0dfbce63a89	90	#define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
elmot	1:d0dfbce63a89	91	#define MSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
elmot	1:d0dfbce63a89	92	#define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
elmot	1:d0dfbce63a89	93	#define HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
elmot	1:d0dfbce63a89	94	#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
elmot	1:d0dfbce63a89	95	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
elmot	1:d0dfbce63a89	96	/**
elmot	1:d0dfbce63a89	97	* @}
elmot	1:d0dfbce63a89	98	*/
elmot	1:d0dfbce63a89	99
elmot	1:d0dfbce63a89	100	/* Private macro -------------------------------------------------------------*/
elmot	1:d0dfbce63a89	101	/** @defgroup RCC_Private_Macros RCC Private Macros
elmot	1:d0dfbce63a89	102	* @{
elmot	1:d0dfbce63a89	103	*/
elmot	1:d0dfbce63a89	104	#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
elmot	1:d0dfbce63a89	105	#define MCO1_GPIO_PORT GPIOA
elmot	1:d0dfbce63a89	106	#define MCO1_PIN GPIO_PIN_8
elmot	1:d0dfbce63a89	107
elmot	1:d0dfbce63a89	108	#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
elmot	1:d0dfbce63a89	109	(MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
elmot	1:d0dfbce63a89	110	/**
elmot	1:d0dfbce63a89	111	* @}
elmot	1:d0dfbce63a89	112	*/
elmot	1:d0dfbce63a89	113
elmot	1:d0dfbce63a89	114	/* Private variables ---------------------------------------------------------*/
elmot	1:d0dfbce63a89	115	/** @defgroup RCC_Private_Variables RCC Private Variables
elmot	1:d0dfbce63a89	116	* @{
elmot	1:d0dfbce63a89	117	*/
elmot	1:d0dfbce63a89	118
elmot	1:d0dfbce63a89	119	/**
elmot	1:d0dfbce63a89	120	* @}
elmot	1:d0dfbce63a89	121	*/
elmot	1:d0dfbce63a89	122
elmot	1:d0dfbce63a89	123	/* Private function prototypes -----------------------------------------------*/
elmot	1:d0dfbce63a89	124	/** @defgroup RCC_Private_Functions RCC Private Functions
elmot	1:d0dfbce63a89	125	* @{
elmot	1:d0dfbce63a89	126	*/
elmot	1:d0dfbce63a89	127	static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
elmot	1:d0dfbce63a89	128	/**
elmot	1:d0dfbce63a89	129	* @}
elmot	1:d0dfbce63a89	130	*/
elmot	1:d0dfbce63a89	131
elmot	1:d0dfbce63a89	132	/* Exported functions --------------------------------------------------------*/
elmot	1:d0dfbce63a89	133
elmot	1:d0dfbce63a89	134	/** @defgroup RCC_Exported_Functions RCC Exported Functions
elmot	1:d0dfbce63a89	135	* @{
elmot	1:d0dfbce63a89	136	*/
elmot	1:d0dfbce63a89	137
elmot	1:d0dfbce63a89	138	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
elmot	1:d0dfbce63a89	139	* @brief Initialization and Configuration functions
elmot	1:d0dfbce63a89	140	*
elmot	1:d0dfbce63a89	141	@verbatim
elmot	1:d0dfbce63a89	142	===============================================================================
elmot	1:d0dfbce63a89	143	##### Initialization and de-initialization functions #####
elmot	1:d0dfbce63a89	144	===============================================================================
elmot	1:d0dfbce63a89	145	[..]
elmot	1:d0dfbce63a89	146	This section provides functions allowing to configure the internal and external oscillators
elmot	1:d0dfbce63a89	147	(HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
elmot	1:d0dfbce63a89	148	and APB2).
elmot	1:d0dfbce63a89	149
elmot	1:d0dfbce63a89	150	[..] Internal/external clock and PLL configuration
elmot	1:d0dfbce63a89	151	(+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
elmot	1:d0dfbce63a89	152	the PLL as System clock source.
elmot	1:d0dfbce63a89	153
elmot	1:d0dfbce63a89	154	(+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
elmot	1:d0dfbce63a89	155	It can be used to generate the clock for the USB OTG FS (48 MHz).
elmot	1:d0dfbce63a89	156	The number of flash wait states is automatically adjusted when MSI range is updated with
elmot	1:d0dfbce63a89	157	HAL_RCC_OscConfig() and the MSI is used as System clock source.
elmot	1:d0dfbce63a89	158
elmot	1:d0dfbce63a89	159	(+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
elmot	1:d0dfbce63a89	160	clock source.
elmot	1:d0dfbce63a89	161
elmot	1:d0dfbce63a89	162	(+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
elmot	1:d0dfbce63a89	163	through the PLL as System clock source. Can be used also optionally as RTC clock source.
elmot	1:d0dfbce63a89	164
elmot	1:d0dfbce63a89	165	(+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
elmot	1:d0dfbce63a89	166
elmot	1:d0dfbce63a89	167	(+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
elmot	1:d0dfbce63a89	168	(++) The first output is used to generate the high speed system clock (up to 80MHz).
elmot	1:d0dfbce63a89	169	(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
elmot	1:d0dfbce63a89	170	the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
elmot	1:d0dfbce63a89	171	(++) The third output is used to generate an accurate clock to achieve
elmot	1:d0dfbce63a89	172	high-quality audio performance on SAI interface.
elmot	1:d0dfbce63a89	173
elmot	1:d0dfbce63a89	174	(+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
elmot	1:d0dfbce63a89	175	(++) The first output is used to generate SAR ADC1 clock.
elmot	1:d0dfbce63a89	176	(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
elmot	1:d0dfbce63a89	177	the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
elmot	1:d0dfbce63a89	178	(++) The Third output is used to generate an accurate clock to achieve
elmot	1:d0dfbce63a89	179	high-quality audio performance on SAI interface.
elmot	1:d0dfbce63a89	180
elmot	1:d0dfbce63a89	181	(+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks:
elmot	1:d0dfbce63a89	182	(++) The first output is used to generate SAR ADC2 clock.
elmot	1:d0dfbce63a89	183	(++) The second output is used to generate an accurate clock to achieve
elmot	1:d0dfbce63a89	184	high-quality audio performance on SAI interface.
elmot	1:d0dfbce63a89	185
elmot	1:d0dfbce63a89	186	(+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
elmot	1:d0dfbce63a89	187	(HSE used directly or through PLL as System clock source), the System clock
elmot	1:d0dfbce63a89	188	is automatically switched to HSI and an interrupt is generated if enabled.
elmot	1:d0dfbce63a89	189	The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
elmot	1:d0dfbce63a89	190	exception vector.
elmot	1:d0dfbce63a89	191
elmot	1:d0dfbce63a89	192	(+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
elmot	1:d0dfbce63a89	193	main PLL clock (through a configurable prescaler) on PA8 pin.
elmot	1:d0dfbce63a89	194
elmot	1:d0dfbce63a89	195	[..] System, AHB and APB busses clocks configuration
elmot	1:d0dfbce63a89	196	(+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
elmot	1:d0dfbce63a89	197	HSE and main PLL.
elmot	1:d0dfbce63a89	198	The AHB clock (HCLK) is derived from System clock through configurable
elmot	1:d0dfbce63a89	199	prescaler and used to clock the CPU, memory and peripherals mapped
elmot	1:d0dfbce63a89	200	on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
elmot	1:d0dfbce63a89	201	from AHB clock through configurable prescalers and used to clock
elmot	1:d0dfbce63a89	202	the peripherals mapped on these busses. You can use
elmot	1:d0dfbce63a89	203	"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
elmot	1:d0dfbce63a89	204
elmot	1:d0dfbce63a89	205	-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
elmot	1:d0dfbce63a89	206
elmot	1:d0dfbce63a89	207	(+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or
elmot	1:d0dfbce63a89	208	from an external clock mapped on the SAI_CKIN pin.
elmot	1:d0dfbce63a89	209	You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
elmot	1:d0dfbce63a89	210	(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
elmot	1:d0dfbce63a89	211	divided by 2 to 31.
elmot	1:d0dfbce63a89	212	You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
elmot	1:d0dfbce63a89	213	to configure this clock.
elmot	1:d0dfbce63a89	214	(+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
elmot	1:d0dfbce63a89	215	to work correctly, while the SDMMC1 and RNG peripherals require a frequency
elmot	1:d0dfbce63a89	216	equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1
elmot	1:d0dfbce63a89	217	through PLLQ divider. You have to enable the peripheral clock and use
elmot	1:d0dfbce63a89	218	HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
elmot	1:d0dfbce63a89	219	(+@) IWDG clock which is always the LSI clock.
elmot	1:d0dfbce63a89	220
elmot	1:d0dfbce63a89	221
elmot	1:d0dfbce63a89	222	(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.
elmot	1:d0dfbce63a89	223	The clock source frequency should be adapted depending on the device voltage range
elmot	1:d0dfbce63a89	224	as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
elmot	1:d0dfbce63a89	225
elmot	1:d0dfbce63a89	226	@endverbatim
elmot	1:d0dfbce63a89	227
elmot	1:d0dfbce63a89	228	Table 1. HCLK clock frequency.
elmot	1:d0dfbce63a89	229	+-------------------------------------------------------+
elmot	1:d0dfbce63a89	230	\| Latency \| HCLK clock frequency (MHz) \|
elmot	1:d0dfbce63a89	231	\| \|-------------------------------------\|
elmot	1:d0dfbce63a89	232	\| \| voltage range 1 \| voltage range 2 \|
elmot	1:d0dfbce63a89	233	\| \| 1.2 V \| 1.0 V \|
elmot	1:d0dfbce63a89	234	\|-----------------\|------------------\|------------------\|
elmot	1:d0dfbce63a89	235	\|0WS(1 CPU cycles)\| 0 < HCLK <= 16 \| 0 < HCLK <= 6 \|
elmot	1:d0dfbce63a89	236	\|-----------------\|------------------\|------------------\|
elmot	1:d0dfbce63a89	237	\|1WS(2 CPU cycles)\| 16 < HCLK <= 32 \| 6 < HCLK <= 12 \|
elmot	1:d0dfbce63a89	238	\|-----------------\|------------------\|------------------\|
elmot	1:d0dfbce63a89	239	\|2WS(3 CPU cycles)\| 32 < HCLK <= 48 \| 12 < HCLK <= 18 \|
elmot	1:d0dfbce63a89	240	\|-----------------\|------------------\|------------------\|
elmot	1:d0dfbce63a89	241	\|3WS(4 CPU cycles)\| 48 < HCLK <= 64 \| 18 < HCLK <= 26 \|
elmot	1:d0dfbce63a89	242	\|-----------------\|------------------\|------------------\|
elmot	1:d0dfbce63a89	243	\|4WS(5 CPU cycles)\| 64 < HCLK <= 80 \| 18 < HCLK <= 26 \|
elmot	1:d0dfbce63a89	244	+-------------------------------------------------------+
elmot	1:d0dfbce63a89	245	* @{
elmot	1:d0dfbce63a89	246	*/
elmot	1:d0dfbce63a89	247
elmot	1:d0dfbce63a89	248	/**
elmot	1:d0dfbce63a89	249	* @brief Reset the RCC clock configuration to the default reset state.
elmot	1:d0dfbce63a89	250	* @note The default reset state of the clock configuration is given below:
elmot	1:d0dfbce63a89	251	* - MSI ON and used as system clock source
elmot	1:d0dfbce63a89	252	* - HSE, HSI, PLL, PLLSAI1 and PLLISAI2 OFF
elmot	1:d0dfbce63a89	253	* - AHB, APB1 and APB2 prescaler set to 1.
elmot	1:d0dfbce63a89	254	* - CSS, MCO1 OFF
elmot	1:d0dfbce63a89	255	* - All interrupts disabled
elmot	1:d0dfbce63a89	256	* @note This function doesn't modify the configuration of the
elmot	1:d0dfbce63a89	257	* - Peripheral clocks
elmot	1:d0dfbce63a89	258	* - LSI, LSE and RTC clocks
elmot	1:d0dfbce63a89	259	* @retval None
elmot	1:d0dfbce63a89	260	*/
elmot	1:d0dfbce63a89	261	void HAL_RCC_DeInit(void)
elmot	1:d0dfbce63a89	262	{
elmot	1:d0dfbce63a89	263	/* Set MSION bit */
elmot	1:d0dfbce63a89	264	SET_BIT(RCC->CR, RCC_CR_MSION);
elmot	1:d0dfbce63a89	265
elmot	1:d0dfbce63a89	266	/* Insure MSIRDY bit is set before writing default MSIRANGE value */
elmot	1:d0dfbce63a89	267	while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) { __NOP(); }
elmot	1:d0dfbce63a89	268
elmot	1:d0dfbce63a89	269	/* Set MSIRANGE default value */
elmot	1:d0dfbce63a89	270	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6);
elmot	1:d0dfbce63a89	271
elmot	1:d0dfbce63a89	272	/* Reset CFGR register (MSI is selected as system clock source) */
elmot	1:d0dfbce63a89	273	CLEAR_REG(RCC->CFGR);
elmot	1:d0dfbce63a89	274
elmot	1:d0dfbce63a89	275	/* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */
elmot	1:d0dfbce63a89	276	#if defined(RCC_PLLSAI2_SUPPORT)
elmot	1:d0dfbce63a89	277
elmot	1:d0dfbce63a89	278	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_HSION \| RCC_CR_HSIKERON\| RCC_CR_HSIASFS \| RCC_CR_PLLON \| RCC_CR_PLLSAI1ON \| RCC_CR_PLLSAI2ON);
elmot	1:d0dfbce63a89	279
elmot	1:d0dfbce63a89	280	#else
elmot	1:d0dfbce63a89	281
elmot	1:d0dfbce63a89	282	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_HSION \| RCC_CR_HSIKERON\| RCC_CR_HSIASFS \| RCC_CR_PLLON \| RCC_CR_PLLSAI1ON);
elmot	1:d0dfbce63a89	283
elmot	1:d0dfbce63a89	284	#endif /* RCC_PLLSAI2_SUPPORT */
elmot	1:d0dfbce63a89	285
elmot	1:d0dfbce63a89	286	/* Reset PLLCFGR register */
elmot	1:d0dfbce63a89	287	CLEAR_REG(RCC->PLLCFGR);
elmot	1:d0dfbce63a89	288	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 );
elmot	1:d0dfbce63a89	289
elmot	1:d0dfbce63a89	290	/* Reset PLLSAI1CFGR register */
elmot	1:d0dfbce63a89	291	CLEAR_REG(RCC->PLLSAI1CFGR);
elmot	1:d0dfbce63a89	292	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 );
elmot	1:d0dfbce63a89	293
elmot	1:d0dfbce63a89	294	#if defined(RCC_PLLSAI2_SUPPORT)
elmot	1:d0dfbce63a89	295
elmot	1:d0dfbce63a89	296	/* Reset PLLSAI2CFGR register */
elmot	1:d0dfbce63a89	297	CLEAR_REG(RCC->PLLSAI2CFGR);
elmot	1:d0dfbce63a89	298	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N_4 );
elmot	1:d0dfbce63a89	299
elmot	1:d0dfbce63a89	300	#endif /* RCC_PLLSAI2_SUPPORT */
elmot	1:d0dfbce63a89	301
elmot	1:d0dfbce63a89	302	/* Reset HSEBYP bit */
elmot	1:d0dfbce63a89	303	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
elmot	1:d0dfbce63a89	304
elmot	1:d0dfbce63a89	305	/* Disable all interrupts */
elmot	1:d0dfbce63a89	306	CLEAR_REG(RCC->CIER);
elmot	1:d0dfbce63a89	307
elmot	1:d0dfbce63a89	308	/* Update the SystemCoreClock global variable */
elmot	1:d0dfbce63a89	309	SystemCoreClock = MSI_VALUE;
elmot	1:d0dfbce63a89	310	}
elmot	1:d0dfbce63a89	311
elmot	1:d0dfbce63a89	312	/**
elmot	1:d0dfbce63a89	313	* @brief Initialize the RCC Oscillators according to the specified parameters in the
elmot	1:d0dfbce63a89	314	* RCC_OscInitTypeDef.
elmot	1:d0dfbce63a89	315	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
elmot	1:d0dfbce63a89	316	* contains the configuration information for the RCC Oscillators.
elmot	1:d0dfbce63a89	317	* @note The PLL is not disabled when used as system clock.
elmot	1:d0dfbce63a89	318	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
elmot	1:d0dfbce63a89	319	* supported by this macro. User should request a transition to LSE Off
elmot	1:d0dfbce63a89	320	* first and then LSE On or LSE Bypass.
elmot	1:d0dfbce63a89	321	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
elmot	1:d0dfbce63a89	322	* supported by this macro. User should request a transition to HSE Off
elmot	1:d0dfbce63a89	323	* first and then HSE On or HSE Bypass.
elmot	1:d0dfbce63a89	324	* @retval HAL status
elmot	1:d0dfbce63a89	325	*/
elmot	1:d0dfbce63a89	326	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
elmot	1:d0dfbce63a89	327	{
elmot	1:d0dfbce63a89	328	uint32_t tickstart = 0;
elmot	1:d0dfbce63a89	329
elmot	1:d0dfbce63a89	330	/* Check the parameters */
elmot	1:d0dfbce63a89	331	assert_param(RCC_OscInitStruct != NULL);
elmot	1:d0dfbce63a89	332	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
elmot	1:d0dfbce63a89	333
elmot	1:d0dfbce63a89	334	/----------------------------- MSI Configuration --------------------------/
elmot	1:d0dfbce63a89	335	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
elmot	1:d0dfbce63a89	336	{
elmot	1:d0dfbce63a89	337	/* Check the parameters */
elmot	1:d0dfbce63a89	338	assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
elmot	1:d0dfbce63a89	339	assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
elmot	1:d0dfbce63a89	340	assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
elmot	1:d0dfbce63a89	341
elmot	1:d0dfbce63a89	342	/* When the MSI is used as system clock it will not be disabled */
elmot	1:d0dfbce63a89	343	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) )
elmot	1:d0dfbce63a89	344	{
elmot	1:d0dfbce63a89	345	if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
elmot	1:d0dfbce63a89	346	{
elmot	1:d0dfbce63a89	347	return HAL_ERROR;
elmot	1:d0dfbce63a89	348	}
elmot	1:d0dfbce63a89	349
elmot	1:d0dfbce63a89	350	/* Otherwise, just the calibration and MSI range change are allowed */
elmot	1:d0dfbce63a89	351	else
elmot	1:d0dfbce63a89	352	{
elmot	1:d0dfbce63a89	353	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
elmot	1:d0dfbce63a89	354	must be correctly programmed according to the frequency of the CPU clock
elmot	1:d0dfbce63a89	355	(HCLK) and the supply voltage of the device. */
elmot	1:d0dfbce63a89	356	if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
elmot	1:d0dfbce63a89	357	{
elmot	1:d0dfbce63a89	358	/* First increase number of wait states update if necessary */
elmot	1:d0dfbce63a89	359	if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
elmot	1:d0dfbce63a89	360	{
elmot	1:d0dfbce63a89	361	return HAL_ERROR;
elmot	1:d0dfbce63a89	362	}
elmot	1:d0dfbce63a89	363
elmot	1:d0dfbce63a89	364	/* Selects the Multiple Speed oscillator (MSI) clock range .*/
elmot	1:d0dfbce63a89	365	__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
elmot	1:d0dfbce63a89	366	/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
elmot	1:d0dfbce63a89	367	__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
elmot	1:d0dfbce63a89	368	}
elmot	1:d0dfbce63a89	369	else
elmot	1:d0dfbce63a89	370	{
elmot	1:d0dfbce63a89	371	/* Else, keep current flash latency while decreasing applies */
elmot	1:d0dfbce63a89	372	/* Selects the Multiple Speed oscillator (MSI) clock range .*/
elmot	1:d0dfbce63a89	373	__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
elmot	1:d0dfbce63a89	374	/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
elmot	1:d0dfbce63a89	375	__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
elmot	1:d0dfbce63a89	376
elmot	1:d0dfbce63a89	377	/* Decrease number of wait states update if necessary */
elmot	1:d0dfbce63a89	378	if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
elmot	1:d0dfbce63a89	379	{
elmot	1:d0dfbce63a89	380	return HAL_ERROR;
elmot	1:d0dfbce63a89	381	}
elmot	1:d0dfbce63a89	382	}
elmot	1:d0dfbce63a89	383
elmot	1:d0dfbce63a89	384	/* Update the SystemCoreClock global variable */
elmot	1:d0dfbce63a89	385	SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
elmot	1:d0dfbce63a89	386
elmot	1:d0dfbce63a89	387	/* Configure the source of time base considering new system clocks settings*/
elmot	1:d0dfbce63a89	388	HAL_InitTick (TICK_INT_PRIORITY);
elmot	1:d0dfbce63a89	389	}
elmot	1:d0dfbce63a89	390	}
elmot	1:d0dfbce63a89	391	else
elmot	1:d0dfbce63a89	392	{
elmot	1:d0dfbce63a89	393	/* Check the MSI State */
elmot	1:d0dfbce63a89	394	if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
elmot	1:d0dfbce63a89	395	{
elmot	1:d0dfbce63a89	396	/* Enable the Internal High Speed oscillator (MSI). */
elmot	1:d0dfbce63a89	397	__HAL_RCC_MSI_ENABLE();
elmot	1:d0dfbce63a89	398
elmot	1:d0dfbce63a89	399	/* Get timeout */
elmot	1:d0dfbce63a89	400	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	401
elmot	1:d0dfbce63a89	402	/* Wait till MSI is ready */
elmot	1:d0dfbce63a89	403	while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET)
elmot	1:d0dfbce63a89	404	{
elmot	1:d0dfbce63a89	405	if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	406	{
elmot	1:d0dfbce63a89	407	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	408	}
elmot	1:d0dfbce63a89	409	}
elmot	1:d0dfbce63a89	410	/* Selects the Multiple Speed oscillator (MSI) clock range .*/
elmot	1:d0dfbce63a89	411	__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
elmot	1:d0dfbce63a89	412	/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
elmot	1:d0dfbce63a89	413	__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
elmot	1:d0dfbce63a89	414
elmot	1:d0dfbce63a89	415	}
elmot	1:d0dfbce63a89	416	else
elmot	1:d0dfbce63a89	417	{
elmot	1:d0dfbce63a89	418	/* Disable the Internal High Speed oscillator (MSI). */
elmot	1:d0dfbce63a89	419	__HAL_RCC_MSI_DISABLE();
elmot	1:d0dfbce63a89	420
elmot	1:d0dfbce63a89	421	/* Get timeout */
elmot	1:d0dfbce63a89	422	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	423
elmot	1:d0dfbce63a89	424	/* Wait till MSI is ready */
elmot	1:d0dfbce63a89	425	while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET)
elmot	1:d0dfbce63a89	426	{
elmot	1:d0dfbce63a89	427	if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	428	{
elmot	1:d0dfbce63a89	429	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	430	}
elmot	1:d0dfbce63a89	431	}
elmot	1:d0dfbce63a89	432	}
elmot	1:d0dfbce63a89	433	}
elmot	1:d0dfbce63a89	434	}
elmot	1:d0dfbce63a89	435	/------------------------------- HSE Configuration ------------------------/
elmot	1:d0dfbce63a89	436	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
elmot	1:d0dfbce63a89	437	{
elmot	1:d0dfbce63a89	438	/* Check the parameters */
elmot	1:d0dfbce63a89	439	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
elmot	1:d0dfbce63a89	440
elmot	1:d0dfbce63a89	441	/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
elmot	1:d0dfbce63a89	442	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|
elmot	1:d0dfbce63a89	443	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
elmot	1:d0dfbce63a89	444	{
elmot	1:d0dfbce63a89	445	if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
elmot	1:d0dfbce63a89	446	{
elmot	1:d0dfbce63a89	447	return HAL_ERROR;
elmot	1:d0dfbce63a89	448	}
elmot	1:d0dfbce63a89	449	}
elmot	1:d0dfbce63a89	450	else
elmot	1:d0dfbce63a89	451	{
elmot	1:d0dfbce63a89	452	/* Set the new HSE configuration ---------------------------------------*/
elmot	1:d0dfbce63a89	453	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
elmot	1:d0dfbce63a89	454
elmot	1:d0dfbce63a89	455	/* Check the HSE State */
elmot	1:d0dfbce63a89	456	if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
elmot	1:d0dfbce63a89	457	{
elmot	1:d0dfbce63a89	458	/* Get Start Tick*/
elmot	1:d0dfbce63a89	459	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	460
elmot	1:d0dfbce63a89	461	/* Wait till HSE is ready */
elmot	1:d0dfbce63a89	462	while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET)
elmot	1:d0dfbce63a89	463	{
elmot	1:d0dfbce63a89	464	if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	465	{
elmot	1:d0dfbce63a89	466	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	467	}
elmot	1:d0dfbce63a89	468	}
elmot	1:d0dfbce63a89	469	}
elmot	1:d0dfbce63a89	470	else
elmot	1:d0dfbce63a89	471	{
elmot	1:d0dfbce63a89	472	/* Get Start Tick*/
elmot	1:d0dfbce63a89	473	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	474
elmot	1:d0dfbce63a89	475	/* Wait till HSE is disabled */
elmot	1:d0dfbce63a89	476	while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
elmot	1:d0dfbce63a89	477	{
elmot	1:d0dfbce63a89	478	if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	479	{
elmot	1:d0dfbce63a89	480	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	481	}
elmot	1:d0dfbce63a89	482	}
elmot	1:d0dfbce63a89	483	}
elmot	1:d0dfbce63a89	484	}
elmot	1:d0dfbce63a89	485	}
elmot	1:d0dfbce63a89	486	/----------------------------- HSI Configuration --------------------------/
elmot	1:d0dfbce63a89	487	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
elmot	1:d0dfbce63a89	488	{
elmot	1:d0dfbce63a89	489	/* Check the parameters */
elmot	1:d0dfbce63a89	490	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
elmot	1:d0dfbce63a89	491	assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
elmot	1:d0dfbce63a89	492
elmot	1:d0dfbce63a89	493	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
elmot	1:d0dfbce63a89	494	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|
elmot	1:d0dfbce63a89	495	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
elmot	1:d0dfbce63a89	496	{
elmot	1:d0dfbce63a89	497	/* When HSI is used as system clock it will not be disabled */
elmot	1:d0dfbce63a89	498	if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
elmot	1:d0dfbce63a89	499	{
elmot	1:d0dfbce63a89	500	return HAL_ERROR;
elmot	1:d0dfbce63a89	501	}
elmot	1:d0dfbce63a89	502	/* Otherwise, just the calibration is allowed */
elmot	1:d0dfbce63a89	503	else
elmot	1:d0dfbce63a89	504	{
elmot	1:d0dfbce63a89	505	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
elmot	1:d0dfbce63a89	506	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
elmot	1:d0dfbce63a89	507	}
elmot	1:d0dfbce63a89	508	}
elmot	1:d0dfbce63a89	509	else
elmot	1:d0dfbce63a89	510	{
elmot	1:d0dfbce63a89	511	/* Check the HSI State */
elmot	1:d0dfbce63a89	512	if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
elmot	1:d0dfbce63a89	513	{
elmot	1:d0dfbce63a89	514	/* Enable the Internal High Speed oscillator (HSI). */
elmot	1:d0dfbce63a89	515	__HAL_RCC_HSI_ENABLE();
elmot	1:d0dfbce63a89	516
elmot	1:d0dfbce63a89	517	/* Get Start Tick*/
elmot	1:d0dfbce63a89	518	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	519
elmot	1:d0dfbce63a89	520	/* Wait till HSI is ready */
elmot	1:d0dfbce63a89	521	while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
elmot	1:d0dfbce63a89	522	{
elmot	1:d0dfbce63a89	523	if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	524	{
elmot	1:d0dfbce63a89	525	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	526	}
elmot	1:d0dfbce63a89	527	}
elmot	1:d0dfbce63a89	528
elmot	1:d0dfbce63a89	529	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
elmot	1:d0dfbce63a89	530	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
elmot	1:d0dfbce63a89	531	}
elmot	1:d0dfbce63a89	532	else
elmot	1:d0dfbce63a89	533	{
elmot	1:d0dfbce63a89	534	/* Disable the Internal High Speed oscillator (HSI). */
elmot	1:d0dfbce63a89	535	__HAL_RCC_HSI_DISABLE();
elmot	1:d0dfbce63a89	536
elmot	1:d0dfbce63a89	537	/* Get Start Tick*/
elmot	1:d0dfbce63a89	538	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	539
elmot	1:d0dfbce63a89	540	/* Wait till HSI is disabled */
elmot	1:d0dfbce63a89	541	while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET)
elmot	1:d0dfbce63a89	542	{
elmot	1:d0dfbce63a89	543	if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	544	{
elmot	1:d0dfbce63a89	545	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	546	}
elmot	1:d0dfbce63a89	547	}
elmot	1:d0dfbce63a89	548	}
elmot	1:d0dfbce63a89	549	}
elmot	1:d0dfbce63a89	550	}
elmot	1:d0dfbce63a89	551	/------------------------------ LSI Configuration -------------------------/
elmot	1:d0dfbce63a89	552	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
elmot	1:d0dfbce63a89	553	{
elmot	1:d0dfbce63a89	554	/* Check the parameters */
elmot	1:d0dfbce63a89	555	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
elmot	1:d0dfbce63a89	556
elmot	1:d0dfbce63a89	557	/* Check the LSI State */
elmot	1:d0dfbce63a89	558	if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
elmot	1:d0dfbce63a89	559	{
elmot	1:d0dfbce63a89	560	/* Enable the Internal Low Speed oscillator (LSI). */
elmot	1:d0dfbce63a89	561	__HAL_RCC_LSI_ENABLE();
elmot	1:d0dfbce63a89	562
elmot	1:d0dfbce63a89	563	/* Get Start Tick*/
elmot	1:d0dfbce63a89	564	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	565
elmot	1:d0dfbce63a89	566	/* Wait till LSI is ready */
elmot	1:d0dfbce63a89	567	while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RESET)
elmot	1:d0dfbce63a89	568	{
elmot	1:d0dfbce63a89	569	if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	570	{
elmot	1:d0dfbce63a89	571	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	572	}
elmot	1:d0dfbce63a89	573	}
elmot	1:d0dfbce63a89	574	}
elmot	1:d0dfbce63a89	575	else
elmot	1:d0dfbce63a89	576	{
elmot	1:d0dfbce63a89	577	/* Disable the Internal Low Speed oscillator (LSI). */
elmot	1:d0dfbce63a89	578	__HAL_RCC_LSI_DISABLE();
elmot	1:d0dfbce63a89	579
elmot	1:d0dfbce63a89	580	/* Get Start Tick*/
elmot	1:d0dfbce63a89	581	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	582
elmot	1:d0dfbce63a89	583	/* Wait till LSI is disabled */
elmot	1:d0dfbce63a89	584	while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != RESET)
elmot	1:d0dfbce63a89	585	{
elmot	1:d0dfbce63a89	586	if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	587	{
elmot	1:d0dfbce63a89	588	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	589	}
elmot	1:d0dfbce63a89	590	}
elmot	1:d0dfbce63a89	591	}
elmot	1:d0dfbce63a89	592	}
elmot	1:d0dfbce63a89	593	/------------------------------ LSE Configuration -------------------------/
elmot	1:d0dfbce63a89	594	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
elmot	1:d0dfbce63a89	595	{
elmot	1:d0dfbce63a89	596	FlagStatus pwrclkchanged = RESET;
elmot	1:d0dfbce63a89	597
elmot	1:d0dfbce63a89	598	/* Check the parameters */
elmot	1:d0dfbce63a89	599	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
elmot	1:d0dfbce63a89	600
elmot	1:d0dfbce63a89	601	/* Update LSE configuration in Backup Domain control register */
elmot	1:d0dfbce63a89	602	/* Requires to enable write access to Backup Domain of necessary */
elmot	1:d0dfbce63a89	603	if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
elmot	1:d0dfbce63a89	604	{
elmot	1:d0dfbce63a89	605	__HAL_RCC_PWR_CLK_ENABLE();
elmot	1:d0dfbce63a89	606	pwrclkchanged = SET;
elmot	1:d0dfbce63a89	607	}
elmot	1:d0dfbce63a89	608
elmot	1:d0dfbce63a89	609	if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
elmot	1:d0dfbce63a89	610	{
elmot	1:d0dfbce63a89	611	/* Enable write access to Backup domain */
elmot	1:d0dfbce63a89	612	SET_BIT(PWR->CR1, PWR_CR1_DBP);
elmot	1:d0dfbce63a89	613
elmot	1:d0dfbce63a89	614	/* Wait for Backup domain Write protection disable */
elmot	1:d0dfbce63a89	615	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	616
elmot	1:d0dfbce63a89	617	while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
elmot	1:d0dfbce63a89	618	{
elmot	1:d0dfbce63a89	619	if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	620	{
elmot	1:d0dfbce63a89	621	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	622	}
elmot	1:d0dfbce63a89	623	}
elmot	1:d0dfbce63a89	624	}
elmot	1:d0dfbce63a89	625
elmot	1:d0dfbce63a89	626	/* Set the new LSE configuration -----------------------------------------*/
elmot	1:d0dfbce63a89	627	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
elmot	1:d0dfbce63a89	628
elmot	1:d0dfbce63a89	629	/* Check the LSE State */
elmot	1:d0dfbce63a89	630	if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
elmot	1:d0dfbce63a89	631	{
elmot	1:d0dfbce63a89	632	/* Get Start Tick*/
elmot	1:d0dfbce63a89	633	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	634
elmot	1:d0dfbce63a89	635	/* Wait till LSE is ready */
elmot	1:d0dfbce63a89	636	while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET)
elmot	1:d0dfbce63a89	637	{
elmot	1:d0dfbce63a89	638	if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	639	{
elmot	1:d0dfbce63a89	640	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	641	}
elmot	1:d0dfbce63a89	642	}
elmot	1:d0dfbce63a89	643	}
elmot	1:d0dfbce63a89	644	else
elmot	1:d0dfbce63a89	645	{
elmot	1:d0dfbce63a89	646	/* Get Start Tick*/
elmot	1:d0dfbce63a89	647	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	648
elmot	1:d0dfbce63a89	649	/* Wait till LSE is disabled */
elmot	1:d0dfbce63a89	650	while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != RESET)
elmot	1:d0dfbce63a89	651	{
elmot	1:d0dfbce63a89	652	if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	653	{
elmot	1:d0dfbce63a89	654	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	655	}
elmot	1:d0dfbce63a89	656	}
elmot	1:d0dfbce63a89	657	}
elmot	1:d0dfbce63a89	658
elmot	1:d0dfbce63a89	659	/* Restore clock configuration if changed */
elmot	1:d0dfbce63a89	660	if(pwrclkchanged == SET)
elmot	1:d0dfbce63a89	661	{
elmot	1:d0dfbce63a89	662	__HAL_RCC_PWR_CLK_DISABLE();
elmot	1:d0dfbce63a89	663	}
elmot	1:d0dfbce63a89	664	}
elmot	1:d0dfbce63a89	665	#if defined(RCC_HSI48_SUPPORT)
elmot	1:d0dfbce63a89	666	/------------------------------ HSI48 Configuration -----------------------/
elmot	1:d0dfbce63a89	667	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
elmot	1:d0dfbce63a89	668	{
elmot	1:d0dfbce63a89	669	/* Check the parameters */
elmot	1:d0dfbce63a89	670	assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
elmot	1:d0dfbce63a89	671
elmot	1:d0dfbce63a89	672	/* Check the LSI State */
elmot	1:d0dfbce63a89	673	if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
elmot	1:d0dfbce63a89	674	{
elmot	1:d0dfbce63a89	675	/* Enable the Internal Low Speed oscillator (HSI48). */
elmot	1:d0dfbce63a89	676	__HAL_RCC_HSI48_ENABLE();
elmot	1:d0dfbce63a89	677
elmot	1:d0dfbce63a89	678	/* Get Start Tick*/
elmot	1:d0dfbce63a89	679	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	680
elmot	1:d0dfbce63a89	681	/* Wait till HSI48 is ready */
elmot	1:d0dfbce63a89	682	while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RESET)
elmot	1:d0dfbce63a89	683	{
elmot	1:d0dfbce63a89	684	if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	685	{
elmot	1:d0dfbce63a89	686	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	687	}
elmot	1:d0dfbce63a89	688	}
elmot	1:d0dfbce63a89	689	}
elmot	1:d0dfbce63a89	690	else
elmot	1:d0dfbce63a89	691	{
elmot	1:d0dfbce63a89	692	/* Disable the Internal Low Speed oscillator (HSI48). */
elmot	1:d0dfbce63a89	693	__HAL_RCC_HSI48_DISABLE();
elmot	1:d0dfbce63a89	694
elmot	1:d0dfbce63a89	695	/* Get Start Tick*/
elmot	1:d0dfbce63a89	696	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	697
elmot	1:d0dfbce63a89	698	/* Wait till HSI48 is disabled */
elmot	1:d0dfbce63a89	699	while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != RESET)
elmot	1:d0dfbce63a89	700	{
elmot	1:d0dfbce63a89	701	if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	702	{
elmot	1:d0dfbce63a89	703	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	704	}
elmot	1:d0dfbce63a89	705	}
elmot	1:d0dfbce63a89	706	}
elmot	1:d0dfbce63a89	707	}
elmot	1:d0dfbce63a89	708	#endif /* RCC_HSI48_SUPPORT */
elmot	1:d0dfbce63a89	709	/-------------------------------- PLL Configuration -----------------------/
elmot	1:d0dfbce63a89	710	/* Check the parameters */
elmot	1:d0dfbce63a89	711	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
elmot	1:d0dfbce63a89	712
elmot	1:d0dfbce63a89	713	if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
elmot	1:d0dfbce63a89	714	{
elmot	1:d0dfbce63a89	715	/* Check if the PLL is used as system clock or not */
elmot	1:d0dfbce63a89	716	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
elmot	1:d0dfbce63a89	717	{
elmot	1:d0dfbce63a89	718	if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
elmot	1:d0dfbce63a89	719	{
elmot	1:d0dfbce63a89	720	/* Check the parameters */
elmot	1:d0dfbce63a89	721	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
elmot	1:d0dfbce63a89	722	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
elmot	1:d0dfbce63a89	723	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
elmot	1:d0dfbce63a89	724	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
elmot	1:d0dfbce63a89	725	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
elmot	1:d0dfbce63a89	726	assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
elmot	1:d0dfbce63a89	727
elmot	1:d0dfbce63a89	728	/* Disable the main PLL. */
elmot	1:d0dfbce63a89	729	__HAL_RCC_PLL_DISABLE();
elmot	1:d0dfbce63a89	730
elmot	1:d0dfbce63a89	731	/* Get Start Tick*/
elmot	1:d0dfbce63a89	732	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	733
elmot	1:d0dfbce63a89	734	/* Wait till PLL is ready */
elmot	1:d0dfbce63a89	735	while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
elmot	1:d0dfbce63a89	736	{
elmot	1:d0dfbce63a89	737	if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	738	{
elmot	1:d0dfbce63a89	739	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	740	}
elmot	1:d0dfbce63a89	741	}
elmot	1:d0dfbce63a89	742
elmot	1:d0dfbce63a89	743	/* Configure the main PLL clock source, multiplication and division factors. */
elmot	1:d0dfbce63a89	744	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
elmot	1:d0dfbce63a89	745	RCC_OscInitStruct->PLL.PLLM,
elmot	1:d0dfbce63a89	746	RCC_OscInitStruct->PLL.PLLN,
elmot	1:d0dfbce63a89	747	RCC_OscInitStruct->PLL.PLLP,
elmot	1:d0dfbce63a89	748	RCC_OscInitStruct->PLL.PLLQ,
elmot	1:d0dfbce63a89	749	RCC_OscInitStruct->PLL.PLLR);
elmot	1:d0dfbce63a89	750
elmot	1:d0dfbce63a89	751	/* Enable the main PLL. */
elmot	1:d0dfbce63a89	752	__HAL_RCC_PLL_ENABLE();
elmot	1:d0dfbce63a89	753
elmot	1:d0dfbce63a89	754	/* Enable PLL System Clock output. */
elmot	1:d0dfbce63a89	755	__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
elmot	1:d0dfbce63a89	756
elmot	1:d0dfbce63a89	757	/* Get Start Tick*/
elmot	1:d0dfbce63a89	758	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	759
elmot	1:d0dfbce63a89	760	/* Wait till PLL is ready */
elmot	1:d0dfbce63a89	761	while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
elmot	1:d0dfbce63a89	762	{
elmot	1:d0dfbce63a89	763	if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	764	{
elmot	1:d0dfbce63a89	765	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	766	}
elmot	1:d0dfbce63a89	767	}
elmot	1:d0dfbce63a89	768	}
elmot	1:d0dfbce63a89	769	else
elmot	1:d0dfbce63a89	770	{
elmot	1:d0dfbce63a89	771	/* Disable the main PLL. */
elmot	1:d0dfbce63a89	772	__HAL_RCC_PLL_DISABLE();
elmot	1:d0dfbce63a89	773
elmot	1:d0dfbce63a89	774	/* Disable all PLL outputs to save power if no PLLs on */
elmot	1:d0dfbce63a89	775	if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET)
elmot	1:d0dfbce63a89	776	#if defined(RCC_PLLSAI2_SUPPORT)
elmot	1:d0dfbce63a89	777	&&
elmot	1:d0dfbce63a89	778	(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET)
elmot	1:d0dfbce63a89	779	#endif /* RCC_PLLSAI2_SUPPORT */
elmot	1:d0dfbce63a89	780	)
elmot	1:d0dfbce63a89	781	{
elmot	1:d0dfbce63a89	782	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
elmot	1:d0dfbce63a89	783	}
elmot	1:d0dfbce63a89	784
elmot	1:d0dfbce63a89	785	#if defined(RCC_PLLSAI2_SUPPORT)
elmot	1:d0dfbce63a89	786	__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK \| RCC_PLL_48M1CLK \| RCC_PLL_SAI3CLK);
elmot	1:d0dfbce63a89	787	#else
elmot	1:d0dfbce63a89	788	__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK \| RCC_PLL_48M1CLK \| RCC_PLL_SAI2CLK);
elmot	1:d0dfbce63a89	789	#endif /* RCC_PLLSAI2_SUPPORT */
elmot	1:d0dfbce63a89	790
elmot	1:d0dfbce63a89	791	/* Get Start Tick*/
elmot	1:d0dfbce63a89	792	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	793
elmot	1:d0dfbce63a89	794	/* Wait till PLL is disabled */
elmot	1:d0dfbce63a89	795	while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
elmot	1:d0dfbce63a89	796	{
elmot	1:d0dfbce63a89	797	if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	798	{
elmot	1:d0dfbce63a89	799	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	800	}
elmot	1:d0dfbce63a89	801	}
elmot	1:d0dfbce63a89	802	}
elmot	1:d0dfbce63a89	803	}
elmot	1:d0dfbce63a89	804	else
elmot	1:d0dfbce63a89	805	{
elmot	1:d0dfbce63a89	806	return HAL_ERROR;
elmot	1:d0dfbce63a89	807	}
elmot	1:d0dfbce63a89	808	}
elmot	1:d0dfbce63a89	809	return HAL_OK;
elmot	1:d0dfbce63a89	810	}
elmot	1:d0dfbce63a89	811
elmot	1:d0dfbce63a89	812	/**
elmot	1:d0dfbce63a89	813	* @brief Initialize the CPU, AHB and APB busses clocks according to the specified
elmot	1:d0dfbce63a89	814	* parameters in the RCC_ClkInitStruct.
elmot	1:d0dfbce63a89	815	* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
elmot	1:d0dfbce63a89	816	* contains the configuration information for the RCC peripheral.
elmot	1:d0dfbce63a89	817	* @param FLatency FLASH Latency
elmot	1:d0dfbce63a89	818	* This parameter can be one of the following values:
elmot	1:d0dfbce63a89	819	* @arg FLASH_LATENCY_0 FLASH 0 Latency cycle
elmot	1:d0dfbce63a89	820	* @arg FLASH_LATENCY_1 FLASH 1 Latency cycle
elmot	1:d0dfbce63a89	821	* @arg FLASH_LATENCY_2 FLASH 2 Latency cycle
elmot	1:d0dfbce63a89	822	* @arg FLASH_LATENCY_3 FLASH 3 Latency cycle
elmot	1:d0dfbce63a89	823	* @arg FLASH_LATENCY_4 FLASH 4 Latency cycle
elmot	1:d0dfbce63a89	824	*
elmot	1:d0dfbce63a89	825	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
elmot	1:d0dfbce63a89	826	* and updated by HAL_RCC_GetHCLKFreq() function called within this function
elmot	1:d0dfbce63a89	827	*
elmot	1:d0dfbce63a89	828	* @note The MSI is used by default as system clock source after
elmot	1:d0dfbce63a89	829	* startup from Reset, wake-up from STANDBY mode. After restart from Reset,
elmot	1:d0dfbce63a89	830	* the MSI frequency is set to its default value 4 MHz.
elmot	1:d0dfbce63a89	831	*
elmot	1:d0dfbce63a89	832	* @note The HSI can be selected as system clock source after
elmot	1:d0dfbce63a89	833	* from STOP modes or in case of failure of the HSE used directly or indirectly
elmot	1:d0dfbce63a89	834	* as system clock (if the Clock Security System CSS is enabled).
elmot	1:d0dfbce63a89	835	*
elmot	1:d0dfbce63a89	836	* @note A switch from one clock source to another occurs only if the target
elmot	1:d0dfbce63a89	837	* clock source is ready (clock stable after startup delay or PLL locked).
elmot	1:d0dfbce63a89	838	* If a clock source which is not yet ready is selected, the switch will
elmot	1:d0dfbce63a89	839	* occur when the clock source is ready.
elmot	1:d0dfbce63a89	840	*
elmot	1:d0dfbce63a89	841	* @note You can use HAL_RCC_GetClockConfig() function to know which clock is
elmot	1:d0dfbce63a89	842	* currently used as system clock source.
elmot	1:d0dfbce63a89	843	*
elmot	1:d0dfbce63a89	844	* @note Depending on the device voltage range, the software has to set correctly
elmot	1:d0dfbce63a89	845	* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
elmot	1:d0dfbce63a89	846	* (for more details refer to section above "Initialization/de-initialization functions")
elmot	1:d0dfbce63a89	847	* @retval None
elmot	1:d0dfbce63a89	848	*/
elmot	1:d0dfbce63a89	849	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
elmot	1:d0dfbce63a89	850	{
elmot	1:d0dfbce63a89	851	uint32_t tickstart = 0;
elmot	1:d0dfbce63a89	852
elmot	1:d0dfbce63a89	853	/* Check the parameters */
elmot	1:d0dfbce63a89	854	assert_param(RCC_ClkInitStruct != NULL);
elmot	1:d0dfbce63a89	855	assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
elmot	1:d0dfbce63a89	856	assert_param(IS_FLASH_LATENCY(FLatency));
elmot	1:d0dfbce63a89	857
elmot	1:d0dfbce63a89	858	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
elmot	1:d0dfbce63a89	859	must be correctly programmed according to the frequency of the CPU clock
elmot	1:d0dfbce63a89	860	(HCLK) and the supply voltage of the device. */
elmot	1:d0dfbce63a89	861
elmot	1:d0dfbce63a89	862	/* Increasing the number of wait states because of higher CPU frequency */
elmot	1:d0dfbce63a89	863	if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
elmot	1:d0dfbce63a89	864	{
elmot	1:d0dfbce63a89	865	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
elmot	1:d0dfbce63a89	866	__HAL_FLASH_SET_LATENCY(FLatency);
elmot	1:d0dfbce63a89	867
elmot	1:d0dfbce63a89	868	/* Check that the new number of wait states is taken into account to access the Flash
elmot	1:d0dfbce63a89	869	memory by reading the FLASH_ACR register */
elmot	1:d0dfbce63a89	870	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
elmot	1:d0dfbce63a89	871	{
elmot	1:d0dfbce63a89	872	return HAL_ERROR;
elmot	1:d0dfbce63a89	873	}
elmot	1:d0dfbce63a89	874	}
elmot	1:d0dfbce63a89	875
elmot	1:d0dfbce63a89	876	/-------------------------- HCLK Configuration --------------------------/
elmot	1:d0dfbce63a89	877	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
elmot	1:d0dfbce63a89	878	{
elmot	1:d0dfbce63a89	879	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
elmot	1:d0dfbce63a89	880	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
elmot	1:d0dfbce63a89	881	}
elmot	1:d0dfbce63a89	882
elmot	1:d0dfbce63a89	883	/------------------------- SYSCLK Configuration ---------------------------/
elmot	1:d0dfbce63a89	884	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
elmot	1:d0dfbce63a89	885	{
elmot	1:d0dfbce63a89	886	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
elmot	1:d0dfbce63a89	887
elmot	1:d0dfbce63a89	888	/* HSE is selected as System Clock Source */
elmot	1:d0dfbce63a89	889	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
elmot	1:d0dfbce63a89	890	{
elmot	1:d0dfbce63a89	891	/* Check the HSE ready flag */
elmot	1:d0dfbce63a89	892	if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET)
elmot	1:d0dfbce63a89	893	{
elmot	1:d0dfbce63a89	894	return HAL_ERROR;
elmot	1:d0dfbce63a89	895	}
elmot	1:d0dfbce63a89	896	}
elmot	1:d0dfbce63a89	897	/* PLL is selected as System Clock Source */
elmot	1:d0dfbce63a89	898	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
elmot	1:d0dfbce63a89	899	{
elmot	1:d0dfbce63a89	900	/* Check the PLL ready flag */
elmot	1:d0dfbce63a89	901	if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET)
elmot	1:d0dfbce63a89	902	{
elmot	1:d0dfbce63a89	903	return HAL_ERROR;
elmot	1:d0dfbce63a89	904	}
elmot	1:d0dfbce63a89	905	}
elmot	1:d0dfbce63a89	906	/* MSI is selected as System Clock Source */
elmot	1:d0dfbce63a89	907	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
elmot	1:d0dfbce63a89	908	{
elmot	1:d0dfbce63a89	909	/* Check the MSI ready flag */
elmot	1:d0dfbce63a89	910	if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET)
elmot	1:d0dfbce63a89	911	{
elmot	1:d0dfbce63a89	912	return HAL_ERROR;
elmot	1:d0dfbce63a89	913	}
elmot	1:d0dfbce63a89	914	}
elmot	1:d0dfbce63a89	915	/* HSI is selected as System Clock Source */
elmot	1:d0dfbce63a89	916	else
elmot	1:d0dfbce63a89	917	{
elmot	1:d0dfbce63a89	918	/* Check the HSI ready flag */
elmot	1:d0dfbce63a89	919	if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
elmot	1:d0dfbce63a89	920	{
elmot	1:d0dfbce63a89	921	return HAL_ERROR;
elmot	1:d0dfbce63a89	922	}
elmot	1:d0dfbce63a89	923	}
elmot	1:d0dfbce63a89	924	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
elmot	1:d0dfbce63a89	925
elmot	1:d0dfbce63a89	926	/* Get Start Tick*/
elmot	1:d0dfbce63a89	927	tickstart = HAL_GetTick();
elmot	1:d0dfbce63a89	928
elmot	1:d0dfbce63a89	929	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
elmot	1:d0dfbce63a89	930	{
elmot	1:d0dfbce63a89	931	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
elmot	1:d0dfbce63a89	932	{
elmot	1:d0dfbce63a89	933	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	934	{
elmot	1:d0dfbce63a89	935	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	936	}
elmot	1:d0dfbce63a89	937	}
elmot	1:d0dfbce63a89	938	}
elmot	1:d0dfbce63a89	939	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
elmot	1:d0dfbce63a89	940	{
elmot	1:d0dfbce63a89	941	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
elmot	1:d0dfbce63a89	942	{
elmot	1:d0dfbce63a89	943	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	944	{
elmot	1:d0dfbce63a89	945	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	946	}
elmot	1:d0dfbce63a89	947	}
elmot	1:d0dfbce63a89	948	}
elmot	1:d0dfbce63a89	949	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
elmot	1:d0dfbce63a89	950	{
elmot	1:d0dfbce63a89	951	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
elmot	1:d0dfbce63a89	952	{
elmot	1:d0dfbce63a89	953	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	954	{
elmot	1:d0dfbce63a89	955	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	956	}
elmot	1:d0dfbce63a89	957	}
elmot	1:d0dfbce63a89	958	}
elmot	1:d0dfbce63a89	959	else
elmot	1:d0dfbce63a89	960	{
elmot	1:d0dfbce63a89	961	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
elmot	1:d0dfbce63a89	962	{
elmot	1:d0dfbce63a89	963	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
elmot	1:d0dfbce63a89	964	{
elmot	1:d0dfbce63a89	965	return HAL_TIMEOUT;
elmot	1:d0dfbce63a89	966	}
elmot	1:d0dfbce63a89	967	}
elmot	1:d0dfbce63a89	968	}
elmot	1:d0dfbce63a89	969	}
elmot	1:d0dfbce63a89	970
elmot	1:d0dfbce63a89	971	/* Decreasing the number of wait states because of lower CPU frequency */
elmot	1:d0dfbce63a89	972	if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
elmot	1:d0dfbce63a89	973	{
elmot	1:d0dfbce63a89	974	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
elmot	1:d0dfbce63a89	975	__HAL_FLASH_SET_LATENCY(FLatency);
elmot	1:d0dfbce63a89	976
elmot	1:d0dfbce63a89	977	/* Check that the new number of wait states is taken into account to access the Flash
elmot	1:d0dfbce63a89	978	memory by reading the FLASH_ACR register */
elmot	1:d0dfbce63a89	979	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
elmot	1:d0dfbce63a89	980	{
elmot	1:d0dfbce63a89	981	return HAL_ERROR;
elmot	1:d0dfbce63a89	982	}
elmot	1:d0dfbce63a89	983	}
elmot	1:d0dfbce63a89	984
elmot	1:d0dfbce63a89	985	/-------------------------- PCLK1 Configuration ---------------------------/
elmot	1:d0dfbce63a89	986	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
elmot	1:d0dfbce63a89	987	{
elmot	1:d0dfbce63a89	988	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
elmot	1:d0dfbce63a89	989	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
elmot	1:d0dfbce63a89	990	}
elmot	1:d0dfbce63a89	991
elmot	1:d0dfbce63a89	992	/-------------------------- PCLK2 Configuration ---------------------------/
elmot	1:d0dfbce63a89	993	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
elmot	1:d0dfbce63a89	994	{
elmot	1:d0dfbce63a89	995	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
elmot	1:d0dfbce63a89	996	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
elmot	1:d0dfbce63a89	997	}
elmot	1:d0dfbce63a89	998
elmot	1:d0dfbce63a89	999	/* Update the SystemCoreClock global variable */
elmot	1:d0dfbce63a89	1000	SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
elmot	1:d0dfbce63a89	1001
elmot	1:d0dfbce63a89	1002	/* Configure the source of time base considering new system clocks settings*/
elmot	1:d0dfbce63a89	1003	HAL_InitTick (TICK_INT_PRIORITY);
elmot	1:d0dfbce63a89	1004
elmot	1:d0dfbce63a89	1005	return HAL_OK;
elmot	1:d0dfbce63a89	1006	}
elmot	1:d0dfbce63a89	1007
elmot	1:d0dfbce63a89	1008	/**
elmot	1:d0dfbce63a89	1009	* @}
elmot	1:d0dfbce63a89	1010	*/
elmot	1:d0dfbce63a89	1011
elmot	1:d0dfbce63a89	1012	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
elmot	1:d0dfbce63a89	1013	* @brief RCC clocks control functions
elmot	1:d0dfbce63a89	1014	*
elmot	1:d0dfbce63a89	1015	@verbatim
elmot	1:d0dfbce63a89	1016	===============================================================================
elmot	1:d0dfbce63a89	1017	##### Peripheral Control functions #####
elmot	1:d0dfbce63a89	1018	===============================================================================
elmot	1:d0dfbce63a89	1019	[..]
elmot	1:d0dfbce63a89	1020	This subsection provides a set of functions allowing to:
elmot	1:d0dfbce63a89	1021
elmot	1:d0dfbce63a89	1022	(+) Ouput clock to MCO pin.
elmot	1:d0dfbce63a89	1023	(+) Retrieve current clock frequencies.
elmot	1:d0dfbce63a89	1024	(+) Enable the Clock Security System.
elmot	1:d0dfbce63a89	1025
elmot	1:d0dfbce63a89	1026	@endverbatim
elmot	1:d0dfbce63a89	1027	* @{
elmot	1:d0dfbce63a89	1028	*/
elmot	1:d0dfbce63a89	1029
elmot	1:d0dfbce63a89	1030	/**
elmot	1:d0dfbce63a89	1031	* @brief Select the clock source to output on MCO pin(PA8).
elmot	1:d0dfbce63a89	1032	* @note PA8 should be configured in alternate function mode.
elmot	1:d0dfbce63a89	1033	* @param RCC_MCOx specifies the output direction for the clock source.
elmot	1:d0dfbce63a89	1034	* For STM32L4xx family this parameter can have only one value:
elmot	1:d0dfbce63a89	1035	* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
elmot	1:d0dfbce63a89	1036	* @param RCC_MCOSource specifies the clock source to output.
elmot	1:d0dfbce63a89	1037	* This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1038	* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
elmot	1:d0dfbce63a89	1039	* @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
elmot	1:d0dfbce63a89	1040	* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
elmot	1:d0dfbce63a89	1041	* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
elmot	1:d0dfbce63a89	1042	* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
elmot	1:d0dfbce63a89	1043	* @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
elmot	1:d0dfbce63a89	1044	* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
elmot	1:d0dfbce63a89	1045	* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
elmot	1:d0dfbce63a89	1046	@if STM32L443xx
elmot	1:d0dfbce63a89	1047	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
elmot	1:d0dfbce63a89	1048	@endif
elmot	1:d0dfbce63a89	1049	* @param RCC_MCODiv specifies the MCO prescaler.
elmot	1:d0dfbce63a89	1050	* This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1051	* @arg @ref RCC_MCODIV_1 no division applied to MCO clock
elmot	1:d0dfbce63a89	1052	* @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
elmot	1:d0dfbce63a89	1053	* @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
elmot	1:d0dfbce63a89	1054	* @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
elmot	1:d0dfbce63a89	1055	* @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
elmot	1:d0dfbce63a89	1056	* @retval None
elmot	1:d0dfbce63a89	1057	*/
elmot	1:d0dfbce63a89	1058	void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
elmot	1:d0dfbce63a89	1059	{
elmot	1:d0dfbce63a89	1060	GPIO_InitTypeDef GPIO_InitStruct;
elmot	1:d0dfbce63a89	1061	/* Check the parameters */
elmot	1:d0dfbce63a89	1062	assert_param(IS_RCC_MCO(RCC_MCOx));
elmot	1:d0dfbce63a89	1063	assert_param(IS_RCC_MCODIV(RCC_MCODiv));
elmot	1:d0dfbce63a89	1064	assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
elmot	1:d0dfbce63a89	1065
elmot	1:d0dfbce63a89	1066	/* MCO Clock Enable */
elmot	1:d0dfbce63a89	1067	__MCO1_CLK_ENABLE();
elmot	1:d0dfbce63a89	1068
elmot	1:d0dfbce63a89	1069	/* Configue the MCO1 pin in alternate function mode */
elmot	1:d0dfbce63a89	1070	GPIO_InitStruct.Pin = MCO1_PIN;
elmot	1:d0dfbce63a89	1071	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
elmot	1:d0dfbce63a89	1072	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
elmot	1:d0dfbce63a89	1073	GPIO_InitStruct.Pull = GPIO_NOPULL;
elmot	1:d0dfbce63a89	1074	GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
elmot	1:d0dfbce63a89	1075	HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
elmot	1:d0dfbce63a89	1076
elmot	1:d0dfbce63a89	1077	/* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */
elmot	1:d0dfbce63a89	1078	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE), (RCC_MCOSource \| RCC_MCODiv ));
elmot	1:d0dfbce63a89	1079	}
elmot	1:d0dfbce63a89	1080
elmot	1:d0dfbce63a89	1081	/**
elmot	1:d0dfbce63a89	1082	* @brief Return the SYSCLK frequency.
elmot	1:d0dfbce63a89	1083	*
elmot	1:d0dfbce63a89	1084	* @note The system frequency computed by this function is not the real
elmot	1:d0dfbce63a89	1085	* frequency in the chip. It is calculated based on the predefined
elmot	1:d0dfbce63a89	1086	* constant and the selected clock source:
elmot	1:d0dfbce63a89	1087	* @note If SYSCLK source is MSI, function returns values based on MSI
elmot	1:d0dfbce63a89	1088	* Value as defined by the MSI range.
elmot	1:d0dfbce63a89	1089	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
elmot	1:d0dfbce63a89	1090	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
elmot	1:d0dfbce63a89	1091	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
elmot	1:d0dfbce63a89	1092	* HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
elmot	1:d0dfbce63a89	1093	* @note (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
elmot	1:d0dfbce63a89	1094	* 16 MHz) but the real value may vary depending on the variations
elmot	1:d0dfbce63a89	1095	* in voltage and temperature.
elmot	1:d0dfbce63a89	1096	* @note (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
elmot	1:d0dfbce63a89	1097	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
elmot	1:d0dfbce63a89	1098	* frequency of the crystal used. Otherwise, this function may
elmot	1:d0dfbce63a89	1099	* have wrong result.
elmot	1:d0dfbce63a89	1100	*
elmot	1:d0dfbce63a89	1101	* @note The result of this function could be not correct when using fractional
elmot	1:d0dfbce63a89	1102	* value for HSE crystal.
elmot	1:d0dfbce63a89	1103	*
elmot	1:d0dfbce63a89	1104	* @note This function can be used by the user application to compute the
elmot	1:d0dfbce63a89	1105	* baudrate for the communication peripherals or configure other parameters.
elmot	1:d0dfbce63a89	1106	*
elmot	1:d0dfbce63a89	1107	* @note Each time SYSCLK changes, this function must be called to update the
elmot	1:d0dfbce63a89	1108	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
elmot	1:d0dfbce63a89	1109	*
elmot	1:d0dfbce63a89	1110	*
elmot	1:d0dfbce63a89	1111	* @retval SYSCLK frequency
elmot	1:d0dfbce63a89	1112	*/
elmot	1:d0dfbce63a89	1113	uint32_t HAL_RCC_GetSysClockFreq(void)
elmot	1:d0dfbce63a89	1114	{
elmot	1:d0dfbce63a89	1115	uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U;
elmot	1:d0dfbce63a89	1116	uint32_t sysclockfreq = 0U;
elmot	1:d0dfbce63a89	1117
elmot	1:d0dfbce63a89	1118	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) \|\|
elmot	1:d0dfbce63a89	1119	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)))
elmot	1:d0dfbce63a89	1120	{
elmot	1:d0dfbce63a89	1121	/* MSI or PLL with MSI source used as system clock source */
elmot	1:d0dfbce63a89	1122
elmot	1:d0dfbce63a89	1123	/* Get SYSCLK source */
elmot	1:d0dfbce63a89	1124	if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET)
elmot	1:d0dfbce63a89	1125	{ /* MSISRANGE from RCC_CSR applies */
elmot	1:d0dfbce63a89	1126	msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> POSITION_VAL(RCC_CSR_MSISRANGE);
elmot	1:d0dfbce63a89	1127	}
elmot	1:d0dfbce63a89	1128	else
elmot	1:d0dfbce63a89	1129	{ /* MSIRANGE from RCC_CR applies */
elmot	1:d0dfbce63a89	1130	msirange = (RCC->CR & RCC_CR_MSIRANGE) >> POSITION_VAL(RCC_CR_MSIRANGE);
elmot	1:d0dfbce63a89	1131	}
elmot	1:d0dfbce63a89	1132	/MSI frequency range in HZ/
elmot	1:d0dfbce63a89	1133	msirange = MSIRangeTable[msirange];
elmot	1:d0dfbce63a89	1134
elmot	1:d0dfbce63a89	1135	if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI)
elmot	1:d0dfbce63a89	1136	{
elmot	1:d0dfbce63a89	1137	/* MSI used as system clock source */
elmot	1:d0dfbce63a89	1138	sysclockfreq = msirange;
elmot	1:d0dfbce63a89	1139	}
elmot	1:d0dfbce63a89	1140	}
elmot	1:d0dfbce63a89	1141	else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
elmot	1:d0dfbce63a89	1142	{
elmot	1:d0dfbce63a89	1143	/* HSI used as system clock source */
elmot	1:d0dfbce63a89	1144	sysclockfreq = HSI_VALUE;
elmot	1:d0dfbce63a89	1145	}
elmot	1:d0dfbce63a89	1146	else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
elmot	1:d0dfbce63a89	1147	{
elmot	1:d0dfbce63a89	1148	/* HSE used as system clock source */
elmot	1:d0dfbce63a89	1149	sysclockfreq = HSE_VALUE;
elmot	1:d0dfbce63a89	1150	}
elmot	1:d0dfbce63a89	1151
elmot	1:d0dfbce63a89	1152	if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
elmot	1:d0dfbce63a89	1153	{
elmot	1:d0dfbce63a89	1154	/* PLL used as system clock source */
elmot	1:d0dfbce63a89	1155
elmot	1:d0dfbce63a89	1156	/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
elmot	1:d0dfbce63a89	1157	SYSCLK = PLL_VCO / PLLR
elmot	1:d0dfbce63a89	1158	*/
elmot	1:d0dfbce63a89	1159	pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
elmot	1:d0dfbce63a89	1160	pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U ;
elmot	1:d0dfbce63a89	1161
elmot	1:d0dfbce63a89	1162	switch (pllsource)
elmot	1:d0dfbce63a89	1163	{
elmot	1:d0dfbce63a89	1164	case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
elmot	1:d0dfbce63a89	1165	pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
elmot	1:d0dfbce63a89	1166	break;
elmot	1:d0dfbce63a89	1167
elmot	1:d0dfbce63a89	1168	case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
elmot	1:d0dfbce63a89	1169	pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
elmot	1:d0dfbce63a89	1170	break;
elmot	1:d0dfbce63a89	1171
elmot	1:d0dfbce63a89	1172	case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
elmot	1:d0dfbce63a89	1173	default:
elmot	1:d0dfbce63a89	1174	pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
elmot	1:d0dfbce63a89	1175	break;
elmot	1:d0dfbce63a89	1176	}
elmot	1:d0dfbce63a89	1177	pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U ) * 2U;
elmot	1:d0dfbce63a89	1178	sysclockfreq = pllvco/pllr;
elmot	1:d0dfbce63a89	1179	}
elmot	1:d0dfbce63a89	1180
elmot	1:d0dfbce63a89	1181	return sysclockfreq;
elmot	1:d0dfbce63a89	1182	}
elmot	1:d0dfbce63a89	1183
elmot	1:d0dfbce63a89	1184	/**
elmot	1:d0dfbce63a89	1185	* @brief Return the HCLK frequency.
elmot	1:d0dfbce63a89	1186	* @note Each time HCLK changes, this function must be called to update the
elmot	1:d0dfbce63a89	1187	* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
elmot	1:d0dfbce63a89	1188	*
elmot	1:d0dfbce63a89	1189	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
elmot	1:d0dfbce63a89	1190	* @retval HCLK frequency in Hz
elmot	1:d0dfbce63a89	1191	*/
elmot	1:d0dfbce63a89	1192	uint32_t HAL_RCC_GetHCLKFreq(void)
elmot	1:d0dfbce63a89	1193	{
elmot	1:d0dfbce63a89	1194	return SystemCoreClock;
elmot	1:d0dfbce63a89	1195	}
elmot	1:d0dfbce63a89	1196
elmot	1:d0dfbce63a89	1197	/**
elmot	1:d0dfbce63a89	1198	* @brief Return the PCLK1 frequency.
elmot	1:d0dfbce63a89	1199	* @note Each time PCLK1 changes, this function must be called to update the
elmot	1:d0dfbce63a89	1200	* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
elmot	1:d0dfbce63a89	1201	* @retval PCLK1 frequency in Hz
elmot	1:d0dfbce63a89	1202	*/
elmot	1:d0dfbce63a89	1203	uint32_t HAL_RCC_GetPCLK1Freq(void)
elmot	1:d0dfbce63a89	1204	{
elmot	1:d0dfbce63a89	1205	/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
elmot	1:d0dfbce63a89	1206	return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
elmot	1:d0dfbce63a89	1207	}
elmot	1:d0dfbce63a89	1208
elmot	1:d0dfbce63a89	1209	/**
elmot	1:d0dfbce63a89	1210	* @brief Return the PCLK2 frequency.
elmot	1:d0dfbce63a89	1211	* @note Each time PCLK2 changes, this function must be called to update the
elmot	1:d0dfbce63a89	1212	* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
elmot	1:d0dfbce63a89	1213	* @retval PCLK2 frequency in Hz
elmot	1:d0dfbce63a89	1214	*/
elmot	1:d0dfbce63a89	1215	uint32_t HAL_RCC_GetPCLK2Freq(void)
elmot	1:d0dfbce63a89	1216	{
elmot	1:d0dfbce63a89	1217	/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
elmot	1:d0dfbce63a89	1218	return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
elmot	1:d0dfbce63a89	1219	}
elmot	1:d0dfbce63a89	1220
elmot	1:d0dfbce63a89	1221	/**
elmot	1:d0dfbce63a89	1222	* @brief Configure the RCC_OscInitStruct according to the internal
elmot	1:d0dfbce63a89	1223	* RCC configuration registers.
elmot	1:d0dfbce63a89	1224	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
elmot	1:d0dfbce63a89	1225	* will be configured.
elmot	1:d0dfbce63a89	1226	* @retval None
elmot	1:d0dfbce63a89	1227	*/
elmot	1:d0dfbce63a89	1228	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
elmot	1:d0dfbce63a89	1229	{
elmot	1:d0dfbce63a89	1230	/* Check the parameters */
elmot	1:d0dfbce63a89	1231	assert_param(RCC_OscInitStruct != NULL);
elmot	1:d0dfbce63a89	1232
elmot	1:d0dfbce63a89	1233	/* Set all possible values for the Oscillator type parameter ---------------*/
elmot	1:d0dfbce63a89	1234	#if defined(RCC_HSI48_SUPPORT)
elmot	1:d0dfbce63a89	1235	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_MSI \| \
elmot	1:d0dfbce63a89	1236	RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI \| RCC_OSCILLATORTYPE_HSI48;
elmot	1:d0dfbce63a89	1237	#else
elmot	1:d0dfbce63a89	1238	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_MSI \| \
elmot	1:d0dfbce63a89	1239	RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
elmot	1:d0dfbce63a89	1240	#endif /* RCC_HSI48_SUPPORT */
elmot	1:d0dfbce63a89	1241
elmot	1:d0dfbce63a89	1242	/* Get the HSE configuration -----------------------------------------------*/
elmot	1:d0dfbce63a89	1243	if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
elmot	1:d0dfbce63a89	1244	{
elmot	1:d0dfbce63a89	1245	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
elmot	1:d0dfbce63a89	1246	}
elmot	1:d0dfbce63a89	1247	else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
elmot	1:d0dfbce63a89	1248	{
elmot	1:d0dfbce63a89	1249	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
elmot	1:d0dfbce63a89	1250	}
elmot	1:d0dfbce63a89	1251	else
elmot	1:d0dfbce63a89	1252	{
elmot	1:d0dfbce63a89	1253	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
elmot	1:d0dfbce63a89	1254	}
elmot	1:d0dfbce63a89	1255
elmot	1:d0dfbce63a89	1256	/* Get the MSI configuration -----------------------------------------------*/
elmot	1:d0dfbce63a89	1257	if((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION)
elmot	1:d0dfbce63a89	1258	{
elmot	1:d0dfbce63a89	1259	RCC_OscInitStruct->MSIState = RCC_MSI_ON;
elmot	1:d0dfbce63a89	1260	}
elmot	1:d0dfbce63a89	1261	else
elmot	1:d0dfbce63a89	1262	{
elmot	1:d0dfbce63a89	1263	RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
elmot	1:d0dfbce63a89	1264	}
elmot	1:d0dfbce63a89	1265
elmot	1:d0dfbce63a89	1266	RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM));
elmot	1:d0dfbce63a89	1267	RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_CR_MSIRANGE) );
elmot	1:d0dfbce63a89	1268
elmot	1:d0dfbce63a89	1269	/* Get the HSI configuration -----------------------------------------------*/
elmot	1:d0dfbce63a89	1270	if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
elmot	1:d0dfbce63a89	1271	{
elmot	1:d0dfbce63a89	1272	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
elmot	1:d0dfbce63a89	1273	}
elmot	1:d0dfbce63a89	1274	else
elmot	1:d0dfbce63a89	1275	{
elmot	1:d0dfbce63a89	1276	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
elmot	1:d0dfbce63a89	1277	}
elmot	1:d0dfbce63a89	1278
elmot	1:d0dfbce63a89	1279	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM));
elmot	1:d0dfbce63a89	1280
elmot	1:d0dfbce63a89	1281	/* Get the LSE configuration -----------------------------------------------*/
elmot	1:d0dfbce63a89	1282	if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
elmot	1:d0dfbce63a89	1283	{
elmot	1:d0dfbce63a89	1284	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
elmot	1:d0dfbce63a89	1285	}
elmot	1:d0dfbce63a89	1286	else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
elmot	1:d0dfbce63a89	1287	{
elmot	1:d0dfbce63a89	1288	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
elmot	1:d0dfbce63a89	1289	}
elmot	1:d0dfbce63a89	1290	else
elmot	1:d0dfbce63a89	1291	{
elmot	1:d0dfbce63a89	1292	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
elmot	1:d0dfbce63a89	1293	}
elmot	1:d0dfbce63a89	1294
elmot	1:d0dfbce63a89	1295	/* Get the LSI configuration -----------------------------------------------*/
elmot	1:d0dfbce63a89	1296	if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
elmot	1:d0dfbce63a89	1297	{
elmot	1:d0dfbce63a89	1298	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
elmot	1:d0dfbce63a89	1299	}
elmot	1:d0dfbce63a89	1300	else
elmot	1:d0dfbce63a89	1301	{
elmot	1:d0dfbce63a89	1302	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
elmot	1:d0dfbce63a89	1303	}
elmot	1:d0dfbce63a89	1304
elmot	1:d0dfbce63a89	1305	#if defined(RCC_HSI48_SUPPORT)
elmot	1:d0dfbce63a89	1306	/* Get the HSI48 configuration ---------------------------------------------*/
elmot	1:d0dfbce63a89	1307	if((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
elmot	1:d0dfbce63a89	1308	{
elmot	1:d0dfbce63a89	1309	RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
elmot	1:d0dfbce63a89	1310	}
elmot	1:d0dfbce63a89	1311	else
elmot	1:d0dfbce63a89	1312	{
elmot	1:d0dfbce63a89	1313	RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
elmot	1:d0dfbce63a89	1314	}
elmot	1:d0dfbce63a89	1315	#else
elmot	1:d0dfbce63a89	1316	RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
elmot	1:d0dfbce63a89	1317	#endif /* RCC_HSI48_SUPPORT */
elmot	1:d0dfbce63a89	1318
elmot	1:d0dfbce63a89	1319	/* Get the PLL configuration -----------------------------------------------*/
elmot	1:d0dfbce63a89	1320	if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
elmot	1:d0dfbce63a89	1321	{
elmot	1:d0dfbce63a89	1322	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
elmot	1:d0dfbce63a89	1323	}
elmot	1:d0dfbce63a89	1324	else
elmot	1:d0dfbce63a89	1325	{
elmot	1:d0dfbce63a89	1326	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
elmot	1:d0dfbce63a89	1327	}
elmot	1:d0dfbce63a89	1328	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
elmot	1:d0dfbce63a89	1329	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U);
elmot	1:d0dfbce63a89	1330	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
elmot	1:d0dfbce63a89	1331	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
elmot	1:d0dfbce63a89	1332	RCC_OscInitStruct->PLL.PLLR = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U) << 1U);
elmot	1:d0dfbce63a89	1333	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
elmot	1:d0dfbce63a89	1334	RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV));
elmot	1:d0dfbce63a89	1335	#else
elmot	1:d0dfbce63a89	1336	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) != RESET)
elmot	1:d0dfbce63a89	1337	{
elmot	1:d0dfbce63a89	1338	RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17;
elmot	1:d0dfbce63a89	1339	}
elmot	1:d0dfbce63a89	1340	else
elmot	1:d0dfbce63a89	1341	{
elmot	1:d0dfbce63a89	1342	RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7;
elmot	1:d0dfbce63a89	1343	}
elmot	1:d0dfbce63a89	1344	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
elmot	1:d0dfbce63a89	1345	}
elmot	1:d0dfbce63a89	1346
elmot	1:d0dfbce63a89	1347	/**
elmot	1:d0dfbce63a89	1348	* @brief Configure the RCC_ClkInitStruct according to the internal
elmot	1:d0dfbce63a89	1349	* RCC configuration registers.
elmot	1:d0dfbce63a89	1350	* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
elmot	1:d0dfbce63a89	1351	* will be configured.
elmot	1:d0dfbce63a89	1352	* @param pFLatency Pointer on the Flash Latency.
elmot	1:d0dfbce63a89	1353	* @retval None
elmot	1:d0dfbce63a89	1354	*/
elmot	1:d0dfbce63a89	1355	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)
elmot	1:d0dfbce63a89	1356	{
elmot	1:d0dfbce63a89	1357	/* Check the parameters */
elmot	1:d0dfbce63a89	1358	assert_param(RCC_ClkInitStruct != NULL);
elmot	1:d0dfbce63a89	1359	assert_param(pFLatency != NULL);
elmot	1:d0dfbce63a89	1360
elmot	1:d0dfbce63a89	1361	/* Set all possible values for the Clock type parameter --------------------*/
elmot	1:d0dfbce63a89	1362	RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2;
elmot	1:d0dfbce63a89	1363
elmot	1:d0dfbce63a89	1364	/* Get the SYSCLK configuration --------------------------------------------*/
elmot	1:d0dfbce63a89	1365	RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
elmot	1:d0dfbce63a89	1366
elmot	1:d0dfbce63a89	1367	/* Get the HCLK configuration ----------------------------------------------*/
elmot	1:d0dfbce63a89	1368	RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
elmot	1:d0dfbce63a89	1369
elmot	1:d0dfbce63a89	1370	/* Get the APB1 configuration ----------------------------------------------*/
elmot	1:d0dfbce63a89	1371	RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
elmot	1:d0dfbce63a89	1372
elmot	1:d0dfbce63a89	1373	/* Get the APB2 configuration ----------------------------------------------*/
elmot	1:d0dfbce63a89	1374	RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
elmot	1:d0dfbce63a89	1375
elmot	1:d0dfbce63a89	1376	/* Get the Flash Wait State (Latency) configuration ------------------------*/
elmot	1:d0dfbce63a89	1377	*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
elmot	1:d0dfbce63a89	1378	}
elmot	1:d0dfbce63a89	1379
elmot	1:d0dfbce63a89	1380	/**
elmot	1:d0dfbce63a89	1381	* @brief Enable the Clock Security System.
elmot	1:d0dfbce63a89	1382	* @note If a failure is detected on the HSE oscillator clock, this oscillator
elmot	1:d0dfbce63a89	1383	* is automatically disabled and an interrupt is generated to inform the
elmot	1:d0dfbce63a89	1384	* software about the failure (Clock Security System Interrupt, CSSI),
elmot	1:d0dfbce63a89	1385	* allowing the MCU to perform rescue operations. The CSSI is linked to
elmot	1:d0dfbce63a89	1386	* the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
elmot	1:d0dfbce63a89	1387	* @note The Clock Security System can only be cleared by reset.
elmot	1:d0dfbce63a89	1388	* @retval None
elmot	1:d0dfbce63a89	1389	*/
elmot	1:d0dfbce63a89	1390	void HAL_RCC_EnableCSS(void)
elmot	1:d0dfbce63a89	1391	{
elmot	1:d0dfbce63a89	1392	SET_BIT(RCC->CR, RCC_CR_CSSON) ;
elmot	1:d0dfbce63a89	1393	}
elmot	1:d0dfbce63a89	1394
elmot	1:d0dfbce63a89	1395	/**
elmot	1:d0dfbce63a89	1396	* @brief Handle the RCC Clock Security System interrupt request.
elmot	1:d0dfbce63a89	1397	* @note This API should be called under the NMI_Handler().
elmot	1:d0dfbce63a89	1398	* @retval None
elmot	1:d0dfbce63a89	1399	*/
elmot	1:d0dfbce63a89	1400	void HAL_RCC_NMI_IRQHandler(void)
elmot	1:d0dfbce63a89	1401	{
elmot	1:d0dfbce63a89	1402	/* Check RCC CSSF interrupt flag */
elmot	1:d0dfbce63a89	1403	if(__HAL_RCC_GET_IT(RCC_IT_CSS))
elmot	1:d0dfbce63a89	1404	{
elmot	1:d0dfbce63a89	1405	/* RCC Clock Security System interrupt user callback */
elmot	1:d0dfbce63a89	1406	HAL_RCC_CSSCallback();
elmot	1:d0dfbce63a89	1407
elmot	1:d0dfbce63a89	1408	/* Clear RCC CSS pending bit */
elmot	1:d0dfbce63a89	1409	__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
elmot	1:d0dfbce63a89	1410	}
elmot	1:d0dfbce63a89	1411	}
elmot	1:d0dfbce63a89	1412
elmot	1:d0dfbce63a89	1413	/**
elmot	1:d0dfbce63a89	1414	* @brief RCC Clock Security System interrupt callback.
elmot	1:d0dfbce63a89	1415	* @retval none
elmot	1:d0dfbce63a89	1416	*/
elmot	1:d0dfbce63a89	1417	__weak void HAL_RCC_CSSCallback(void)
elmot	1:d0dfbce63a89	1418	{
elmot	1:d0dfbce63a89	1419	/* NOTE : This function should not be modified, when the callback is needed,
elmot	1:d0dfbce63a89	1420	the HAL_RCC_CSSCallback should be implemented in the user file
elmot	1:d0dfbce63a89	1421	*/
elmot	1:d0dfbce63a89	1422	}
elmot	1:d0dfbce63a89	1423
elmot	1:d0dfbce63a89	1424	/**
elmot	1:d0dfbce63a89	1425	* @}
elmot	1:d0dfbce63a89	1426	*/
elmot	1:d0dfbce63a89	1427
elmot	1:d0dfbce63a89	1428	/**
elmot	1:d0dfbce63a89	1429	* @}
elmot	1:d0dfbce63a89	1430	*/
elmot	1:d0dfbce63a89	1431
elmot	1:d0dfbce63a89	1432	/* Private function prototypes -----------------------------------------------*/
elmot	1:d0dfbce63a89	1433	/** @addtogroup RCC_Private_Functions
elmot	1:d0dfbce63a89	1434	* @{
elmot	1:d0dfbce63a89	1435	*/
elmot	1:d0dfbce63a89	1436	/**
elmot	1:d0dfbce63a89	1437	* @brief Update number of Flash wait states in line with MSI range and current
elmot	1:d0dfbce63a89	1438	voltage range.
elmot	1:d0dfbce63a89	1439	* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
elmot	1:d0dfbce63a89	1440	* @retval HAL status
elmot	1:d0dfbce63a89	1441	*/
elmot	1:d0dfbce63a89	1442	static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
elmot	1:d0dfbce63a89	1443	{
elmot	1:d0dfbce63a89	1444	uint32_t vos = 0;
elmot	1:d0dfbce63a89	1445	uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
elmot	1:d0dfbce63a89	1446
elmot	1:d0dfbce63a89	1447	if(__HAL_RCC_PWR_IS_CLK_ENABLED())
elmot	1:d0dfbce63a89	1448	{
elmot	1:d0dfbce63a89	1449	vos = HAL_PWREx_GetVoltageRange();
elmot	1:d0dfbce63a89	1450	}
elmot	1:d0dfbce63a89	1451	else
elmot	1:d0dfbce63a89	1452	{
elmot	1:d0dfbce63a89	1453	__HAL_RCC_PWR_CLK_ENABLE();
elmot	1:d0dfbce63a89	1454	vos = HAL_PWREx_GetVoltageRange();
elmot	1:d0dfbce63a89	1455	__HAL_RCC_PWR_CLK_DISABLE();
elmot	1:d0dfbce63a89	1456	}
elmot	1:d0dfbce63a89	1457
elmot	1:d0dfbce63a89	1458	if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
elmot	1:d0dfbce63a89	1459	{
elmot	1:d0dfbce63a89	1460	if(msirange > RCC_MSIRANGE_8)
elmot	1:d0dfbce63a89	1461	{
elmot	1:d0dfbce63a89	1462	/* MSI > 16Mhz */
elmot	1:d0dfbce63a89	1463	if(msirange > RCC_MSIRANGE_10)
elmot	1:d0dfbce63a89	1464	{
elmot	1:d0dfbce63a89	1465	/* MSI 48Mhz */
elmot	1:d0dfbce63a89	1466	latency = FLASH_LATENCY_2; /* 2WS */
elmot	1:d0dfbce63a89	1467	}
elmot	1:d0dfbce63a89	1468	else
elmot	1:d0dfbce63a89	1469	{
elmot	1:d0dfbce63a89	1470	/* MSI 24Mhz or 32Mhz */
elmot	1:d0dfbce63a89	1471	latency = FLASH_LATENCY_1; /* 1WS */
elmot	1:d0dfbce63a89	1472	}
elmot	1:d0dfbce63a89	1473	}
elmot	1:d0dfbce63a89	1474	/* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */
elmot	1:d0dfbce63a89	1475	}
elmot	1:d0dfbce63a89	1476	else
elmot	1:d0dfbce63a89	1477	{
elmot	1:d0dfbce63a89	1478	if(msirange > RCC_MSIRANGE_8)
elmot	1:d0dfbce63a89	1479	{
elmot	1:d0dfbce63a89	1480	/* MSI > 16Mhz */
elmot	1:d0dfbce63a89	1481	latency = FLASH_LATENCY_3; /* 3WS */
elmot	1:d0dfbce63a89	1482	}
elmot	1:d0dfbce63a89	1483	else
elmot	1:d0dfbce63a89	1484	{
elmot	1:d0dfbce63a89	1485	if(msirange == RCC_MSIRANGE_8)
elmot	1:d0dfbce63a89	1486	{
elmot	1:d0dfbce63a89	1487	/* MSI 16Mhz */
elmot	1:d0dfbce63a89	1488	latency = FLASH_LATENCY_2; /* 2WS */
elmot	1:d0dfbce63a89	1489	}
elmot	1:d0dfbce63a89	1490	else if(msirange == RCC_MSIRANGE_7)
elmot	1:d0dfbce63a89	1491	{
elmot	1:d0dfbce63a89	1492	/* MSI 8Mhz */
elmot	1:d0dfbce63a89	1493	latency = FLASH_LATENCY_1; /* 1WS */
elmot	1:d0dfbce63a89	1494	}
elmot	1:d0dfbce63a89	1495	/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
elmot	1:d0dfbce63a89	1496	}
elmot	1:d0dfbce63a89	1497	}
elmot	1:d0dfbce63a89	1498
elmot	1:d0dfbce63a89	1499	__HAL_FLASH_SET_LATENCY(latency);
elmot	1:d0dfbce63a89	1500
elmot	1:d0dfbce63a89	1501	/* Check that the new number of wait states is taken into account to access the Flash
elmot	1:d0dfbce63a89	1502	memory by reading the FLASH_ACR register */
elmot	1:d0dfbce63a89	1503	if((FLASH->ACR & FLASH_ACR_LATENCY) != latency)
elmot	1:d0dfbce63a89	1504	{
elmot	1:d0dfbce63a89	1505	return HAL_ERROR;
elmot	1:d0dfbce63a89	1506	}
elmot	1:d0dfbce63a89	1507
elmot	1:d0dfbce63a89	1508	return HAL_OK;
elmot	1:d0dfbce63a89	1509	}
elmot	1:d0dfbce63a89	1510
elmot	1:d0dfbce63a89	1511	/**
elmot	1:d0dfbce63a89	1512	* @}
elmot	1:d0dfbce63a89	1513	*/
elmot	1:d0dfbce63a89	1514
elmot	1:d0dfbce63a89	1515	#endif /* HAL_RCC_MODULE_ENABLED */
elmot	1:d0dfbce63a89	1516	/**
elmot	1:d0dfbce63a89	1517	* @}
elmot	1:d0dfbce63a89	1518	*/
elmot	1:d0dfbce63a89	1519
elmot	1:d0dfbce63a89	1520	/**
elmot	1:d0dfbce63a89	1521	* @}
elmot	1:d0dfbce63a89	1522	*/
elmot	1:d0dfbce63a89	1523
elmot	1:d0dfbce63a89	1524	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Repository details

Type:	Program
Created:	25 Feb 2017
Imports:	20
Forks:	1
Commits:	3
Dependents:	0
Dependencies:	0
Followers:	10

The code in this repository is Apache licensed.

Important changes to repositories hosted on mbed.com

HAL_L476/stm32l4xx_hal_rcc.c@1:d0dfbce63a89, 2017-02-24 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Important changes to repositories hosted on mbed.com

HAL_L476/stm32l4xx_hal_rcc.c@1:d0dfbce63a89, 2017-02-24 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning