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stm32l4xx_ll_spi.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_spi.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of SPI LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_SPI_H 00040 #define __STM32L4xx_LL_SPI_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined (SPI1) || defined (SPI2) || defined (SPI3) 00054 00055 /** @defgroup SPI_LL SPI 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 /* Private macros ------------------------------------------------------------*/ 00062 00063 /* Exported types ------------------------------------------------------------*/ 00064 #if defined(USE_FULL_LL_DRIVER) 00065 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure 00066 * @{ 00067 */ 00068 00069 /** 00070 * @brief SPI Init structures definition 00071 */ 00072 typedef struct 00073 { 00074 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. 00075 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. 00076 00077 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ 00078 00079 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). 00080 This parameter can be a value of @ref SPI_LL_EC_MODE. 00081 00082 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ 00083 00084 uint32_t DataWidth; /*!< Specifies the SPI data width. 00085 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. 00086 00087 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ 00088 00089 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. 00090 This parameter can be a value of @ref SPI_LL_EC_POLARITY. 00091 00092 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ 00093 00094 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. 00095 This parameter can be a value of @ref SPI_LL_EC_PHASE. 00096 00097 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ 00098 00099 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. 00100 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. 00101 00102 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ 00103 00104 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. 00105 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. 00106 @note The communication clock is derived from the master clock. The slave clock does not need to be set. 00107 00108 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ 00109 00110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. 00111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. 00112 00113 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ 00114 00115 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 00116 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. 00117 00118 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ 00119 00120 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. 00121 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. 00122 00123 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ 00124 00125 } LL_SPI_InitTypeDef; 00126 00127 /** 00128 * @} 00129 */ 00130 #endif /* USE_FULL_LL_DRIVER */ 00131 00132 /* Exported constants --------------------------------------------------------*/ 00133 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants 00134 * @{ 00135 */ 00136 00137 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines 00138 * @brief Flags defines which can be used with LL_SPI_ReadReg function 00139 * @{ 00140 */ 00141 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ 00142 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ 00143 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ 00144 #define LL_SPI_SR_UDR SPI_SR_UDR /*!< Underrun flag */ 00145 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ 00146 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ 00147 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ 00148 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ 00149 /** 00150 * @} 00151 */ 00152 00153 /** @defgroup SPI_LL_EC_IT IT Defines 00154 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions 00155 * @{ 00156 */ 00157 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ 00158 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ 00159 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ 00160 /** 00161 * @} 00162 */ 00163 00164 /** @defgroup SPI_LL_EC_MODE Operation Mode 00165 * @{ 00166 */ 00167 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ 00168 #define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /*!< Slave configuration */ 00169 /** 00170 * @} 00171 */ 00172 00173 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol 00174 * @{ 00175 */ 00176 #define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /*!< Motorola mode. Used as default value */ 00177 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ 00178 /** 00179 * @} 00180 */ 00181 00182 /** @defgroup SPI_LL_EC_PHASE Clock Phase 00183 * @{ 00184 */ 00185 #define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /*!< First clock transition is the first data capture edge */ 00186 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ 00187 /** 00188 * @} 00189 */ 00190 00191 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity 00192 * @{ 00193 */ 00194 #define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock to 0 when idle */ 00195 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ 00196 /** 00197 * @} 00198 */ 00199 00200 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler 00201 * @{ 00202 */ 00203 #define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /*!< BaudRate control equal to fPCLK/2 */ 00204 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ 00205 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ 00206 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ 00207 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ 00208 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ 00209 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ 00210 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ 00211 /** 00212 * @} 00213 */ 00214 00215 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order 00216 * @{ 00217 */ 00218 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ 00219 #define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /*!< Data is transmitted/received with the MSB first */ 00220 /** 00221 * @} 00222 */ 00223 00224 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode 00225 * @{ 00226 */ 00227 #define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ 00228 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ 00229 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ 00230 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ 00231 /** 00232 * @} 00233 */ 00234 00235 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode 00236 * @{ 00237 */ 00238 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ 00239 #define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /*!< NSS pin used in Input. Only used in Master mode */ 00240 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ 00241 /** 00242 * @} 00243 */ 00244 00245 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth 00246 * @{ 00247 */ 00248 #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */ 00249 #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */ 00250 #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */ 00251 #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */ 00252 #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */ 00253 #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */ 00254 #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */ 00255 #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */ 00256 #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */ 00257 #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */ 00258 #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */ 00259 #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */ 00260 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */ 00261 /** 00262 * @} 00263 */ 00264 #if defined(USE_FULL_LL_DRIVER) 00265 00266 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation 00267 * @{ 00268 */ 00269 #define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /*!< CRC calculation disabled */ 00270 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ 00271 /** 00272 * @} 00273 */ 00274 #endif /* USE_FULL_LL_DRIVER */ 00275 00276 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length 00277 * @{ 00278 */ 00279 #define LL_SPI_CRC_8BIT ((uint32_t)0x00000000U) /*!< 8-bit CRC length */ 00280 #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ 00281 /** 00282 * @} 00283 */ 00284 00285 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold 00286 * @{ 00287 */ 00288 #define LL_SPI_RX_FIFO_TH_HALF ((uint32_t)0x00000000U) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ 00289 #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ 00290 /** 00291 * @} 00292 */ 00293 00294 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level 00295 * @{ 00296 */ 00297 #define LL_SPI_RX_FIFO_EMPTY ((uint32_t)0x00000000U) /*!< FIFO reception empty */ 00298 #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ 00299 #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ 00300 #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ 00301 /** 00302 * @} 00303 */ 00304 00305 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level 00306 * @{ 00307 */ 00308 #define LL_SPI_TX_FIFO_EMPTY ((uint32_t)0x00000000U) /*!< FIFO transmission empty */ 00309 #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ 00310 #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ 00311 #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ 00312 /** 00313 * @} 00314 */ 00315 00316 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity 00317 * @{ 00318 */ 00319 #define LL_SPI_DMA_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Select DMA parity Even */ 00320 #define LL_SPI_DMA_PARITY_ODD ((uint32_t)0x00000001U) /*!< Select DMA parity Odd */ 00321 00322 /** 00323 * @} 00324 */ 00325 00326 /** 00327 * @} 00328 */ 00329 00330 /* Exported macro ------------------------------------------------------------*/ 00331 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros 00332 * @{ 00333 */ 00334 00335 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros 00336 * @{ 00337 */ 00338 00339 /** 00340 * @brief Write a value in SPI register 00341 * @param __INSTANCE__ SPI Instance 00342 * @param __REG__ Register to be written 00343 * @param __VALUE__ Value to be written in the register 00344 * @retval None 00345 */ 00346 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00347 00348 /** 00349 * @brief Read a value in SPI register 00350 * @param __INSTANCE__ SPI Instance 00351 * @param __REG__ Register to be read 00352 * @retval Register value 00353 */ 00354 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00355 /** 00356 * @} 00357 */ 00358 00359 /** 00360 * @} 00361 */ 00362 00363 /* Exported functions --------------------------------------------------------*/ 00364 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions 00365 * @{ 00366 */ 00367 00368 /** @defgroup SPI_LL_EF_Configuration Configuration 00369 * @{ 00370 */ 00371 00372 /** 00373 * @brief Enable SPI peripheral 00374 * @rmtoll CR1 SPE LL_SPI_Enable 00375 * @param SPIx SPI Instance 00376 * @retval None 00377 */ 00378 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) 00379 { 00380 SET_BIT(SPIx->CR1, SPI_CR1_SPE); 00381 } 00382 00383 /** 00384 * @brief Disable SPI peripheral 00385 * @note When disabling the SPI, follow the procedure described in the Reference Manual. 00386 * @rmtoll CR1 SPE LL_SPI_Disable 00387 * @param SPIx SPI Instance 00388 * @retval None 00389 */ 00390 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) 00391 { 00392 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 00393 } 00394 00395 /** 00396 * @brief Check if SPI peripheral is enabled 00397 * @rmtoll CR1 SPE LL_SPI_IsEnabled 00398 * @param SPIx SPI Instance 00399 * @retval State of bit (1 or 0). 00400 */ 00401 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) 00402 { 00403 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)); 00404 } 00405 00406 /** 00407 * @brief Set SPI operation mode to Master or Slave 00408 * @note This bit should not be changed when communication is ongoing. 00409 * @rmtoll CR1 MSTR LL_SPI_SetMode\n 00410 * CR1 SSI LL_SPI_SetMode 00411 * @param SPIx SPI Instance 00412 * @param Mode This parameter can be one of the following values: 00413 * @arg @ref LL_SPI_MODE_MASTER 00414 * @arg @ref LL_SPI_MODE_SLAVE 00415 * @retval None 00416 */ 00417 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) 00418 { 00419 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); 00420 } 00421 00422 /** 00423 * @brief Get SPI operation mode (Master or Slave) 00424 * @rmtoll CR1 MSTR LL_SPI_GetMode\n 00425 * CR1 SSI LL_SPI_GetMode 00426 * @param SPIx SPI Instance 00427 * @retval Returned value can be one of the following values: 00428 * @arg @ref LL_SPI_MODE_MASTER 00429 * @arg @ref LL_SPI_MODE_SLAVE 00430 */ 00431 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) 00432 { 00433 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); 00434 } 00435 00436 /** 00437 * @brief Set serial protocol used 00438 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00439 * @rmtoll CR2 FRF LL_SPI_SetStandard 00440 * @param SPIx SPI Instance 00441 * @param Standard This parameter can be one of the following values: 00442 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 00443 * @arg @ref LL_SPI_PROTOCOL_TI 00444 * @retval None 00445 */ 00446 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) 00447 { 00448 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); 00449 } 00450 00451 /** 00452 * @brief Get serial protocol used 00453 * @rmtoll CR2 FRF LL_SPI_GetStandard 00454 * @param SPIx SPI Instance 00455 * @retval Returned value can be one of the following values: 00456 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 00457 * @arg @ref LL_SPI_PROTOCOL_TI 00458 */ 00459 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) 00460 { 00461 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); 00462 } 00463 00464 /** 00465 * @brief Set clock phase 00466 * @note This bit should not be changed when communication is ongoing. 00467 * This bit is not used in SPI TI mode. 00468 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase 00469 * @param SPIx SPI Instance 00470 * @param ClockPhase This parameter can be one of the following values: 00471 * @arg @ref LL_SPI_PHASE_1EDGE 00472 * @arg @ref LL_SPI_PHASE_2EDGE 00473 * @retval None 00474 */ 00475 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) 00476 { 00477 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); 00478 } 00479 00480 /** 00481 * @brief Get clock phase 00482 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase 00483 * @param SPIx SPI Instance 00484 * @retval Returned value can be one of the following values: 00485 * @arg @ref LL_SPI_PHASE_1EDGE 00486 * @arg @ref LL_SPI_PHASE_2EDGE 00487 */ 00488 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) 00489 { 00490 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); 00491 } 00492 00493 /** 00494 * @brief Set clock polarity 00495 * @note This bit should not be changed when communication is ongoing. 00496 * This bit is not used in SPI TI mode. 00497 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity 00498 * @param SPIx SPI Instance 00499 * @param ClockPolarity This parameter can be one of the following values: 00500 * @arg @ref LL_SPI_POLARITY_LOW 00501 * @arg @ref LL_SPI_POLARITY_HIGH 00502 * @retval None 00503 */ 00504 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) 00505 { 00506 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); 00507 } 00508 00509 /** 00510 * @brief Get clock polarity 00511 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity 00512 * @param SPIx SPI Instance 00513 * @retval Returned value can be one of the following values: 00514 * @arg @ref LL_SPI_POLARITY_LOW 00515 * @arg @ref LL_SPI_POLARITY_HIGH 00516 */ 00517 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) 00518 { 00519 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); 00520 } 00521 00522 /** 00523 * @brief Set baud rate prescaler 00524 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. 00525 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler 00526 * @param SPIx SPI Instance 00527 * @param BaudRate This parameter can be one of the following values: 00528 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 00529 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 00530 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 00531 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 00532 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 00533 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 00534 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 00535 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 00536 * @retval None 00537 */ 00538 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) 00539 { 00540 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); 00541 } 00542 00543 /** 00544 * @brief Get baud rate prescaler 00545 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler 00546 * @param SPIx SPI Instance 00547 * @retval Returned value can be one of the following values: 00548 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 00549 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 00550 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 00551 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 00552 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 00553 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 00554 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 00555 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 00556 */ 00557 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) 00558 { 00559 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); 00560 } 00561 00562 /** 00563 * @brief Set transfer bit order 00564 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00565 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder 00566 * @param SPIx SPI Instance 00567 * @param BitOrder This parameter can be one of the following values: 00568 * @arg @ref LL_SPI_LSB_FIRST 00569 * @arg @ref LL_SPI_MSB_FIRST 00570 * @retval None 00571 */ 00572 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) 00573 { 00574 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); 00575 } 00576 00577 /** 00578 * @brief Get transfer bit order 00579 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder 00580 * @param SPIx SPI Instance 00581 * @retval Returned value can be one of the following values: 00582 * @arg @ref LL_SPI_LSB_FIRST 00583 * @arg @ref LL_SPI_MSB_FIRST 00584 */ 00585 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) 00586 { 00587 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); 00588 } 00589 00590 /** 00591 * @brief Set transfer direction mode 00592 * @note For Half-Duplex mode, Rx Direction is set by default. 00593 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. 00594 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n 00595 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n 00596 * CR1 BIDIOE LL_SPI_SetTransferDirection 00597 * @param SPIx SPI Instance 00598 * @param TransferDirection This parameter can be one of the following values: 00599 * @arg @ref LL_SPI_FULL_DUPLEX 00600 * @arg @ref LL_SPI_SIMPLEX_RX 00601 * @arg @ref LL_SPI_HALF_DUPLEX_RX 00602 * @arg @ref LL_SPI_HALF_DUPLEX_TX 00603 * @retval None 00604 */ 00605 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) 00606 { 00607 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); 00608 } 00609 00610 /** 00611 * @brief Get transfer direction mode 00612 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n 00613 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n 00614 * CR1 BIDIOE LL_SPI_GetTransferDirection 00615 * @param SPIx SPI Instance 00616 * @retval Returned value can be one of the following values: 00617 * @arg @ref LL_SPI_FULL_DUPLEX 00618 * @arg @ref LL_SPI_SIMPLEX_RX 00619 * @arg @ref LL_SPI_HALF_DUPLEX_RX 00620 * @arg @ref LL_SPI_HALF_DUPLEX_TX 00621 */ 00622 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) 00623 { 00624 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); 00625 } 00626 00627 /** 00628 * @brief Set frame data width 00629 * @rmtoll CR2 DS LL_SPI_SetDataWidth 00630 * @param SPIx SPI Instance 00631 * @param DataWidth This parameter can be one of the following values: 00632 * @arg @ref LL_SPI_DATAWIDTH_4BIT 00633 * @arg @ref LL_SPI_DATAWIDTH_5BIT 00634 * @arg @ref LL_SPI_DATAWIDTH_6BIT 00635 * @arg @ref LL_SPI_DATAWIDTH_7BIT 00636 * @arg @ref LL_SPI_DATAWIDTH_8BIT 00637 * @arg @ref LL_SPI_DATAWIDTH_9BIT 00638 * @arg @ref LL_SPI_DATAWIDTH_10BIT 00639 * @arg @ref LL_SPI_DATAWIDTH_11BIT 00640 * @arg @ref LL_SPI_DATAWIDTH_12BIT 00641 * @arg @ref LL_SPI_DATAWIDTH_13BIT 00642 * @arg @ref LL_SPI_DATAWIDTH_14BIT 00643 * @arg @ref LL_SPI_DATAWIDTH_15BIT 00644 * @arg @ref LL_SPI_DATAWIDTH_16BIT 00645 * @retval None 00646 */ 00647 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) 00648 { 00649 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); 00650 } 00651 00652 /** 00653 * @brief Get frame data width 00654 * @rmtoll CR2 DS LL_SPI_GetDataWidth 00655 * @param SPIx SPI Instance 00656 * @retval Returned value can be one of the following values: 00657 * @arg @ref LL_SPI_DATAWIDTH_4BIT 00658 * @arg @ref LL_SPI_DATAWIDTH_5BIT 00659 * @arg @ref LL_SPI_DATAWIDTH_6BIT 00660 * @arg @ref LL_SPI_DATAWIDTH_7BIT 00661 * @arg @ref LL_SPI_DATAWIDTH_8BIT 00662 * @arg @ref LL_SPI_DATAWIDTH_9BIT 00663 * @arg @ref LL_SPI_DATAWIDTH_10BIT 00664 * @arg @ref LL_SPI_DATAWIDTH_11BIT 00665 * @arg @ref LL_SPI_DATAWIDTH_12BIT 00666 * @arg @ref LL_SPI_DATAWIDTH_13BIT 00667 * @arg @ref LL_SPI_DATAWIDTH_14BIT 00668 * @arg @ref LL_SPI_DATAWIDTH_15BIT 00669 * @arg @ref LL_SPI_DATAWIDTH_16BIT 00670 */ 00671 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) 00672 { 00673 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); 00674 } 00675 00676 /** 00677 * @brief Set threshold of RXFIFO that triggers an RXNE event 00678 * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold 00679 * @param SPIx SPI Instance 00680 * @param Threshold This parameter can be one of the following values: 00681 * @arg @ref LL_SPI_RX_FIFO_TH_HALF 00682 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 00683 * @retval None 00684 */ 00685 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) 00686 { 00687 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); 00688 } 00689 00690 /** 00691 * @brief Get threshold of RXFIFO that triggers an RXNE event 00692 * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold 00693 * @param SPIx SPI Instance 00694 * @retval Returned value can be one of the following values: 00695 * @arg @ref LL_SPI_RX_FIFO_TH_HALF 00696 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 00697 */ 00698 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) 00699 { 00700 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); 00701 } 00702 00703 /** 00704 * @} 00705 */ 00706 00707 /** @defgroup SPI_LL_EF_CRC_Management CRC Management 00708 * @{ 00709 */ 00710 00711 /** 00712 * @brief Enable CRC 00713 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00714 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC 00715 * @param SPIx SPI Instance 00716 * @retval None 00717 */ 00718 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) 00719 { 00720 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); 00721 } 00722 00723 /** 00724 * @brief Disable CRC 00725 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00726 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC 00727 * @param SPIx SPI Instance 00728 * @retval None 00729 */ 00730 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) 00731 { 00732 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); 00733 } 00734 00735 /** 00736 * @brief Check if CRC is enabled 00737 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00738 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC 00739 * @param SPIx SPI Instance 00740 * @retval State of bit (1 or 0). 00741 */ 00742 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) 00743 { 00744 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)); 00745 } 00746 00747 /** 00748 * @brief Set CRC Length 00749 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00750 * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth 00751 * @param SPIx SPI Instance 00752 * @param CRCLength This parameter can be one of the following values: 00753 * @arg @ref LL_SPI_CRC_8BIT 00754 * @arg @ref LL_SPI_CRC_16BIT 00755 * @retval None 00756 */ 00757 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) 00758 { 00759 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); 00760 } 00761 00762 /** 00763 * @brief Get CRC Length 00764 * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth 00765 * @param SPIx SPI Instance 00766 * @retval Returned value can be one of the following values: 00767 * @arg @ref LL_SPI_CRC_8BIT 00768 * @arg @ref LL_SPI_CRC_16BIT 00769 */ 00770 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) 00771 { 00772 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); 00773 } 00774 00775 /** 00776 * @brief Set CRCNext to transfer CRC on the line 00777 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. 00778 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext 00779 * @param SPIx SPI Instance 00780 * @retval None 00781 */ 00782 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) 00783 { 00784 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); 00785 } 00786 00787 /** 00788 * @brief Set polynomial for CRC calculation 00789 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial 00790 * @param SPIx SPI Instance 00791 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00792 * @retval None 00793 */ 00794 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) 00795 { 00796 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); 00797 } 00798 00799 /** 00800 * @brief Get polynomial for CRC calculation 00801 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial 00802 * @param SPIx SPI Instance 00803 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00804 */ 00805 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) 00806 { 00807 return (uint32_t)(READ_REG(SPIx->CRCPR)); 00808 } 00809 00810 /** 00811 * @brief Get Rx CRC 00812 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC 00813 * @param SPIx SPI Instance 00814 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00815 */ 00816 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) 00817 { 00818 return (uint32_t)(READ_REG(SPIx->RXCRCR)); 00819 } 00820 00821 /** 00822 * @brief Get Tx CRC 00823 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC 00824 * @param SPIx SPI Instance 00825 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00826 */ 00827 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) 00828 { 00829 return (uint32_t)(READ_REG(SPIx->TXCRCR)); 00830 } 00831 00832 /** 00833 * @} 00834 */ 00835 00836 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management 00837 * @{ 00838 */ 00839 00840 /** 00841 * @brief Set NSS mode 00842 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. 00843 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n 00844 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode 00845 * @param SPIx SPI Instance 00846 * @param NSS This parameter can be one of the following values: 00847 * @arg @ref LL_SPI_NSS_SOFT 00848 * @arg @ref LL_SPI_NSS_HARD_INPUT 00849 * @arg @ref LL_SPI_NSS_HARD_OUTPUT 00850 * @retval None 00851 */ 00852 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) 00853 { 00854 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); 00855 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); 00856 } 00857 00858 /** 00859 * @brief Get NSS mode 00860 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n 00861 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode 00862 * @param SPIx SPI Instance 00863 * @retval Returned value can be one of the following values: 00864 * @arg @ref LL_SPI_NSS_SOFT 00865 * @arg @ref LL_SPI_NSS_HARD_INPUT 00866 * @arg @ref LL_SPI_NSS_HARD_OUTPUT 00867 */ 00868 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) 00869 { 00870 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); 00871 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); 00872 return (Ssm | Ssoe); 00873 } 00874 00875 /** 00876 * @brief Enable NSS pulse management 00877 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00878 * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt 00879 * @param SPIx SPI Instance 00880 * @retval None 00881 */ 00882 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) 00883 { 00884 SET_BIT(SPIx->CR2, SPI_CR2_NSSP); 00885 } 00886 00887 /** 00888 * @brief Disable NSS pulse management 00889 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00890 * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt 00891 * @param SPIx SPI Instance 00892 * @retval None 00893 */ 00894 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) 00895 { 00896 CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); 00897 } 00898 00899 /** 00900 * @brief Check if NSS pulse is enabled 00901 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00902 * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse 00903 * @param SPIx SPI Instance 00904 * @retval State of bit (1 or 0). 00905 */ 00906 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) 00907 { 00908 return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)); 00909 } 00910 00911 /** 00912 * @} 00913 */ 00914 00915 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management 00916 * @{ 00917 */ 00918 00919 /** 00920 * @brief Check if Rx buffer is not empty 00921 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE 00922 * @param SPIx SPI Instance 00923 * @retval State of bit (1 or 0). 00924 */ 00925 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) 00926 { 00927 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)); 00928 } 00929 00930 /** 00931 * @brief Check if Tx buffer is empty 00932 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE 00933 * @param SPIx SPI Instance 00934 * @retval State of bit (1 or 0). 00935 */ 00936 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) 00937 { 00938 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)); 00939 } 00940 00941 /** 00942 * @brief Get CRC error flag 00943 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR 00944 * @param SPIx SPI Instance 00945 * @retval State of bit (1 or 0). 00946 */ 00947 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) 00948 { 00949 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)); 00950 } 00951 00952 /** 00953 * @brief Get mode fault error flag 00954 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF 00955 * @param SPIx SPI Instance 00956 * @retval State of bit (1 or 0). 00957 */ 00958 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) 00959 { 00960 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)); 00961 } 00962 00963 /** 00964 * @brief Get overrun error flag 00965 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR 00966 * @param SPIx SPI Instance 00967 * @retval State of bit (1 or 0). 00968 */ 00969 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) 00970 { 00971 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)); 00972 } 00973 00974 /** 00975 * @brief Get busy flag 00976 * @note The BSY flag is cleared under any one of the following conditions: 00977 * -When the SPI is correctly disabled 00978 * -When a fault is detected in Master mode (MODF bit set to 1) 00979 * -In Master mode, when it finishes a data transmission and no new data is ready to be 00980 * sent 00981 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between 00982 * each data transfer. 00983 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY 00984 * @param SPIx SPI Instance 00985 * @retval State of bit (1 or 0). 00986 */ 00987 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) 00988 { 00989 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)); 00990 } 00991 00992 /** 00993 * @brief Get frame format error flag 00994 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE 00995 * @param SPIx SPI Instance 00996 * @retval State of bit (1 or 0). 00997 */ 00998 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) 00999 { 01000 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)); 01001 } 01002 01003 /** 01004 * @brief Get FIFO reception Level 01005 * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel 01006 * @param SPIx SPI Instance 01007 * @retval Returned value can be one of the following values: 01008 * @arg @ref LL_SPI_RX_FIFO_EMPTY 01009 * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL 01010 * @arg @ref LL_SPI_RX_FIFO_HALF_FULL 01011 * @arg @ref LL_SPI_RX_FIFO_FULL 01012 */ 01013 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) 01014 { 01015 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); 01016 } 01017 01018 /** 01019 * @brief Get FIFO Transmission Level 01020 * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel 01021 * @param SPIx SPI Instance 01022 * @retval Returned value can be one of the following values: 01023 * @arg @ref LL_SPI_TX_FIFO_EMPTY 01024 * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL 01025 * @arg @ref LL_SPI_TX_FIFO_HALF_FULL 01026 * @arg @ref LL_SPI_TX_FIFO_FULL 01027 */ 01028 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) 01029 { 01030 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); 01031 } 01032 01033 /** 01034 * @brief Clear CRC error flag 01035 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR 01036 * @param SPIx SPI Instance 01037 * @retval None 01038 */ 01039 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) 01040 { 01041 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); 01042 } 01043 01044 /** 01045 * @brief Clear mode fault error flag 01046 * @note Clearing this flag is done by a read access to the SPIx_SR 01047 * register followed by a write access to the SPIx_CR1 register 01048 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF 01049 * @param SPIx SPI Instance 01050 * @retval None 01051 */ 01052 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) 01053 { 01054 __IO uint32_t tmpreg; 01055 tmpreg = SPIx->SR; 01056 (void) tmpreg; 01057 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 01058 (void) tmpreg; 01059 } 01060 01061 /** 01062 * @brief Clear overrun error flag 01063 * @note Clearing this flag is done by a read access to the SPIx_DR 01064 * register followed by a read access to the SPIx_SR register 01065 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR 01066 * @param SPIx SPI Instance 01067 * @retval None 01068 */ 01069 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) 01070 { 01071 __IO uint32_t tmpreg; 01072 tmpreg = SPIx->DR; 01073 (void) tmpreg; 01074 tmpreg = SPIx->SR; 01075 (void) tmpreg; 01076 } 01077 01078 /** 01079 * @brief Clear frame format error flag 01080 * @note Clearing this flag is done by reading SPIx_SR register 01081 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE 01082 * @param SPIx SPI Instance 01083 * @retval None 01084 */ 01085 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) 01086 { 01087 __IO uint32_t tmpreg; 01088 tmpreg = SPIx->SR; 01089 (void) tmpreg; 01090 } 01091 01092 /** 01093 * @} 01094 */ 01095 01096 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management 01097 * @{ 01098 */ 01099 01100 /** 01101 * @brief Enable error interrupt 01102 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). 01103 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR 01104 * @param SPIx SPI Instance 01105 * @retval None 01106 */ 01107 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) 01108 { 01109 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); 01110 } 01111 01112 /** 01113 * @brief Enable Rx buffer not empty interrupt 01114 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE 01115 * @param SPIx SPI Instance 01116 * @retval None 01117 */ 01118 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) 01119 { 01120 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 01121 } 01122 01123 /** 01124 * @brief Enable Tx buffer empty interrupt 01125 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE 01126 * @param SPIx SPI Instance 01127 * @retval None 01128 */ 01129 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) 01130 { 01131 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); 01132 } 01133 01134 /** 01135 * @brief Disable error interrupt 01136 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). 01137 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR 01138 * @param SPIx SPI Instance 01139 * @retval None 01140 */ 01141 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) 01142 { 01143 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); 01144 } 01145 01146 /** 01147 * @brief Disable Rx buffer not empty interrupt 01148 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE 01149 * @param SPIx SPI Instance 01150 * @retval None 01151 */ 01152 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) 01153 { 01154 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 01155 } 01156 01157 /** 01158 * @brief Disable Tx buffer empty interrupt 01159 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE 01160 * @param SPIx SPI Instance 01161 * @retval None 01162 */ 01163 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) 01164 { 01165 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); 01166 } 01167 01168 /** 01169 * @brief Check if error interrupt is enabled 01170 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR 01171 * @param SPIx SPI Instance 01172 * @retval State of bit (1 or 0). 01173 */ 01174 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) 01175 { 01176 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)); 01177 } 01178 01179 /** 01180 * @brief Check if Rx buffer not empty interrupt is enabled 01181 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE 01182 * @param SPIx SPI Instance 01183 * @retval State of bit (1 or 0). 01184 */ 01185 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) 01186 { 01187 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)); 01188 } 01189 01190 /** 01191 * @brief Check if Tx buffer empty interrupt 01192 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE 01193 * @param SPIx SPI Instance 01194 * @retval State of bit (1 or 0). 01195 */ 01196 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) 01197 { 01198 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)); 01199 } 01200 01201 /** 01202 * @} 01203 */ 01204 01205 /** @defgroup SPI_LL_EF_DMA_Management DMA Management 01206 * @{ 01207 */ 01208 01209 /** 01210 * @brief Enable DMA Rx 01211 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX 01212 * @param SPIx SPI Instance 01213 * @retval None 01214 */ 01215 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) 01216 { 01217 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 01218 } 01219 01220 /** 01221 * @brief Disable DMA Rx 01222 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX 01223 * @param SPIx SPI Instance 01224 * @retval None 01225 */ 01226 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) 01227 { 01228 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 01229 } 01230 01231 /** 01232 * @brief Check if DMA Rx is enabled 01233 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX 01234 * @param SPIx SPI Instance 01235 * @retval State of bit (1 or 0). 01236 */ 01237 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) 01238 { 01239 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)); 01240 } 01241 01242 /** 01243 * @brief Enable DMA Tx 01244 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX 01245 * @param SPIx SPI Instance 01246 * @retval None 01247 */ 01248 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) 01249 { 01250 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 01251 } 01252 01253 /** 01254 * @brief Disable DMA Tx 01255 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX 01256 * @param SPIx SPI Instance 01257 * @retval None 01258 */ 01259 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) 01260 { 01261 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 01262 } 01263 01264 /** 01265 * @brief Check if DMA Tx is enabled 01266 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX 01267 * @param SPIx SPI Instance 01268 * @retval State of bit (1 or 0). 01269 */ 01270 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) 01271 { 01272 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)); 01273 } 01274 01275 /** 01276 * @brief Set parity of Last DMA reception 01277 * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX 01278 * @param SPIx SPI Instance 01279 * @param Parity This parameter can be one of the following values: 01280 * @arg @ref LL_SPI_DMA_PARITY_ODD 01281 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01282 * @retval None 01283 */ 01284 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) 01285 { 01286 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << POSITION_VAL(SPI_CR2_LDMARX))); 01287 } 01288 01289 /** 01290 * @brief Get parity configuration for Last DMA reception 01291 * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX 01292 * @param SPIx SPI Instance 01293 * @retval Returned value can be one of the following values: 01294 * @arg @ref LL_SPI_DMA_PARITY_ODD 01295 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01296 */ 01297 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) 01298 { 01299 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> POSITION_VAL(SPI_CR2_LDMARX)); 01300 } 01301 01302 /** 01303 * @brief Set parity of Last DMA transmission 01304 * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX 01305 * @param SPIx SPI Instance 01306 * @param Parity This parameter can be one of the following values: 01307 * @arg @ref LL_SPI_DMA_PARITY_ODD 01308 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01309 * @retval None 01310 */ 01311 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) 01312 { 01313 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << POSITION_VAL(SPI_CR2_LDMATX))); 01314 } 01315 01316 /** 01317 * @brief Get parity configuration for Last DMA transmission 01318 * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX 01319 * @param SPIx SPI Instance 01320 * @retval Returned value can be one of the following values: 01321 * @arg @ref LL_SPI_DMA_PARITY_ODD 01322 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01323 */ 01324 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) 01325 { 01326 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> POSITION_VAL(SPI_CR2_LDMATX)); 01327 } 01328 01329 /** 01330 * @brief Get the data register address used for DMA transfer 01331 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr 01332 * @param SPIx SPI Instance 01333 * @retval Address of data register 01334 */ 01335 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) 01336 { 01337 return (uint32_t) & (SPIx->DR); 01338 } 01339 01340 /** 01341 * @} 01342 */ 01343 01344 /** @defgroup SPI_LL_EF_DATA_Management DATA Management 01345 * @{ 01346 */ 01347 01348 /** 01349 * @brief Read 8-Bits in the data register 01350 * @rmtoll DR DR LL_SPI_ReceiveData8 01351 * @param SPIx SPI Instance 01352 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF 01353 */ 01354 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) 01355 { 01356 return (uint8_t)(READ_REG(SPIx->DR)); 01357 } 01358 01359 /** 01360 * @brief Read 16-Bits in the data register 01361 * @rmtoll DR DR LL_SPI_ReceiveData16 01362 * @param SPIx SPI Instance 01363 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF 01364 */ 01365 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) 01366 { 01367 return (uint16_t)(READ_REG(SPIx->DR)); 01368 } 01369 01370 /** 01371 * @brief Write 8-Bits in the data register 01372 * @rmtoll DR DR LL_SPI_TransmitData8 01373 * @param SPIx SPI Instance 01374 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF 01375 * @retval None 01376 */ 01377 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) 01378 { 01379 *((__IO uint8_t *)&SPIx->DR) = TxData; 01380 } 01381 01382 /** 01383 * @brief Write 16-Bits in the data register 01384 * @rmtoll DR DR LL_SPI_TransmitData16 01385 * @param SPIx SPI Instance 01386 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF 01387 * @retval None 01388 */ 01389 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) 01390 { 01391 *((__IO uint16_t *)&SPIx->DR) = TxData; 01392 } 01393 01394 /** 01395 * @} 01396 */ 01397 #if defined(USE_FULL_LL_DRIVER) 01398 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions 01399 * @{ 01400 */ 01401 01402 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); 01403 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); 01404 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); 01405 01406 /** 01407 * @} 01408 */ 01409 #endif /* USE_FULL_LL_DRIVER */ 01410 /** 01411 * @} 01412 */ 01413 01414 /** 01415 * @} 01416 */ 01417 01418 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */ 01419 01420 /** 01421 * @} 01422 */ 01423 01424 #ifdef __cplusplus 01425 } 01426 #endif 01427 01428 #endif /* __STM32L4xx_LL_SPI_H */ 01429 01430 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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