stm32l4xx_ll_sdmmc.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_sdmmc.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    $DATE$
00007   * @brief   Header file of low layer SDMMC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */ 
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_SDMMC_H
00040 #define __STM32L4xx_LL_SDMMC_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 #if defined(SDMMC1)
00047 
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32l4xx_hal_def.h"
00050 
00051 /** @addtogroup STM32L4xx_Driver
00052   * @{
00053   */
00054 
00055 /** @addtogroup SDMMC_LL
00056   * @{
00057   */ 
00058 
00059 /* Exported types ------------------------------------------------------------*/ 
00060 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
00061   * @{
00062   */
00063   
00064 /** 
00065   * @brief  SDMMC Configuration Structure definition  
00066   */
00067 typedef struct
00068 {
00069   uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
00070                                       This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
00071 
00072   uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
00073                                       enabled or disabled.
00074                                       This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
00075 
00076   uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
00077                                       disabled when the bus is idle.
00078                                       This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
00079 
00080   uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
00081                                       This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
00082 
00083   uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
00084                                       This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
00085 
00086   uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
00087                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
00088   
00089 }SDMMC_InitTypeDef;
00090   
00091 
00092 /** 
00093   * @brief  SDMMC Command Control structure 
00094   */
00095 typedef struct                                                                                            
00096 {
00097   uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
00098                                      to a card as part of a command message. If a command
00099                                      contains an argument, it must be loaded into this register
00100                                      before writing the command to the command register.              */
00101 
00102   uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 
00103                                      Max_Data = 64                                                    */
00104 
00105   uint32_t Response;            /*!< Specifies the SDMMC response type.
00106                                      This parameter can be a value of @ref SDMMC_LL_Response_Type         */
00107 
00108   uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is 
00109                                      enabled or disabled.
00110                                      This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
00111 
00112   uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
00113                                      is enabled or disabled.
00114                                      This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
00115 }SDMMC_CmdInitTypeDef;
00116 
00117 
00118 /** 
00119   * @brief  SDMMC Data Control structure 
00120   */
00121 typedef struct
00122 {
00123   uint32_t DataTimeOut ;         /*!< Specifies the data timeout period in card bus clock periods.  */
00124 
00125   uint32_t DataLength ;          /*!< Specifies the number of data bytes to be transferred.         */
00126  
00127   uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
00128                                      This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
00129  
00130   uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
00131                                      is a read or write.
00132                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
00133  
00134   uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
00135                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
00136  
00137   uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
00138                                      is enabled or disabled.
00139                                      This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
00140 }SDMMC_DataInitTypeDef;
00141 
00142 /**
00143   * @}
00144   */
00145   
00146 /* Exported constants --------------------------------------------------------*/
00147 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
00148   * @{
00149   */
00150 
00151 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
00152   * @{
00153   */
00154 #define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
00155 #define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE
00156 
00157 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
00158                                   ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
00159 /**
00160   * @}
00161   */
00162 
00163 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
00164   * @{
00165   */
00166 #define SDMMC_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
00167 #define SDMMC_CLOCK_BYPASS_ENABLE              SDMMC_CLKCR_BYPASS   
00168 
00169 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
00170                                       ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
00171 /**
00172   * @}
00173   */ 
00174 
00175 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
00176   * @{
00177   */
00178 #define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
00179 #define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV
00180 
00181 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
00182                                         ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
00183 /**
00184   * @}
00185   */
00186 
00187 /** @defgroup SDMMC_LL_Bus_Wide Bus Width
00188   * @{
00189   */
00190 #define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000)
00191 #define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0
00192 #define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1
00193 
00194 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
00195                                 ((WIDE) == SDMMC_BUS_WIDE_4B) || \
00196                                 ((WIDE) == SDMMC_BUS_WIDE_8B))
00197 /**
00198   * @}
00199   */
00200 
00201 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
00202   * @{
00203   */
00204 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
00205 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN
00206 
00207 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
00208                                                 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
00209 /**
00210   * @}
00211   */
00212   
00213 /** @defgroup SDMMC_LL_Clock_Division Clock Division
00214   * @{
00215   */
00216 #define IS_SDMMC_CLKDIV(DIV)   ((DIV) <= 0xFF)
00217 /**
00218   * @}
00219   */  
00220     
00221 /** @defgroup SDMMC_LL_Command_Index Command Index
00222   * @{
00223   */
00224 #define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
00225 /**
00226   * @}
00227   */
00228 
00229 /** @defgroup SDMMC_LL_Response_Type Response Type
00230   * @{
00231   */
00232 #define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000)
00233 #define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0
00234 #define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP
00235 
00236 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \
00237                                     ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
00238                                     ((RESPONSE) == SDMMC_RESPONSE_LONG))
00239 /**
00240   * @}
00241   */
00242 
00243 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
00244   * @{
00245   */
00246 #define SDMMC_WAIT_NO                        ((uint32_t)0x00000000)
00247 #define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT 
00248 #define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND
00249 
00250 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
00251                             ((WAIT) == SDMMC_WAIT_IT) || \
00252                             ((WAIT) == SDMMC_WAIT_PEND))
00253 /**
00254   * @}
00255   */
00256 
00257 /** @defgroup SDMMC_LL_CPSM_State CPSM State
00258   * @{
00259   */
00260 #define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000)
00261 #define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN
00262 
00263 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
00264                             ((CPSM) == SDMMC_CPSM_ENABLE))
00265 /**
00266   * @}
00267   */  
00268 
00269 /** @defgroup SDMMC_LL_Response_Registers Response Register
00270   * @{
00271   */
00272 #define SDMMC_RESP1                          ((uint32_t)0x00000000)
00273 #define SDMMC_RESP2                          ((uint32_t)0x00000004)
00274 #define SDMMC_RESP3                          ((uint32_t)0x00000008)
00275 #define SDMMC_RESP4                          ((uint32_t)0x0000000C)
00276 
00277 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
00278                             ((RESP) == SDMMC_RESP2) || \
00279                             ((RESP) == SDMMC_RESP3) || \
00280                             ((RESP) == SDMMC_RESP4))
00281 /**
00282   * @}
00283   */
00284 
00285 /** @defgroup SDMMC_LL_Data_Length Data Lenght
00286   * @{
00287   */
00288 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
00289 /**
00290   * @}
00291   */
00292 
00293 /** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
00294   * @{
00295   */
00296 #define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
00297 #define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0
00298 #define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1
00299 #define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
00300 #define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2
00301 #define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
00302 #define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
00303 #define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
00304 #define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3
00305 #define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
00306 #define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
00307 #define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 
00308 #define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
00309 #define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
00310 #define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
00311 
00312 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \
00313                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \
00314                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \
00315                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \
00316                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \
00317                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \
00318                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \
00319                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \
00320                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \
00321                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \
00322                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
00323                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
00324                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
00325                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
00326                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 
00327 /**
00328   * @}
00329   */
00330 
00331 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
00332   * @{
00333   */
00334 #define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
00335 #define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR
00336 
00337 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
00338                                    ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
00339 /**
00340   * @}
00341   */
00342 
00343 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
00344   * @{
00345   */
00346 #define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
00347 #define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE
00348 
00349 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
00350                                      ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
00351 /**
00352   * @}
00353   */
00354 
00355 /** @defgroup SDMMC_LL_DPSM_State DPSM State
00356   * @{
00357   */
00358 #define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000)
00359 #define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN
00360 
00361 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
00362                             ((DPSM) == SDMMC_DPSM_ENABLE))
00363 /**
00364   * @}
00365   */
00366   
00367 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
00368   * @{
00369   */
00370 #define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000)
00371 #define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)
00372 
00373 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
00374                                      ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
00375 /**
00376   * @}
00377   */  
00378 
00379 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
00380   * @{
00381   */
00382 #define SDMMC_IT_CCRCFAIL                    SDMMC_STA_CCRCFAIL
00383 #define SDMMC_IT_DCRCFAIL                    SDMMC_STA_DCRCFAIL
00384 #define SDMMC_IT_CTIMEOUT                    SDMMC_STA_CTIMEOUT
00385 #define SDMMC_IT_DTIMEOUT                    SDMMC_STA_DTIMEOUT
00386 #define SDMMC_IT_TXUNDERR                    SDMMC_STA_TXUNDERR
00387 #define SDMMC_IT_RXOVERR                     SDMMC_STA_RXOVERR
00388 #define SDMMC_IT_CMDREND                     SDMMC_STA_CMDREND
00389 #define SDMMC_IT_CMDSENT                     SDMMC_STA_CMDSENT
00390 #define SDMMC_IT_DATAEND                     SDMMC_STA_DATAEND
00391 #define SDMMC_IT_DBCKEND                     SDMMC_STA_DBCKEND
00392 #define SDMMC_IT_CMDACT                      SDMMC_STA_CMDACT
00393 #define SDMMC_IT_TXACT                       SDMMC_STA_TXACT
00394 #define SDMMC_IT_RXACT                       SDMMC_STA_RXACT
00395 #define SDMMC_IT_TXFIFOHE                    SDMMC_STA_TXFIFOHE
00396 #define SDMMC_IT_RXFIFOHF                    SDMMC_STA_RXFIFOHF
00397 #define SDMMC_IT_TXFIFOF                     SDMMC_STA_TXFIFOF
00398 #define SDMMC_IT_RXFIFOF                     SDMMC_STA_RXFIFOF
00399 #define SDMMC_IT_TXFIFOE                     SDMMC_STA_TXFIFOE
00400 #define SDMMC_IT_RXFIFOE                     SDMMC_STA_RXFIFOE
00401 #define SDMMC_IT_TXDAVL                      SDMMC_STA_TXDAVL
00402 #define SDMMC_IT_RXDAVL                      SDMMC_STA_RXDAVL
00403 #define SDMMC_IT_SDIOIT                      SDMMC_STA_SDIOIT
00404 /**
00405   * @}
00406   */ 
00407 
00408 /** @defgroup SDMMC_LL_Flags Flags
00409   * @{
00410   */
00411 #define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL
00412 #define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL
00413 #define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT
00414 #define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT
00415 #define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR
00416 #define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR
00417 #define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND
00418 #define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT
00419 #define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND
00420 #define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND
00421 #define SDMMC_FLAG_CMDACT                    SDMMC_STA_CMDACT
00422 #define SDMMC_FLAG_TXACT                     SDMMC_STA_TXACT
00423 #define SDMMC_FLAG_RXACT                     SDMMC_STA_RXACT
00424 #define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE
00425 #define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF
00426 #define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF
00427 #define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF
00428 #define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE
00429 #define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE
00430 #define SDMMC_FLAG_TXDAVL                    SDMMC_STA_TXDAVL
00431 #define SDMMC_FLAG_RXDAVL                    SDMMC_STA_RXDAVL
00432 #define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT
00433 /**
00434   * @}
00435   */
00436 
00437 /**
00438   * @}
00439   */
00440   
00441 /* Exported macro ------------------------------------------------------------*/
00442 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
00443   * @{
00444   */
00445   
00446 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
00447   * @brief SDMMC_LL registers bit address in the alias region
00448   * @{
00449   */
00450 /* ---------------------- SDMMC registers bit mask --------------------------- */
00451 /* --- CLKCR Register ---*/
00452 /* CLKCR register clear mask */ 
00453 #define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\
00454                                              SDMMC_CLKCR_BYPASS  | SDMMC_CLKCR_WIDBUS |\
00455                                              SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
00456 
00457 /* --- DCTRL Register ---*/
00458 /* SDMMC DCTRL Clear Mask */
00459 #define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\
00460                                              SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))
00461 
00462 /* --- CMD Register ---*/
00463 /* CMD Register clear mask */
00464 #define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
00465                                              SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\
00466                                              SDMMC_CMD_CPSMEN   | SDMMC_CMD_SDIOSUSPEND))
00467 
00468 /* SDMMC Intialization Frequency (400KHz max) */
00469 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
00470 
00471 /* SDMMC Data Transfer Frequency (25MHz max) */
00472 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
00473 
00474 /**
00475   * @}
00476   */
00477 
00478 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
00479  *  @brief macros to handle interrupts and specific clock configurations
00480  * @{
00481  */
00482  
00483 /**
00484   * @brief  Enable the SDMMC device.
00485   * @param  __INSTANCE__: SDMMC Instance  
00486   * @retval None
00487   */ 
00488 #define __SDMMC_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
00489 
00490 /**
00491   * @brief  Disable the SDMMC device.
00492   * @param  __INSTANCE__: SDMMC Instance  
00493   * @retval None
00494   */
00495 #define __SDMMC_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
00496 
00497 /**
00498   * @brief  Enable the SDMMC DMA transfer.
00499   * @param  None  
00500   * @retval None
00501   */ 
00502 #define __SDMMC_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
00503 /**
00504   * @brief  Disable the SDMMC DMA transfer.
00505   * @param  None   
00506   * @retval None
00507   */
00508 #define __SDMMC_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
00509  
00510 /**
00511   * @brief  Enable the SDMMC device interrupt.
00512   * @param  __INSTANCE__: Pointer to SDMMC register base  
00513   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
00514   *         This parameter can be one or a combination of the following values:
00515   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00516   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00517   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00518   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00519   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00520   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00521   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00522   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00523   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00524   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00525   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
00526   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
00527   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
00528   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00529   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00530   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
00531   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
00532   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
00533   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
00534   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
00535   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
00536   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   
00537   * @retval None
00538   */
00539 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
00540 
00541 /**
00542   * @brief  Disable the SDMMC device interrupt.
00543   * @param  __INSTANCE__: Pointer to SDMMC register base   
00544   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
00545   *          This parameter can be one or a combination of the following values:
00546   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00547   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00548   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00549   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00550   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00551   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00552   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00553   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00554   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00555   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00556   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
00557   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
00558   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
00559   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00560   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00561   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
00562   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
00563   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
00564   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
00565   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
00566   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
00567   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   
00568   * @retval None
00569   */
00570 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
00571 
00572 /**
00573   * @brief  Checks whether the specified SDMMC flag is set or not. 
00574   * @param  __INSTANCE__: Pointer to SDMMC register base   
00575   * @param  __FLAG__: specifies the flag to check. 
00576   *          This parameter can be one of the following values:
00577   *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
00578   *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00579   *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
00580   *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
00581   *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
00582   *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
00583   *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
00584   *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
00585   *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00586   *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00587   *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
00588   *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
00589   *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
00590   *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
00591   *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
00592   *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
00593   *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
00594   *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
00595   *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
00596   *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
00597   *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
00598   *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received
00599   * @retval The new state of SDMMC_FLAG (SET or RESET).
00600   */
00601 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
00602 
00603 
00604 /**
00605   * @brief  Clears the SDMMC pending flags.
00606   * @param  __INSTANCE__: Pointer to SDMMC register base  
00607   * @param  __FLAG__: specifies the flag to clear.  
00608   *          This parameter can be one or a combination of the following values:
00609   *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
00610   *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00611   *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
00612   *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
00613   *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
00614   *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
00615   *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
00616   *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
00617   *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00618   *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00619   *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received
00620   * @retval None
00621   */
00622 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
00623 
00624 /**
00625   * @brief  Checks whether the specified SDMMC interrupt has occurred or not.
00626   * @param  __INSTANCE__: Pointer to SDMMC register base   
00627   * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
00628   *          This parameter can be one of the following values:
00629   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00630   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00631   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00632   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00633   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00634   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00635   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00636   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00637   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00638   *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00639   *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
00640   *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
00641   *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
00642   *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00643   *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00644   *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
00645   *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
00646   *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
00647   *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
00648   *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
00649   *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
00650   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
00651   * @retval The new state of SDMMC_IT (SET or RESET).
00652   */
00653 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
00654 
00655 /**
00656   * @brief  Clears the SDMMC's interrupt pending bits.
00657   * @param  __INSTANCE__: Pointer to SDMMC register base 
00658   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
00659   *          This parameter can be one or a combination of the following values:
00660   *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00661   *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00662   *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
00663   *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
00664   *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00665   *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
00666   *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
00667   *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
00668   *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
00669   *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
00670   * @retval None
00671   */
00672 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
00673 
00674 /**
00675   * @brief  Enable Start the SD I/O Read Wait operation.
00676   * @param  __INSTANCE__: Pointer to SDMMC register base  
00677   * @retval None
00678   */  
00679 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
00680 
00681 /**
00682   * @brief  Disable Start the SD I/O Read Wait operations.
00683   * @param  __INSTANCE__: Pointer to SDMMC register base   
00684   * @retval None
00685   */  
00686 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
00687 
00688 /**
00689   * @brief  Enable Start the SD I/O Read Wait operation.
00690   * @param  __INSTANCE__: Pointer to SDMMC register base   
00691   * @retval None
00692   */  
00693 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
00694 
00695 /**
00696   * @brief  Disable Stop the SD I/O Read Wait operations.
00697   * @param  __INSTANCE__: Pointer to SDMMC register base  
00698   * @retval None
00699   */  
00700 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
00701 
00702 /**
00703   * @brief  Enable the SD I/O Mode Operation.
00704   * @param  __INSTANCE__: Pointer to SDMMC register base   
00705   * @retval None
00706   */  
00707 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 
00708 
00709 /**
00710   * @brief  Disable the SD I/O Mode Operation.
00711   * @param  __INSTANCE__: Pointer to SDMMC register base 
00712   * @retval None
00713   */  
00714 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 
00715 
00716 /**
00717   * @brief  Enable the SD I/O Suspend command sending.
00718   * @param  __INSTANCE__: Pointer to SDMMC register base  
00719   * @retval None
00720   */  
00721 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 
00722 
00723 /**
00724   * @brief  Disable the SD I/O Suspend command sending.
00725   * @param  __INSTANCE__: Pointer to SDMMC register base  
00726   * @retval None
00727   */  
00728 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 
00729       
00730 /**
00731   * @}
00732   */
00733 
00734 /**
00735   * @}
00736   */  
00737 
00738 /* Exported functions --------------------------------------------------------*/
00739 /** @addtogroup SDMMC_LL_Exported_Functions
00740   * @{
00741   */
00742   
00743 /* Initialization/de-initialization functions  **********************************/
00744 /** @addtogroup HAL_SDMMC_LL_Group1
00745   * @{
00746   */
00747 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
00748 /**
00749   * @}
00750   */
00751   
00752 /* I/O operation functions  *****************************************************/
00753 /** @addtogroup HAL_SDMMC_LL_Group2
00754   * @{
00755   */
00756 /* Blocking mode: Polling */
00757 uint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
00758 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
00759 /**
00760   * @}
00761   */
00762   
00763 /* Peripheral Control functions  ************************************************/
00764 /** @addtogroup HAL_SDMMC_LL_Group3
00765   * @{
00766   */
00767 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
00768 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
00769 uint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
00770 
00771 /* Command path state machine (CPSM) management functions */
00772 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
00773 uint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
00774 uint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
00775 
00776 /* Data path state machine (DPSM) management functions */
00777 HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
00778 uint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
00779 uint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
00780 
00781 /* SDMMC Cards mode management functions */
00782 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
00783 
00784 /**
00785   * @}
00786   */
00787   
00788 /**
00789   * @}
00790   */
00791   
00792 /**
00793   * @}
00794   */ 
00795 
00796 /**
00797   * @}
00798   */
00799 
00800 #endif /* SDMMC1 */
00801 
00802 #ifdef __cplusplus
00803 }
00804 #endif
00805 
00806 #endif /* __STM32L4xx_LL_SDMMC_H */
00807 
00808 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/