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stm32l4xx_ll_rcc.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_rcc.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of RCC LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_RCC_H 00040 #define __STM32L4xx_LL_RCC_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined(RCC) 00054 00055 /** @defgroup RCC_LL RCC 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 /** @defgroup RCC_LL_Private_Variables RCC Private Variables 00062 * @{ 00063 */ 00064 00065 static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 00066 00067 /** 00068 * @} 00069 */ 00070 00071 /* Private constants ---------------------------------------------------------*/ 00072 /** @defgroup RCC_LL_Private_Constants RCC Private Constants 00073 * @{ 00074 */ 00075 /* Defines used for the bit position in the register and perform offsets*/ 00076 #define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) 00077 #define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) 00078 #define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) 00079 #define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL) 00080 #define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM) 00081 #define RCC_POSITION_MSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL) 00082 #define RCC_POSITION_MSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM) 00083 #if defined(RCC_HSI48_SUPPORT) 00084 #define RCC_POSITION_HSI48CAL (uint32_t)POSITION_VAL(RCC_CRRCR_HSI48CAL) 00085 #endif /* RCC_HSI48_SUPPORT */ 00086 #define RCC_POSITION_PLLN (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLN) 00087 #define RCC_POSITION_PLLM (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLM) 00088 #define RCC_POSITION_PLLR (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLR) 00089 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 00090 #define RCC_POSITION_PLLP (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLPDIV) 00091 #else 00092 #define RCC_POSITION_PLLP (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLP) 00093 #endif /* RCC_PLLP_DIV_2_31_SUPPOR T*/ 00094 #define RCC_POSITION_PLLQ (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLQ) 00095 #define RCC_POSITION_PLLSAI1N (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N) 00096 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 00097 #define RCC_POSITION_PLLSAI1P (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV) 00098 #else 00099 #define RCC_POSITION_PLLSAI1P (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P) 00100 #endif /*RCC_PLLSAI1P_DIV_2_31_SUPPORT*/ 00101 #define RCC_POSITION_PLLSAI1Q (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q) 00102 #define RCC_POSITION_PLLSAI1R (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R) 00103 #if defined(RCC_PLLSAI2_SUPPORT) 00104 #define RCC_POSITION_PLLSAI2N (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N) 00105 #define RCC_POSITION_PLLSAI2P (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P) 00106 #define RCC_POSITION_PLLSAI2R (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R) 00107 #endif /* RCC_PLLSAI2_SUPPORT */ 00108 00109 /** 00110 * @} 00111 */ 00112 00113 /* Private macros ------------------------------------------------------------*/ 00114 #if defined(USE_FULL_LL_DRIVER) 00115 /** @defgroup RCC_LL_Private_Macros RCC Private Macros 00116 * @{ 00117 */ 00118 /** 00119 * @} 00120 */ 00121 #endif /*USE_FULL_LL_DRIVER*/ 00122 /* Exported types ------------------------------------------------------------*/ 00123 #if defined(USE_FULL_LL_DRIVER) 00124 /** @defgroup RCC_LL_Exported_Types RCC Exported Types 00125 * @{ 00126 */ 00127 00128 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure 00129 * @{ 00130 */ 00131 00132 /** 00133 * @brief RCC Clocks Frequency Structure 00134 */ 00135 typedef struct 00136 { 00137 uint32_t SYSCLK_Frequency ; /*!< SYSCLK clock frequency */ 00138 uint32_t HCLK_Frequency ; /*!< HCLK clock frequency */ 00139 uint32_t PCLK1_Frequency ; /*!< PCLK1 clock frequency */ 00140 uint32_t PCLK2_Frequency ; /*!< PCLK2 clock frequency */ 00141 } LL_RCC_ClocksTypeDef; 00142 00143 /** 00144 * @} 00145 */ 00146 00147 /** 00148 * @} 00149 */ 00150 #endif /* USE_FULL_LL_DRIVER */ 00151 00152 /* Exported constants --------------------------------------------------------*/ 00153 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants 00154 * @{ 00155 */ 00156 00157 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation 00158 * @brief Defines used to adapt values of different oscillators 00159 * @note These values could be modified in the user environment according to 00160 * HW set-up. 00161 * @{ 00162 */ 00163 #if !defined (HSE_VALUE) 00164 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the HSE oscillator in Hz */ 00165 #endif /* HSE_VALUE */ 00166 00167 #if !defined (HSI_VALUE) 00168 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the HSI oscillator in Hz */ 00169 #endif /* HSI_VALUE */ 00170 00171 #if !defined (LSE_VALUE) 00172 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the LSE oscillator in Hz */ 00173 #endif /* LSE_VALUE */ 00174 00175 #if !defined (LSI_VALUE) 00176 #define LSI_VALUE ((uint32_t)32000) /*!< Value of the LSI oscillator in Hz */ 00177 #endif /* LSI_VALUE */ 00178 #if defined(RCC_HSI48_SUPPORT) 00179 00180 #if !defined (HSI48_VALUE) 00181 #define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the HSI48 oscillator in Hz */ 00182 #endif /* HSI48_VALUE */ 00183 #endif /* RCC_HSI48_SUPPORT */ 00184 /** 00185 * @} 00186 */ 00187 00188 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines 00189 * @brief Flags defines which can be used with LL_RCC_WriteReg function 00190 * @{ 00191 */ 00192 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ 00193 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ 00194 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ 00195 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ 00196 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ 00197 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ 00198 #if defined(RCC_HSI48_SUPPORT) 00199 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ 00200 #endif /* RCC_HSI48_SUPPORT */ 00201 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */ 00202 #if defined(RCC_PLLSAI2_SUPPORT) 00203 #define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */ 00204 #endif /* RCC_PLLSAI2_SUPPORT */ 00205 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ 00206 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ 00207 /** 00208 * @} 00209 */ 00210 00211 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines 00212 * @brief Flags defines which can be used with LL_RCC_ReadReg function 00213 * @{ 00214 */ 00215 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 00216 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 00217 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 00218 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 00219 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 00220 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 00221 #if defined(RCC_HSI48_SUPPORT) 00222 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 00223 #endif /* RCC_HSI48_SUPPORT */ 00224 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 00225 #if defined(RCC_PLLSAI2_SUPPORT) 00226 #define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 00227 #endif /* RCC_PLLSAI2_SUPPORT */ 00228 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 00229 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 00230 #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */ 00231 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ 00232 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ 00233 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ 00234 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ 00235 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 00236 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 00237 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ 00238 /** 00239 * @} 00240 */ 00241 00242 /** @defgroup RCC_LL_EC_IT IT Defines 00243 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions 00244 * @{ 00245 */ 00246 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ 00247 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ 00248 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */ 00249 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ 00250 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ 00251 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ 00252 #if defined(RCC_HSI48_SUPPORT) 00253 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ 00254 #endif /* RCC_HSI48_SUPPORT */ 00255 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */ 00256 #if defined(RCC_PLLSAI2_SUPPORT) 00257 #define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */ 00258 #endif /* RCC_PLLSAI2_SUPPORT */ 00259 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ 00260 /** 00261 * @} 00262 */ 00263 00264 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability 00265 * @{ 00266 */ 00267 #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /*!< Xtal mode lower driving capability */ 00268 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ 00269 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ 00270 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ 00271 /** 00272 * @} 00273 */ 00274 00275 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges 00276 * @{ 00277 */ 00278 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ 00279 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ 00280 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ 00281 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ 00282 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ 00283 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ 00284 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ 00285 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ 00286 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ 00287 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ 00288 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ 00289 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ 00290 /** 00291 * @} 00292 */ 00293 00294 /** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode 00295 * @{ 00296 */ 00297 #define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */ 00298 #define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */ 00299 #define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */ 00300 #define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */ 00301 /** 00302 * @} 00303 */ 00304 00305 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection 00306 * @{ 00307 */ 00308 #define LL_RCC_LSCO_CLKSOURCE_LSI (uint32_t)0x00000000 /*!< LSI selection for low speed clock */ 00309 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ 00310 /** 00311 * @} 00312 */ 00313 00314 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch 00315 * @{ 00316 */ 00317 #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ 00318 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 00319 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 00320 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 00321 /** 00322 * @} 00323 */ 00324 00325 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status 00326 * @{ 00327 */ 00328 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 00329 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00330 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00331 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00332 /** 00333 * @} 00334 */ 00335 00336 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler 00337 * @{ 00338 */ 00339 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 00340 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 00341 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 00342 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 00343 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 00344 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 00345 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 00346 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 00347 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 00348 /** 00349 * @} 00350 */ 00351 00352 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) 00353 * @{ 00354 */ 00355 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 00356 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 00357 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 00358 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 00359 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 00360 /** 00361 * @} 00362 */ 00363 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) 00364 * @{ 00365 */ 00366 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ 00367 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ 00368 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ 00369 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ 00370 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ 00371 /** 00372 * @} 00373 */ 00374 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection 00375 * @{ 00376 */ 00377 #define LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000) /*!< MSI selection after wake-up from STOP */ 00378 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 00379 /** 00380 * @} 00381 */ 00382 00383 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection 00384 * @{ 00385 */ 00386 #define LL_RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000) /*!< MCO output disabled, no clock on MCO */ 00387 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 00388 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 00389 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */ 00390 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 00391 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ 00392 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 00393 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 00394 #if defined(RCC_HSI48_SUPPORT) 00395 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 00396 #endif /* RCC_HSI48_SUPPORT */ 00397 /** 00398 * @} 00399 */ 00400 00401 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler 00402 * @{ 00403 */ 00404 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ 00405 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ 00406 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ 00407 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ 00408 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ 00409 /** 00410 * @} 00411 */ 00412 00413 #if defined(USE_FULL_LL_DRIVER) 00414 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency 00415 * @{ 00416 */ 00417 #define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000 /*!< No clock enabled for the peripheral */ 00418 #define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ 00419 /** 00420 * @} 00421 */ 00422 #endif /* USE_FULL_LL_DRIVER */ 00423 00424 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection 00425 * @{ 00426 */ 00427 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16) | 0x00000000) /*!< PCLK2 clock used as USART1 clock source */ 00428 #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ 00429 #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ 00430 #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */ 00431 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16) | 0x00000000) /*!< PCLK1 clock used as USART2 clock source */ 00432 #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ 00433 #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ 00434 #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */ 00435 #if defined(RCC_CCIPR_USART3SEL) 00436 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART3SEL << 16) | 0x00000000) /*!< PCLK1 clock used as USART3 clock source */ 00437 #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ 00438 #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ 00439 #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */ 00440 #endif /* RCC_CCIPR_USART3SEL */ 00441 /** 00442 * @} 00443 */ 00444 00445 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL) 00446 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection 00447 * @{ 00448 */ 00449 #if defined(RCC_CCIPR_UART4SEL) 00450 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART4SEL << 16) | 0x00000000) /*!< PCLK1 clock used as UART4 clock source */ 00451 #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */ 00452 #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */ 00453 #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */ 00454 #endif /* RCC_CCIPR_UART4SEL */ 00455 #if defined(RCC_CCIPR_UART5SEL) 00456 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART5SEL << 16) | 0x00000000) /*!< PCLK1 clock used as UART5 clock source */ 00457 #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */ 00458 #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */ 00459 #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */ 00460 #endif /* RCC_CCIPR_UART5SEL */ 00461 /** 00462 * @} 00463 */ 00464 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */ 00465 00466 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection 00467 * @{ 00468 */ 00469 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000 /*!< PCLK1 clock used as LPUART1 clock source */ 00470 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */ 00471 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */ 00472 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */ 00473 /** 00474 * @} 00475 */ 00476 00477 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection 00478 * @{ 00479 */ 00480 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000 >> 4)) /*!< PCLK1 clock used as I2C1 clock source */ 00481 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK clock used as I2C1 clock source */ 00482 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI clock used as I2C1 clock source */ 00483 #if defined(RCC_CCIPR_I2C2SEL) 00484 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (0x00000000 >> 4)) /*!< PCLK1 clock used as I2C2 clock source */ 00485 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_0 >> 4)) /*!< SYSCLK clock used as I2C2 clock source */ 00486 #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_1 >> 4)) /*!< HSI clock used as I2C2 clock source */ 00487 #endif /* RCC_CCIPR_I2C2SEL */ 00488 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000 >> 4)) /*!< PCLK1 clock used as I2C3 clock source */ 00489 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK clock used as I2C3 clock source */ 00490 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI clock used as I2C3 clock source */ 00491 /** 00492 * @} 00493 */ 00494 00495 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection 00496 * @{ 00497 */ 00498 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000 >> 16)) /*!< PCLK1 clock used as LPTIM1 clock source */ 00499 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI clock used as LPTIM1 clock source */ 00500 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI clock used as LPTIM1 clock source */ 00501 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE clock used as LPTIM1 clock source */ 00502 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000 >> 16)) /*!< PCLK1 clock used as LPTIM2 clock source */ 00503 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI clock used as LPTIM2 clock source */ 00504 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI clock used as LPTIM2 clock source */ 00505 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE clock used as LPTIM2 clock source */ 00506 /** 00507 * @} 00508 */ 00509 00510 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection 00511 * @{ 00512 */ 00513 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI1SEL | (0x00000000 >> 16)) /*!< PLLSAI1 clock used as SAI1 clock source */ 00514 #if defined(RCC_PLLSAI2_SUPPORT) 00515 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16)) /*!< PLLSAI2 clock used as SAI1 clock source */ 00516 #endif /* RCC_PLLSAI2_SUPPORT */ 00517 #define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16)) /*!< PLL clock used as SAI1 clock source */ 00518 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16)) /*!< External input clock used as SAI1 clock source */ 00519 #if defined(RCC_CCIPR_SAI2SEL) 00520 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI2SEL | (0x00000000 >> 16)) /*!< PLLSAI1 clock used as SAI2 clock source */ 00521 #if defined(RCC_PLLSAI2_SUPPORT) 00522 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16)) /*!< PLLSAI2 clock used as SAI2 clock source */ 00523 #endif /* RCC_PLLSAI2_SUPPORT */ 00524 #define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16)) /*!< PLL clock used as SAI2 clock source */ 00525 #define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16)) /*!< External input clock used as SAI2 clock source */ 00526 #endif /* RCC_CCIPR_SAI2SEL */ 00527 /** 00528 * @} 00529 */ 00530 00531 /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection 00532 * @{ 00533 */ 00534 #define LL_RCC_SDMMC1_CLKSOURCE_NONE (uint32_t)(0x00000000) /*!< No clock used as SDMMC1 clock source */ 00535 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0) /*!< PLLSAI1 clock used as SDMMC1 clock source */ 00536 #define LL_RCC_SDMMC1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1) /*!< PLL clock used as SDMMC1 clock source */ 00537 #define LL_RCC_SDMMC1_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL) /*!< MSI clock used as SDMMC1 clock source */ 00538 /** 00539 * @} 00540 */ 00541 00542 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection 00543 * @{ 00544 */ 00545 #define LL_RCC_RNG_CLKSOURCE_NONE (uint32_t)(0x00000000) /*!< No clock used as RNG clock source */ 00546 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0) /*!< PLLSAI1 clock used as RNG clock source */ 00547 #define LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1) /*!< PLL clock used as RNG clock source */ 00548 #define LL_RCC_RNG_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL) /*!< MSI clock used as RNG clock source */ 00549 /** 00550 * @} 00551 */ 00552 00553 #if defined(USB_OTG_FS) || defined(USB) 00554 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection 00555 * @{ 00556 */ 00557 #define LL_RCC_USB_CLKSOURCE_NONE (uint32_t)(0x00000000) /*!< No clock used as USB clock source */ 00558 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0) /*!< PLLSAI1 clock used as USB clock source */ 00559 #define LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1) /*!< PLL clock used as USB clock source */ 00560 #define LL_RCC_USB_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL) /*!< MSI clock used as USB clock source */ 00561 /** 00562 * @} 00563 */ 00564 00565 #endif /* USB_OTG_FS || USB */ 00566 00567 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection 00568 * @{ 00569 */ 00570 #define LL_RCC_ADC_CLKSOURCE_NONE (uint32_t)(0x00000000) /*!< No clock used as ADC clock source */ 00571 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_ADCSEL_0) /*!< PLLSAI1 clock used as ADC clock source */ 00572 #if defined(RCC_PLLSAI2_SUPPORT) 00573 #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_ADCSEL_1) /*!< PLLSAI2 clock used as ADC clock source */ 00574 #endif /* RCC_PLLSAI2_SUPPORT */ 00575 #define LL_RCC_ADC_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_ADCSEL) /*!< SYSCLK clock used as ADC clock source */ 00576 /** 00577 * @} 00578 */ 00579 00580 /** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI clock source selection 00581 * @{ 00582 */ 00583 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK (uint32_t)(0x00000000) /*!< PCLK used as SWPMI1 clock source */ 00584 #define LL_RCC_SWPMI1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_SWPMI1SEL) /*!< HSI used as SWPMI1 clock source */ 00585 /** 00586 * @} 00587 */ 00588 00589 #if defined(DFSDM1_Channel0) 00590 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection 00591 * @{ 00592 */ 00593 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK (uint32_t)(0x00000000) /*!< PCLK used as DFSDM1 clock source */ 00594 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_DFSDM1SEL) /*!< SYSCLK used as DFSDM1 clock source */ 00595 /** 00596 * @} 00597 */ 00598 #endif /* DFSDM1_Channel0 */ 00599 00600 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source 00601 * @{ 00602 */ 00603 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */ 00604 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */ 00605 #if defined(RCC_CCIPR_USART3SEL) 00606 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */ 00607 #endif /* RCC_CCIPR_USART3SEL */ 00608 /** 00609 * @} 00610 */ 00611 00612 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL) 00613 /** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source 00614 * @{ 00615 */ 00616 #if defined(RCC_CCIPR_UART4SEL) 00617 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */ 00618 #endif /* RCC_CCIPR_UART4SEL */ 00619 #if defined(RCC_CCIPR_UART5SEL) 00620 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */ 00621 #endif /* RCC_CCIPR_UART5SEL */ 00622 /** 00623 * @} 00624 */ 00625 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */ 00626 00627 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source 00628 * @{ 00629 */ 00630 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */ 00631 /** 00632 * @} 00633 */ 00634 00635 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source 00636 * @{ 00637 */ 00638 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */ 00639 #if defined(RCC_CCIPR_I2C2SEL) 00640 #define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL /*!< I2C2 Clock source selection */ 00641 #endif /* RCC_CCIPR_I2C2SEL */ 00642 #define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 Clock source selection */ 00643 /** 00644 * @} 00645 */ 00646 00647 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source 00648 * @{ 00649 */ 00650 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */ 00651 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */ 00652 /** 00653 * @} 00654 */ 00655 00656 /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source 00657 * @{ 00658 */ 00659 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */ 00660 #if defined(RCC_CCIPR_SAI2SEL) 00661 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */ 00662 #endif /* RCC_CCIPR_SAI2SEL */ 00663 /** 00664 * @} 00665 */ 00666 00667 /** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source 00668 * @{ 00669 */ 00670 #define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */ 00671 /** 00672 * @} 00673 */ 00674 00675 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source 00676 * @{ 00677 */ 00678 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */ 00679 /** 00680 * @} 00681 */ 00682 00683 #if defined(USB_OTG_FS) || defined(USB) 00684 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source 00685 * @{ 00686 */ 00687 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */ 00688 /** 00689 * @} 00690 */ 00691 00692 #endif /* USB_OTG_FS || USB */ 00693 00694 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source 00695 * @{ 00696 */ 00697 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */ 00698 /** 00699 * @} 00700 */ 00701 00702 /** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI get clock source 00703 * @{ 00704 */ 00705 #define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */ 00706 /** 00707 * @} 00708 */ 00709 00710 #if defined(DFSDM1_Channel0) 00711 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source 00712 * @{ 00713 */ 00714 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */ 00715 /** 00716 * @} 00717 */ 00718 #endif /* DFSDM1_Channel0 */ 00719 00720 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection 00721 * @{ 00722 */ 00723 #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000) /*!< No clock used as RTC clock */ 00724 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 00725 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 00726 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 00727 /** 00728 * @} 00729 */ 00730 00731 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source 00732 * @{ 00733 */ 00734 #define LL_RCC_PLLSOURCE_NONE (uint32_t)0x00000000 /*!< No clock */ 00735 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ 00736 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ 00737 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 00738 /** 00739 * @} 00740 */ 00741 00742 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLSAI1 and PLLSAI2 division factor 00743 * @{ 00744 */ 00745 #define LL_RCC_PLLM_DIV_1 ((uint32_t)0x00000000) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 1 */ 00746 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 2 */ 00747 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 3 */ 00748 #define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 4 */ 00749 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 5 */ 00750 #define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 6 */ 00751 #define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 7 */ 00752 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 8 */ 00753 /** 00754 * @} 00755 */ 00756 00757 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) 00758 * @{ 00759 */ 00760 #define LL_RCC_PLLR_DIV_2 ((uint32_t)0x00000000) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ 00761 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ 00762 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ 00763 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */ 00764 /** 00765 * @} 00766 */ 00767 00768 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) 00769 * @{ 00770 */ 00771 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 00772 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */ 00773 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 3 */ 00774 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */ 00775 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 5 */ 00776 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 6 */ 00777 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 7 */ 00778 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */ 00779 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 9 */ 00780 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 10 */ 00781 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3)) /*!< Main PLL division factor for PLLP output by 11 */ 00782 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 12 */ 00783 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 13 */ 00784 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 14 */ 00785 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 15 */ 00786 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */ 00787 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 17 */ 00788 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 18 */ 00789 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4)) /*!< Main PLL division factor for PLLP output by 19 */ 00790 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 20 */ 00791 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 21 */ 00792 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 22 */ 00793 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 23 */ 00794 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 24 */ 00795 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 25 */ 00796 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 26 */ 00797 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 27 */ 00798 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 28 */ 00799 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 29 */ 00800 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 30 */ 00801 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 31 */ 00802 #else 00803 #define LL_RCC_PLLP_DIV_7 ((uint32_t)0x00000000) /*!< Main PLL division factor for PLLP output by 7 */ 00804 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */ 00805 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 00806 /** 00807 * @} 00808 */ 00809 00810 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) 00811 * @{ 00812 */ 00813 #define LL_RCC_PLLQ_DIV_2 ((uint32_t)0x00000000) /*!< Main PLL division factor for PLLQ output by 2 */ 00814 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */ 00815 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ 00816 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */ 00817 /** 00818 * @} 00819 */ 00820 00821 /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q) 00822 * @{ 00823 */ 00824 #define LL_RCC_PLLSAI1Q_DIV_2 ((uint32_t)0x00000000) /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */ 00825 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */ 00826 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */ 00827 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */ 00828 /** 00829 * @} 00830 */ 00831 00832 /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P) 00833 * @{ 00834 */ 00835 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 00836 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */ 00837 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */ 00838 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */ 00839 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */ 00840 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */ 00841 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ 00842 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */ 00843 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */ 00844 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */ 00845 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */ 00846 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */ 00847 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */ 00848 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */ 00849 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */ 00850 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */ 00851 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ 00852 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */ 00853 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */ 00854 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */ 00855 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */ 00856 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */ 00857 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */ 00858 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */ 00859 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */ 00860 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */ 00861 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */ 00862 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */ 00863 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */ 00864 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */ 00865 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ 00866 #else 00867 #define LL_RCC_PLLSAI1P_DIV_7 ((uint32_t)0x00000000) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ 00868 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ 00869 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 00870 /** 00871 * @} 00872 */ 00873 00874 /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R) 00875 * @{ 00876 */ 00877 #define LL_RCC_PLLSAI1R_DIV_2 ((uint32_t)0x00000000) /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */ 00878 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */ 00879 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */ 00880 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */ 00881 /** 00882 * @} 00883 */ 00884 00885 #if defined(RCC_PLLSAI2_SUPPORT) 00886 /** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P) 00887 * @{ 00888 */ 00889 #define LL_RCC_PLLSAI2P_DIV_7 ((uint32_t)0x00000000) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ 00890 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ 00891 /** 00892 * @} 00893 */ 00894 00895 /** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R) 00896 * @{ 00897 */ 00898 #define LL_RCC_PLLSAI2R_DIV_2 ((uint32_t)0x00000000) /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */ 00899 #define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */ 00900 #define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */ 00901 #define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */ 00902 /** 00903 * @} 00904 */ 00905 #endif /* RCC_PLLSAI2_SUPPORT */ 00906 00907 /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection 00908 * @{ 00909 */ 00910 #define LL_RCC_MSIRANGESEL_STANDBY (uint32_t)0 /*!< MSI Range is provided by MSISRANGE */ 00911 #define LL_RCC_MSIRANGESEL_RUN (uint32_t)1 /*!< MSI Range is provided by MSIRANGE */ 00912 /** 00913 * @} 00914 */ 00915 00916 /** Legacy definitions for compatibility purpose 00917 @cond 0 00918 */ 00919 #if defined(DFSDM1_Channel0) 00920 #define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK 00921 #define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 00922 #define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE 00923 #endif /* DFSDM1_Channel0 */ 00924 /** 00925 @endcond 00926 */ 00927 00928 /** 00929 * @} 00930 */ 00931 00932 /* Exported macro ------------------------------------------------------------*/ 00933 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros 00934 * @{ 00935 */ 00936 00937 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros 00938 * @{ 00939 */ 00940 00941 /** 00942 * @brief Write a value in RCC register 00943 * @param __REG__ Register to be written 00944 * @param __VALUE__ Value to be written in the register 00945 * @retval None 00946 */ 00947 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) 00948 00949 /** 00950 * @brief Read a value in RCC register 00951 * @param __REG__ Register to be read 00952 * @retval Register value 00953 */ 00954 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) 00955 /** 00956 * @} 00957 */ 00958 00959 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies 00960 * @{ 00961 */ 00962 00963 /** 00964 * @brief Helper macro to calculate the PLLCLK frequency on system domain 00965 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 00966 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 00967 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 00968 * @param __PLLM__ This parameter can be one of the following values: 00969 * @arg @ref LL_RCC_PLLM_DIV_1 00970 * @arg @ref LL_RCC_PLLM_DIV_2 00971 * @arg @ref LL_RCC_PLLM_DIV_3 00972 * @arg @ref LL_RCC_PLLM_DIV_4 00973 * @arg @ref LL_RCC_PLLM_DIV_5 00974 * @arg @ref LL_RCC_PLLM_DIV_6 00975 * @arg @ref LL_RCC_PLLM_DIV_7 00976 * @arg @ref LL_RCC_PLLM_DIV_8 00977 * @param __PLLN__ Between 8 and 86 00978 * @param __PLLR__ This parameter can be one of the following values: 00979 * @arg @ref LL_RCC_PLLR_DIV_2 00980 * @arg @ref LL_RCC_PLLR_DIV_4 00981 * @arg @ref LL_RCC_PLLR_DIV_6 00982 * @arg @ref LL_RCC_PLLR_DIV_8 00983 * @retval PLL clock frequency (in Hz) 00984 */ 00985 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \ 00986 ((((__PLLR__) >> RCC_POSITION_PLLR ) + 1 ) * 2)) 00987 00988 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 00989 /** 00990 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain 00991 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 00992 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); 00993 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 00994 * @param __PLLM__ This parameter can be one of the following values: 00995 * @arg @ref LL_RCC_PLLM_DIV_1 00996 * @arg @ref LL_RCC_PLLM_DIV_2 00997 * @arg @ref LL_RCC_PLLM_DIV_3 00998 * @arg @ref LL_RCC_PLLM_DIV_4 00999 * @arg @ref LL_RCC_PLLM_DIV_5 01000 * @arg @ref LL_RCC_PLLM_DIV_6 01001 * @arg @ref LL_RCC_PLLM_DIV_7 01002 * @arg @ref LL_RCC_PLLM_DIV_8 01003 * @param __PLLN__ Between 8 and 86 01004 * @param __PLLP__ This parameter can be one of the following values: 01005 * @arg @ref LL_RCC_PLLP_DIV_2 01006 * @arg @ref LL_RCC_PLLP_DIV_3 01007 * @arg @ref LL_RCC_PLLP_DIV_4 01008 * @arg @ref LL_RCC_PLLP_DIV_5 01009 * @arg @ref LL_RCC_PLLP_DIV_6 01010 * @arg @ref LL_RCC_PLLP_DIV_7 01011 * @arg @ref LL_RCC_PLLP_DIV_8 01012 * @arg @ref LL_RCC_PLLP_DIV_9 01013 * @arg @ref LL_RCC_PLLP_DIV_10 01014 * @arg @ref LL_RCC_PLLP_DIV_11 01015 * @arg @ref LL_RCC_PLLP_DIV_12 01016 * @arg @ref LL_RCC_PLLP_DIV_13 01017 * @arg @ref LL_RCC_PLLP_DIV_14 01018 * @arg @ref LL_RCC_PLLP_DIV_15 01019 * @arg @ref LL_RCC_PLLP_DIV_16 01020 * @arg @ref LL_RCC_PLLP_DIV_17 01021 * @arg @ref LL_RCC_PLLP_DIV_18 01022 * @arg @ref LL_RCC_PLLP_DIV_19 01023 * @arg @ref LL_RCC_PLLP_DIV_20 01024 * @arg @ref LL_RCC_PLLP_DIV_21 01025 * @arg @ref LL_RCC_PLLP_DIV_22 01026 * @arg @ref LL_RCC_PLLP_DIV_23 01027 * @arg @ref LL_RCC_PLLP_DIV_24 01028 * @arg @ref LL_RCC_PLLP_DIV_25 01029 * @arg @ref LL_RCC_PLLP_DIV_26 01030 * @arg @ref LL_RCC_PLLP_DIV_27 01031 * @arg @ref LL_RCC_PLLP_DIV_28 01032 * @arg @ref LL_RCC_PLLP_DIV_29 01033 * @arg @ref LL_RCC_PLLP_DIV_30 01034 * @arg @ref LL_RCC_PLLP_DIV_31 01035 * @retval PLL clock frequency (in Hz) 01036 */ 01037 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \ 01038 ((__PLLP__) >> RCC_POSITION_PLLP)) 01039 01040 #else 01041 /** 01042 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain 01043 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01044 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); 01045 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01046 * @param __PLLM__ This parameter can be one of the following values: 01047 * @arg @ref LL_RCC_PLLM_DIV_1 01048 * @arg @ref LL_RCC_PLLM_DIV_2 01049 * @arg @ref LL_RCC_PLLM_DIV_3 01050 * @arg @ref LL_RCC_PLLM_DIV_4 01051 * @arg @ref LL_RCC_PLLM_DIV_5 01052 * @arg @ref LL_RCC_PLLM_DIV_6 01053 * @arg @ref LL_RCC_PLLM_DIV_7 01054 * @arg @ref LL_RCC_PLLM_DIV_8 01055 * @param __PLLN__ Between 8 and 86 01056 * @param __PLLP__ This parameter can be one of the following values: 01057 * @arg @ref LL_RCC_PLLP_DIV_7 01058 * @arg @ref LL_RCC_PLLP_DIV_17 01059 * @retval PLL clock frequency (in Hz) 01060 */ 01061 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \ 01062 (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7 : 17)) 01063 01064 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 01065 /** 01066 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain 01067 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01068 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); 01069 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01070 * @param __PLLM__ This parameter can be one of the following values: 01071 * @arg @ref LL_RCC_PLLM_DIV_1 01072 * @arg @ref LL_RCC_PLLM_DIV_2 01073 * @arg @ref LL_RCC_PLLM_DIV_3 01074 * @arg @ref LL_RCC_PLLM_DIV_4 01075 * @arg @ref LL_RCC_PLLM_DIV_5 01076 * @arg @ref LL_RCC_PLLM_DIV_6 01077 * @arg @ref LL_RCC_PLLM_DIV_7 01078 * @arg @ref LL_RCC_PLLM_DIV_8 01079 * @param __PLLN__ Between 8 and 86 01080 * @param __PLLQ__ This parameter can be one of the following values: 01081 * @arg @ref LL_RCC_PLLQ_DIV_2 01082 * @arg @ref LL_RCC_PLLQ_DIV_4 01083 * @arg @ref LL_RCC_PLLQ_DIV_6 01084 * @arg @ref LL_RCC_PLLQ_DIV_8 01085 * @retval PLL clock frequency (in Hz) 01086 */ 01087 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLN__) / \ 01088 ((((__PLLQ__) >> RCC_POSITION_PLLQ) + 1) << 1)) 01089 01090 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 01091 /** 01092 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain 01093 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01094 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); 01095 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01096 * @param __PLLM__ This parameter can be one of the following values: 01097 * @arg @ref LL_RCC_PLLM_DIV_1 01098 * @arg @ref LL_RCC_PLLM_DIV_2 01099 * @arg @ref LL_RCC_PLLM_DIV_3 01100 * @arg @ref LL_RCC_PLLM_DIV_4 01101 * @arg @ref LL_RCC_PLLM_DIV_5 01102 * @arg @ref LL_RCC_PLLM_DIV_6 01103 * @arg @ref LL_RCC_PLLM_DIV_7 01104 * @arg @ref LL_RCC_PLLM_DIV_8 01105 * @param __PLLSAI1N__ Between 8 and 86 01106 * @param __PLLSAI1P__ This parameter can be one of the following values: 01107 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 01108 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 01109 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 01110 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 01111 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 01112 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 01113 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 01114 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 01115 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 01116 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 01117 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 01118 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 01119 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 01120 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 01121 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 01122 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 01123 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 01124 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 01125 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 01126 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 01127 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 01128 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 01129 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 01130 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 01131 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 01132 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 01133 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 01134 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 01135 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 01136 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 01137 * @retval PLLSAI1 clock frequency (in Hz) 01138 */ 01139 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \ 01140 ((__PLLSAI1P__) >> RCC_POSITION_PLLSAI1P)) 01141 #else 01142 /** 01143 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain 01144 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01145 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); 01146 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01147 * @param __PLLM__ This parameter can be one of the following values: 01148 * @arg @ref LL_RCC_PLLM_DIV_1 01149 * @arg @ref LL_RCC_PLLM_DIV_2 01150 * @arg @ref LL_RCC_PLLM_DIV_3 01151 * @arg @ref LL_RCC_PLLM_DIV_4 01152 * @arg @ref LL_RCC_PLLM_DIV_5 01153 * @arg @ref LL_RCC_PLLM_DIV_6 01154 * @arg @ref LL_RCC_PLLM_DIV_7 01155 * @arg @ref LL_RCC_PLLM_DIV_8 01156 * @param __PLLSAI1N__ Between 8 and 86 01157 * @param __PLLSAI1P__ This parameter can be one of the following values: 01158 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 01159 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 01160 * @retval PLLSAI1 clock frequency (in Hz) 01161 */ 01162 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \ 01163 (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7 : 17)) 01164 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 01165 01166 /** 01167 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain 01168 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01169 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ()); 01170 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01171 * @param __PLLM__ This parameter can be one of the following values: 01172 * @arg @ref LL_RCC_PLLM_DIV_1 01173 * @arg @ref LL_RCC_PLLM_DIV_2 01174 * @arg @ref LL_RCC_PLLM_DIV_3 01175 * @arg @ref LL_RCC_PLLM_DIV_4 01176 * @arg @ref LL_RCC_PLLM_DIV_5 01177 * @arg @ref LL_RCC_PLLM_DIV_6 01178 * @arg @ref LL_RCC_PLLM_DIV_7 01179 * @arg @ref LL_RCC_PLLM_DIV_8 01180 * @param __PLLSAI1N__ Between 8 and 86 01181 * @param __PLLSAI1Q__ This parameter can be one of the following values: 01182 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 01183 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 01184 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 01185 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 01186 * @retval PLLSAI1 clock frequency (in Hz) 01187 */ 01188 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \ 01189 ((((__PLLSAI1Q__) >> RCC_POSITION_PLLSAI1Q) + 1) << 1)) 01190 01191 /** 01192 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain 01193 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01194 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ()); 01195 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01196 * @param __PLLM__ This parameter can be one of the following values: 01197 * @arg @ref LL_RCC_PLLM_DIV_1 01198 * @arg @ref LL_RCC_PLLM_DIV_2 01199 * @arg @ref LL_RCC_PLLM_DIV_3 01200 * @arg @ref LL_RCC_PLLM_DIV_4 01201 * @arg @ref LL_RCC_PLLM_DIV_5 01202 * @arg @ref LL_RCC_PLLM_DIV_6 01203 * @arg @ref LL_RCC_PLLM_DIV_7 01204 * @arg @ref LL_RCC_PLLM_DIV_8 01205 * @param __PLLSAI1N__ Between 8 and 86 01206 * @param __PLLSAI1R__ This parameter can be one of the following values: 01207 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 01208 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 01209 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 01210 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 01211 * @retval PLLSAI1 clock frequency (in Hz) 01212 */ 01213 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI1N__) / \ 01214 ((((__PLLSAI1R__) >> RCC_POSITION_PLLSAI1R ) + 1 ) * 2)) 01215 01216 /** 01217 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain 01218 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01219 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); 01220 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01221 * @param __PLLM__ This parameter can be one of the following values: 01222 * @arg @ref LL_RCC_PLLM_DIV_1 01223 * @arg @ref LL_RCC_PLLM_DIV_2 01224 * @arg @ref LL_RCC_PLLM_DIV_3 01225 * @arg @ref LL_RCC_PLLM_DIV_4 01226 * @arg @ref LL_RCC_PLLM_DIV_5 01227 * @arg @ref LL_RCC_PLLM_DIV_6 01228 * @arg @ref LL_RCC_PLLM_DIV_7 01229 * @arg @ref LL_RCC_PLLM_DIV_8 01230 * @param __PLLSAI2N__ Between 8 and 86 01231 * @param __PLLSAI2P__ This parameter can be one of the following values: 01232 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 01233 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 01234 * @retval PLLSAI2 clock frequency (in Hz) 01235 */ 01236 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI2N__) / \ 01237 (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7 : 17)) 01238 01239 /** 01240 * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain 01241 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01242 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ()); 01243 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01244 * @param __PLLM__ This parameter can be one of the following values: 01245 * @arg @ref LL_RCC_PLLM_DIV_1 01246 * @arg @ref LL_RCC_PLLM_DIV_2 01247 * @arg @ref LL_RCC_PLLM_DIV_3 01248 * @arg @ref LL_RCC_PLLM_DIV_4 01249 * @arg @ref LL_RCC_PLLM_DIV_5 01250 * @arg @ref LL_RCC_PLLM_DIV_6 01251 * @arg @ref LL_RCC_PLLM_DIV_7 01252 * @arg @ref LL_RCC_PLLM_DIV_8 01253 * @param __PLLSAI2N__ Between 8 and 86 01254 * @param __PLLSAI2R__ This parameter can be one of the following values: 01255 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 01256 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 01257 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 01258 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 01259 * @retval PLLSAI2 clock frequency (in Hz) 01260 */ 01261 #define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_POSITION_PLLM) + 1)) * (__PLLSAI2N__) / \ 01262 ((((__PLLSAI2R__) >> RCC_POSITION_PLLSAI2R ) + 1 ) * 2)) 01263 01264 /** 01265 * @brief Helper macro to calculate the HCLK frequency 01266 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) 01267 * @param __AHBPRESCALER__ This parameter can be one of the following values: 01268 * @arg @ref LL_RCC_SYSCLK_DIV_1 01269 * @arg @ref LL_RCC_SYSCLK_DIV_2 01270 * @arg @ref LL_RCC_SYSCLK_DIV_4 01271 * @arg @ref LL_RCC_SYSCLK_DIV_8 01272 * @arg @ref LL_RCC_SYSCLK_DIV_16 01273 * @arg @ref LL_RCC_SYSCLK_DIV_64 01274 * @arg @ref LL_RCC_SYSCLK_DIV_128 01275 * @arg @ref LL_RCC_SYSCLK_DIV_256 01276 * @arg @ref LL_RCC_SYSCLK_DIV_512 01277 * @retval HCLK clock frequency (in Hz) 01278 */ 01279 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]) 01280 01281 /** 01282 * @brief Helper macro to calculate the PCLK1 frequency (ABP1) 01283 * @param __HCLKFREQ__ HCLK frequency 01284 * @param __APB1PRESCALER__ This parameter can be one of the following values: 01285 * @arg @ref LL_RCC_APB1_DIV_1 01286 * @arg @ref LL_RCC_APB1_DIV_2 01287 * @arg @ref LL_RCC_APB1_DIV_4 01288 * @arg @ref LL_RCC_APB1_DIV_8 01289 * @arg @ref LL_RCC_APB1_DIV_16 01290 * @retval PCLK1 clock frequency (in Hz) 01291 */ 01292 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1]) 01293 01294 /** 01295 * @brief Helper macro to calculate the PCLK2 frequency (ABP2) 01296 * @param __HCLKFREQ__ HCLK frequency 01297 * @param __APB2PRESCALER__ This parameter can be one of the following values: 01298 * @arg @ref LL_RCC_APB2_DIV_1 01299 * @arg @ref LL_RCC_APB2_DIV_2 01300 * @arg @ref LL_RCC_APB2_DIV_4 01301 * @arg @ref LL_RCC_APB2_DIV_8 01302 * @arg @ref LL_RCC_APB2_DIV_16 01303 * @retval PCLK2 clock frequency (in Hz) 01304 */ 01305 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2]) 01306 01307 /** 01308 * @brief Helper macro to calculate the MSI frequency (in Hz) 01309 * @note: __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect 01310 * @note: if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY, 01311 * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby 01312 * else by LL_RCC_MSI_GetRange 01313 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01314 * (LL_RCC_MSI_IsEnabledRangeSelect()? 01315 * LL_RCC_MSI_GetRange(): 01316 * LL_RCC_MSI_GetRangeAfterStandby())) 01317 * @param __MSISEL__ This parameter can be one of the following values: 01318 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY 01319 * @arg @ref LL_RCC_MSIRANGESEL_RUN 01320 * @param __MSIRANGE__ This parameter can be one of the following values: 01321 * @arg @ref LL_RCC_MSIRANGE_0 01322 * @arg @ref LL_RCC_MSIRANGE_1 01323 * @arg @ref LL_RCC_MSIRANGE_2 01324 * @arg @ref LL_RCC_MSIRANGE_3 01325 * @arg @ref LL_RCC_MSIRANGE_4 01326 * @arg @ref LL_RCC_MSIRANGE_5 01327 * @arg @ref LL_RCC_MSIRANGE_6 01328 * @arg @ref LL_RCC_MSIRANGE_7 01329 * @arg @ref LL_RCC_MSIRANGE_8 01330 * @arg @ref LL_RCC_MSIRANGE_9 01331 * @arg @ref LL_RCC_MSIRANGE_10 01332 * @arg @ref LL_RCC_MSIRANGE_11 01333 * @arg @ref LL_RCC_MSISRANGE_4 01334 * @arg @ref LL_RCC_MSISRANGE_5 01335 * @arg @ref LL_RCC_MSISRANGE_6 01336 * @arg @ref LL_RCC_MSISRANGE_7 01337 * @retval MSI clock frequency (in Hz) 01338 */ 01339 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \ 01340 (MSIRangeTable[(__MSIRANGE__) >> 8]) : \ 01341 (MSIRangeTable[(__MSIRANGE__) >> 4])) 01342 01343 /** 01344 * @} 01345 */ 01346 01347 /** 01348 * @} 01349 */ 01350 01351 /* Exported functions --------------------------------------------------------*/ 01352 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions 01353 * @{ 01354 */ 01355 01356 /** @defgroup RCC_LL_EF_HSE HSE 01357 * @{ 01358 */ 01359 01360 /** 01361 * @brief Enable the Clock Security System. 01362 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS 01363 * @retval None 01364 */ 01365 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) 01366 { 01367 SET_BIT(RCC->CR, RCC_CR_CSSON); 01368 } 01369 01370 /** 01371 * @brief Enable HSE external oscillator (HSE Bypass) 01372 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass 01373 * @retval None 01374 */ 01375 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) 01376 { 01377 SET_BIT(RCC->CR, RCC_CR_HSEBYP); 01378 } 01379 01380 /** 01381 * @brief Disable HSE external oscillator (HSE Bypass) 01382 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass 01383 * @retval None 01384 */ 01385 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) 01386 { 01387 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 01388 } 01389 01390 /** 01391 * @brief Enable HSE crystal oscillator (HSE ON) 01392 * @rmtoll CR HSEON LL_RCC_HSE_Enable 01393 * @retval None 01394 */ 01395 __STATIC_INLINE void LL_RCC_HSE_Enable(void) 01396 { 01397 SET_BIT(RCC->CR, RCC_CR_HSEON); 01398 } 01399 01400 /** 01401 * @brief Disable HSE crystal oscillator (HSE ON) 01402 * @rmtoll CR HSEON LL_RCC_HSE_Disable 01403 * @retval None 01404 */ 01405 __STATIC_INLINE void LL_RCC_HSE_Disable(void) 01406 { 01407 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 01408 } 01409 01410 /** 01411 * @brief Check if HSE oscillator Ready 01412 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady 01413 * @retval State of bit (1 or 0). 01414 */ 01415 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) 01416 { 01417 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); 01418 } 01419 01420 /** 01421 * @} 01422 */ 01423 01424 /** @defgroup RCC_LL_EF_HSI HSI 01425 * @{ 01426 */ 01427 01428 /** 01429 * @brief Enable HSI even in stop mode 01430 * @note HSI oscillator is forced ON even in Stop mode 01431 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode 01432 * @retval None 01433 */ 01434 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) 01435 { 01436 SET_BIT(RCC->CR, RCC_CR_HSIKERON); 01437 } 01438 01439 /** 01440 * @brief Disable HSI in stop mode 01441 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode 01442 * @retval None 01443 */ 01444 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) 01445 { 01446 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); 01447 } 01448 01449 /** 01450 * @brief Enable HSI oscillator 01451 * @rmtoll CR HSION LL_RCC_HSI_Enable 01452 * @retval None 01453 */ 01454 __STATIC_INLINE void LL_RCC_HSI_Enable(void) 01455 { 01456 SET_BIT(RCC->CR, RCC_CR_HSION); 01457 } 01458 01459 /** 01460 * @brief Disable HSI oscillator 01461 * @rmtoll CR HSION LL_RCC_HSI_Disable 01462 * @retval None 01463 */ 01464 __STATIC_INLINE void LL_RCC_HSI_Disable(void) 01465 { 01466 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 01467 } 01468 01469 /** 01470 * @brief Check if HSI clock is ready 01471 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady 01472 * @retval State of bit (1 or 0). 01473 */ 01474 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) 01475 { 01476 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); 01477 } 01478 01479 /** 01480 * @brief Enable HSI Automatic from stop mode 01481 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop 01482 * @retval None 01483 */ 01484 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void) 01485 { 01486 SET_BIT(RCC->CR, RCC_CR_HSIASFS); 01487 } 01488 01489 /** 01490 * @brief Disable HSI Automatic from stop mode 01491 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop 01492 * @retval None 01493 */ 01494 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void) 01495 { 01496 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS); 01497 } 01498 /** 01499 * @brief Get HSI Calibration value 01500 * @note When HSITRIM is written, HSICAL is updated with the sum of 01501 * HSITRIM and the factory trim value 01502 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration 01503 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF 01504 */ 01505 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) 01506 { 01507 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL); 01508 } 01509 01510 /** 01511 * @brief Set HSI Calibration trimming 01512 * @note user-programmable trimming value that is added to the HSICAL 01513 * @note Default value is 16, which, when added to the HSICAL value, 01514 * should trim the HSI to 16 MHz +/- 1 % 01515 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming 01516 * @param Value Between Min_Data = 0 and Max_Data = 31 01517 * @retval None 01518 */ 01519 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) 01520 { 01521 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM); 01522 } 01523 01524 /** 01525 * @brief Get HSI Calibration trimming 01526 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming 01527 * @retval Between Min_Data = 0 and Max_Data = 31 01528 */ 01529 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) 01530 { 01531 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM); 01532 } 01533 01534 /** 01535 * @} 01536 */ 01537 01538 #if defined(RCC_HSI48_SUPPORT) 01539 /** @defgroup RCC_LL_EF_HSI48 HSI48 01540 * @{ 01541 */ 01542 01543 /** 01544 * @brief Enable HSI48 01545 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable 01546 * @retval None 01547 */ 01548 __STATIC_INLINE void LL_RCC_HSI48_Enable(void) 01549 { 01550 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); 01551 } 01552 01553 /** 01554 * @brief Disable HSI48 01555 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable 01556 * @retval None 01557 */ 01558 __STATIC_INLINE void LL_RCC_HSI48_Disable(void) 01559 { 01560 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); 01561 } 01562 01563 /** 01564 * @brief Check if HSI48 oscillator Ready 01565 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady 01566 * @retval State of bit (1 or 0). 01567 */ 01568 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) 01569 { 01570 return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)); 01571 } 01572 01573 /** 01574 * @brief Get HSI48 Calibration value 01575 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration 01576 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF 01577 */ 01578 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) 01579 { 01580 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_POSITION_HSI48CAL); 01581 } 01582 01583 /** 01584 * @} 01585 */ 01586 #endif /* RCC_HSI48_SUPPORT */ 01587 01588 /** @defgroup RCC_LL_EF_LSE LSE 01589 * @{ 01590 */ 01591 01592 /** 01593 * @brief Enable Low Speed External (LSE) crystal. 01594 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable 01595 * @retval None 01596 */ 01597 __STATIC_INLINE void LL_RCC_LSE_Enable(void) 01598 { 01599 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 01600 } 01601 01602 /** 01603 * @brief Disable Low Speed External (LSE) crystal. 01604 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable 01605 * @retval None 01606 */ 01607 __STATIC_INLINE void LL_RCC_LSE_Disable(void) 01608 { 01609 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 01610 } 01611 01612 /** 01613 * @brief Enable external clock source (LSE bypass). 01614 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass 01615 * @retval None 01616 */ 01617 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) 01618 { 01619 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 01620 } 01621 01622 /** 01623 * @brief Disable external clock source (LSE bypass). 01624 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass 01625 * @retval None 01626 */ 01627 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) 01628 { 01629 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 01630 } 01631 01632 /** 01633 * @brief Set LSE oscillator drive capability 01634 * @note The oscillator is in Xtal mode when it is not in bypass mode. 01635 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability 01636 * @param LSEDrive This parameter can be one of the following values: 01637 * @arg @ref LL_RCC_LSEDRIVE_LOW 01638 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW 01639 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH 01640 * @arg @ref LL_RCC_LSEDRIVE_HIGH 01641 * @retval None 01642 */ 01643 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) 01644 { 01645 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); 01646 } 01647 01648 /** 01649 * @brief Get LSE oscillator drive capability 01650 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability 01651 * @retval Returned value can be one of the following values: 01652 * @arg @ref LL_RCC_LSEDRIVE_LOW 01653 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW 01654 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH 01655 * @arg @ref LL_RCC_LSEDRIVE_HIGH 01656 */ 01657 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) 01658 { 01659 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); 01660 } 01661 01662 /** 01663 * @brief Enable Clock security system on LSE. 01664 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS 01665 * @retval None 01666 */ 01667 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) 01668 { 01669 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); 01670 } 01671 01672 /** 01673 * @brief Disable Clock security system on LSE. 01674 * @note Clock security system can be disabled only after a LSE 01675 * failure detection. In that case it MUST be disabled by software. 01676 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS 01677 * @retval None 01678 */ 01679 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) 01680 { 01681 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); 01682 } 01683 01684 /** 01685 * @brief Check if LSE oscillator Ready 01686 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady 01687 * @retval State of bit (1 or 0). 01688 */ 01689 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) 01690 { 01691 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); 01692 } 01693 01694 /** 01695 * @brief Check if CSS on LSE failure Detection 01696 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected 01697 * @retval State of bit (1 or 0). 01698 */ 01699 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) 01700 { 01701 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)); 01702 } 01703 01704 /** 01705 * @} 01706 */ 01707 01708 /** @defgroup RCC_LL_EF_LSI LSI 01709 * @{ 01710 */ 01711 01712 /** 01713 * @brief Enable LSI Oscillator 01714 * @rmtoll CSR LSION LL_RCC_LSI_Enable 01715 * @retval None 01716 */ 01717 __STATIC_INLINE void LL_RCC_LSI_Enable(void) 01718 { 01719 SET_BIT(RCC->CSR, RCC_CSR_LSION); 01720 } 01721 01722 /** 01723 * @brief Disable LSI Oscillator 01724 * @rmtoll CSR LSION LL_RCC_LSI_Disable 01725 * @retval None 01726 */ 01727 __STATIC_INLINE void LL_RCC_LSI_Disable(void) 01728 { 01729 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 01730 } 01731 01732 /** 01733 * @brief Check if LSI is Ready 01734 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady 01735 * @retval State of bit (1 or 0). 01736 */ 01737 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) 01738 { 01739 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); 01740 } 01741 01742 /** 01743 * @} 01744 */ 01745 01746 /** @defgroup RCC_LL_EF_MSI MSI 01747 * @{ 01748 */ 01749 01750 /** 01751 * @brief Enable MSI oscillator 01752 * @rmtoll CR MSION LL_RCC_MSI_Enable 01753 * @retval None 01754 */ 01755 __STATIC_INLINE void LL_RCC_MSI_Enable(void) 01756 { 01757 SET_BIT(RCC->CR, RCC_CR_MSION); 01758 } 01759 01760 /** 01761 * @brief Disable MSI oscillator 01762 * @rmtoll CR MSION LL_RCC_MSI_Disable 01763 * @retval None 01764 */ 01765 __STATIC_INLINE void LL_RCC_MSI_Disable(void) 01766 { 01767 CLEAR_BIT(RCC->CR, RCC_CR_MSION); 01768 } 01769 01770 /** 01771 * @brief Check if MSI oscillator Ready 01772 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady 01773 * @retval State of bit (1 or 0). 01774 */ 01775 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) 01776 { 01777 return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)); 01778 } 01779 01780 /** 01781 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE) 01782 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) 01783 * and ready (LSERDY set by hardware) 01784 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not 01785 * ready 01786 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode 01787 * @retval None 01788 */ 01789 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void) 01790 { 01791 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); 01792 } 01793 01794 /** 01795 * @brief Disable MSI-PLL mode 01796 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when 01797 * the Clock Security System on LSE detects a LSE failure 01798 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode 01799 * @retval None 01800 */ 01801 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void) 01802 { 01803 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); 01804 } 01805 01806 /** 01807 * @brief Enable MSI clock range selection with MSIRANGE register 01808 * @note Write 0 has no effect. After a standby or a reset 01809 * MSIRGSEL is at 0 and the MSI range value is provided by 01810 * MSISRANGE 01811 * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection 01812 * @retval None 01813 */ 01814 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void) 01815 { 01816 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); 01817 } 01818 01819 /** 01820 * @brief Check if MSI clock range is selected with MSIRANGE register 01821 * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect 01822 * @retval State of bit (1 or 0). 01823 */ 01824 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) 01825 { 01826 return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)); 01827 } 01828 01829 /** 01830 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. 01831 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange 01832 * @param Range This parameter can be one of the following values: 01833 * @arg @ref LL_RCC_MSIRANGE_0 01834 * @arg @ref LL_RCC_MSIRANGE_1 01835 * @arg @ref LL_RCC_MSIRANGE_2 01836 * @arg @ref LL_RCC_MSIRANGE_3 01837 * @arg @ref LL_RCC_MSIRANGE_4 01838 * @arg @ref LL_RCC_MSIRANGE_5 01839 * @arg @ref LL_RCC_MSIRANGE_6 01840 * @arg @ref LL_RCC_MSIRANGE_7 01841 * @arg @ref LL_RCC_MSIRANGE_8 01842 * @arg @ref LL_RCC_MSIRANGE_9 01843 * @arg @ref LL_RCC_MSIRANGE_10 01844 * @arg @ref LL_RCC_MSIRANGE_11 01845 * @retval None 01846 */ 01847 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) 01848 { 01849 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range); 01850 } 01851 01852 /** 01853 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. 01854 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange 01855 * @retval Returned value can be one of the following values: 01856 * @arg @ref LL_RCC_MSIRANGE_0 01857 * @arg @ref LL_RCC_MSIRANGE_1 01858 * @arg @ref LL_RCC_MSIRANGE_2 01859 * @arg @ref LL_RCC_MSIRANGE_3 01860 * @arg @ref LL_RCC_MSIRANGE_4 01861 * @arg @ref LL_RCC_MSIRANGE_5 01862 * @arg @ref LL_RCC_MSIRANGE_6 01863 * @arg @ref LL_RCC_MSIRANGE_7 01864 * @arg @ref LL_RCC_MSIRANGE_8 01865 * @arg @ref LL_RCC_MSIRANGE_9 01866 * @arg @ref LL_RCC_MSIRANGE_10 01867 * @arg @ref LL_RCC_MSIRANGE_11 01868 */ 01869 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) 01870 { 01871 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)); 01872 } 01873 01874 /** 01875 * @brief Configure MSI range used after standby 01876 * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby 01877 * @param Range This parameter can be one of the following values: 01878 * @arg @ref LL_RCC_MSISRANGE_4 01879 * @arg @ref LL_RCC_MSISRANGE_5 01880 * @arg @ref LL_RCC_MSISRANGE_6 01881 * @arg @ref LL_RCC_MSISRANGE_7 01882 * @retval None 01883 */ 01884 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range) 01885 { 01886 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range); 01887 } 01888 01889 /** 01890 * @brief Get MSI range used after standby 01891 * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby 01892 * @retval Returned value can be one of the following values: 01893 * @arg @ref LL_RCC_MSISRANGE_4 01894 * @arg @ref LL_RCC_MSISRANGE_5 01895 * @arg @ref LL_RCC_MSISRANGE_6 01896 * @arg @ref LL_RCC_MSISRANGE_7 01897 */ 01898 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void) 01899 { 01900 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE)); 01901 } 01902 01903 /** 01904 * @brief Get MSI Calibration value 01905 * @note When MSITRIM is written, MSICAL is updated with the sum of 01906 * MSITRIM and the factory trim value 01907 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration 01908 * @retval Between Min_Data = 0 and Max_Data = 255 01909 */ 01910 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) 01911 { 01912 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL); 01913 } 01914 01915 /** 01916 * @brief Set MSI Calibration trimming 01917 * @note user-programmable trimming value that is added to the MSICAL 01918 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming 01919 * @param Value Between Min_Data = 0 and Max_Data = 255 01920 * @retval None 01921 */ 01922 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) 01923 { 01924 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM); 01925 } 01926 01927 /** 01928 * @brief Get MSI Calibration trimming 01929 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming 01930 * @retval Between 0 and 255 01931 */ 01932 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) 01933 { 01934 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM); 01935 } 01936 01937 /** 01938 * @} 01939 */ 01940 01941 /** @defgroup RCC_LL_EF_LSCO LSCO 01942 * @{ 01943 */ 01944 01945 /** 01946 * @brief Enable Low speed clock 01947 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable 01948 * @retval None 01949 */ 01950 __STATIC_INLINE void LL_RCC_LSCO_Enable(void) 01951 { 01952 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); 01953 } 01954 01955 /** 01956 * @brief Disable Low speed clock 01957 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable 01958 * @retval None 01959 */ 01960 __STATIC_INLINE void LL_RCC_LSCO_Disable(void) 01961 { 01962 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); 01963 } 01964 01965 /** 01966 * @brief Configure Low speed clock selection 01967 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource 01968 * @param Source This parameter can be one of the following values: 01969 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI 01970 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE 01971 * @retval None 01972 */ 01973 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) 01974 { 01975 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); 01976 } 01977 01978 /** 01979 * @brief Get Low speed clock selection 01980 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource 01981 * @retval Returned value can be one of the following values: 01982 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI 01983 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE 01984 */ 01985 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) 01986 { 01987 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); 01988 } 01989 01990 /** 01991 * @} 01992 */ 01993 01994 /** @defgroup RCC_LL_EF_System System 01995 * @{ 01996 */ 01997 01998 /** 01999 * @brief Configure the system clock source 02000 * @rmtoll CFGR SW LL_RCC_SetSysClkSource 02001 * @param Source This parameter can be one of the following values: 02002 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI 02003 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI 02004 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE 02005 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL 02006 * @retval None 02007 */ 02008 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) 02009 { 02010 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 02011 } 02012 02013 /** 02014 * @brief Get the system clock source 02015 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource 02016 * @retval Returned value can be one of the following values: 02017 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI 02018 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI 02019 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE 02020 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL 02021 */ 02022 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) 02023 { 02024 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 02025 } 02026 02027 /** 02028 * @brief Set AHB prescaler 02029 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler 02030 * @param Prescaler This parameter can be one of the following values: 02031 * @arg @ref LL_RCC_SYSCLK_DIV_1 02032 * @arg @ref LL_RCC_SYSCLK_DIV_2 02033 * @arg @ref LL_RCC_SYSCLK_DIV_4 02034 * @arg @ref LL_RCC_SYSCLK_DIV_8 02035 * @arg @ref LL_RCC_SYSCLK_DIV_16 02036 * @arg @ref LL_RCC_SYSCLK_DIV_64 02037 * @arg @ref LL_RCC_SYSCLK_DIV_128 02038 * @arg @ref LL_RCC_SYSCLK_DIV_256 02039 * @arg @ref LL_RCC_SYSCLK_DIV_512 02040 * @retval None 02041 */ 02042 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) 02043 { 02044 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 02045 } 02046 02047 /** 02048 * @brief Set APB1 prescaler 02049 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler 02050 * @param Prescaler This parameter can be one of the following values: 02051 * @arg @ref LL_RCC_APB1_DIV_1 02052 * @arg @ref LL_RCC_APB1_DIV_2 02053 * @arg @ref LL_RCC_APB1_DIV_4 02054 * @arg @ref LL_RCC_APB1_DIV_8 02055 * @arg @ref LL_RCC_APB1_DIV_16 02056 * @retval None 02057 */ 02058 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) 02059 { 02060 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 02061 } 02062 02063 /** 02064 * @brief Set APB2 prescaler 02065 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler 02066 * @param Prescaler This parameter can be one of the following values: 02067 * @arg @ref LL_RCC_APB2_DIV_1 02068 * @arg @ref LL_RCC_APB2_DIV_2 02069 * @arg @ref LL_RCC_APB2_DIV_4 02070 * @arg @ref LL_RCC_APB2_DIV_8 02071 * @arg @ref LL_RCC_APB2_DIV_16 02072 * @retval None 02073 */ 02074 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) 02075 { 02076 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 02077 } 02078 02079 /** 02080 * @brief Get AHB prescaler 02081 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler 02082 * @retval Returned value can be one of the following values: 02083 * @arg @ref LL_RCC_SYSCLK_DIV_1 02084 * @arg @ref LL_RCC_SYSCLK_DIV_2 02085 * @arg @ref LL_RCC_SYSCLK_DIV_4 02086 * @arg @ref LL_RCC_SYSCLK_DIV_8 02087 * @arg @ref LL_RCC_SYSCLK_DIV_16 02088 * @arg @ref LL_RCC_SYSCLK_DIV_64 02089 * @arg @ref LL_RCC_SYSCLK_DIV_128 02090 * @arg @ref LL_RCC_SYSCLK_DIV_256 02091 * @arg @ref LL_RCC_SYSCLK_DIV_512 02092 */ 02093 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) 02094 { 02095 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); 02096 } 02097 02098 /** 02099 * @brief Get APB1 prescaler 02100 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler 02101 * @retval Returned value can be one of the following values: 02102 * @arg @ref LL_RCC_APB1_DIV_1 02103 * @arg @ref LL_RCC_APB1_DIV_2 02104 * @arg @ref LL_RCC_APB1_DIV_4 02105 * @arg @ref LL_RCC_APB1_DIV_8 02106 * @arg @ref LL_RCC_APB1_DIV_16 02107 */ 02108 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) 02109 { 02110 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); 02111 } 02112 02113 /** 02114 * @brief Get APB2 prescaler 02115 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler 02116 * @retval Returned value can be one of the following values: 02117 * @arg @ref LL_RCC_APB2_DIV_1 02118 * @arg @ref LL_RCC_APB2_DIV_2 02119 * @arg @ref LL_RCC_APB2_DIV_4 02120 * @arg @ref LL_RCC_APB2_DIV_8 02121 * @arg @ref LL_RCC_APB2_DIV_16 02122 */ 02123 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) 02124 { 02125 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); 02126 } 02127 02128 02129 /** 02130 * @brief Set Clock After Wake-Up From Stop mode 02131 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop 02132 * @param Clock This parameter can be one of the following values: 02133 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI 02134 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI 02135 * @retval None 02136 */ 02137 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) 02138 { 02139 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); 02140 } 02141 02142 /** 02143 * @brief Get Clock After Wake-Up From Stop mode 02144 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop 02145 * @retval Returned value can be one of the following values: 02146 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI 02147 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI 02148 */ 02149 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) 02150 { 02151 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); 02152 } 02153 02154 /** 02155 * @} 02156 */ 02157 02158 /** @defgroup RCC_LL_EF_MCO MCO 02159 * @{ 02160 */ 02161 02162 /** 02163 * @brief Configure MCOx 02164 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n 02165 * CFGR MCOPRE LL_RCC_ConfigMCO 02166 * @param MCOxSource This parameter can be one of the following values: 02167 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK 02168 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK 02169 * @arg @ref LL_RCC_MCO1SOURCE_MSI 02170 * @arg @ref LL_RCC_MCO1SOURCE_HSI 02171 * @arg @ref LL_RCC_MCO1SOURCE_HSE 02172 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) 02173 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK 02174 * @arg @ref LL_RCC_MCO1SOURCE_LSI 02175 * @arg @ref LL_RCC_MCO1SOURCE_LSE 02176 * 02177 * (*) value not defined in all devices. 02178 * @param MCOxPrescaler This parameter can be one of the following values: 02179 * @arg @ref LL_RCC_MCO1_DIV_1 02180 * @arg @ref LL_RCC_MCO1_DIV_2 02181 * @arg @ref LL_RCC_MCO1_DIV_4 02182 * @arg @ref LL_RCC_MCO1_DIV_8 02183 * @arg @ref LL_RCC_MCO1_DIV_16 02184 * @retval None 02185 */ 02186 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) 02187 { 02188 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); 02189 } 02190 02191 /** 02192 * @} 02193 */ 02194 02195 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source 02196 * @{ 02197 */ 02198 02199 /** 02200 * @brief Configure USARTx clock source 02201 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource 02202 * @param USARTxSource This parameter can be one of the following values: 02203 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 02204 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK 02205 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI 02206 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE 02207 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 02208 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK 02209 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI 02210 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE 02211 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) 02212 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) 02213 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) 02214 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) 02215 * 02216 * (*) value not defined in all devices. 02217 * @retval None 02218 */ 02219 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) 02220 { 02221 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF)); 02222 } 02223 02224 #if defined(UART4) || defined(UART5) 02225 /** 02226 * @brief Configure UARTx clock source 02227 * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource 02228 * @param UARTxSource This parameter can be one of the following values: 02229 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 02230 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK 02231 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI 02232 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE 02233 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 02234 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK 02235 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI 02236 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE 02237 * @retval None 02238 */ 02239 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) 02240 { 02241 MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF)); 02242 } 02243 #endif /* UART4 || UART5 */ 02244 02245 /** 02246 * @brief Configure LPUART1x clock source 02247 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource 02248 * @param LPUARTxSource This parameter can be one of the following values: 02249 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 02250 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK 02251 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI 02252 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE 02253 * @retval None 02254 */ 02255 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) 02256 { 02257 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); 02258 } 02259 02260 /** 02261 * @brief Configure I2Cx clock source 02262 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource 02263 * @param I2CxSource This parameter can be one of the following values: 02264 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 02265 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK 02266 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI 02267 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) 02268 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) 02269 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) 02270 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 02271 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK 02272 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI 02273 * 02274 * (*) value not defined in all devices. 02275 * @retval None 02276 */ 02277 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) 02278 { 02279 MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000), ((I2CxSource << 4) & 0x000FF000)); 02280 } 02281 02282 /** 02283 * @brief Configure LPTIMx clock source 02284 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource 02285 * @param LPTIMxSource This parameter can be one of the following values: 02286 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 02287 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 02288 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 02289 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 02290 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 02291 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 02292 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI 02293 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 02294 * @retval None 02295 */ 02296 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) 02297 { 02298 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); 02299 } 02300 02301 /** 02302 * @brief Configure SAIx clock source 02303 * @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource 02304 * @param SAIxSource This parameter can be one of the following values: 02305 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 02306 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*) 02307 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL 02308 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN 02309 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*) 02310 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*) 02311 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) 02312 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) 02313 * 02314 * (*) value not defined in all devices. 02315 * @retval None 02316 */ 02317 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) 02318 { 02319 MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16)); 02320 } 02321 02322 /** 02323 * @brief Configure SDMMC1 clock source 02324 * @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource 02325 * @param SDMMCxSource This parameter can be one of the following values: 02326 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE 02327 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 02328 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL 02329 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI 02330 * @retval None 02331 */ 02332 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) 02333 { 02334 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource); 02335 } 02336 02337 /** 02338 * @brief Configure RNG clock source 02339 * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource 02340 * @param RNGxSource This parameter can be one of the following values: 02341 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE 02342 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 02343 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL 02344 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI 02345 * @retval None 02346 */ 02347 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) 02348 { 02349 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource); 02350 } 02351 02352 #if defined(USB_OTG_FS) || defined(USB) 02353 /** 02354 * @brief Configure USB clock source 02355 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource 02356 * @param USBxSource This parameter can be one of the following values: 02357 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE 02358 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 02359 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL 02360 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI 02361 * @retval None 02362 */ 02363 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) 02364 { 02365 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource); 02366 } 02367 #endif /* USB_OTG_FS || USB */ 02368 02369 /** 02370 * @brief Configure ADC clock source 02371 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource 02372 * @param ADCxSource This parameter can be one of the following values: 02373 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE 02374 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 02375 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) 02376 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK 02377 * 02378 * (*) value not defined in all devices. 02379 * @retval None 02380 */ 02381 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) 02382 { 02383 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); 02384 } 02385 02386 /** 02387 * @brief Configure SWPMI clock source 02388 * @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource 02389 * @param SWPMIxSource This parameter can be one of the following values: 02390 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK 02391 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI 02392 * @retval None 02393 */ 02394 __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource) 02395 { 02396 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource); 02397 } 02398 02399 #if defined(DFSDM1_Channel0) 02400 /** 02401 * @brief Configure DFSDM clock source 02402 * @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource 02403 * @param DFSDMxSource This parameter can be one of the following values: 02404 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK 02405 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 02406 * @retval None 02407 */ 02408 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource) 02409 { 02410 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource); 02411 } 02412 #endif /* DFSDM1_Channel0 */ 02413 02414 /** 02415 * @brief Get USARTx clock source 02416 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource 02417 * @param USARTx This parameter can be one of the following values: 02418 * @arg @ref LL_RCC_USART1_CLKSOURCE 02419 * @arg @ref LL_RCC_USART2_CLKSOURCE 02420 * @arg @ref LL_RCC_USART3_CLKSOURCE (*) 02421 * 02422 * (*) value not defined in all devices. 02423 * @retval Returned value can be one of the following values: 02424 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 02425 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK 02426 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI 02427 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE 02428 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 02429 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK 02430 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI 02431 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE 02432 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) 02433 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) 02434 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) 02435 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) 02436 * 02437 * (*) value not defined in all devices. 02438 */ 02439 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) 02440 { 02441 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16)); 02442 } 02443 02444 #if defined(UART4) || defined(UART5) 02445 /** 02446 * @brief Get UARTx clock source 02447 * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource 02448 * @param UARTx This parameter can be one of the following values: 02449 * @arg @ref LL_RCC_UART4_CLKSOURCE 02450 * @arg @ref LL_RCC_UART5_CLKSOURCE 02451 * @retval Returned value can be one of the following values: 02452 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 02453 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK 02454 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI 02455 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE 02456 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 02457 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK 02458 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI 02459 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE 02460 */ 02461 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) 02462 { 02463 return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16)); 02464 } 02465 #endif /* UART4 || UART5 */ 02466 02467 /** 02468 * @brief Get LPUARTx clock source 02469 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource 02470 * @param LPUARTx This parameter can be one of the following values: 02471 * @arg @ref LL_RCC_LPUART1_CLKSOURCE 02472 * @retval Returned value can be one of the following values: 02473 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 02474 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK 02475 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI 02476 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE 02477 */ 02478 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) 02479 { 02480 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); 02481 } 02482 02483 /** 02484 * @brief Get I2Cx clock source 02485 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource 02486 * @param I2Cx This parameter can be one of the following values: 02487 * @arg @ref LL_RCC_I2C1_CLKSOURCE 02488 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) 02489 * @arg @ref LL_RCC_I2C3_CLKSOURCE 02490 * 02491 * (*) value not defined in all devices. 02492 * @retval Returned value can be one of the following values: 02493 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 02494 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK 02495 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI 02496 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) 02497 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) 02498 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) 02499 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 02500 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK 02501 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI 02502 * 02503 * (*) value not defined in all devices. 02504 */ 02505 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) 02506 { 02507 return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) | (I2Cx << 4)); 02508 } 02509 02510 /** 02511 * @brief Get LPTIMx clock source 02512 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource 02513 * @param LPTIMx This parameter can be one of the following values: 02514 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE 02515 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE 02516 * @retval Returned value can be one of the following values: 02517 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 02518 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 02519 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 02520 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 02521 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 02522 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 02523 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI 02524 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 02525 */ 02526 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) 02527 { 02528 return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16 | LPTIMx); 02529 } 02530 02531 /** 02532 * @brief Get SAIx clock source 02533 * @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource 02534 * @param SAIx This parameter can be one of the following values: 02535 * @arg @ref LL_RCC_SAI1_CLKSOURCE 02536 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) 02537 * 02538 * (*) value not defined in all devices. 02539 * @retval Returned value can be one of the following values: 02540 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 02541 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*) 02542 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL 02543 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN 02544 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*) 02545 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*) 02546 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) 02547 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) 02548 * 02549 * (*) value not defined in all devices. 02550 */ 02551 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) 02552 { 02553 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16 | SAIx); 02554 } 02555 02556 /** 02557 * @brief Get SDMMCx clock source 02558 * @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource 02559 * @param SDMMCx This parameter can be one of the following values: 02560 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE 02561 * @retval Returned value can be one of the following values: 02562 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE 02563 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 02564 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL 02565 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI 02566 */ 02567 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) 02568 { 02569 return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx)); 02570 } 02571 02572 /** 02573 * @brief Get RNGx clock source 02574 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource 02575 * @param RNGx This parameter can be one of the following values: 02576 * @arg @ref LL_RCC_RNG_CLKSOURCE 02577 * @retval Returned value can be one of the following values: 02578 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE 02579 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 02580 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL 02581 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI 02582 */ 02583 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) 02584 { 02585 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); 02586 } 02587 02588 #if defined(USB_OTG_FS) || defined(USB) 02589 /** 02590 * @brief Get USBx clock source 02591 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource 02592 * @param USBx This parameter can be one of the following values: 02593 * @arg @ref LL_RCC_USB_CLKSOURCE 02594 * @retval Returned value can be one of the following values: 02595 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE 02596 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 02597 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL 02598 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI 02599 */ 02600 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) 02601 { 02602 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx)); 02603 } 02604 #endif /* USB_OTG_FS || USB */ 02605 02606 /** 02607 * @brief Get ADCx clock source 02608 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource 02609 * @param ADCx This parameter can be one of the following values: 02610 * @arg @ref LL_RCC_ADC_CLKSOURCE 02611 * @retval Returned value can be one of the following values: 02612 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE 02613 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 02614 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) 02615 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK 02616 * 02617 * (*) value not defined in all devices. 02618 */ 02619 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) 02620 { 02621 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); 02622 } 02623 02624 /** 02625 * @brief Get SWPMIx clock source 02626 * @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource 02627 * @param SPWMIx This parameter can be one of the following values: 02628 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE 02629 * @retval Returned value can be one of the following values: 02630 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK 02631 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI 02632 */ 02633 __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx) 02634 { 02635 return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx)); 02636 } 02637 02638 #if defined(DFSDM1_Channel0) 02639 /** 02640 * @brief Get DFSDMx clock source 02641 * @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource 02642 * @param DFSDMx This parameter can be one of the following values: 02643 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE 02644 * @retval Returned value can be one of the following values: 02645 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK 02646 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 02647 */ 02648 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) 02649 { 02650 return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx)); 02651 } 02652 #endif /* DFSDM1_Channel0 */ 02653 02654 /** 02655 * @} 02656 */ 02657 02658 /** @defgroup RCC_LL_EF_RTC RTC 02659 * @{ 02660 */ 02661 02662 /** 02663 * @brief Set RTC Clock Source 02664 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless 02665 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is 02666 * set). The BDRST bit can be used to reset them. 02667 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource 02668 * @param Source This parameter can be one of the following values: 02669 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 02670 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 02671 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 02672 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 02673 * @retval None 02674 */ 02675 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) 02676 { 02677 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 02678 } 02679 02680 /** 02681 * @brief Get RTC Clock Source 02682 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource 02683 * @retval Returned value can be one of the following values: 02684 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 02685 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 02686 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 02687 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 02688 */ 02689 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) 02690 { 02691 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 02692 } 02693 02694 /** 02695 * @brief Enable RTC 02696 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC 02697 * @retval None 02698 */ 02699 __STATIC_INLINE void LL_RCC_EnableRTC(void) 02700 { 02701 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 02702 } 02703 02704 /** 02705 * @brief Disable RTC 02706 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC 02707 * @retval None 02708 */ 02709 __STATIC_INLINE void LL_RCC_DisableRTC(void) 02710 { 02711 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 02712 } 02713 02714 /** 02715 * @brief Check if RTC has been enabled or not 02716 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC 02717 * @retval State of bit (1 or 0). 02718 */ 02719 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) 02720 { 02721 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); 02722 } 02723 02724 /** 02725 * @brief Force the Backup domain reset 02726 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset 02727 * @retval None 02728 */ 02729 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) 02730 { 02731 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 02732 } 02733 02734 /** 02735 * @brief Release the Backup domain reset 02736 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset 02737 * @retval None 02738 */ 02739 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) 02740 { 02741 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 02742 } 02743 02744 /** 02745 * @} 02746 */ 02747 02748 /** @defgroup RCC_LL_EF_PLL PLL 02749 * @{ 02750 */ 02751 02752 /** 02753 * @brief Enable PLL 02754 * @rmtoll CR PLLON LL_RCC_PLL_Enable 02755 * @retval None 02756 */ 02757 __STATIC_INLINE void LL_RCC_PLL_Enable(void) 02758 { 02759 SET_BIT(RCC->CR, RCC_CR_PLLON); 02760 } 02761 02762 /** 02763 * @brief Disable PLL 02764 * @note Cannot be disabled if the PLL clock is used as the system clock 02765 * @rmtoll CR PLLON LL_RCC_PLL_Disable 02766 * @retval None 02767 */ 02768 __STATIC_INLINE void LL_RCC_PLL_Disable(void) 02769 { 02770 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 02771 } 02772 02773 /** 02774 * @brief Check if PLL Ready 02775 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady 02776 * @retval State of bit (1 or 0). 02777 */ 02778 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) 02779 { 02780 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); 02781 } 02782 02783 /** 02784 * @brief Configure PLL used for SYSCLK Domain 02785 * @note PLL Source and PLLM Divider can be written only when PLL, 02786 * PLLSAI1 and PLLSAI2 (*) are disabled 02787 * @note PLLN/PLLR can be written only when PLL is disabled 02788 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n 02789 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n 02790 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n 02791 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS 02792 * @param Source This parameter can be one of the following values: 02793 * @arg @ref LL_RCC_PLLSOURCE_NONE 02794 * @arg @ref LL_RCC_PLLSOURCE_MSI 02795 * @arg @ref LL_RCC_PLLSOURCE_HSI 02796 * @arg @ref LL_RCC_PLLSOURCE_HSE 02797 * @param PLLM This parameter can be one of the following values: 02798 * @arg @ref LL_RCC_PLLM_DIV_1 02799 * @arg @ref LL_RCC_PLLM_DIV_2 02800 * @arg @ref LL_RCC_PLLM_DIV_3 02801 * @arg @ref LL_RCC_PLLM_DIV_4 02802 * @arg @ref LL_RCC_PLLM_DIV_5 02803 * @arg @ref LL_RCC_PLLM_DIV_6 02804 * @arg @ref LL_RCC_PLLM_DIV_7 02805 * @arg @ref LL_RCC_PLLM_DIV_8 02806 * @param PLLN Between 8 and 86 02807 * @param PLLR This parameter can be one of the following values: 02808 * @arg @ref LL_RCC_PLLR_DIV_2 02809 * @arg @ref LL_RCC_PLLR_DIV_4 02810 * @arg @ref LL_RCC_PLLR_DIV_6 02811 * @arg @ref LL_RCC_PLLR_DIV_8 02812 * @retval None 02813 */ 02814 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 02815 { 02816 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 02817 Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLR); 02818 } 02819 02820 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 02821 /** 02822 * @brief Configure PLL used for SAI domain clock 02823 * @note PLL Source and PLLM Divider can be written only when PLL, 02824 * PLLSAI1 and PLLSAI2 (*) are disabled 02825 * @note PLLN/PLLP can be written only when PLL is disabled 02826 * @note This can be selected for SAI1 or SAI2 (*) 02827 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n 02828 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n 02829 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n 02830 * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI 02831 * @param Source This parameter can be one of the following values: 02832 * @arg @ref LL_RCC_PLLSOURCE_NONE 02833 * @arg @ref LL_RCC_PLLSOURCE_MSI 02834 * @arg @ref LL_RCC_PLLSOURCE_HSI 02835 * @arg @ref LL_RCC_PLLSOURCE_HSE 02836 * @param PLLM This parameter can be one of the following values: 02837 * @arg @ref LL_RCC_PLLM_DIV_1 02838 * @arg @ref LL_RCC_PLLM_DIV_2 02839 * @arg @ref LL_RCC_PLLM_DIV_3 02840 * @arg @ref LL_RCC_PLLM_DIV_4 02841 * @arg @ref LL_RCC_PLLM_DIV_5 02842 * @arg @ref LL_RCC_PLLM_DIV_6 02843 * @arg @ref LL_RCC_PLLM_DIV_7 02844 * @arg @ref LL_RCC_PLLM_DIV_8 02845 * @param PLLN Between 8 and 86 02846 * @param PLLP This parameter can be one of the following values: 02847 * @arg @ref LL_RCC_PLLP_DIV_2 02848 * @arg @ref LL_RCC_PLLP_DIV_3 02849 * @arg @ref LL_RCC_PLLP_DIV_4 02850 * @arg @ref LL_RCC_PLLP_DIV_5 02851 * @arg @ref LL_RCC_PLLP_DIV_6 02852 * @arg @ref LL_RCC_PLLP_DIV_7 02853 * @arg @ref LL_RCC_PLLP_DIV_8 02854 * @arg @ref LL_RCC_PLLP_DIV_9 02855 * @arg @ref LL_RCC_PLLP_DIV_10 02856 * @arg @ref LL_RCC_PLLP_DIV_11 02857 * @arg @ref LL_RCC_PLLP_DIV_12 02858 * @arg @ref LL_RCC_PLLP_DIV_13 02859 * @arg @ref LL_RCC_PLLP_DIV_14 02860 * @arg @ref LL_RCC_PLLP_DIV_15 02861 * @arg @ref LL_RCC_PLLP_DIV_16 02862 * @arg @ref LL_RCC_PLLP_DIV_17 02863 * @arg @ref LL_RCC_PLLP_DIV_18 02864 * @arg @ref LL_RCC_PLLP_DIV_19 02865 * @arg @ref LL_RCC_PLLP_DIV_20 02866 * @arg @ref LL_RCC_PLLP_DIV_21 02867 * @arg @ref LL_RCC_PLLP_DIV_22 02868 * @arg @ref LL_RCC_PLLP_DIV_23 02869 * @arg @ref LL_RCC_PLLP_DIV_24 02870 * @arg @ref LL_RCC_PLLP_DIV_25 02871 * @arg @ref LL_RCC_PLLP_DIV_26 02872 * @arg @ref LL_RCC_PLLP_DIV_27 02873 * @arg @ref LL_RCC_PLLP_DIV_28 02874 * @arg @ref LL_RCC_PLLP_DIV_29 02875 * @arg @ref LL_RCC_PLLP_DIV_30 02876 * @arg @ref LL_RCC_PLLP_DIV_31 02877 * @retval None 02878 */ 02879 #else 02880 /** 02881 * @brief Configure PLL used for SAI domain clock 02882 * @note PLL Source and PLLM Divider can be written only when PLL, 02883 * PLLSAI1 and PLLSAI2 (*) are disabled 02884 * @note PLLN/PLLP can be written only when PLL is disabled 02885 * @note This can be selected for SAI1 or SAI2 (*) 02886 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n 02887 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n 02888 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n 02889 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI 02890 * @param Source This parameter can be one of the following values: 02891 * @arg @ref LL_RCC_PLLSOURCE_NONE 02892 * @arg @ref LL_RCC_PLLSOURCE_MSI 02893 * @arg @ref LL_RCC_PLLSOURCE_HSI 02894 * @arg @ref LL_RCC_PLLSOURCE_HSE 02895 * @param PLLM This parameter can be one of the following values: 02896 * @arg @ref LL_RCC_PLLM_DIV_1 02897 * @arg @ref LL_RCC_PLLM_DIV_2 02898 * @arg @ref LL_RCC_PLLM_DIV_3 02899 * @arg @ref LL_RCC_PLLM_DIV_4 02900 * @arg @ref LL_RCC_PLLM_DIV_5 02901 * @arg @ref LL_RCC_PLLM_DIV_6 02902 * @arg @ref LL_RCC_PLLM_DIV_7 02903 * @arg @ref LL_RCC_PLLM_DIV_8 02904 * @param PLLN Between 8 and 86 02905 * @param PLLP This parameter can be one of the following values: 02906 * @arg @ref LL_RCC_PLLP_DIV_7 02907 * @arg @ref LL_RCC_PLLP_DIV_17 02908 * @retval None 02909 */ 02910 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 02911 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 02912 { 02913 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 02914 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV, 02915 Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLP); 02916 #else 02917 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, 02918 Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLP); 02919 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 02920 } 02921 02922 /** 02923 * @brief Configure PLL used for 48Mhz domain clock 02924 * @note PLL Source and PLLM Divider can be written only when PLL, 02925 * PLLSAI1 and PLLSAI2 (*) are disabled 02926 * @note PLLN/PLLQ can be written only when PLL is disabled 02927 * @note This can be selected for USB, RNG, SDMMC 02928 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n 02929 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n 02930 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n 02931 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M 02932 * @param Source This parameter can be one of the following values: 02933 * @arg @ref LL_RCC_PLLSOURCE_NONE 02934 * @arg @ref LL_RCC_PLLSOURCE_MSI 02935 * @arg @ref LL_RCC_PLLSOURCE_HSI 02936 * @arg @ref LL_RCC_PLLSOURCE_HSE 02937 * @param PLLM This parameter can be one of the following values: 02938 * @arg @ref LL_RCC_PLLM_DIV_1 02939 * @arg @ref LL_RCC_PLLM_DIV_2 02940 * @arg @ref LL_RCC_PLLM_DIV_3 02941 * @arg @ref LL_RCC_PLLM_DIV_4 02942 * @arg @ref LL_RCC_PLLM_DIV_5 02943 * @arg @ref LL_RCC_PLLM_DIV_6 02944 * @arg @ref LL_RCC_PLLM_DIV_7 02945 * @arg @ref LL_RCC_PLLM_DIV_8 02946 * @param PLLN Between 8 and 86 02947 * @param PLLQ This parameter can be one of the following values: 02948 * @arg @ref LL_RCC_PLLQ_DIV_2 02949 * @arg @ref LL_RCC_PLLQ_DIV_4 02950 * @arg @ref LL_RCC_PLLQ_DIV_6 02951 * @arg @ref LL_RCC_PLLQ_DIV_8 02952 * @retval None 02953 */ 02954 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 02955 { 02956 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, 02957 Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLQ); 02958 } 02959 02960 /** 02961 * @brief Get Main PLL multiplication factor for VCO 02962 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN 02963 * @retval Between 8 and 86 02964 */ 02965 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) 02966 { 02967 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_POSITION_PLLN); 02968 } 02969 02970 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 02971 /** 02972 * @brief Get Main PLL division factor for PLLP 02973 * @note used for PLLSAI3CLK (SAI1 and SAI2 clock) 02974 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP 02975 * @retval Returned value can be one of the following values: 02976 * @arg @ref LL_RCC_PLLP_DIV_2 02977 * @arg @ref LL_RCC_PLLP_DIV_3 02978 * @arg @ref LL_RCC_PLLP_DIV_4 02979 * @arg @ref LL_RCC_PLLP_DIV_5 02980 * @arg @ref LL_RCC_PLLP_DIV_6 02981 * @arg @ref LL_RCC_PLLP_DIV_7 02982 * @arg @ref LL_RCC_PLLP_DIV_8 02983 * @arg @ref LL_RCC_PLLP_DIV_9 02984 * @arg @ref LL_RCC_PLLP_DIV_10 02985 * @arg @ref LL_RCC_PLLP_DIV_11 02986 * @arg @ref LL_RCC_PLLP_DIV_12 02987 * @arg @ref LL_RCC_PLLP_DIV_13 02988 * @arg @ref LL_RCC_PLLP_DIV_14 02989 * @arg @ref LL_RCC_PLLP_DIV_15 02990 * @arg @ref LL_RCC_PLLP_DIV_16 02991 * @arg @ref LL_RCC_PLLP_DIV_17 02992 * @arg @ref LL_RCC_PLLP_DIV_18 02993 * @arg @ref LL_RCC_PLLP_DIV_19 02994 * @arg @ref LL_RCC_PLLP_DIV_20 02995 * @arg @ref LL_RCC_PLLP_DIV_21 02996 * @arg @ref LL_RCC_PLLP_DIV_22 02997 * @arg @ref LL_RCC_PLLP_DIV_23 02998 * @arg @ref LL_RCC_PLLP_DIV_24 02999 * @arg @ref LL_RCC_PLLP_DIV_25 03000 * @arg @ref LL_RCC_PLLP_DIV_26 03001 * @arg @ref LL_RCC_PLLP_DIV_27 03002 * @arg @ref LL_RCC_PLLP_DIV_28 03003 * @arg @ref LL_RCC_PLLP_DIV_29 03004 * @arg @ref LL_RCC_PLLP_DIV_30 03005 * @arg @ref LL_RCC_PLLP_DIV_31 03006 */ 03007 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) 03008 { 03009 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV)); 03010 } 03011 #else 03012 /** 03013 * @brief Get Main PLL division factor for PLLP 03014 * @note used for PLLSAI3CLK (SAI1 and SAI2 clock) 03015 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP 03016 * @retval Returned value can be one of the following values: 03017 * @arg @ref LL_RCC_PLLP_DIV_7 03018 * @arg @ref LL_RCC_PLLP_DIV_17 03019 */ 03020 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) 03021 { 03022 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); 03023 } 03024 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 03025 03026 /** 03027 * @brief Get Main PLL division factor for PLLQ 03028 * @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock) 03029 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ 03030 * @retval Returned value can be one of the following values: 03031 * @arg @ref LL_RCC_PLLQ_DIV_2 03032 * @arg @ref LL_RCC_PLLQ_DIV_4 03033 * @arg @ref LL_RCC_PLLQ_DIV_6 03034 * @arg @ref LL_RCC_PLLQ_DIV_8 03035 */ 03036 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) 03037 { 03038 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); 03039 } 03040 03041 /** 03042 * @brief Get Main PLL division factor for PLLR 03043 * @note used for PLLCLK (system clock) 03044 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR 03045 * @retval Returned value can be one of the following values: 03046 * @arg @ref LL_RCC_PLLR_DIV_2 03047 * @arg @ref LL_RCC_PLLR_DIV_4 03048 * @arg @ref LL_RCC_PLLR_DIV_6 03049 * @arg @ref LL_RCC_PLLR_DIV_8 03050 */ 03051 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) 03052 { 03053 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); 03054 } 03055 03056 /** 03057 * @brief Get the oscillator used as PLL clock source. 03058 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource 03059 * @retval Returned value can be one of the following values: 03060 * @arg @ref LL_RCC_PLLSOURCE_NONE 03061 * @arg @ref LL_RCC_PLLSOURCE_MSI 03062 * @arg @ref LL_RCC_PLLSOURCE_HSI 03063 * @arg @ref LL_RCC_PLLSOURCE_HSE 03064 */ 03065 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) 03066 { 03067 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); 03068 } 03069 03070 /** 03071 * @brief Get Division factor for the main PLL and other PLL 03072 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider 03073 * @retval Returned value can be one of the following values: 03074 * @arg @ref LL_RCC_PLLM_DIV_1 03075 * @arg @ref LL_RCC_PLLM_DIV_2 03076 * @arg @ref LL_RCC_PLLM_DIV_3 03077 * @arg @ref LL_RCC_PLLM_DIV_4 03078 * @arg @ref LL_RCC_PLLM_DIV_5 03079 * @arg @ref LL_RCC_PLLM_DIV_6 03080 * @arg @ref LL_RCC_PLLM_DIV_7 03081 * @arg @ref LL_RCC_PLLM_DIV_8 03082 */ 03083 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) 03084 { 03085 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 03086 } 03087 03088 /** 03089 * @brief Enable PLL output mapped on SAI domain clock 03090 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI 03091 * @retval None 03092 */ 03093 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void) 03094 { 03095 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); 03096 } 03097 03098 /** 03099 * @brief Disable PLL output mapped on SAI domain clock 03100 * @note Cannot be disabled if the PLL clock is used as the system 03101 * clock 03102 * @note In order to save power, when the PLLCLK of the PLL is 03103 * not used, should be 0 03104 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI 03105 * @retval None 03106 */ 03107 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void) 03108 { 03109 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); 03110 } 03111 03112 /** 03113 * @brief Enable PLL output mapped on 48MHz domain clock 03114 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M 03115 * @retval None 03116 */ 03117 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void) 03118 { 03119 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); 03120 } 03121 03122 /** 03123 * @brief Disable PLL output mapped on 48MHz domain clock 03124 * @note Cannot be disabled if the PLL clock is used as the system 03125 * clock 03126 * @note In order to save power, when the PLLCLK of the PLL is 03127 * not used, should be 0 03128 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M 03129 * @retval None 03130 */ 03131 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void) 03132 { 03133 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); 03134 } 03135 03136 /** 03137 * @brief Enable PLL output mapped on SYSCLK domain 03138 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS 03139 * @retval None 03140 */ 03141 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) 03142 { 03143 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); 03144 } 03145 03146 /** 03147 * @brief Disable PLL output mapped on SYSCLK domain 03148 * @note Cannot be disabled if the PLL clock is used as the system 03149 * clock 03150 * @note In order to save power, when the PLLCLK of the PLL is 03151 * not used, Main PLL should be 0 03152 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS 03153 * @retval None 03154 */ 03155 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) 03156 { 03157 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); 03158 } 03159 03160 /** 03161 * @} 03162 */ 03163 03164 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1 03165 * @{ 03166 */ 03167 03168 /** 03169 * @brief Enable PLLSAI1 03170 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable 03171 * @retval None 03172 */ 03173 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void) 03174 { 03175 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON); 03176 } 03177 03178 /** 03179 * @brief Disable PLLSAI1 03180 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable 03181 * @retval None 03182 */ 03183 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void) 03184 { 03185 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON); 03186 } 03187 03188 /** 03189 * @brief Check if PLLSAI1 Ready 03190 * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady 03191 * @retval State of bit (1 or 0). 03192 */ 03193 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void) 03194 { 03195 return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)); 03196 } 03197 03198 /** 03199 * @brief Configure PLLSAI1 used for 48Mhz domain clock 03200 * @note PLL Source and PLLM Divider can be written only when PLL, 03201 * PLLSAI1 and PLLSAI2 (*) are disabled 03202 * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled 03203 * @note This can be selected for USB, RNG, SDMMC 03204 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n 03205 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n 03206 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n 03207 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M 03208 * @param Source This parameter can be one of the following values: 03209 * @arg @ref LL_RCC_PLLSOURCE_NONE 03210 * @arg @ref LL_RCC_PLLSOURCE_MSI 03211 * @arg @ref LL_RCC_PLLSOURCE_HSI 03212 * @arg @ref LL_RCC_PLLSOURCE_HSE 03213 * @param PLLM This parameter can be one of the following values: 03214 * @arg @ref LL_RCC_PLLM_DIV_1 03215 * @arg @ref LL_RCC_PLLM_DIV_2 03216 * @arg @ref LL_RCC_PLLM_DIV_3 03217 * @arg @ref LL_RCC_PLLM_DIV_4 03218 * @arg @ref LL_RCC_PLLM_DIV_5 03219 * @arg @ref LL_RCC_PLLM_DIV_6 03220 * @arg @ref LL_RCC_PLLM_DIV_7 03221 * @arg @ref LL_RCC_PLLM_DIV_8 03222 * @param PLLN Between 8 and 86 03223 * @param PLLQ This parameter can be one of the following values: 03224 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 03225 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 03226 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 03227 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 03228 * @retval None 03229 */ 03230 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 03231 { 03232 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 03233 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_POSITION_PLLSAI1N | PLLQ); 03234 } 03235 03236 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 03237 /** 03238 * @brief Configure PLLSAI1 used for SAI domain clock 03239 * @note PLL Source and PLLM Divider can be written only when PLL, 03240 * PLLSAI1 and PLLSAI2 (*) are disabled 03241 * @note PLLN/PLLP can be written only when PLLSAI1 is disabled 03242 * @note This can be selected for SAI1 or SAI2 (*) 03243 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n 03244 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n 03245 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n 03246 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI 03247 * @param Source This parameter can be one of the following values: 03248 * @arg @ref LL_RCC_PLLSOURCE_NONE 03249 * @arg @ref LL_RCC_PLLSOURCE_MSI 03250 * @arg @ref LL_RCC_PLLSOURCE_HSI 03251 * @arg @ref LL_RCC_PLLSOURCE_HSE 03252 * @param PLLM This parameter can be one of the following values: 03253 * @arg @ref LL_RCC_PLLM_DIV_1 03254 * @arg @ref LL_RCC_PLLM_DIV_2 03255 * @arg @ref LL_RCC_PLLM_DIV_3 03256 * @arg @ref LL_RCC_PLLM_DIV_4 03257 * @arg @ref LL_RCC_PLLM_DIV_5 03258 * @arg @ref LL_RCC_PLLM_DIV_6 03259 * @arg @ref LL_RCC_PLLM_DIV_7 03260 * @arg @ref LL_RCC_PLLM_DIV_8 03261 * @param PLLN Between 8 and 86 03262 * @param PLLP This parameter can be one of the following values: 03263 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 03264 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 03265 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 03266 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 03267 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 03268 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 03269 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 03270 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 03271 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 03272 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 03273 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 03274 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 03275 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 03276 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 03277 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 03278 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 03279 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 03280 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 03281 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 03282 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 03283 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 03284 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 03285 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 03286 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 03287 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 03288 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 03289 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 03290 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 03291 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 03292 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 03293 * @retval None 03294 */ 03295 #else 03296 /** 03297 * @brief Configure PLLSAI1 used for SAI domain clock 03298 * @note PLL Source and PLLM Divider can be written only when PLL, 03299 * PLLSAI1 and PLLSAI2 (*) are disabled 03300 * @note PLLN/PLLP can be written only when PLLSAI1 is disabled 03301 * @note This can be selected for SAI1 or SAI2 (*) 03302 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n 03303 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n 03304 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n 03305 * PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI 03306 * @param Source This parameter can be one of the following values: 03307 * @arg @ref LL_RCC_PLLSOURCE_NONE 03308 * @arg @ref LL_RCC_PLLSOURCE_MSI 03309 * @arg @ref LL_RCC_PLLSOURCE_HSI 03310 * @arg @ref LL_RCC_PLLSOURCE_HSE 03311 * @param PLLM This parameter can be one of the following values: 03312 * @arg @ref LL_RCC_PLLM_DIV_1 03313 * @arg @ref LL_RCC_PLLM_DIV_2 03314 * @arg @ref LL_RCC_PLLM_DIV_3 03315 * @arg @ref LL_RCC_PLLM_DIV_4 03316 * @arg @ref LL_RCC_PLLM_DIV_5 03317 * @arg @ref LL_RCC_PLLM_DIV_6 03318 * @arg @ref LL_RCC_PLLM_DIV_7 03319 * @arg @ref LL_RCC_PLLM_DIV_8 03320 * @param PLLN Between 8 and 86 03321 * @param PLLP This parameter can be one of the following values: 03322 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 03323 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 03324 * @retval None 03325 */ 03326 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 03327 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 03328 { 03329 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 03330 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 03331 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, 03332 PLLN << RCC_POSITION_PLLSAI1N | PLLP); 03333 #else 03334 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_POSITION_PLLSAI1N | PLLP); 03335 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 03336 } 03337 03338 /** 03339 * @brief Configure PLLSAI1 used for ADC domain clock 03340 * @note PLL Source and PLLM Divider can be written only when PLL, 03341 * PLLSAI1 and PLLSAI2 (*) are disabled 03342 * @note PLLN/PLLR can be written only when PLLSAI1 is disabled 03343 * @note This can be selected for ADC 03344 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n 03345 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n 03346 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n 03347 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC 03348 * @param Source This parameter can be one of the following values: 03349 * @arg @ref LL_RCC_PLLSOURCE_NONE 03350 * @arg @ref LL_RCC_PLLSOURCE_MSI 03351 * @arg @ref LL_RCC_PLLSOURCE_HSI 03352 * @arg @ref LL_RCC_PLLSOURCE_HSE 03353 * @param PLLM This parameter can be one of the following values: 03354 * @arg @ref LL_RCC_PLLM_DIV_1 03355 * @arg @ref LL_RCC_PLLM_DIV_2 03356 * @arg @ref LL_RCC_PLLM_DIV_3 03357 * @arg @ref LL_RCC_PLLM_DIV_4 03358 * @arg @ref LL_RCC_PLLM_DIV_5 03359 * @arg @ref LL_RCC_PLLM_DIV_6 03360 * @arg @ref LL_RCC_PLLM_DIV_7 03361 * @arg @ref LL_RCC_PLLM_DIV_8 03362 * @param PLLN Between 8 and 86 03363 * @param PLLR This parameter can be one of the following values: 03364 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 03365 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 03366 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 03367 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 03368 * @retval None 03369 */ 03370 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 03371 { 03372 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 03373 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_POSITION_PLLSAI1N | PLLR); 03374 } 03375 03376 /** 03377 * @brief Get SAI1PLL multiplication factor for VCO 03378 * @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN 03379 * @retval Between 8 and 86 03380 */ 03381 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void) 03382 { 03383 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_POSITION_PLLSAI1N); 03384 } 03385 03386 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 03387 /** 03388 * @brief Get SAI1PLL division factor for PLLSAI1P 03389 * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). 03390 * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP 03391 * @retval Returned value can be one of the following values: 03392 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 03393 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 03394 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 03395 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 03396 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 03397 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 03398 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 03399 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 03400 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 03401 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 03402 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 03403 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 03404 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 03405 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 03406 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 03407 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 03408 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 03409 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 03410 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 03411 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 03412 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 03413 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 03414 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 03415 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 03416 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 03417 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 03418 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 03419 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 03420 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 03421 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 03422 */ 03423 #else 03424 /** 03425 * @brief Get SAI1PLL division factor for PLLSAI1P 03426 * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). 03427 * @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP 03428 * @retval Returned value can be one of the following values: 03429 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 03430 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 03431 */ 03432 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 03433 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) 03434 { 03435 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 03436 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV)); 03437 #else 03438 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P)); 03439 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 03440 } 03441 03442 /** 03443 * @brief Get SAI1PLL division factor for PLLSAI1Q 03444 * @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock) 03445 * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ 03446 * @retval Returned value can be one of the following values: 03447 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 03448 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 03449 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 03450 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 03451 */ 03452 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void) 03453 { 03454 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q)); 03455 } 03456 03457 /** 03458 * @brief Get PLLSAI1 division factor for PLLSAIR 03459 * @note used for PLLADC1CLK (ADC clock) 03460 * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR 03461 * @retval Returned value can be one of the following values: 03462 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 03463 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 03464 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 03465 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 03466 */ 03467 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void) 03468 { 03469 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R)); 03470 } 03471 03472 /** 03473 * @brief Enable PLLSAI1 output mapped on SAI domain clock 03474 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI 03475 * @retval None 03476 */ 03477 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void) 03478 { 03479 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN); 03480 } 03481 03482 /** 03483 * @brief Disable PLLSAI1 output mapped on SAI domain clock 03484 * @note In order to save power, when of the PLLSAI1 is 03485 * not used, should be 0 03486 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI 03487 * @retval None 03488 */ 03489 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void) 03490 { 03491 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN); 03492 } 03493 03494 /** 03495 * @brief Enable PLLSAI1 output mapped on 48MHz domain clock 03496 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M 03497 * @retval None 03498 */ 03499 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void) 03500 { 03501 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN); 03502 } 03503 03504 /** 03505 * @brief Disable PLLSAI1 output mapped on 48MHz domain clock 03506 * @note In order to save power, when of the PLLSAI1 is 03507 * not used, should be 0 03508 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M 03509 * @retval None 03510 */ 03511 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void) 03512 { 03513 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN); 03514 } 03515 03516 /** 03517 * @brief Enable PLLSAI1 output mapped on ADC domain clock 03518 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC 03519 * @retval None 03520 */ 03521 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void) 03522 { 03523 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN); 03524 } 03525 03526 /** 03527 * @brief Disable PLLSAI1 output mapped on ADC domain clock 03528 * @note In order to save power, when of the PLLSAI1 is 03529 * not used, Main PLLSAI1 should be 0 03530 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC 03531 * @retval None 03532 */ 03533 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void) 03534 { 03535 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN); 03536 } 03537 03538 /** 03539 * @} 03540 */ 03541 03542 #if defined(RCC_PLLSAI2_SUPPORT) 03543 /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2 03544 * @{ 03545 */ 03546 03547 /** 03548 * @brief Enable PLLSAI2 03549 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable 03550 * @retval None 03551 */ 03552 __STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void) 03553 { 03554 SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON); 03555 } 03556 03557 /** 03558 * @brief Disable PLLSAI2 03559 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable 03560 * @retval None 03561 */ 03562 __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void) 03563 { 03564 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON); 03565 } 03566 03567 /** 03568 * @brief Check if PLLSAI2 Ready 03569 * @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady 03570 * @retval State of bit (1 or 0). 03571 */ 03572 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void) 03573 { 03574 return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)); 03575 } 03576 03577 /** 03578 * @brief Configure PLLSAI2 used for SAI domain clock 03579 * @note PLL Source and PLLM Divider can be written only when PLL, 03580 * PLLSAI2 and PLLSAI2 are disabled 03581 * @note PLLN/PLLP can be written only when PLLSAI2 is disabled 03582 * @note This can be selected for SAI1 or SAI2 03583 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n 03584 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n 03585 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n 03586 * PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI 03587 * @param Source This parameter can be one of the following values: 03588 * @arg @ref LL_RCC_PLLSOURCE_NONE 03589 * @arg @ref LL_RCC_PLLSOURCE_MSI 03590 * @arg @ref LL_RCC_PLLSOURCE_HSI 03591 * @arg @ref LL_RCC_PLLSOURCE_HSE 03592 * @param PLLM This parameter can be one of the following values: 03593 * @arg @ref LL_RCC_PLLM_DIV_1 03594 * @arg @ref LL_RCC_PLLM_DIV_2 03595 * @arg @ref LL_RCC_PLLM_DIV_3 03596 * @arg @ref LL_RCC_PLLM_DIV_4 03597 * @arg @ref LL_RCC_PLLM_DIV_5 03598 * @arg @ref LL_RCC_PLLM_DIV_6 03599 * @arg @ref LL_RCC_PLLM_DIV_7 03600 * @arg @ref LL_RCC_PLLM_DIV_8 03601 * @param PLLN Between 8 and 86 03602 * @param PLLP This parameter can be one of the following values: 03603 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 03604 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 03605 * @retval None 03606 */ 03607 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 03608 { 03609 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 03610 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_POSITION_PLLSAI2N | PLLP); 03611 } 03612 03613 /** 03614 * @brief Configure PLLSAI2 used for ADC domain clock 03615 * @note PLL Source and PLLM Divider can be written only when PLL, 03616 * PLLSAI2 and PLLSAI2 are disabled 03617 * @note PLLN/PLLR can be written only when PLLSAI2 is disabled 03618 * @note This can be selected for ADC 03619 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n 03620 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n 03621 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n 03622 * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC 03623 * @param Source This parameter can be one of the following values: 03624 * @arg @ref LL_RCC_PLLSOURCE_NONE 03625 * @arg @ref LL_RCC_PLLSOURCE_MSI 03626 * @arg @ref LL_RCC_PLLSOURCE_HSI 03627 * @arg @ref LL_RCC_PLLSOURCE_HSE 03628 * @param PLLM This parameter can be one of the following values: 03629 * @arg @ref LL_RCC_PLLM_DIV_1 03630 * @arg @ref LL_RCC_PLLM_DIV_2 03631 * @arg @ref LL_RCC_PLLM_DIV_3 03632 * @arg @ref LL_RCC_PLLM_DIV_4 03633 * @arg @ref LL_RCC_PLLM_DIV_5 03634 * @arg @ref LL_RCC_PLLM_DIV_6 03635 * @arg @ref LL_RCC_PLLM_DIV_7 03636 * @arg @ref LL_RCC_PLLM_DIV_8 03637 * @param PLLN Between 8 and 86 03638 * @param PLLR This parameter can be one of the following values: 03639 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 03640 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 03641 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 03642 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 03643 * @retval None 03644 */ 03645 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 03646 { 03647 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 03648 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_POSITION_PLLSAI2N | PLLR); 03649 } 03650 03651 /** 03652 * @brief Get SAI2PLL multiplication factor for VCO 03653 * @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN 03654 * @retval Between 8 and 86 03655 */ 03656 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void) 03657 { 03658 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_POSITION_PLLSAI2N); 03659 } 03660 03661 /** 03662 * @brief Get SAI2PLL division factor for PLLSAI2P 03663 * @note used for PLLSAI2CLK (SAI1 or SAI2 clock). 03664 * @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP 03665 * @retval Returned value can be one of the following values: 03666 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 03667 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 03668 */ 03669 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) 03670 { 03671 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P)); 03672 } 03673 03674 /** 03675 * @brief Get SAI2PLL division factor for PLLSAI2R 03676 * @note used for PLLADC2CLK (ADC clock) 03677 * @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR 03678 * @retval Returned value can be one of the following values: 03679 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 03680 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 03681 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 03682 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 03683 */ 03684 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void) 03685 { 03686 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)); 03687 } 03688 03689 /** 03690 * @brief Enable PLLSAI2 output mapped on SAI domain clock 03691 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI 03692 * @retval None 03693 */ 03694 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void) 03695 { 03696 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN); 03697 } 03698 03699 /** 03700 * @brief Disable PLLSAI2 output mapped on SAI domain clock 03701 * @note In order to save power, when of the PLLSAI2 is 03702 * not used, should be 0 03703 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI 03704 * @retval None 03705 */ 03706 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void) 03707 { 03708 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN); 03709 } 03710 03711 /** 03712 * @brief Enable PLLSAI2 output mapped on ADC domain clock 03713 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC 03714 * @retval None 03715 */ 03716 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void) 03717 { 03718 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); 03719 } 03720 03721 /** 03722 * @brief Disable PLLSAI2 output mapped on ADC domain clock 03723 * @note In order to save power, when of the PLLSAI2 is 03724 * not used, Main PLLSAI2 should be 0 03725 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC 03726 * @retval None 03727 */ 03728 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void) 03729 { 03730 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); 03731 } 03732 03733 /** 03734 * @} 03735 */ 03736 03737 #endif /* RCC_PLLSAI2_SUPPORT */ 03738 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management 03739 * @{ 03740 */ 03741 03742 /** 03743 * @brief Clear LSI ready interrupt flag 03744 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY 03745 * @retval None 03746 */ 03747 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) 03748 { 03749 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); 03750 } 03751 03752 /** 03753 * @brief Clear LSE ready interrupt flag 03754 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY 03755 * @retval None 03756 */ 03757 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) 03758 { 03759 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); 03760 } 03761 03762 /** 03763 * @brief Clear MSI ready interrupt flag 03764 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY 03765 * @retval None 03766 */ 03767 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) 03768 { 03769 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC); 03770 } 03771 03772 /** 03773 * @brief Clear HSI ready interrupt flag 03774 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY 03775 * @retval None 03776 */ 03777 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) 03778 { 03779 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); 03780 } 03781 03782 /** 03783 * @brief Clear HSE ready interrupt flag 03784 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY 03785 * @retval None 03786 */ 03787 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) 03788 { 03789 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); 03790 } 03791 03792 /** 03793 * @brief Clear PLL ready interrupt flag 03794 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY 03795 * @retval None 03796 */ 03797 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) 03798 { 03799 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); 03800 } 03801 03802 #if defined(RCC_HSI48_SUPPORT) 03803 /** 03804 * @brief Clear HSI48 ready interrupt flag 03805 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY 03806 * @retval None 03807 */ 03808 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) 03809 { 03810 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); 03811 } 03812 #endif /* RCC_HSI48_SUPPORT */ 03813 03814 /** 03815 * @brief Clear PLLSAI1 ready interrupt flag 03816 * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY 03817 * @retval None 03818 */ 03819 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void) 03820 { 03821 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC); 03822 } 03823 03824 #if defined(RCC_PLLSAI2_SUPPORT) 03825 /** 03826 * @brief Clear PLLSAI1 ready interrupt flag 03827 * @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY 03828 * @retval None 03829 */ 03830 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void) 03831 { 03832 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC); 03833 } 03834 03835 #endif /* RCC_PLLSAI2_SUPPORT */ 03836 /** 03837 * @brief Clear Clock security system interrupt flag 03838 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS 03839 * @retval None 03840 */ 03841 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) 03842 { 03843 SET_BIT(RCC->CICR, RCC_CICR_CSSC); 03844 } 03845 03846 /** 03847 * @brief Clear LSE Clock security system interrupt flag 03848 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS 03849 * @retval None 03850 */ 03851 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) 03852 { 03853 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); 03854 } 03855 03856 /** 03857 * @brief Check if LSI ready interrupt occurred or not 03858 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY 03859 * @retval State of bit (1 or 0). 03860 */ 03861 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) 03862 { 03863 return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)); 03864 } 03865 03866 /** 03867 * @brief Check if LSE ready interrupt occurred or not 03868 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY 03869 * @retval State of bit (1 or 0). 03870 */ 03871 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) 03872 { 03873 return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)); 03874 } 03875 03876 /** 03877 * @brief Check if MSI ready interrupt occurred or not 03878 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY 03879 * @retval State of bit (1 or 0). 03880 */ 03881 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) 03882 { 03883 return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)); 03884 } 03885 03886 /** 03887 * @brief Check if HSI ready interrupt occurred or not 03888 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY 03889 * @retval State of bit (1 or 0). 03890 */ 03891 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) 03892 { 03893 return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)); 03894 } 03895 03896 /** 03897 * @brief Check if HSE ready interrupt occurred or not 03898 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY 03899 * @retval State of bit (1 or 0). 03900 */ 03901 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) 03902 { 03903 return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)); 03904 } 03905 03906 /** 03907 * @brief Check if PLL ready interrupt occurred or not 03908 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY 03909 * @retval State of bit (1 or 0). 03910 */ 03911 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) 03912 { 03913 return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)); 03914 } 03915 03916 #if defined(RCC_HSI48_SUPPORT) 03917 /** 03918 * @brief Check if HSI48 ready interrupt occurred or not 03919 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY 03920 * @retval State of bit (1 or 0). 03921 */ 03922 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) 03923 { 03924 return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)); 03925 } 03926 #endif /* RCC_HSI48_SUPPORT */ 03927 03928 /** 03929 * @brief Check if PLLSAI1 ready interrupt occurred or not 03930 * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY 03931 * @retval State of bit (1 or 0). 03932 */ 03933 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void) 03934 { 03935 return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF)); 03936 } 03937 03938 #if defined(RCC_PLLSAI2_SUPPORT) 03939 /** 03940 * @brief Check if PLLSAI1 ready interrupt occurred or not 03941 * @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY 03942 * @retval State of bit (1 or 0). 03943 */ 03944 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void) 03945 { 03946 return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF)); 03947 } 03948 03949 #endif /* RCC_PLLSAI2_SUPPORT */ 03950 /** 03951 * @brief Check if Clock security system interrupt occurred or not 03952 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS 03953 * @retval State of bit (1 or 0). 03954 */ 03955 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) 03956 { 03957 return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)); 03958 } 03959 03960 /** 03961 * @brief Check if LSE Clock security system interrupt occurred or not 03962 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS 03963 * @retval State of bit (1 or 0). 03964 */ 03965 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) 03966 { 03967 return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)); 03968 } 03969 03970 03971 /** 03972 * @brief Check if RCC flag FW reset is set or not. 03973 * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST 03974 * @retval State of bit (1 or 0). 03975 */ 03976 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void) 03977 { 03978 return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF)); 03979 } 03980 03981 /** 03982 * @brief Check if RCC flag Independent Watchdog reset is set or not. 03983 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST 03984 * @retval State of bit (1 or 0). 03985 */ 03986 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) 03987 { 03988 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); 03989 } 03990 03991 /** 03992 * @brief Check if RCC flag Low Power reset is set or not. 03993 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST 03994 * @retval State of bit (1 or 0). 03995 */ 03996 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) 03997 { 03998 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); 03999 } 04000 04001 /** 04002 * @brief Check if RCC flag is set or not. 04003 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST 04004 * @retval State of bit (1 or 0). 04005 */ 04006 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) 04007 { 04008 return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); 04009 } 04010 04011 /** 04012 * @brief Check if RCC flag Pin reset is set or not. 04013 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST 04014 * @retval State of bit (1 or 0). 04015 */ 04016 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) 04017 { 04018 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); 04019 } 04020 04021 /** 04022 * @brief Check if RCC flag Software reset is set or not. 04023 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST 04024 * @retval State of bit (1 or 0). 04025 */ 04026 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) 04027 { 04028 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); 04029 } 04030 04031 /** 04032 * @brief Check if RCC flag Window Watchdog reset is set or not. 04033 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST 04034 * @retval State of bit (1 or 0). 04035 */ 04036 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) 04037 { 04038 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); 04039 } 04040 04041 /** 04042 * @brief Check if RCC flag BOR reset is set or not. 04043 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST 04044 * @retval State of bit (1 or 0). 04045 */ 04046 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) 04047 { 04048 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); 04049 } 04050 04051 /** 04052 * @brief Set RMVF bit to clear the reset flags. 04053 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags 04054 * @retval None 04055 */ 04056 __STATIC_INLINE void LL_RCC_ClearResetFlags(void) 04057 { 04058 SET_BIT(RCC->CSR, RCC_CSR_RMVF); 04059 } 04060 04061 /** 04062 * @} 04063 */ 04064 04065 /** @defgroup RCC_LL_EF_IT_Management IT Management 04066 * @{ 04067 */ 04068 04069 /** 04070 * @brief Enable LSI ready interrupt 04071 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY 04072 * @retval None 04073 */ 04074 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) 04075 { 04076 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); 04077 } 04078 04079 /** 04080 * @brief Enable LSE ready interrupt 04081 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY 04082 * @retval None 04083 */ 04084 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) 04085 { 04086 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); 04087 } 04088 04089 /** 04090 * @brief Enable MSI ready interrupt 04091 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY 04092 * @retval None 04093 */ 04094 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) 04095 { 04096 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); 04097 } 04098 04099 /** 04100 * @brief Enable HSI ready interrupt 04101 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY 04102 * @retval None 04103 */ 04104 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) 04105 { 04106 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); 04107 } 04108 04109 /** 04110 * @brief Enable HSE ready interrupt 04111 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY 04112 * @retval None 04113 */ 04114 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) 04115 { 04116 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); 04117 } 04118 04119 /** 04120 * @brief Enable PLL ready interrupt 04121 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY 04122 * @retval None 04123 */ 04124 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) 04125 { 04126 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); 04127 } 04128 04129 #if defined(RCC_HSI48_SUPPORT) 04130 /** 04131 * @brief Enable HSI48 ready interrupt 04132 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY 04133 * @retval None 04134 */ 04135 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) 04136 { 04137 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); 04138 } 04139 #endif /* RCC_HSI48_SUPPORT */ 04140 04141 /** 04142 * @brief Enable PLLSAI1 ready interrupt 04143 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY 04144 * @retval None 04145 */ 04146 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void) 04147 { 04148 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); 04149 } 04150 04151 #if defined(RCC_PLLSAI2_SUPPORT) 04152 /** 04153 * @brief Enable PLLSAI2 ready interrupt 04154 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY 04155 * @retval None 04156 */ 04157 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void) 04158 { 04159 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE); 04160 } 04161 04162 #endif /* RCC_PLLSAI2_SUPPORT */ 04163 /** 04164 * @brief Enable LSE clock security system interrupt 04165 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS 04166 * @retval None 04167 */ 04168 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) 04169 { 04170 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); 04171 } 04172 04173 /** 04174 * @brief Disable LSI ready interrupt 04175 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY 04176 * @retval None 04177 */ 04178 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) 04179 { 04180 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); 04181 } 04182 04183 /** 04184 * @brief Disable LSE ready interrupt 04185 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY 04186 * @retval None 04187 */ 04188 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) 04189 { 04190 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); 04191 } 04192 04193 /** 04194 * @brief Disable MSI ready interrupt 04195 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY 04196 * @retval None 04197 */ 04198 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) 04199 { 04200 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); 04201 } 04202 04203 /** 04204 * @brief Disable HSI ready interrupt 04205 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY 04206 * @retval None 04207 */ 04208 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) 04209 { 04210 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); 04211 } 04212 04213 /** 04214 * @brief Disable HSE ready interrupt 04215 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY 04216 * @retval None 04217 */ 04218 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) 04219 { 04220 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); 04221 } 04222 04223 /** 04224 * @brief Disable PLL ready interrupt 04225 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY 04226 * @retval None 04227 */ 04228 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) 04229 { 04230 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); 04231 } 04232 04233 #if defined(RCC_HSI48_SUPPORT) 04234 /** 04235 * @brief Disable HSI48 ready interrupt 04236 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY 04237 * @retval None 04238 */ 04239 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) 04240 { 04241 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); 04242 } 04243 #endif /* RCC_HSI48_SUPPORT */ 04244 04245 /** 04246 * @brief Disable PLLSAI1 ready interrupt 04247 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY 04248 * @retval None 04249 */ 04250 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void) 04251 { 04252 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); 04253 } 04254 04255 #if defined(RCC_PLLSAI2_SUPPORT) 04256 /** 04257 * @brief Disable PLLSAI2 ready interrupt 04258 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY 04259 * @retval None 04260 */ 04261 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void) 04262 { 04263 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE); 04264 } 04265 04266 #endif /* RCC_PLLSAI2_SUPPORT */ 04267 /** 04268 * @brief Disable LSE clock security system interrupt 04269 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS 04270 * @retval None 04271 */ 04272 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) 04273 { 04274 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); 04275 } 04276 04277 /** 04278 * @brief Checks if LSI ready interrupt source is enabled or disabled. 04279 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY 04280 * @retval State of bit (1 or 0). 04281 */ 04282 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) 04283 { 04284 return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)); 04285 } 04286 04287 /** 04288 * @brief Checks if LSE ready interrupt source is enabled or disabled. 04289 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY 04290 * @retval State of bit (1 or 0). 04291 */ 04292 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) 04293 { 04294 return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)); 04295 } 04296 04297 /** 04298 * @brief Checks if MSI ready interrupt source is enabled or disabled. 04299 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY 04300 * @retval State of bit (1 or 0). 04301 */ 04302 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) 04303 { 04304 return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)); 04305 } 04306 04307 /** 04308 * @brief Checks if HSI ready interrupt source is enabled or disabled. 04309 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY 04310 * @retval State of bit (1 or 0). 04311 */ 04312 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) 04313 { 04314 return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)); 04315 } 04316 04317 /** 04318 * @brief Checks if HSE ready interrupt source is enabled or disabled. 04319 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY 04320 * @retval State of bit (1 or 0). 04321 */ 04322 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) 04323 { 04324 return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)); 04325 } 04326 04327 /** 04328 * @brief Checks if PLL ready interrupt source is enabled or disabled. 04329 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY 04330 * @retval State of bit (1 or 0). 04331 */ 04332 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) 04333 { 04334 return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)); 04335 } 04336 04337 #if defined(RCC_HSI48_SUPPORT) 04338 /** 04339 * @brief Checks if HSI48 ready interrupt source is enabled or disabled. 04340 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY 04341 * @retval State of bit (1 or 0). 04342 */ 04343 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) 04344 { 04345 return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)); 04346 } 04347 #endif /* RCC_HSI48_SUPPORT */ 04348 04349 /** 04350 * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled. 04351 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY 04352 * @retval State of bit (1 or 0). 04353 */ 04354 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void) 04355 { 04356 return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE)); 04357 } 04358 04359 #if defined(RCC_PLLSAI2_SUPPORT) 04360 /** 04361 * @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled. 04362 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY 04363 * @retval State of bit (1 or 0). 04364 */ 04365 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void) 04366 { 04367 return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE)); 04368 } 04369 04370 #endif /* RCC_PLLSAI2_SUPPORT */ 04371 /** 04372 * @brief Checks if LSECSS interrupt source is enabled or disabled. 04373 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS 04374 * @retval State of bit (1 or 0). 04375 */ 04376 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) 04377 { 04378 return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)); 04379 } 04380 04381 /** 04382 * @} 04383 */ 04384 04385 #if defined(USE_FULL_LL_DRIVER) 04386 /** @defgroup RCC_LL_EF_Init De-initialization function 04387 * @{ 04388 */ 04389 ErrorStatus LL_RCC_DeInit(void); 04390 /** 04391 * @} 04392 */ 04393 04394 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions 04395 * @{ 04396 */ 04397 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); 04398 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); 04399 #if defined(UART4) || defined(UART5) 04400 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); 04401 #endif /* UART4 || UART5 */ 04402 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); 04403 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); 04404 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); 04405 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); 04406 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); 04407 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); 04408 #if defined(USB_OTG_FS) || defined(USB) 04409 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); 04410 #endif /* USB_OTG_FS || USB */ 04411 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); 04412 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource); 04413 #if defined(DFSDM1_Channel0) 04414 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); 04415 #endif /* DFSDM1_Channel0 */ 04416 /** 04417 * @} 04418 */ 04419 #endif /* USE_FULL_LL_DRIVER */ 04420 04421 /** 04422 * @} 04423 */ 04424 04425 /** 04426 * @} 04427 */ 04428 04429 #endif /* defined(RCC) */ 04430 04431 /** 04432 * @} 04433 */ 04434 04435 #ifdef __cplusplus 04436 } 04437 #endif 04438 04439 #endif /* __STM32L4xx_LL_RCC_H */ 04440 04441 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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