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stm32l4xx_ll_pwr.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_pwr.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of PWR LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_PWR_H 00040 #define __STM32L4xx_LL_PWR_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined(PWR) 00054 00055 /** @defgroup PWR_LL PWR 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 00062 /* Private constants ---------------------------------------------------------*/ 00063 00064 /* Private macros ------------------------------------------------------------*/ 00065 00066 /* Exported types ------------------------------------------------------------*/ 00067 /* Exported constants --------------------------------------------------------*/ 00068 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants 00069 * @{ 00070 */ 00071 00072 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines 00073 * @brief Flags defines which can be used with LL_PWR_WriteReg function 00074 * @{ 00075 */ 00076 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF 00077 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF 00078 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 00079 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 00080 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 00081 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 00082 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 00083 /** 00084 * @} 00085 */ 00086 00087 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines 00088 * @brief Flags defines which can be used with LL_PWR_ReadReg function 00089 * @{ 00090 */ 00091 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI 00092 #define LL_PWR_SR1_SBF PWR_SR1_SBF 00093 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 00094 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 00095 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 00096 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 00097 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 00098 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4 00099 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3 00100 #if defined(PWR_SR2_PVMO2) 00101 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2 00102 #endif /* PWR_SR2_PVMO2 */ 00103 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1 00104 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO 00105 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF 00106 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF 00107 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS 00108 /** 00109 * @} 00110 */ 00111 00112 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE 00113 * @{ 00114 */ 00115 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) 00116 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) 00117 /** 00118 * @} 00119 */ 00120 00121 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR 00122 * @{ 00123 */ 00124 #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0) 00125 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1) 00126 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2) 00127 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY) 00128 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN) 00129 /** 00130 * @} 00131 */ 00132 00133 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 PVM VDDUSB 1 00134 * @{ 00135 */ 00136 #if defined(USB_OTG_FS) 00137 #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */ 00138 #endif /* USB_OTG_FS */ 00139 #if defined(PWR_CR2_PVME2) 00140 #define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */ 00141 #endif /* PWR_CR2_PVME2 */ 00142 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */ 00143 #define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */ 00144 /** 00145 * @} 00146 */ 00147 00148 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL 00149 * @{ 00150 */ 00151 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */ 00152 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */ 00153 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */ 00154 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */ 00155 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */ 00156 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */ 00157 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */ 00158 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */ 00159 /** 00160 * @} 00161 */ 00162 00163 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP 00164 * @{ 00165 */ 00166 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) 00167 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) 00168 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) 00169 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) 00170 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) 00171 /** 00172 * @} 00173 */ 00174 00175 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR 00176 * @{ 00177 */ 00178 #define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000) 00179 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS) 00180 /** 00181 * @} 00182 */ 00183 00184 /** @defgroup PWR_LL_EC_GPIO GPIO 00185 * @{ 00186 */ 00187 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA))) 00188 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) 00189 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) 00190 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) 00191 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE))) 00192 #if defined(GPIOF) 00193 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) 00194 #endif /* GPIOF */ 00195 #if defined(GPIOG) 00196 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG))) 00197 #endif /* GPIOG */ 00198 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH))) 00199 /** 00200 * @} 00201 */ 00202 00203 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT 00204 * @{ 00205 */ 00206 #define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001) 00207 #define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002) 00208 #define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004) 00209 #define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008) 00210 #define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010) 00211 #define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020) 00212 #define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040) 00213 #define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080) 00214 #define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100) 00215 #define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200) 00216 #define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400) 00217 #define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800) 00218 #define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000) 00219 #define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000) 00220 #define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000) 00221 #define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000) 00222 /** 00223 * @} 00224 */ 00225 00226 /** 00227 * @} 00228 */ 00229 00230 /* Exported macro ------------------------------------------------------------*/ 00231 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros 00232 * @{ 00233 */ 00234 00235 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros 00236 * @{ 00237 */ 00238 00239 /** 00240 * @brief Write a value in PWR register 00241 * @param __REG__ Register to be written 00242 * @param __VALUE__ Value to be written in the register 00243 * @retval None 00244 */ 00245 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) 00246 00247 /** 00248 * @brief Read a value in PWR register 00249 * @param __REG__ Register to be read 00250 * @retval Register value 00251 */ 00252 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) 00253 /** 00254 * @} 00255 */ 00256 00257 /** 00258 * @} 00259 */ 00260 00261 00262 /* Exported functions --------------------------------------------------------*/ 00263 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions 00264 * @{ 00265 */ 00266 00267 /** @defgroup PWR_LL_EF_Configuration Configuration 00268 * @{ 00269 */ 00270 00271 /** 00272 * @brief Switch the regulator from main mode to low-power mode 00273 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode 00274 * @retval None 00275 */ 00276 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) 00277 { 00278 SET_BIT(PWR->CR1, PWR_CR1_LPR); 00279 } 00280 00281 /** 00282 * @brief Switch the regulator from low-power mode to main mode 00283 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode 00284 * @retval None 00285 */ 00286 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) 00287 { 00288 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); 00289 } 00290 00291 /** 00292 * @brief Check if the regulator is in low-power mode 00293 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode 00294 * @retval State of bit (1 or 0). 00295 */ 00296 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) 00297 { 00298 return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); 00299 } 00300 00301 /** 00302 * @brief Switch from run main mode to run low-power mode. 00303 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode 00304 * @retval None 00305 */ 00306 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) 00307 { 00308 LL_PWR_EnableLowPowerRunMode(); 00309 } 00310 00311 /** 00312 * @brief Switch from run main mode to low-power mode. 00313 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode 00314 * @retval None 00315 */ 00316 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) 00317 { 00318 LL_PWR_DisableLowPowerRunMode(); 00319 } 00320 00321 /** 00322 * @brief Set the main internal regulator output voltage 00323 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling 00324 * @param VoltageScaling This parameter can be one of the following values: 00325 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 00326 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 00327 * @retval None 00328 */ 00329 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) 00330 { 00331 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); 00332 } 00333 00334 /** 00335 * @brief Get the main internal regulator output voltage 00336 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling 00337 * @retval Returned value can be one of the following values: 00338 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 00339 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 00340 */ 00341 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) 00342 { 00343 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); 00344 } 00345 00346 /** 00347 * @brief Enable access to the backup domain 00348 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess 00349 * @retval None 00350 */ 00351 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) 00352 { 00353 SET_BIT(PWR->CR1, PWR_CR1_DBP); 00354 } 00355 00356 /** 00357 * @brief Disable access to the backup domain 00358 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess 00359 * @retval None 00360 */ 00361 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) 00362 { 00363 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); 00364 } 00365 00366 /** 00367 * @brief Check if the backup domain is enabled 00368 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess 00369 * @retval State of bit (1 or 0). 00370 */ 00371 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) 00372 { 00373 return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)); 00374 } 00375 00376 /** 00377 * @brief Set Low-Power mode 00378 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode 00379 * @param LowPowerMode This parameter can be one of the following values: 00380 * @arg @ref LL_PWR_MODE_STOP0 00381 * @arg @ref LL_PWR_MODE_STOP1 00382 * @arg @ref LL_PWR_MODE_STOP2 00383 * @arg @ref LL_PWR_MODE_STANDBY 00384 * @arg @ref LL_PWR_MODE_SHUTDOWN 00385 * @retval None 00386 */ 00387 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) 00388 { 00389 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); 00390 } 00391 00392 /** 00393 * @brief Get Low-Power mode 00394 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode 00395 * @retval Returned value can be one of the following values: 00396 * @arg @ref LL_PWR_MODE_STOP0 00397 * @arg @ref LL_PWR_MODE_STOP1 00398 * @arg @ref LL_PWR_MODE_STOP2 00399 * @arg @ref LL_PWR_MODE_STANDBY 00400 * @arg @ref LL_PWR_MODE_SHUTDOWN 00401 */ 00402 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) 00403 { 00404 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); 00405 } 00406 00407 #if defined(USB_OTG_FS) 00408 /** 00409 * @brief Enable VDDUSB supply 00410 * @rmtoll CR2 USV LL_PWR_EnableVddUSB 00411 * @retval None 00412 */ 00413 __STATIC_INLINE void LL_PWR_EnableVddUSB(void) 00414 { 00415 SET_BIT(PWR->CR2, PWR_CR2_USV); 00416 } 00417 #endif /* USB_OTG_FS */ 00418 00419 #if defined(USB_OTG_FS) 00420 /** 00421 * @brief Disable VDDUSB supply 00422 * @rmtoll CR2 USV LL_PWR_DisableVddUSB 00423 * @retval None 00424 */ 00425 __STATIC_INLINE void LL_PWR_DisableVddUSB(void) 00426 { 00427 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); 00428 } 00429 #endif /* USB_OTG_FS */ 00430 00431 #if defined(USB_OTG_FS) 00432 /** 00433 * @brief Check if VDDUSB supply is enabled 00434 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB 00435 * @retval State of bit (1 or 0). 00436 */ 00437 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) 00438 { 00439 return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)); 00440 } 00441 #endif /* USB_OTG_FS */ 00442 00443 #if defined(PWR_CR2_IOSV) 00444 /** 00445 * @brief Enable VDDIO2 supply 00446 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2 00447 * @retval None 00448 */ 00449 __STATIC_INLINE void LL_PWR_EnableVddIO2(void) 00450 { 00451 SET_BIT(PWR->CR2, PWR_CR2_IOSV); 00452 } 00453 00454 /** 00455 * @brief Disable VDDIO2 supply 00456 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2 00457 * @retval None 00458 */ 00459 __STATIC_INLINE void LL_PWR_DisableVddIO2(void) 00460 { 00461 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); 00462 } 00463 00464 /** 00465 * @brief Check if VDDIO2 supply is enabled 00466 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2 00467 * @retval State of bit (1 or 0). 00468 */ 00469 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) 00470 { 00471 return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)); 00472 } 00473 #endif /* PWR_CR2_IOSV */ 00474 00475 /** 00476 * @brief Enable the Power Voltage Monitoring on a peripheral 00477 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n 00478 * CR2 PVME2 LL_PWR_EnablePVM\n 00479 * CR2 PVME3 LL_PWR_EnablePVM\n 00480 * CR2 PVME4 LL_PWR_EnablePVM 00481 * @param PeriphVoltage This parameter can be one of the following values: 00482 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00483 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) 00484 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00485 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00486 * 00487 * (*) value not defined in all devices 00488 * @retval None 00489 */ 00490 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) 00491 { 00492 SET_BIT(PWR->CR2, PeriphVoltage); 00493 } 00494 00495 /** 00496 * @brief Disable the Power Voltage Monitoring on a peripheral 00497 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n 00498 * CR2 PVME2 LL_PWR_DisablePVM\n 00499 * CR2 PVME3 LL_PWR_DisablePVM\n 00500 * CR2 PVME4 LL_PWR_DisablePVM 00501 * @param PeriphVoltage This parameter can be one of the following values: 00502 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00503 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) 00504 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00505 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00506 * 00507 * (*) value not defined in all devices 00508 * @retval None 00509 */ 00510 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) 00511 { 00512 CLEAR_BIT(PWR->CR2, PeriphVoltage); 00513 } 00514 00515 /** 00516 * @brief Check if Power Voltage Monitoring is enabled on a peripheral 00517 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n 00518 * CR2 PVME2 LL_PWR_IsEnabledPVM\n 00519 * CR2 PVME3 LL_PWR_IsEnabledPVM\n 00520 * CR2 PVME4 LL_PWR_IsEnabledPVM 00521 * @param PeriphVoltage This parameter can be one of the following values: 00522 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00523 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) 00524 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00525 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00526 * 00527 * (*) value not defined in all devices 00528 * @retval State of bit (1 or 0). 00529 */ 00530 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) 00531 { 00532 return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)); 00533 } 00534 00535 /** 00536 * @brief Configure the voltage threshold detected by the Power Voltage Detector 00537 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel 00538 * @param PVDLevel This parameter can be one of the following values: 00539 * @arg @ref LL_PWR_PVDLEVEL_0 00540 * @arg @ref LL_PWR_PVDLEVEL_1 00541 * @arg @ref LL_PWR_PVDLEVEL_2 00542 * @arg @ref LL_PWR_PVDLEVEL_3 00543 * @arg @ref LL_PWR_PVDLEVEL_4 00544 * @arg @ref LL_PWR_PVDLEVEL_5 00545 * @arg @ref LL_PWR_PVDLEVEL_6 00546 * @arg @ref LL_PWR_PVDLEVEL_7 00547 * @retval None 00548 */ 00549 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) 00550 { 00551 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); 00552 } 00553 00554 /** 00555 * @brief Get the voltage threshold detection 00556 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel 00557 * @retval Returned value can be one of the following values: 00558 * @arg @ref LL_PWR_PVDLEVEL_0 00559 * @arg @ref LL_PWR_PVDLEVEL_1 00560 * @arg @ref LL_PWR_PVDLEVEL_2 00561 * @arg @ref LL_PWR_PVDLEVEL_3 00562 * @arg @ref LL_PWR_PVDLEVEL_4 00563 * @arg @ref LL_PWR_PVDLEVEL_5 00564 * @arg @ref LL_PWR_PVDLEVEL_6 00565 * @arg @ref LL_PWR_PVDLEVEL_7 00566 */ 00567 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) 00568 { 00569 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); 00570 } 00571 00572 /** 00573 * @brief Enable Power Voltage Detector 00574 * @rmtoll CR2 PVDE LL_PWR_EnablePVD 00575 * @retval None 00576 */ 00577 __STATIC_INLINE void LL_PWR_EnablePVD(void) 00578 { 00579 SET_BIT(PWR->CR2, PWR_CR2_PVDE); 00580 } 00581 00582 /** 00583 * @brief Disable Power Voltage Detector 00584 * @rmtoll CR2 PVDE LL_PWR_DisablePVD 00585 * @retval None 00586 */ 00587 __STATIC_INLINE void LL_PWR_DisablePVD(void) 00588 { 00589 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); 00590 } 00591 00592 /** 00593 * @brief Check if Power Voltage Detector is enabled 00594 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD 00595 * @retval State of bit (1 or 0). 00596 */ 00597 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) 00598 { 00599 return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)); 00600 } 00601 00602 /** 00603 * @brief Enable Internal Wake-up line 00604 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU 00605 * @retval None 00606 */ 00607 __STATIC_INLINE void LL_PWR_EnableInternWU(void) 00608 { 00609 SET_BIT(PWR->CR3, PWR_CR3_EIWF); 00610 } 00611 00612 /** 00613 * @brief Disable Internal Wake-up line 00614 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU 00615 * @retval None 00616 */ 00617 __STATIC_INLINE void LL_PWR_DisableInternWU(void) 00618 { 00619 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); 00620 } 00621 00622 /** 00623 * @brief Check if Internal Wake-up line is enabled 00624 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU 00625 * @retval State of bit (1 or 0). 00626 */ 00627 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) 00628 { 00629 return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)); 00630 } 00631 00632 /** 00633 * @brief Enable pull-up and pull-down configuration 00634 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg 00635 * @retval None 00636 */ 00637 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) 00638 { 00639 SET_BIT(PWR->CR3, PWR_CR3_APC); 00640 } 00641 00642 /** 00643 * @brief Disable pull-up and pull-down configuration 00644 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg 00645 * @retval None 00646 */ 00647 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) 00648 { 00649 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); 00650 } 00651 00652 /** 00653 * @brief Check if pull-up and pull-down configuration is enabled 00654 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg 00655 * @retval State of bit (1 or 0). 00656 */ 00657 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) 00658 { 00659 return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)); 00660 } 00661 00662 /** 00663 * @brief Enable SRAM2 content retention in Standby mode 00664 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention 00665 * @retval None 00666 */ 00667 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) 00668 { 00669 SET_BIT(PWR->CR3, PWR_CR3_RRS); 00670 } 00671 00672 /** 00673 * @brief Disable SRAM2 content retention in Standby mode 00674 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention 00675 * @retval None 00676 */ 00677 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) 00678 { 00679 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); 00680 } 00681 00682 /** 00683 * @brief Check if SRAM2 content retention in Standby mode is enabled 00684 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention 00685 * @retval State of bit (1 or 0). 00686 */ 00687 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) 00688 { 00689 return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)); 00690 } 00691 00692 /** 00693 * @brief Enable the WakeUp PINx functionality 00694 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n 00695 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n 00696 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n 00697 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n 00698 * CR3 EWUP5 LL_PWR_EnableWakeUpPin 00699 * @param WakeUpPin This parameter can be one of the following values: 00700 * @arg @ref LL_PWR_WAKEUP_PIN1 00701 * @arg @ref LL_PWR_WAKEUP_PIN2 00702 * @arg @ref LL_PWR_WAKEUP_PIN3 00703 * @arg @ref LL_PWR_WAKEUP_PIN4 00704 * @arg @ref LL_PWR_WAKEUP_PIN5 00705 * @retval None 00706 */ 00707 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) 00708 { 00709 SET_BIT(PWR->CR3, WakeUpPin); 00710 } 00711 00712 /** 00713 * @brief Disable the WakeUp PINx functionality 00714 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n 00715 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n 00716 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n 00717 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n 00718 * CR3 EWUP5 LL_PWR_DisableWakeUpPin 00719 * @param WakeUpPin This parameter can be one of the following values: 00720 * @arg @ref LL_PWR_WAKEUP_PIN1 00721 * @arg @ref LL_PWR_WAKEUP_PIN2 00722 * @arg @ref LL_PWR_WAKEUP_PIN3 00723 * @arg @ref LL_PWR_WAKEUP_PIN4 00724 * @arg @ref LL_PWR_WAKEUP_PIN5 00725 * @retval None 00726 */ 00727 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) 00728 { 00729 CLEAR_BIT(PWR->CR3, WakeUpPin); 00730 } 00731 00732 /** 00733 * @brief Check if the WakeUp PINx functionality is enabled 00734 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n 00735 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n 00736 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n 00737 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n 00738 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin 00739 * @param WakeUpPin This parameter can be one of the following values: 00740 * @arg @ref LL_PWR_WAKEUP_PIN1 00741 * @arg @ref LL_PWR_WAKEUP_PIN2 00742 * @arg @ref LL_PWR_WAKEUP_PIN3 00743 * @arg @ref LL_PWR_WAKEUP_PIN4 00744 * @arg @ref LL_PWR_WAKEUP_PIN5 00745 * @retval State of bit (1 or 0). 00746 */ 00747 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) 00748 { 00749 return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)); 00750 } 00751 00752 /** 00753 * @brief Set the resistor impedance 00754 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor 00755 * @param Resistor This parameter can be one of the following values: 00756 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 00757 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 00758 * @retval None 00759 */ 00760 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) 00761 { 00762 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); 00763 } 00764 00765 /** 00766 * @brief Get the resistor impedance 00767 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor 00768 * @retval Returned value can be one of the following values: 00769 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 00770 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 00771 */ 00772 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) 00773 { 00774 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); 00775 } 00776 00777 /** 00778 * @brief Enable battery charging 00779 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging 00780 * @retval None 00781 */ 00782 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) 00783 { 00784 SET_BIT(PWR->CR4, PWR_CR4_VBE); 00785 } 00786 00787 /** 00788 * @brief Disable battery charging 00789 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging 00790 * @retval None 00791 */ 00792 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) 00793 { 00794 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); 00795 } 00796 00797 /** 00798 * @brief Check if battery charging is enabled 00799 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging 00800 * @retval State of bit (1 or 0). 00801 */ 00802 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) 00803 { 00804 return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)); 00805 } 00806 00807 /** 00808 * @brief Set the Wake-Up pin polarity low for the event detection 00809 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n 00810 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n 00811 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n 00812 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n 00813 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow 00814 * @param WakeUpPin This parameter can be one of the following values: 00815 * @arg @ref LL_PWR_WAKEUP_PIN1 00816 * @arg @ref LL_PWR_WAKEUP_PIN2 00817 * @arg @ref LL_PWR_WAKEUP_PIN3 00818 * @arg @ref LL_PWR_WAKEUP_PIN4 00819 * @arg @ref LL_PWR_WAKEUP_PIN5 00820 * @retval None 00821 */ 00822 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) 00823 { 00824 SET_BIT(PWR->CR4, WakeUpPin); 00825 } 00826 00827 /** 00828 * @brief Set the Wake-Up pin polarity high for the event detection 00829 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n 00830 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n 00831 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n 00832 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n 00833 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh 00834 * @param WakeUpPin This parameter can be one of the following values: 00835 * @arg @ref LL_PWR_WAKEUP_PIN1 00836 * @arg @ref LL_PWR_WAKEUP_PIN2 00837 * @arg @ref LL_PWR_WAKEUP_PIN3 00838 * @arg @ref LL_PWR_WAKEUP_PIN4 00839 * @arg @ref LL_PWR_WAKEUP_PIN5 00840 * @retval None 00841 */ 00842 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) 00843 { 00844 CLEAR_BIT(PWR->CR4, WakeUpPin); 00845 } 00846 00847 /** 00848 * @brief Get the Wake-Up pin polarity for the event detection 00849 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n 00850 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n 00851 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n 00852 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n 00853 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow 00854 * @param WakeUpPin This parameter can be one of the following values: 00855 * @arg @ref LL_PWR_WAKEUP_PIN1 00856 * @arg @ref LL_PWR_WAKEUP_PIN2 00857 * @arg @ref LL_PWR_WAKEUP_PIN3 00858 * @arg @ref LL_PWR_WAKEUP_PIN4 00859 * @arg @ref LL_PWR_WAKEUP_PIN5 00860 * @retval State of bit (1 or 0). 00861 */ 00862 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) 00863 { 00864 return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)); 00865 } 00866 00867 /** 00868 * @brief Enable GPIO pull-up state in Standby and Shutdown modes 00869 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n 00870 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n 00871 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n 00872 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n 00873 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n 00874 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n 00875 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n 00876 * PUCRH PU0-1 LL_PWR_EnableGPIOPullUp 00877 * @param GPIO This parameter can be one of the following values: 00878 * @arg @ref LL_PWR_GPIO_A 00879 * @arg @ref LL_PWR_GPIO_B 00880 * @arg @ref LL_PWR_GPIO_C 00881 * @arg @ref LL_PWR_GPIO_D 00882 * @arg @ref LL_PWR_GPIO_E 00883 * @arg @ref LL_PWR_GPIO_F (*) 00884 * @arg @ref LL_PWR_GPIO_G (*) 00885 * @arg @ref LL_PWR_GPIO_H 00886 * 00887 * (*) value not defined in all devices 00888 * @param GPIONumber This parameter can be one of the following values: 00889 * @arg @ref LL_PWR_GPIO_BIT_0 00890 * @arg @ref LL_PWR_GPIO_BIT_1 00891 * @arg @ref LL_PWR_GPIO_BIT_2 00892 * @arg @ref LL_PWR_GPIO_BIT_3 00893 * @arg @ref LL_PWR_GPIO_BIT_4 00894 * @arg @ref LL_PWR_GPIO_BIT_5 00895 * @arg @ref LL_PWR_GPIO_BIT_6 00896 * @arg @ref LL_PWR_GPIO_BIT_7 00897 * @arg @ref LL_PWR_GPIO_BIT_8 00898 * @arg @ref LL_PWR_GPIO_BIT_9 00899 * @arg @ref LL_PWR_GPIO_BIT_10 00900 * @arg @ref LL_PWR_GPIO_BIT_11 00901 * @arg @ref LL_PWR_GPIO_BIT_12 00902 * @arg @ref LL_PWR_GPIO_BIT_13 00903 * @arg @ref LL_PWR_GPIO_BIT_14 00904 * @arg @ref LL_PWR_GPIO_BIT_15 00905 * @retval None 00906 */ 00907 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00908 { 00909 SET_BIT(*((uint32_t *)GPIO), GPIONumber); 00910 } 00911 00912 /** 00913 * @brief Disable GPIO pull-up state in Standby and Shutdown modes 00914 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n 00915 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n 00916 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n 00917 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n 00918 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n 00919 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n 00920 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n 00921 * PUCRH PU0-1 LL_PWR_DisableGPIOPullUp 00922 * @param GPIO This parameter can be one of the following values: 00923 * @arg @ref LL_PWR_GPIO_A 00924 * @arg @ref LL_PWR_GPIO_B 00925 * @arg @ref LL_PWR_GPIO_C 00926 * @arg @ref LL_PWR_GPIO_D 00927 * @arg @ref LL_PWR_GPIO_E 00928 * @arg @ref LL_PWR_GPIO_F (*) 00929 * @arg @ref LL_PWR_GPIO_G (*) 00930 * @arg @ref LL_PWR_GPIO_H 00931 * 00932 * (*) value not defined in all devices 00933 * @param GPIONumber This parameter can be one of the following values: 00934 * @arg @ref LL_PWR_GPIO_BIT_0 00935 * @arg @ref LL_PWR_GPIO_BIT_1 00936 * @arg @ref LL_PWR_GPIO_BIT_2 00937 * @arg @ref LL_PWR_GPIO_BIT_3 00938 * @arg @ref LL_PWR_GPIO_BIT_4 00939 * @arg @ref LL_PWR_GPIO_BIT_5 00940 * @arg @ref LL_PWR_GPIO_BIT_6 00941 * @arg @ref LL_PWR_GPIO_BIT_7 00942 * @arg @ref LL_PWR_GPIO_BIT_8 00943 * @arg @ref LL_PWR_GPIO_BIT_9 00944 * @arg @ref LL_PWR_GPIO_BIT_10 00945 * @arg @ref LL_PWR_GPIO_BIT_11 00946 * @arg @ref LL_PWR_GPIO_BIT_12 00947 * @arg @ref LL_PWR_GPIO_BIT_13 00948 * @arg @ref LL_PWR_GPIO_BIT_14 00949 * @arg @ref LL_PWR_GPIO_BIT_15 00950 * @retval None 00951 */ 00952 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00953 { 00954 CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber); 00955 } 00956 00957 /** 00958 * @brief Check if GPIO pull-up state is enabled 00959 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00960 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00961 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00962 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00963 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00964 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00965 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 00966 * PUCRH PU0-1 LL_PWR_IsEnabledGPIOPullUp 00967 * @param GPIO This parameter can be one of the following values: 00968 * @arg @ref LL_PWR_GPIO_A 00969 * @arg @ref LL_PWR_GPIO_B 00970 * @arg @ref LL_PWR_GPIO_C 00971 * @arg @ref LL_PWR_GPIO_D 00972 * @arg @ref LL_PWR_GPIO_E 00973 * @arg @ref LL_PWR_GPIO_F (*) 00974 * @arg @ref LL_PWR_GPIO_G (*) 00975 * @arg @ref LL_PWR_GPIO_H 00976 * 00977 * (*) value not defined in all devices 00978 * @param GPIONumber This parameter can be one of the following values: 00979 * @arg @ref LL_PWR_GPIO_BIT_0 00980 * @arg @ref LL_PWR_GPIO_BIT_1 00981 * @arg @ref LL_PWR_GPIO_BIT_2 00982 * @arg @ref LL_PWR_GPIO_BIT_3 00983 * @arg @ref LL_PWR_GPIO_BIT_4 00984 * @arg @ref LL_PWR_GPIO_BIT_5 00985 * @arg @ref LL_PWR_GPIO_BIT_6 00986 * @arg @ref LL_PWR_GPIO_BIT_7 00987 * @arg @ref LL_PWR_GPIO_BIT_8 00988 * @arg @ref LL_PWR_GPIO_BIT_9 00989 * @arg @ref LL_PWR_GPIO_BIT_10 00990 * @arg @ref LL_PWR_GPIO_BIT_11 00991 * @arg @ref LL_PWR_GPIO_BIT_12 00992 * @arg @ref LL_PWR_GPIO_BIT_13 00993 * @arg @ref LL_PWR_GPIO_BIT_14 00994 * @arg @ref LL_PWR_GPIO_BIT_15 00995 * @retval State of bit (1 or 0). 00996 */ 00997 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00998 { 00999 return (READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)); 01000 } 01001 01002 /** 01003 * @brief Enable GPIO pull-down state in Standby and Shutdown modes 01004 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n 01005 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n 01006 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n 01007 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n 01008 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n 01009 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n 01010 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n 01011 * PDCRH PD0-1 LL_PWR_EnableGPIOPullDown 01012 * @param GPIO This parameter can be one of the following values: 01013 * @arg @ref LL_PWR_GPIO_A 01014 * @arg @ref LL_PWR_GPIO_B 01015 * @arg @ref LL_PWR_GPIO_C 01016 * @arg @ref LL_PWR_GPIO_D 01017 * @arg @ref LL_PWR_GPIO_E 01018 * @arg @ref LL_PWR_GPIO_F (*) 01019 * @arg @ref LL_PWR_GPIO_G (*) 01020 * @arg @ref LL_PWR_GPIO_H 01021 * 01022 * (*) value not defined in all devices 01023 * @param GPIONumber This parameter can be one of the following values: 01024 * @arg @ref LL_PWR_GPIO_BIT_0 01025 * @arg @ref LL_PWR_GPIO_BIT_1 01026 * @arg @ref LL_PWR_GPIO_BIT_2 01027 * @arg @ref LL_PWR_GPIO_BIT_3 01028 * @arg @ref LL_PWR_GPIO_BIT_4 01029 * @arg @ref LL_PWR_GPIO_BIT_5 01030 * @arg @ref LL_PWR_GPIO_BIT_6 01031 * @arg @ref LL_PWR_GPIO_BIT_7 01032 * @arg @ref LL_PWR_GPIO_BIT_8 01033 * @arg @ref LL_PWR_GPIO_BIT_9 01034 * @arg @ref LL_PWR_GPIO_BIT_10 01035 * @arg @ref LL_PWR_GPIO_BIT_11 01036 * @arg @ref LL_PWR_GPIO_BIT_12 01037 * @arg @ref LL_PWR_GPIO_BIT_13 01038 * @arg @ref LL_PWR_GPIO_BIT_14 01039 * @arg @ref LL_PWR_GPIO_BIT_15 01040 * @retval None 01041 */ 01042 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01043 { 01044 register uint32_t temp = (uint32_t)(GPIO) + 4; 01045 SET_BIT(*((uint32_t *)(temp)), GPIONumber); 01046 } 01047 01048 /** 01049 * @brief Disable GPIO pull-down state in Standby and Shutdown modes 01050 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n 01051 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n 01052 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n 01053 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n 01054 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n 01055 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n 01056 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n 01057 * PDCRH PD0-1 LL_PWR_DisableGPIOPullDown 01058 * @param GPIO This parameter can be one of the following values: 01059 * @arg @ref LL_PWR_GPIO_A 01060 * @arg @ref LL_PWR_GPIO_B 01061 * @arg @ref LL_PWR_GPIO_C 01062 * @arg @ref LL_PWR_GPIO_D 01063 * @arg @ref LL_PWR_GPIO_E 01064 * @arg @ref LL_PWR_GPIO_F (*) 01065 * @arg @ref LL_PWR_GPIO_G (*) 01066 * @arg @ref LL_PWR_GPIO_H 01067 * 01068 * (*) value not defined in all devices 01069 * @param GPIONumber This parameter can be one of the following values: 01070 * @arg @ref LL_PWR_GPIO_BIT_0 01071 * @arg @ref LL_PWR_GPIO_BIT_1 01072 * @arg @ref LL_PWR_GPIO_BIT_2 01073 * @arg @ref LL_PWR_GPIO_BIT_3 01074 * @arg @ref LL_PWR_GPIO_BIT_4 01075 * @arg @ref LL_PWR_GPIO_BIT_5 01076 * @arg @ref LL_PWR_GPIO_BIT_6 01077 * @arg @ref LL_PWR_GPIO_BIT_7 01078 * @arg @ref LL_PWR_GPIO_BIT_8 01079 * @arg @ref LL_PWR_GPIO_BIT_9 01080 * @arg @ref LL_PWR_GPIO_BIT_10 01081 * @arg @ref LL_PWR_GPIO_BIT_11 01082 * @arg @ref LL_PWR_GPIO_BIT_12 01083 * @arg @ref LL_PWR_GPIO_BIT_13 01084 * @arg @ref LL_PWR_GPIO_BIT_14 01085 * @arg @ref LL_PWR_GPIO_BIT_15 01086 * @retval None 01087 */ 01088 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01089 { 01090 register uint32_t temp = (uint32_t)(GPIO) + 4; 01091 CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber); 01092 } 01093 01094 /** 01095 * @brief Check if GPIO pull-down state is enabled 01096 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01097 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01098 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01099 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01100 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01101 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01102 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01103 * PDCRH PD0-1 LL_PWR_IsEnabledGPIOPullDown 01104 * @param GPIO This parameter can be one of the following values: 01105 * @arg @ref LL_PWR_GPIO_A 01106 * @arg @ref LL_PWR_GPIO_B 01107 * @arg @ref LL_PWR_GPIO_C 01108 * @arg @ref LL_PWR_GPIO_D 01109 * @arg @ref LL_PWR_GPIO_E 01110 * @arg @ref LL_PWR_GPIO_F (*) 01111 * @arg @ref LL_PWR_GPIO_G (*) 01112 * @arg @ref LL_PWR_GPIO_H 01113 * 01114 * (*) value not defined in all devices 01115 * @param GPIONumber This parameter can be one of the following values: 01116 * @arg @ref LL_PWR_GPIO_BIT_0 01117 * @arg @ref LL_PWR_GPIO_BIT_1 01118 * @arg @ref LL_PWR_GPIO_BIT_2 01119 * @arg @ref LL_PWR_GPIO_BIT_3 01120 * @arg @ref LL_PWR_GPIO_BIT_4 01121 * @arg @ref LL_PWR_GPIO_BIT_5 01122 * @arg @ref LL_PWR_GPIO_BIT_6 01123 * @arg @ref LL_PWR_GPIO_BIT_7 01124 * @arg @ref LL_PWR_GPIO_BIT_8 01125 * @arg @ref LL_PWR_GPIO_BIT_9 01126 * @arg @ref LL_PWR_GPIO_BIT_10 01127 * @arg @ref LL_PWR_GPIO_BIT_11 01128 * @arg @ref LL_PWR_GPIO_BIT_12 01129 * @arg @ref LL_PWR_GPIO_BIT_13 01130 * @arg @ref LL_PWR_GPIO_BIT_14 01131 * @arg @ref LL_PWR_GPIO_BIT_15 01132 * @retval State of bit (1 or 0). 01133 */ 01134 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01135 { 01136 register uint32_t temp = (uint32_t)(GPIO) + 4; 01137 return (READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)); 01138 } 01139 01140 /** 01141 * @} 01142 */ 01143 01144 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management 01145 * @{ 01146 */ 01147 01148 /** 01149 * @brief Get Internal Wake-up line Flag 01150 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU 01151 * @retval State of bit (1 or 0). 01152 */ 01153 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) 01154 { 01155 return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)); 01156 } 01157 01158 /** 01159 * @brief Get Stand-By Flag 01160 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB 01161 * @retval State of bit (1 or 0). 01162 */ 01163 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) 01164 { 01165 return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)); 01166 } 01167 01168 /** 01169 * @brief Get Wake-up Flag 5 01170 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5 01171 * @retval State of bit (1 or 0). 01172 */ 01173 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) 01174 { 01175 return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)); 01176 } 01177 01178 /** 01179 * @brief Get Wake-up Flag 4 01180 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4 01181 * @retval State of bit (1 or 0). 01182 */ 01183 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) 01184 { 01185 return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)); 01186 } 01187 01188 /** 01189 * @brief Get Wake-up Flag 3 01190 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 01191 * @retval State of bit (1 or 0). 01192 */ 01193 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) 01194 { 01195 return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)); 01196 } 01197 01198 /** 01199 * @brief Get Wake-up Flag 2 01200 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 01201 * @retval State of bit (1 or 0). 01202 */ 01203 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) 01204 { 01205 return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)); 01206 } 01207 01208 /** 01209 * @brief Get Wake-up Flag 1 01210 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1 01211 * @retval State of bit (1 or 0). 01212 */ 01213 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) 01214 { 01215 return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)); 01216 } 01217 01218 /** 01219 * @brief Clear Stand-By Flag 01220 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB 01221 * @retval None 01222 */ 01223 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) 01224 { 01225 WRITE_REG(PWR->SCR, PWR_SCR_CSBF); 01226 } 01227 01228 /** 01229 * @brief Clear Wake-up Flags 01230 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU 01231 * @retval None 01232 */ 01233 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) 01234 { 01235 WRITE_REG(PWR->SCR, PWR_SCR_CWUF); 01236 } 01237 01238 /** 01239 * @brief Clear Wake-up Flag 5 01240 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5 01241 * @retval None 01242 */ 01243 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) 01244 { 01245 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); 01246 } 01247 01248 /** 01249 * @brief Clear Wake-up Flag 4 01250 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4 01251 * @retval None 01252 */ 01253 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) 01254 { 01255 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); 01256 } 01257 01258 /** 01259 * @brief Clear Wake-up Flag 3 01260 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 01261 * @retval None 01262 */ 01263 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) 01264 { 01265 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); 01266 } 01267 01268 /** 01269 * @brief Clear Wake-up Flag 2 01270 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 01271 * @retval None 01272 */ 01273 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) 01274 { 01275 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); 01276 } 01277 01278 /** 01279 * @brief Clear Wake-up Flag 1 01280 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1 01281 * @retval None 01282 */ 01283 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) 01284 { 01285 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); 01286 } 01287 01288 /** 01289 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold 01290 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4 01291 * @retval State of bit (1 or 0). 01292 */ 01293 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) 01294 { 01295 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)); 01296 } 01297 01298 /** 01299 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold 01300 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3 01301 * @retval State of bit (1 or 0). 01302 */ 01303 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) 01304 { 01305 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)); 01306 } 01307 01308 #if defined(PWR_SR2_PVMO2) 01309 /** 01310 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold 01311 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2 01312 * @retval State of bit (1 or 0). 01313 */ 01314 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) 01315 { 01316 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)); 01317 } 01318 #endif /* PWR_SR2_PVMO2 */ 01319 01320 #if defined(USB_OTG_FS) 01321 /** 01322 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold 01323 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1 01324 * @retval State of bit (1 or 0). 01325 */ 01326 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) 01327 { 01328 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)); 01329 } 01330 #endif /* USB_OTG_FS */ 01331 01332 /** 01333 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold 01334 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO 01335 * @retval State of bit (1 or 0). 01336 */ 01337 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) 01338 { 01339 return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)); 01340 } 01341 01342 /** 01343 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level 01344 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOSF 01345 * @retval State of bit (1 or 0). 01346 */ 01347 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF(void) 01348 { 01349 return (READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)); 01350 } 01351 01352 /** 01353 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode 01354 * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. 01355 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF 01356 * @retval State of bit (1 or 0). 01357 */ 01358 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) 01359 { 01360 return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)); 01361 } 01362 01363 /** 01364 * @brief Indicate whether or not the low-power regulator is ready 01365 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS 01366 * @retval State of bit (1 or 0). 01367 */ 01368 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) 01369 { 01370 return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)); 01371 } 01372 01373 #if defined(USE_FULL_LL_DRIVER) 01374 /** @defgroup PWR_LL_EF_Init De-initialization function 01375 * @{ 01376 */ 01377 ErrorStatus LL_PWR_DeInit(void); 01378 /** 01379 * @} 01380 */ 01381 #endif /* USE_FULL_LL_DRIVER */ 01382 01383 /** 01384 * @} 01385 */ 01386 01387 01388 /** 01389 * @} 01390 */ 01391 01392 /** 01393 * @} 01394 */ 01395 01396 #endif /* defined(PWR) */ 01397 01398 /** 01399 * @} 01400 */ 01401 01402 #ifdef __cplusplus 01403 } 01404 #endif 01405 01406 #endif /* __STM32L4xx_LL_PWR_H */ 01407 01408 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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