stm32l4xx_ll_lpuart.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_lpuart.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of LPUART LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_LPUART_H
00040 #define __STM32L4xx_LL_LPUART_H
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048 
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052 
00053 #if defined (LPUART1)
00054 
00055 /** @defgroup LPUART_LL LPUART
00056   * @{
00057   */
00058 
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
00064   * @{
00065   */
00066 
00067 /* Defines used for the bit position in the register and perform offsets*/
00068 #define LPUART_POSITION_CR1_DEDT      (uint32_t)POSITION_VAL(USART_CR1_DEDT)
00069 #define LPUART_POSITION_CR1_DEAT      (uint32_t)POSITION_VAL(USART_CR1_DEAT)
00070 #define LPUART_POSITION_CR2_ADD       (uint32_t)POSITION_VAL(USART_CR2_ADD)
00071 
00072 /* Defines used in Baud Rate related macros and corresponding register setting computation */
00073 #define LPUART_LPUARTDIV_FREQ_MUL     (uint32_t)(256U)
00074 #define LPUART_BRR_MASK               (uint32_t)(0x000FFFFFU)
00075 #define LPUART_BRR_MIN_VALUE          (uint32_t)(0x00000300U)
00076 /**
00077   * @}
00078   */
00079 
00080 
00081 /* Private macros ------------------------------------------------------------*/
00082 #if defined(USE_FULL_LL_DRIVER)
00083 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
00084   * @{
00085   */
00086 /**
00087   * @}
00088   */
00089 #endif /*USE_FULL_LL_DRIVER*/
00090 
00091 /* Exported types ------------------------------------------------------------*/
00092 #if defined(USE_FULL_LL_DRIVER)
00093 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
00094   * @{
00095   */
00096 
00097 /**
00098   * @brief LL LPUART Init Structure definition
00099   */
00100 typedef struct
00101 {
00102   uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
00103 
00104                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
00105 
00106   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00107                                            This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
00108 
00109                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
00110 
00111   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00112                                            This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
00113 
00114                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
00115 
00116   uint32_t Parity;                    /*!< Specifies the parity mode.
00117                                            This parameter can be a value of @ref LPUART_LL_EC_PARITY.
00118 
00119                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
00120 
00121   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00122                                            This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
00123 
00124                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
00125 
00126   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00127                                            This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
00128 
00129                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
00130 
00131 } LL_LPUART_InitTypeDef;
00132 
00133 /**
00134   * @}
00135   */
00136 #endif /* USE_FULL_LL_DRIVER */
00137 
00138 /* Exported constants --------------------------------------------------------*/
00139 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
00140   * @{
00141   */
00142 
00143 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
00144   * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
00145   * @{
00146   */
00147 #define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error flag */
00148 #define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error flag */
00149 #define LL_LPUART_ICR_NCF                  USART_ICR_NCF                 /*!< Noise detected flag */
00150 #define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error flag */
00151 #define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected flag */
00152 #define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete flag */
00153 #define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS flag */
00154 #define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match flag */
00155 #define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
00156 /**
00157   * @}
00158   */
00159 
00160 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
00161   * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
00162   * @{
00163   */
00164 #define LL_LPUART_ISR_PE                   USART_ISR_PE                  /*!< Parity error flag */
00165 #define LL_LPUART_ISR_FE                   USART_ISR_FE                  /*!< Framing error flag */
00166 #define LL_LPUART_ISR_NE                   USART_ISR_NE                  /*!< Noise detected flag */
00167 #define LL_LPUART_ISR_ORE                  USART_ISR_ORE                 /*!< Overrun error flag */
00168 #define LL_LPUART_ISR_IDLE                 USART_ISR_IDLE                /*!< Idle line detected flag */
00169 #define LL_LPUART_ISR_RXNE                 USART_ISR_RXNE                /*!< Read data register not empty flag */
00170 #define LL_LPUART_ISR_TC                   USART_ISR_TC                  /*!< Transmission complete flag */
00171 #define LL_LPUART_ISR_TXE                  USART_ISR_TXE                 /*!< Transmit data register empty flag */
00172 #define LL_LPUART_ISR_CTSIF                USART_ISR_CTSIF               /*!< CTS interrupt flag */
00173 #define LL_LPUART_ISR_CTS                  USART_ISR_CTS                 /*!< CTS flag */
00174 #define LL_LPUART_ISR_BUSY                 USART_ISR_BUSY                /*!< Busy flag */
00175 #define LL_LPUART_ISR_CMF                  USART_ISR_CMF                 /*!< Character match flag */
00176 #define LL_LPUART_ISR_SBKF                 USART_ISR_SBKF                /*!< Send break flag */
00177 #define LL_LPUART_ISR_RWU                  USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00178 #define LL_LPUART_ISR_WUF                  USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00179 #define LL_LPUART_ISR_TEACK                USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00180 #define LL_LPUART_ISR_REACK                USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00181 /**
00182   * @}
00183   */
00184 
00185 /** @defgroup LPUART_LL_EC_IT IT Defines
00186   * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
00187   * @{
00188   */
00189 #define LL_LPUART_CR1_IDLEIE               USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00190 #define LL_LPUART_CR1_RXNEIE               USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
00191 #define LL_LPUART_CR1_TCIE                 USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00192 #define LL_LPUART_CR1_TXEIE                USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
00193 #define LL_LPUART_CR1_PEIE                 USART_CR1_PEIE                /*!< Parity error */
00194 #define LL_LPUART_CR1_CMIE                 USART_CR1_CMIE                /*!< Character match interrupt enable */
00195 #define LL_LPUART_CR3_EIE                  USART_CR3_EIE                 /*!< Error interrupt enable */
00196 #define LL_LPUART_CR3_CTSIE                USART_CR3_CTSIE               /*!< CTS interrupt enable */
00197 #define LL_LPUART_CR3_WUFIE                USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00198 /**
00199   * @}
00200   */
00201 
00202 /** @defgroup LPUART_LL_EC_DIRECTION Direction
00203   * @{
00204   */
00205 #define LL_LPUART_DIRECTION_NONE           (uint32_t)0x00000000U              /*!< Transmitter and Receiver are disabled */
00206 #define LL_LPUART_DIRECTION_RX             USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00207 #define LL_LPUART_DIRECTION_TX             USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00208 #define LL_LPUART_DIRECTION_TX_RX          (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00209 /**
00210   * @}
00211   */
00212 
00213 /** @defgroup LPUART_LL_EC_PARITY Parity Control
00214   * @{
00215   */
00216 #define LL_LPUART_PARITY_NONE              (uint32_t)0x00000000U              /*!< Parity control disabled */
00217 #define LL_LPUART_PARITY_EVEN              USART_CR1_PCE                      /*!< Parity control enabled and Even Parity is selected */
00218 #define LL_LPUART_PARITY_ODD               (USART_CR1_PCE | USART_CR1_PS)     /*!< Parity control enabled and Odd Parity is selected */
00219 /**
00220   * @}
00221   */
00222 
00223 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
00224   * @{
00225   */
00226 #define LL_LPUART_WAKEUP_IDLELINE          (uint32_t)0x00000000U              /*!<  LPUART wake up from Mute mode on Idle Line */
00227 #define LL_LPUART_WAKEUP_ADDRESSMARK       USART_CR1_WAKE                     /*!<  LPUART wake up from Mute mode on Address Mark */
00228 /**
00229   * @}
00230   */
00231 
00232 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
00233   * @{
00234   */
00235 #define LL_LPUART_DATAWIDTH_7B             USART_CR1_M1                       /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00236 #define LL_LPUART_DATAWIDTH_8B             (uint32_t)0x00000000U              /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00237 #define LL_LPUART_DATAWIDTH_9B             USART_CR1_M0                       /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00238 /**
00239   * @}
00240   */
00241 
00242 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
00243   * @{
00244   */
00245 #define LL_LPUART_STOPBITS_1               (uint32_t)0x00000000U              /*!< 1 stop bit */
00246 #define LL_LPUART_STOPBITS_2               USART_CR2_STOP_1                   /*!< 2 stop bits */
00247 /**
00248   * @}
00249   */
00250 
00251 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
00252   * @{
00253   */
00254 #define LL_LPUART_TXRX_STANDARD            (uint32_t)0x00000000U              /*!< TX/RX pins are used as defined in standard pinout */
00255 #define LL_LPUART_TXRX_SWAPPED             (USART_CR2_SWAP)                   /*!< TX and RX pins functions are swapped.             */
00256 /**
00257   * @}
00258   */
00259 
00260 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00261   * @{
00262   */
00263 #define LL_LPUART_RXPIN_LEVEL_STANDARD     (uint32_t)0x00000000U              /*!< RX pin signal works using the standard logic levels */
00264 #define LL_LPUART_RXPIN_LEVEL_INVERTED     (USART_CR2_RXINV)                  /*!< RX pin signal values are inverted.                  */
00265 /**
00266   * @}
00267   */
00268 
00269 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00270   * @{
00271   */
00272 #define LL_LPUART_TXPIN_LEVEL_STANDARD     (uint32_t)0x00000000U              /*!< TX pin signal works using the standard logic levels */
00273 #define LL_LPUART_TXPIN_LEVEL_INVERTED     (USART_CR2_TXINV)                  /*!< TX pin signal values are inverted.                  */
00274 /**
00275   * @}
00276   */
00277 
00278 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
00279   * @{
00280   */
00281 #define LL_LPUART_BINARY_LOGIC_POSITIVE    (uint32_t)0x00000000U              /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00282 #define LL_LPUART_BINARY_LOGIC_NEGATIVE    USART_CR2_DATAINV                  /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00283 /**
00284   * @}
00285   */
00286 
00287 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
00288   * @{
00289   */
00290 #define LL_LPUART_BITORDER_LSBFIRST        (uint32_t)0x00000000U              /*!< data is transmitted/received with data bit 0 first, following the start bit */
00291 #define LL_LPUART_BITORDER_MSBFIRST        USART_CR2_MSBFIRST                 /*!< data is transmitted/received with the MSB first, following the start bit */
00292 /**
00293   * @}
00294   */
00295 
00296 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
00297   * @{
00298   */
00299 #define LL_LPUART_ADDRESS_DETECT_4B        (uint32_t)0x00000000U              /*!< 4-bit address detection method selected */
00300 #define LL_LPUART_ADDRESS_DETECT_7B        USART_CR2_ADDM7                    /*!< 7-bit address detection (in 8-bit data mode) method selected */
00301 /**
00302   * @}
00303   */
00304 
00305 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
00306   * @{
00307   */
00308 #define LL_LPUART_HWCONTROL_NONE           (uint32_t)0x00000000U              /*!< CTS and RTS hardware flow control disabled */
00309 #define LL_LPUART_HWCONTROL_RTS            USART_CR3_RTSE                     /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00310 #define LL_LPUART_HWCONTROL_CTS            USART_CR3_CTSE                     /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00311 #define LL_LPUART_HWCONTROL_RTS_CTS        (USART_CR3_RTSE | USART_CR3_CTSE)  /*!< CTS and RTS hardware flow control enabled */
00312 /**
00313   * @}
00314   */
00315 
00316 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
00317   * @{
00318   */
00319 #define LL_LPUART_WAKEUP_ON_ADDRESS        (uint32_t)0x00000000U                   /*!< Wake up active on address match */
00320 #define LL_LPUART_WAKEUP_ON_STARTBIT       USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00321 #define LL_LPUART_WAKEUP_ON_RXNE           (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00322 /**
00323   * @}
00324   */
00325 
00326 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
00327   * @{
00328   */
00329 #define LL_LPUART_DE_POLARITY_HIGH         (uint32_t)0x00000000U              /*!< DE signal is active high */
00330 #define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP                      /*!< DE signal is active low */
00331 /**
00332   * @}
00333   */
00334 
00335 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
00336   * @{
00337   */
00338 #define LL_LPUART_DMA_REG_DATA_TRANSMIT    (uint32_t)0U                       /*!< Get address of data register used for transmission */
00339 #define LL_LPUART_DMA_REG_DATA_RECEIVE     (uint32_t)1U                       /*!< Get address of data register used for reception */
00340 /**
00341   * @}
00342   */
00343 
00344 /**
00345   * @}
00346   */
00347 
00348 /* Exported macro ------------------------------------------------------------*/
00349 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
00350   * @{
00351   */
00352 
00353 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
00354   * @{
00355   */
00356 
00357 /**
00358   * @brief  Write a value in LPUART register
00359   * @param  __INSTANCE__ LPUART Instance
00360   * @param  __REG__ Register to be written
00361   * @param  __VALUE__ Value to be written in the register
00362   * @retval None
00363   */
00364 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00365 
00366 /**
00367   * @brief  Read a value in LPUART register
00368   * @param  __INSTANCE__ LPUART Instance
00369   * @param  __REG__ Register to be read
00370   * @retval Register value
00371   */
00372 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00373 /**
00374   * @}
00375   */
00376 
00377 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
00378   * @{
00379   */
00380 
00381 /**
00382   * @brief  Compute LPUARTDIV value according to Peripheral Clock and
00383   *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
00384   * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
00385   * @param  __BAUDRATE__ Baud Rate value to achieve
00386   * @retval LPUARTDIV value to be used for BRR register filling
00387   */
00388 #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
00389 
00390 /**
00391   * @}
00392   */
00393 
00394 /**
00395   * @}
00396   */
00397 
00398 /* Exported functions --------------------------------------------------------*/
00399 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
00400   * @{
00401   */
00402 
00403 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
00404   * @{
00405   */
00406 
00407 /**
00408   * @brief  LPUART Enable
00409   * @rmtoll CR1          UE            LL_LPUART_Enable
00410   * @param  LPUARTx LPUART Instance
00411   * @retval None
00412   */
00413 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
00414 {
00415   SET_BIT(LPUARTx->CR1, USART_CR1_UE);
00416 }
00417 
00418 /**
00419   * @brief  LPUART Disable
00420   * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
00421   *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
00422   *         flags, in the LPUARTx_ISR are set to their default values.
00423   * @note   In order to go into low-power mode without generating errors on the line,
00424   *         the TE bit must be reset before and the software must wait
00425   *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
00426   *         The DMA requests are also reset when UE = 0 so the DMA channel must
00427   *         be disabled before resetting the UE bit.
00428   * @rmtoll CR1          UE            LL_LPUART_Disable
00429   * @param  LPUARTx LPUART Instance
00430   * @retval None
00431   */
00432 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
00433 {
00434   CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
00435 }
00436 
00437 /**
00438   * @brief  Indicate if LPUART is enabled
00439   * @rmtoll CR1          UE            LL_LPUART_IsEnabled
00440   * @param  LPUARTx LPUART Instance
00441   * @retval State of bit (1 or 0).
00442   */
00443 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
00444 {
00445   return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
00446 }
00447 
00448 /**
00449   * @brief  LPUART enabled in STOP Mode
00450   * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
00451   *         LPUART clock selection is HSI or LSE in RCC.
00452   * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
00453   * @param  LPUARTx LPUART Instance
00454   * @retval None
00455   */
00456 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
00457 {
00458   SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
00459 }
00460 
00461 /**
00462   * @brief  LPUART disabled in STOP Mode
00463   * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
00464   * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
00465   * @param  LPUARTx LPUART Instance
00466   * @retval None
00467   */
00468 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
00469 {
00470   CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
00471 }
00472 
00473 /**
00474   * @brief  Indicate if LPUART is enabled in STOP Mode
00475   *         (able to wake up MCU from Stop mode or not)
00476   * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
00477   * @param  LPUARTx LPUART Instance
00478   * @retval State of bit (1 or 0).
00479   */
00480 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
00481 {
00482   return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
00483 }
00484 
00485 /**
00486   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00487   * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
00488   * @param  LPUARTx LPUART Instance
00489   * @retval None
00490   */
00491 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
00492 {
00493   SET_BIT(LPUARTx->CR1, USART_CR1_RE);
00494 }
00495 
00496 /**
00497   * @brief  Receiver Disable
00498   * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
00499   * @param  LPUARTx LPUART Instance
00500   * @retval None
00501   */
00502 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
00503 {
00504   CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
00505 }
00506 
00507 /**
00508   * @brief  Transmitter Enable
00509   * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
00510   * @param  LPUARTx LPUART Instance
00511   * @retval None
00512   */
00513 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
00514 {
00515   SET_BIT(LPUARTx->CR1, USART_CR1_TE);
00516 }
00517 
00518 /**
00519   * @brief  Transmitter Disable
00520   * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
00521   * @param  LPUARTx LPUART Instance
00522   * @retval None
00523   */
00524 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
00525 {
00526   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
00527 }
00528 
00529 /**
00530   * @brief  Configure simultaneously enabled/disabled states
00531   *         of Transmitter and Receiver
00532   * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
00533   *         CR1          TE            LL_LPUART_SetTransferDirection
00534   * @param  LPUARTx LPUART Instance
00535   * @param  TransferDirection This parameter can be one of the following values:
00536   *         @arg @ref LL_LPUART_DIRECTION_NONE
00537   *         @arg @ref LL_LPUART_DIRECTION_RX
00538   *         @arg @ref LL_LPUART_DIRECTION_TX
00539   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00540   * @retval None
00541   */
00542 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
00543 {
00544   MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00545 }
00546 
00547 /**
00548   * @brief  Return enabled/disabled states of Transmitter and Receiver
00549   * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
00550   *         CR1          TE            LL_LPUART_GetTransferDirection
00551   * @param  LPUARTx LPUART Instance
00552   * @retval Returned value can be one of the following values:
00553   *         @arg @ref LL_LPUART_DIRECTION_NONE
00554   *         @arg @ref LL_LPUART_DIRECTION_RX
00555   *         @arg @ref LL_LPUART_DIRECTION_TX
00556   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00557   */
00558 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
00559 {
00560   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00561 }
00562 
00563 /**
00564   * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
00565   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00566   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00567   *         (depending on data width) and parity is checked on the received data.
00568   * @rmtoll CR1          PS            LL_LPUART_SetParity\n
00569   *         CR1          PCE           LL_LPUART_SetParity
00570   * @param  LPUARTx LPUART Instance
00571   * @param  Parity This parameter can be one of the following values:
00572   *         @arg @ref LL_LPUART_PARITY_NONE
00573   *         @arg @ref LL_LPUART_PARITY_EVEN
00574   *         @arg @ref LL_LPUART_PARITY_ODD
00575   * @retval None
00576   */
00577 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
00578 {
00579   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00580 }
00581 
00582 /**
00583   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00584   * @rmtoll CR1          PS            LL_LPUART_GetParity\n
00585   *         CR1          PCE           LL_LPUART_GetParity
00586   * @param  LPUARTx LPUART Instance
00587   * @retval Returned value can be one of the following values:
00588   *         @arg @ref LL_LPUART_PARITY_NONE
00589   *         @arg @ref LL_LPUART_PARITY_EVEN
00590   *         @arg @ref LL_LPUART_PARITY_ODD
00591   */
00592 __STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
00593 {
00594   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00595 }
00596 
00597 /**
00598   * @brief  Set Receiver Wake Up method from Mute mode.
00599   * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
00600   * @param  LPUARTx LPUART Instance
00601   * @param  Method This parameter can be one of the following values:
00602   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00603   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00604   * @retval None
00605   */
00606 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
00607 {
00608   MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
00609 }
00610 
00611 /**
00612   * @brief  Return Receiver Wake Up method from Mute mode
00613   * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
00614   * @param  LPUARTx LPUART Instance
00615   * @retval Returned value can be one of the following values:
00616   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00617   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00618   */
00619 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
00620 {
00621   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
00622 }
00623 
00624 /**
00625   * @brief  Set Word length (nb of data bits, excluding start and stop bits)
00626   * @rmtoll CR1          M             LL_LPUART_SetDataWidth
00627   * @param  LPUARTx LPUART Instance
00628   * @param  DataWidth This parameter can be one of the following values:
00629   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00630   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00631   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00632   * @retval None
00633   */
00634 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
00635 {
00636   MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
00637 }
00638 
00639 /**
00640   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00641   * @rmtoll CR1          M             LL_LPUART_GetDataWidth
00642   * @param  LPUARTx LPUART Instance
00643   * @retval Returned value can be one of the following values:
00644   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00645   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00646   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00647   */
00648 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
00649 {
00650   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
00651 }
00652 
00653 /**
00654   * @brief  Allow switch between Mute Mode and Active mode
00655   * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
00656   * @param  LPUARTx LPUART Instance
00657   * @retval None
00658   */
00659 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
00660 {
00661   SET_BIT(LPUARTx->CR1, USART_CR1_MME);
00662 }
00663 
00664 /**
00665   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
00666   * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
00667   * @param  LPUARTx LPUART Instance
00668   * @retval None
00669   */
00670 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
00671 {
00672   CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
00673 }
00674 
00675 /**
00676   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
00677   * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
00678   * @param  LPUARTx LPUART Instance
00679   * @retval State of bit (1 or 0).
00680   */
00681 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
00682 {
00683   return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
00684 }
00685 
00686 /**
00687   * @brief  Set the length of the stop bits
00688   * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
00689   * @param  LPUARTx LPUART Instance
00690   * @param  StopBits This parameter can be one of the following values:
00691   *         @arg @ref LL_LPUART_STOPBITS_1
00692   *         @arg @ref LL_LPUART_STOPBITS_2
00693   * @retval None
00694   */
00695 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
00696 {
00697   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
00698 }
00699 
00700 /**
00701   * @brief  Retrieve the length of the stop bits
00702   * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
00703   * @param  LPUARTx LPUART Instance
00704   * @retval Returned value can be one of the following values:
00705   *         @arg @ref LL_LPUART_STOPBITS_1
00706   *         @arg @ref LL_LPUART_STOPBITS_2
00707   */
00708 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
00709 {
00710   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
00711 }
00712 
00713 /**
00714   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
00715   * @note   Call of this function is equivalent to following function call sequence :
00716   *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
00717   *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
00718   *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
00719   * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
00720   *         CR1          PCE           LL_LPUART_ConfigCharacter\n
00721   *         CR1          M             LL_LPUART_ConfigCharacter\n
00722   *         CR2          STOP          LL_LPUART_ConfigCharacter
00723   * @param  LPUARTx LPUART Instance
00724   * @param  DataWidth This parameter can be one of the following values:
00725   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00726   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00727   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00728   * @param  Parity This parameter can be one of the following values:
00729   *         @arg @ref LL_LPUART_PARITY_NONE
00730   *         @arg @ref LL_LPUART_PARITY_EVEN
00731   *         @arg @ref LL_LPUART_PARITY_ODD
00732   * @param  StopBits This parameter can be one of the following values:
00733   *         @arg @ref LL_LPUART_STOPBITS_1
00734   *         @arg @ref LL_LPUART_STOPBITS_2
00735   * @retval None
00736   */
00737 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
00738                                                uint32_t StopBits)
00739 {
00740   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
00741   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
00742 }
00743 
00744 /**
00745   * @brief  Configure TX/RX pins swapping setting.
00746   * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
00747   * @param  LPUARTx LPUART Instance
00748   * @param  SwapConfig This parameter can be one of the following values:
00749   *         @arg @ref LL_LPUART_TXRX_STANDARD
00750   *         @arg @ref LL_LPUART_TXRX_SWAPPED
00751   * @retval None
00752   */
00753 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
00754 {
00755   MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
00756 }
00757 
00758 /**
00759   * @brief  Retrieve TX/RX pins swapping configuration.
00760   * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
00761   * @param  LPUARTx LPUART Instance
00762   * @retval Returned value can be one of the following values:
00763   *         @arg @ref LL_LPUART_TXRX_STANDARD
00764   *         @arg @ref LL_LPUART_TXRX_SWAPPED
00765   */
00766 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
00767 {
00768   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
00769 }
00770 
00771 /**
00772   * @brief  Configure RX pin active level logic
00773   * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
00774   * @param  LPUARTx LPUART Instance
00775   * @param  PinInvMethod This parameter can be one of the following values:
00776   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
00777   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
00778   * @retval None
00779   */
00780 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
00781 {
00782   MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
00783 }
00784 
00785 /**
00786   * @brief  Retrieve RX pin active level logic configuration
00787   * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
00788   * @param  LPUARTx LPUART Instance
00789   * @retval Returned value can be one of the following values:
00790   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
00791   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
00792   */
00793 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
00794 {
00795   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
00796 }
00797 
00798 /**
00799   * @brief  Configure TX pin active level logic
00800   * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
00801   * @param  LPUARTx LPUART Instance
00802   * @param  PinInvMethod This parameter can be one of the following values:
00803   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
00804   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
00805   * @retval None
00806   */
00807 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
00808 {
00809   MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
00810 }
00811 
00812 /**
00813   * @brief  Retrieve TX pin active level logic configuration
00814   * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
00815   * @param  LPUARTx LPUART Instance
00816   * @retval Returned value can be one of the following values:
00817   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
00818   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
00819   */
00820 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
00821 {
00822   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
00823 }
00824 
00825 /**
00826   * @brief  Configure Binary data logic.
00827   *
00828   * @note   Allow to define how Logical data from the data register are send/received :
00829   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
00830   * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
00831   * @param  LPUARTx LPUART Instance
00832   * @param  DataLogic This parameter can be one of the following values:
00833   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
00834   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
00835   * @retval None
00836   */
00837 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
00838 {
00839   MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
00840 }
00841 
00842 /**
00843   * @brief  Retrieve Binary data configuration
00844   * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
00845   * @param  LPUARTx LPUART Instance
00846   * @retval Returned value can be one of the following values:
00847   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
00848   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
00849   */
00850 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
00851 {
00852   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
00853 }
00854 
00855 /**
00856   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
00857   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
00858   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
00859   * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
00860   * @param  LPUARTx LPUART Instance
00861   * @param  BitOrder This parameter can be one of the following values:
00862   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
00863   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
00864   * @retval None
00865   */
00866 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
00867 {
00868   MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
00869 }
00870 
00871 /**
00872   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
00873   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
00874   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
00875   * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
00876   * @param  LPUARTx LPUART Instance
00877   * @retval Returned value can be one of the following values:
00878   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
00879   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
00880   */
00881 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
00882 {
00883   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
00884 }
00885 
00886 /**
00887   * @brief  Set Address of the LPUART node.
00888   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
00889   *         for wake up with address mark detection.
00890   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
00891   *         (b7-b4 should be set to 0)
00892   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
00893   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
00894   *         for wake up with 7-bit address mark detection.
00895   *         The MSB of the character sent by the transmitter should be equal to 1.
00896   *         It may also be used for character detection during normal reception,
00897   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
00898   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
00899   *         value and CMF flag is set on match)
00900   * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
00901   *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
00902   * @param  LPUARTx LPUART Instance
00903   * @param  AddressLen This parameter can be one of the following values:
00904   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
00905   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
00906   * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
00907   * @retval None
00908   */
00909 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
00910 {
00911   MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
00912              (uint32_t)(AddressLen | (NodeAddress << LPUART_POSITION_CR2_ADD)));
00913 }
00914 
00915 /**
00916   * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
00917   * @note   If 4-bit Address Detection is selected in ADDM7,
00918   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
00919   *         If 7-bit Address Detection is selected in ADDM7,
00920   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
00921   * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
00922   * @param  LPUARTx LPUART Instance
00923   * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
00924   */
00925 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
00926 {
00927   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> LPUART_POSITION_CR2_ADD);
00928 }
00929 
00930 /**
00931   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
00932   * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
00933   * @param  LPUARTx LPUART Instance
00934   * @retval Returned value can be one of the following values:
00935   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
00936   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
00937   */
00938 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
00939 {
00940   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
00941 }
00942 
00943 /**
00944   * @brief  Enable RTS HW Flow Control
00945   * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
00946   * @param  LPUARTx LPUART Instance
00947   * @retval None
00948   */
00949 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
00950 {
00951   SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
00952 }
00953 
00954 /**
00955   * @brief  Disable RTS HW Flow Control
00956   * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
00957   * @param  LPUARTx LPUART Instance
00958   * @retval None
00959   */
00960 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
00961 {
00962   CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
00963 }
00964 
00965 /**
00966   * @brief  Enable CTS HW Flow Control
00967   * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
00968   * @param  LPUARTx LPUART Instance
00969   * @retval None
00970   */
00971 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
00972 {
00973   SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
00974 }
00975 
00976 /**
00977   * @brief  Disable CTS HW Flow Control
00978   * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
00979   * @param  LPUARTx LPUART Instance
00980   * @retval None
00981   */
00982 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
00983 {
00984   CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
00985 }
00986 
00987 /**
00988   * @brief  Configure HW Flow Control mode (both CTS and RTS)
00989   * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
00990   *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
00991   * @param  LPUARTx LPUART Instance
00992   * @param  HardwareFlowControl This parameter can be one of the following values:
00993   *         @arg @ref LL_LPUART_HWCONTROL_NONE
00994   *         @arg @ref LL_LPUART_HWCONTROL_RTS
00995   *         @arg @ref LL_LPUART_HWCONTROL_CTS
00996   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
00997   * @retval None
00998   */
00999 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
01000 {
01001   MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01002 }
01003 
01004 /**
01005   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01006   * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
01007   *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
01008   * @param  LPUARTx LPUART Instance
01009   * @retval Returned value can be one of the following values:
01010   *         @arg @ref LL_LPUART_HWCONTROL_NONE
01011   *         @arg @ref LL_LPUART_HWCONTROL_RTS
01012   *         @arg @ref LL_LPUART_HWCONTROL_CTS
01013   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
01014   */
01015 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
01016 {
01017   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01018 }
01019 
01020 /**
01021   * @brief  Enable Overrun detection
01022   * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
01023   * @param  LPUARTx LPUART Instance
01024   * @retval None
01025   */
01026 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
01027 {
01028   CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01029 }
01030 
01031 /**
01032   * @brief  Disable Overrun detection
01033   * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
01034   * @param  LPUARTx LPUART Instance
01035   * @retval None
01036   */
01037 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
01038 {
01039   SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01040 }
01041 
01042 /**
01043   * @brief  Indicate if Overrun detection is enabled
01044   * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
01045   * @param  LPUARTx LPUART Instance
01046   * @retval State of bit (1 or 0).
01047   */
01048 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
01049 {
01050   return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
01051 }
01052 
01053 /**
01054   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01055   * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
01056   * @param  LPUARTx LPUART Instance
01057   * @param  Type This parameter can be one of the following values:
01058   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01059   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01060   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01061   * @retval None
01062   */
01063 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
01064 {
01065   MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
01066 }
01067 
01068 /**
01069   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01070   * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
01071   * @param  LPUARTx LPUART Instance
01072   * @retval Returned value can be one of the following values:
01073   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01074   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01075   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01076   */
01077 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
01078 {
01079   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
01080 }
01081 
01082 /**
01083   * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
01084   *
01085   * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
01086   *         according to used Peripheral Clock and expected Baud Rate values
01087   * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
01088   *         (Baud rate value != 0).
01089   * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
01090   *         a care should be taken when generating high baud rates using high PeriphClk
01091   *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
01092   * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
01093   * @param  LPUARTx LPUART Instance
01094   * @param  PeriphClk Peripheral Clock
01095   * @param  BaudRate Baud Rate
01096   * @retval None
01097   */
01098 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
01099 {
01100   LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
01101 }
01102 
01103 /**
01104   * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
01105   *         (full BRR content), and to used Peripheral Clock values
01106   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01107   * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
01108   * @param  LPUARTx LPUART Instance
01109   * @param  PeriphClk Peripheral Clock
01110   * @retval Baud Rate
01111   */
01112 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
01113 {
01114   register uint32_t lpuartdiv = 0x0U;
01115   register uint32_t brrresult = 0x0U;
01116 
01117   lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
01118 
01119   if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
01120   {
01121     brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
01122   }
01123 
01124   return (brrresult);
01125 }
01126 
01127 /**
01128   * @}
01129   */
01130 
01131 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
01132   * @{
01133   */
01134 
01135 /**
01136   * @brief  Enable Single Wire Half-Duplex mode
01137   * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
01138   * @param  LPUARTx LPUART Instance
01139   * @retval None
01140   */
01141 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
01142 {
01143   SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01144 }
01145 
01146 /**
01147   * @brief  Disable Single Wire Half-Duplex mode
01148   * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
01149   * @param  LPUARTx LPUART Instance
01150   * @retval None
01151   */
01152 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
01153 {
01154   CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01155 }
01156 
01157 /**
01158   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
01159   * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
01160   * @param  LPUARTx LPUART Instance
01161   * @retval State of bit (1 or 0).
01162   */
01163 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
01164 {
01165   return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
01166 }
01167 
01168 /**
01169   * @}
01170   */
01171 
01172 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
01173   * @{
01174   */
01175 
01176 /**
01177   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01178   * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
01179   * @param  LPUARTx LPUART Instance
01180   * @param  Time Value between Min_Data=0 and Max_Data=31
01181   * @retval None
01182   */
01183 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01184 {
01185   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << LPUART_POSITION_CR1_DEDT);
01186 }
01187 
01188 /**
01189   * @brief  Return DEDT (Driver Enable De-Assertion Time)
01190   * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
01191   * @param  LPUARTx LPUART Instance
01192   * @retval Time value expressed on 5 bits ([4:0] bits) : c
01193   */
01194 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
01195 {
01196   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> LPUART_POSITION_CR1_DEDT);
01197 }
01198 
01199 /**
01200   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01201   * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
01202   * @param  LPUARTx LPUART Instance
01203   * @param  Time Value between Min_Data=0 and Max_Data=31
01204   * @retval None
01205   */
01206 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01207 {
01208   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << LPUART_POSITION_CR1_DEAT);
01209 }
01210 
01211 /**
01212   * @brief  Return DEAT (Driver Enable Assertion Time)
01213   * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
01214   * @param  LPUARTx LPUART Instance
01215   * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
01216   */
01217 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
01218 {
01219   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> LPUART_POSITION_CR1_DEAT);
01220 }
01221 
01222 /**
01223   * @brief  Enable Driver Enable (DE) Mode
01224   * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
01225   * @param  LPUARTx LPUART Instance
01226   * @retval None
01227   */
01228 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
01229 {
01230   SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
01231 }
01232 
01233 /**
01234   * @brief  Disable Driver Enable (DE) Mode
01235   * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
01236   * @param  LPUARTx LPUART Instance
01237   * @retval None
01238   */
01239 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
01240 {
01241   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
01242 }
01243 
01244 /**
01245   * @brief  Indicate if Driver Enable (DE) Mode is enabled
01246   * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
01247   * @param  LPUARTx LPUART Instance
01248   * @retval State of bit (1 or 0).
01249   */
01250 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
01251 {
01252   return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
01253 }
01254 
01255 /**
01256   * @brief  Select Driver Enable Polarity
01257   * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
01258   * @param  LPUARTx LPUART Instance
01259   * @param  Polarity This parameter can be one of the following values:
01260   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01261   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01262   * @retval None
01263   */
01264 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
01265 {
01266   MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
01267 }
01268 
01269 /**
01270   * @brief  Return Driver Enable Polarity
01271   * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
01272   * @param  LPUARTx LPUART Instance
01273   * @retval Returned value can be one of the following values:
01274   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01275   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01276   */
01277 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
01278 {
01279   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
01280 }
01281 
01282 /**
01283   * @}
01284   */
01285 
01286 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
01287   * @{
01288   */
01289 
01290 /**
01291   * @brief  Check if the LPUART Parity Error Flag is set or not
01292   * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
01293   * @param  LPUARTx LPUART Instance
01294   * @retval State of bit (1 or 0).
01295   */
01296 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
01297 {
01298   return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
01299 }
01300 
01301 /**
01302   * @brief  Check if the LPUART Framing Error Flag is set or not
01303   * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
01304   * @param  LPUARTx LPUART Instance
01305   * @retval State of bit (1 or 0).
01306   */
01307 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
01308 {
01309   return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
01310 }
01311 
01312 /**
01313   * @brief  Check if the LPUART Noise detected Flag is set or not
01314   * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
01315   * @param  LPUARTx LPUART Instance
01316   * @retval State of bit (1 or 0).
01317   */
01318 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
01319 {
01320   return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
01321 }
01322 
01323 /**
01324   * @brief  Check if the LPUART OverRun Error Flag is set or not
01325   * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
01326   * @param  LPUARTx LPUART Instance
01327   * @retval State of bit (1 or 0).
01328   */
01329 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
01330 {
01331   return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
01332 }
01333 
01334 /**
01335   * @brief  Check if the LPUART IDLE line detected Flag is set or not
01336   * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
01337   * @param  LPUARTx LPUART Instance
01338   * @retval State of bit (1 or 0).
01339   */
01340 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
01341 {
01342   return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
01343 }
01344 
01345 /**
01346   * @brief  Check if the LPUART Read Data Register Not Empty Flag is set or not
01347   * @rmtoll ISR          RXNE          LL_LPUART_IsActiveFlag_RXNE
01348   * @param  LPUARTx LPUART Instance
01349   * @retval State of bit (1 or 0).
01350   */
01351 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
01352 {
01353   return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
01354 }
01355 
01356 /**
01357   * @brief  Check if the LPUART Transmission Complete Flag is set or not
01358   * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
01359   * @param  LPUARTx LPUART Instance
01360   * @retval State of bit (1 or 0).
01361   */
01362 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
01363 {
01364   return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
01365 }
01366 
01367 /**
01368   * @brief  Check if the LPUART Transmit Data Register Empty Flag is set or not
01369   * @rmtoll ISR          TXE           LL_LPUART_IsActiveFlag_TXE
01370   * @param  LPUARTx LPUART Instance
01371   * @retval State of bit (1 or 0).
01372   */
01373 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
01374 {
01375   return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
01376 }
01377 
01378 /**
01379   * @brief  Check if the LPUART CTS interrupt Flag is set or not
01380   * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
01381   * @param  LPUARTx LPUART Instance
01382   * @retval State of bit (1 or 0).
01383   */
01384 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
01385 {
01386   return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
01387 }
01388 
01389 /**
01390   * @brief  Check if the LPUART CTS Flag is set or not
01391   * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
01392   * @param  LPUARTx LPUART Instance
01393   * @retval State of bit (1 or 0).
01394   */
01395 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
01396 {
01397   return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
01398 }
01399 
01400 /**
01401   * @brief  Check if the LPUART Busy Flag is set or not
01402   * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
01403   * @param  LPUARTx LPUART Instance
01404   * @retval State of bit (1 or 0).
01405   */
01406 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
01407 {
01408   return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
01409 }
01410 
01411 /**
01412   * @brief  Check if the LPUART Character Match Flag is set or not
01413   * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
01414   * @param  LPUARTx LPUART Instance
01415   * @retval State of bit (1 or 0).
01416   */
01417 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
01418 {
01419   return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
01420 }
01421 
01422 /**
01423   * @brief  Check if the LPUART Send Break Flag is set or not
01424   * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
01425   * @param  LPUARTx LPUART Instance
01426   * @retval State of bit (1 or 0).
01427   */
01428 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
01429 {
01430   return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
01431 }
01432 
01433 /**
01434   * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
01435   * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
01436   * @param  LPUARTx LPUART Instance
01437   * @retval State of bit (1 or 0).
01438   */
01439 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
01440 {
01441   return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
01442 }
01443 
01444 /**
01445   * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
01446   * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
01447   * @param  LPUARTx LPUART Instance
01448   * @retval State of bit (1 or 0).
01449   */
01450 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
01451 {
01452   return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
01453 }
01454 
01455 /**
01456   * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
01457   * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
01458   * @param  LPUARTx LPUART Instance
01459   * @retval State of bit (1 or 0).
01460   */
01461 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
01462 {
01463   return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
01464 }
01465 
01466 /**
01467   * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
01468   * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
01469   * @param  LPUARTx LPUART Instance
01470   * @retval State of bit (1 or 0).
01471   */
01472 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
01473 {
01474   return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
01475 }
01476 
01477 /**
01478   * @brief  Clear Parity Error Flag
01479   * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
01480   * @param  LPUARTx LPUART Instance
01481   * @retval None
01482   */
01483 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
01484 {
01485   WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
01486 }
01487 
01488 /**
01489   * @brief  Clear Framing Error Flag
01490   * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
01491   * @param  LPUARTx LPUART Instance
01492   * @retval None
01493   */
01494 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
01495 {
01496   WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
01497 }
01498 
01499 /**
01500   * @brief  Clear Noise detected Flag
01501   * @rmtoll ICR          NCF           LL_LPUART_ClearFlag_NE
01502   * @param  LPUARTx LPUART Instance
01503   * @retval None
01504   */
01505 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
01506 {
01507   WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);
01508 }
01509 
01510 /**
01511   * @brief  Clear OverRun Error Flag
01512   * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
01513   * @param  LPUARTx LPUART Instance
01514   * @retval None
01515   */
01516 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
01517 {
01518   WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
01519 }
01520 
01521 /**
01522   * @brief  Clear IDLE line detected Flag
01523   * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
01524   * @param  LPUARTx LPUART Instance
01525   * @retval None
01526   */
01527 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
01528 {
01529   WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
01530 }
01531 
01532 /**
01533   * @brief  Clear Transmission Complete Flag
01534   * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
01535   * @param  LPUARTx LPUART Instance
01536   * @retval None
01537   */
01538 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
01539 {
01540   WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
01541 }
01542 
01543 /**
01544   * @brief  Clear CTS Interrupt Flag
01545   * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
01546   * @param  LPUARTx LPUART Instance
01547   * @retval None
01548   */
01549 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
01550 {
01551   WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
01552 }
01553 
01554 /**
01555   * @brief  Clear Character Match Flag
01556   * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
01557   * @param  LPUARTx LPUART Instance
01558   * @retval None
01559   */
01560 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
01561 {
01562   WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
01563 }
01564 
01565 /**
01566   * @brief  Clear Wake Up from stop mode Flag
01567   * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
01568   * @param  LPUARTx LPUART Instance
01569   * @retval None
01570   */
01571 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
01572 {
01573   WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
01574 }
01575 
01576 /**
01577   * @}
01578   */
01579 
01580 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
01581   * @{
01582   */
01583 
01584 /**
01585   * @brief  Enable IDLE Interrupt
01586   * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
01587   * @param  LPUARTx LPUART Instance
01588   * @retval None
01589   */
01590 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
01591 {
01592   SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
01593 }
01594 
01595 /**
01596   * @brief  Enable RX Not Empty Interrupt
01597   * @rmtoll CR1          RXNEIE        LL_LPUART_EnableIT_RXNE
01598   * @param  LPUARTx LPUART Instance
01599   * @retval None
01600   */
01601 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
01602 {
01603   SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
01604 }
01605 
01606 /**
01607   * @brief  Enable Transmission Complete Interrupt
01608   * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
01609   * @param  LPUARTx LPUART Instance
01610   * @retval None
01611   */
01612 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
01613 {
01614   SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
01615 }
01616 
01617 /**
01618   * @brief  Enable TX Empty Interrupt
01619   * @rmtoll CR1          TXEIE         LL_LPUART_EnableIT_TXE
01620   * @param  LPUARTx LPUART Instance
01621   * @retval None
01622   */
01623 __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
01624 {
01625   SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
01626 }
01627 
01628 /**
01629   * @brief  Enable Parity Error Interrupt
01630   * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
01631   * @param  LPUARTx LPUART Instance
01632   * @retval None
01633   */
01634 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
01635 {
01636   SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
01637 }
01638 
01639 /**
01640   * @brief  Enable Character Match Interrupt
01641   * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
01642   * @param  LPUARTx LPUART Instance
01643   * @retval None
01644   */
01645 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
01646 {
01647   SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
01648 }
01649 
01650 /**
01651   * @brief  Enable Error Interrupt
01652   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
01653   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
01654   *         - 0: Interrupt is inhibited
01655   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
01656   * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
01657   * @param  LPUARTx LPUART Instance
01658   * @retval None
01659   */
01660 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
01661 {
01662   SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
01663 }
01664 
01665 /**
01666   * @brief  Enable CTS Interrupt
01667   * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
01668   * @param  LPUARTx LPUART Instance
01669   * @retval None
01670   */
01671 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
01672 {
01673   SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
01674 }
01675 
01676 /**
01677   * @brief  Enable Wake Up from Stop Mode Interrupt
01678   * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
01679   * @param  LPUARTx LPUART Instance
01680   * @retval None
01681   */
01682 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
01683 {
01684   SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
01685 }
01686 
01687 /**
01688   * @brief  Disable IDLE Interrupt
01689   * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
01690   * @param  LPUARTx LPUART Instance
01691   * @retval None
01692   */
01693 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
01694 {
01695   CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
01696 }
01697 
01698 /**
01699   * @brief  Disable RX Not Empty Interrupt
01700   * @rmtoll CR1          RXNEIE        LL_LPUART_DisableIT_RXNE
01701   * @param  LPUARTx LPUART Instance
01702   * @retval None
01703   */
01704 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
01705 {
01706   CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
01707 }
01708 
01709 /**
01710   * @brief  Disable Transmission Complete Interrupt
01711   * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
01712   * @param  LPUARTx LPUART Instance
01713   * @retval None
01714   */
01715 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
01716 {
01717   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
01718 }
01719 
01720 /**
01721   * @brief  Disable TX Empty Interrupt
01722   * @rmtoll CR1          TXEIE         LL_LPUART_DisableIT_TXE
01723   * @param  LPUARTx LPUART Instance
01724   * @retval None
01725   */
01726 __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
01727 {
01728   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
01729 }
01730 
01731 /**
01732   * @brief  Disable Parity Error Interrupt
01733   * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
01734   * @param  LPUARTx LPUART Instance
01735   * @retval None
01736   */
01737 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
01738 {
01739   CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
01740 }
01741 
01742 /**
01743   * @brief  Disable Character Match Interrupt
01744   * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
01745   * @param  LPUARTx LPUART Instance
01746   * @retval None
01747   */
01748 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
01749 {
01750   CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
01751 }
01752 
01753 /**
01754   * @brief  Disable Error Interrupt
01755   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
01756   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
01757   *         - 0: Interrupt is inhibited
01758   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
01759   * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
01760   * @param  LPUARTx LPUART Instance
01761   * @retval None
01762   */
01763 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
01764 {
01765   CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
01766 }
01767 
01768 /**
01769   * @brief  Disable CTS Interrupt
01770   * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
01771   * @param  LPUARTx LPUART Instance
01772   * @retval None
01773   */
01774 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
01775 {
01776   CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
01777 }
01778 
01779 /**
01780   * @brief  Disable Wake Up from Stop Mode Interrupt
01781   * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
01782   * @param  LPUARTx LPUART Instance
01783   * @retval None
01784   */
01785 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
01786 {
01787   CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
01788 }
01789 
01790 /**
01791   * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
01792   * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
01793   * @param  LPUARTx LPUART Instance
01794   * @retval State of bit (1 or 0).
01795   */
01796 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
01797 {
01798   return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
01799 }
01800 
01801 /**
01802   * @brief  Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
01803   * @rmtoll CR1          RXNEIE        LL_LPUART_IsEnabledIT_RXNE
01804   * @param  LPUARTx LPUART Instance
01805   * @retval State of bit (1 or 0).
01806   */
01807 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
01808 {
01809   return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
01810 }
01811 
01812 /**
01813   * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
01814   * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
01815   * @param  LPUARTx LPUART Instance
01816   * @retval State of bit (1 or 0).
01817   */
01818 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
01819 {
01820   return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
01821 }
01822 
01823 /**
01824   * @brief  Check if the LPUART TX Empty Interrupt is enabled or disabled.
01825   * @rmtoll CR1          TXEIE         LL_LPUART_IsEnabledIT_TXE
01826   * @param  LPUARTx LPUART Instance
01827   * @retval State of bit (1 or 0).
01828   */
01829 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
01830 {
01831   return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
01832 }
01833 
01834 /**
01835   * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
01836   * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
01837   * @param  LPUARTx LPUART Instance
01838   * @retval State of bit (1 or 0).
01839   */
01840 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
01841 {
01842   return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
01843 }
01844 
01845 /**
01846   * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
01847   * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
01848   * @param  LPUARTx LPUART Instance
01849   * @retval State of bit (1 or 0).
01850   */
01851 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
01852 {
01853   return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
01854 }
01855 
01856 /**
01857   * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
01858   * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
01859   * @param  LPUARTx LPUART Instance
01860   * @retval State of bit (1 or 0).
01861   */
01862 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
01863 {
01864   return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
01865 }
01866 
01867 /**
01868   * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
01869   * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
01870   * @param  LPUARTx LPUART Instance
01871   * @retval State of bit (1 or 0).
01872   */
01873 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
01874 {
01875   return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
01876 }
01877 
01878 /**
01879   * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
01880   * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
01881   * @param  LPUARTx LPUART Instance
01882   * @retval State of bit (1 or 0).
01883   */
01884 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
01885 {
01886   return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
01887 }
01888 
01889 /**
01890   * @}
01891   */
01892 
01893 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
01894   * @{
01895   */
01896 
01897 /**
01898   * @brief  Enable DMA Mode for reception
01899   * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
01900   * @param  LPUARTx LPUART Instance
01901   * @retval None
01902   */
01903 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
01904 {
01905   SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
01906 }
01907 
01908 /**
01909   * @brief  Disable DMA Mode for reception
01910   * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
01911   * @param  LPUARTx LPUART Instance
01912   * @retval None
01913   */
01914 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
01915 {
01916   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
01917 }
01918 
01919 /**
01920   * @brief  Check if DMA Mode is enabled for reception
01921   * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
01922   * @param  LPUARTx LPUART Instance
01923   * @retval State of bit (1 or 0).
01924   */
01925 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
01926 {
01927   return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
01928 }
01929 
01930 /**
01931   * @brief  Enable DMA Mode for transmission
01932   * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
01933   * @param  LPUARTx LPUART Instance
01934   * @retval None
01935   */
01936 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
01937 {
01938   SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
01939 }
01940 
01941 /**
01942   * @brief  Disable DMA Mode for transmission
01943   * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
01944   * @param  LPUARTx LPUART Instance
01945   * @retval None
01946   */
01947 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
01948 {
01949   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
01950 }
01951 
01952 /**
01953   * @brief  Check if DMA Mode is enabled for transmission
01954   * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
01955   * @param  LPUARTx LPUART Instance
01956   * @retval State of bit (1 or 0).
01957   */
01958 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
01959 {
01960   return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
01961 }
01962 
01963 /**
01964   * @brief  Enable DMA Disabling on Reception Error
01965   * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
01966   * @param  LPUARTx LPUART Instance
01967   * @retval None
01968   */
01969 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
01970 {
01971   SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
01972 }
01973 
01974 /**
01975   * @brief  Disable DMA Disabling on Reception Error
01976   * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
01977   * @param  LPUARTx LPUART Instance
01978   * @retval None
01979   */
01980 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
01981 {
01982   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
01983 }
01984 
01985 /**
01986   * @brief  Indicate if DMA Disabling on Reception Error is disabled
01987   * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
01988   * @param  LPUARTx LPUART Instance
01989   * @retval State of bit (1 or 0).
01990   */
01991 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
01992 {
01993   return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
01994 }
01995 
01996 /**
01997   * @brief  Get the LPUART data register address used for DMA transfer
01998   * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
01999   * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
02000   * @param  LPUARTx LPUART Instance
02001   * @param  Direction This parameter can be one of the following values:
02002   *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
02003   *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
02004   * @retval Address of data register
02005   */
02006 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
02007 {
02008   register uint32_t data_reg_addr = 0U;
02009 
02010   if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
02011   {
02012     /* return address of TDR register */
02013     data_reg_addr = (uint32_t) &(LPUARTx->TDR);
02014   }
02015   else
02016   {
02017     /* return address of RDR register */
02018     data_reg_addr = (uint32_t) &(LPUARTx->RDR);
02019   }
02020 
02021   return data_reg_addr;
02022 }
02023 
02024 /**
02025   * @}
02026   */
02027 
02028 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
02029   * @{
02030   */
02031 
02032 /**
02033   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
02034   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
02035   * @param  LPUARTx LPUART Instance
02036   * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
02037   */
02038 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
02039 {
02040   return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
02041 }
02042 
02043 /**
02044   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
02045   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
02046   * @param  LPUARTx LPUART Instance
02047   * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
02048   */
02049 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
02050 {
02051   return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
02052 }
02053 
02054 /**
02055   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
02056   * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
02057   * @param  LPUARTx LPUART Instance
02058   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
02059   * @retval None
02060   */
02061 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
02062 {
02063   LPUARTx->TDR = Value;
02064 }
02065 
02066 /**
02067   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
02068   * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
02069   * @param  LPUARTx LPUART Instance
02070   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
02071   * @retval None
02072   */
02073 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
02074 {
02075   LPUARTx->TDR = Value & 0x1FFU;
02076 }
02077 
02078 /**
02079   * @}
02080   */
02081 
02082 /** @defgroup LPUART_LL_EF_Execution Execution
02083   * @{
02084   */
02085 
02086 /**
02087   * @brief  Request Break sending
02088   * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
02089   * @param  LPUARTx LPUART Instance
02090   * @retval None
02091   */
02092 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
02093 {
02094   SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ);
02095 }
02096 
02097 /**
02098   * @brief  Put LPUART in mute mode and set the RWU flag
02099   * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
02100   * @param  LPUARTx LPUART Instance
02101   * @retval None
02102   */
02103 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
02104 {
02105   SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ);
02106 }
02107 
02108 /**
02109   * @brief  Request a Receive Data flush
02110   * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
02111   * @param  LPUARTx LPUART Instance
02112   * @retval None
02113   */
02114 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
02115 {
02116   SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ);
02117 }
02118 
02119 /**
02120   * @}
02121   */
02122 
02123 #if defined(USE_FULL_LL_DRIVER)
02124 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
02125   * @{
02126   */
02127 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
02128 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
02129 void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
02130 /**
02131   * @}
02132   */
02133 #endif /* USE_FULL_LL_DRIVER */
02134 
02135 /**
02136   * @}
02137   */
02138 
02139 /**
02140   * @}
02141   */
02142 
02143 #endif /* LPUART1 */
02144 
02145 /**
02146   * @}
02147   */
02148 
02149 #ifdef __cplusplus
02150 }
02151 #endif
02152 
02153 #endif /* __STM32L4xx_LL_LPUART_H */
02154 
02155 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/