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stm32l4xx_ll_fmc.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_fmc.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of FMC HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_FMC_H 00040 #define __STM32L4xx_LL_FMC_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00047 00048 /* Includes ------------------------------------------------------------------*/ 00049 #include "stm32l4xx_hal_def.h" 00050 00051 /** @addtogroup STM32L4xx_HAL_Driver 00052 * @{ 00053 */ 00054 00055 /** @addtogroup FMC_LL FMC Low Layer 00056 * @{ 00057 */ 00058 00059 /** @addtogroup FMC_LL_Private_Macros FMC Low Layer Private Macros 00060 * @{ 00061 */ 00062 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 00063 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 00064 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 00065 ((__BANK__) == FMC_NORSRAM_BANK4)) 00066 00067 00068 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 00069 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 00070 00071 00072 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 00073 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 00074 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 00075 00076 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 00077 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 00078 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 00079 00080 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 00081 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 00082 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 00083 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 00084 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 00085 00086 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 00087 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 00088 00089 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 00090 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 00091 00092 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 00093 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 00094 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 00095 ((__MODE__) == FMC_ACCESS_MODE_D)) 00096 00097 00098 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 00099 00100 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 00101 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 00102 00103 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 00104 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 00105 00106 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 00107 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 00108 00109 00110 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 00111 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 00112 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 00113 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 00114 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 00115 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 00116 00117 00118 /** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance 00119 * @{ 00120 */ 00121 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 00122 /** 00123 * @} 00124 */ 00125 00126 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance 00127 * @{ 00128 */ 00129 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 00130 /** 00131 * @} 00132 */ 00133 00134 /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance 00135 * @{ 00136 */ 00137 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 00138 /** 00139 * @} 00140 */ 00141 00142 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 00143 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 00144 00145 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 00146 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 00147 00148 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 00149 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 00150 00151 00152 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 00153 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 00154 00155 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 00156 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 00157 00158 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 00159 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 00160 00161 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 00162 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 00163 00164 /** @defgroup FMC_Address_Setup_Time 00165 * @{ 00166 */ 00167 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) 00168 /** 00169 * @} 00170 */ 00171 00172 /** @defgroup FMC_Address_Hold_Time 00173 * @{ 00174 */ 00175 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) 00176 /** 00177 * @} 00178 */ 00179 00180 /** @defgroup FMC_Data_Setup_Time 00181 * @{ 00182 */ 00183 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) 00184 /** 00185 * @} 00186 */ 00187 00188 /** @defgroup FMC_Bus_Turn_around_Duration 00189 * @{ 00190 */ 00191 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) 00192 /** 00193 * @} 00194 */ 00195 00196 /** @defgroup FMC_CLK_Division 00197 * @{ 00198 */ 00199 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) 00200 /** 00201 * @} 00202 */ 00203 00204 /** @defgroup FMC_Data_Latency 00205 * @{ 00206 */ 00207 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) 00208 /** 00209 * @} 00210 */ 00211 00212 /** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time 00213 * @{ 00214 */ 00215 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) 00216 /** 00217 * @} 00218 */ 00219 00220 /** @defgroup FMC_TAR_Setup_Time 00221 * @{ 00222 */ 00223 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) 00224 /** 00225 * @} 00226 */ 00227 00228 /** @defgroup FMC_Setup_Time 00229 * @{ 00230 */ 00231 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255) 00232 /** 00233 * @} 00234 */ 00235 00236 /** @defgroup FMC_Wait_Setup_Time 00237 * @{ 00238 */ 00239 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255) 00240 /** 00241 * @} 00242 */ 00243 00244 /** @defgroup FMC_Hold_Setup_Time 00245 * @{ 00246 */ 00247 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255) 00248 /** 00249 * @} 00250 */ 00251 00252 /** @defgroup FMC_HiZ_Setup_Time 00253 * @{ 00254 */ 00255 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255) 00256 /** 00257 * @} 00258 */ 00259 00260 /** 00261 * @} 00262 */ 00263 00264 /* Exported typedef ----------------------------------------------------------*/ 00265 /** @addtogroup FMC_LL_Exported_Typedef FMC Low Layer Exported Typedef 00266 * @{ 00267 */ 00268 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 00269 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 00270 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 00271 00272 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 00273 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 00274 #define FMC_NAND_DEVICE FMC_Bank3_R 00275 00276 /** 00277 * @brief FMC_NORSRAM Configuration Structure definition 00278 */ 00279 typedef struct 00280 { 00281 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 00282 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 00283 00284 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 00285 multiplexed on the data bus or not. 00286 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 00287 00288 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 00289 the corresponding memory device. 00290 This parameter can be a value of @ref FMC_Memory_Type */ 00291 00292 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 00293 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 00294 00295 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 00296 valid only with synchronous burst Flash memories. 00297 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 00298 00299 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 00300 the Flash memory in burst mode. 00301 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 00302 00303 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 00304 clock cycle before the wait state or during the wait state, 00305 valid only when accessing memories in burst mode. 00306 This parameter can be a value of @ref FMC_Wait_Timing */ 00307 00308 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 00309 This parameter can be a value of @ref FMC_Write_Operation */ 00310 00311 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 00312 signal, valid for Flash memory access in burst mode. 00313 This parameter can be a value of @ref FMC_Wait_Signal */ 00314 00315 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 00316 This parameter can be a value of @ref FMC_Extended_Mode */ 00317 00318 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 00319 valid only with asynchronous Flash memories. 00320 This parameter can be a value of @ref FMC_AsynchronousWait */ 00321 00322 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 00323 This parameter can be a value of @ref FMC_Write_Burst */ 00324 00325 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 00326 This parameter is only enabled through the FMC_BCR1 register, and don't care 00327 through FMC_BCR2..4 registers. 00328 This parameter can be a value of @ref FMC_Continous_Clock */ 00329 00330 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 00331 This parameter is only enabled through the FMC_BCR1 register, and don't care 00332 through FMC_BCR2..4 registers. 00333 This parameter can be a value of @ref FMC_Write_FIFO. 00334 @note This Parameter is not available for STM32L47x/L48x devices. */ 00335 00336 uint32_t PageSize; /*!< Specifies the memory page size. 00337 This parameter can be a value of @ref FMC_Page_Size */ 00338 00339 }FMC_NORSRAM_InitTypeDef; 00340 00341 /** 00342 * @brief FMC_NORSRAM Timing parameters structure definition 00343 */ 00344 typedef struct 00345 { 00346 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 00347 the duration of the address setup time. 00348 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 00349 @note This parameter is not used with synchronous NOR Flash memories. */ 00350 00351 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 00352 the duration of the address hold time. 00353 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 00354 @note This parameter is not used with synchronous NOR Flash memories. */ 00355 00356 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 00357 the duration of the data setup time. 00358 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 00359 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 00360 NOR Flash memories. */ 00361 00362 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 00363 the duration of the bus turnaround. 00364 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 00365 @note This parameter is only used for multiplexed NOR Flash memories. */ 00366 00367 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 00368 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. 00369 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 00370 accesses. */ 00371 00372 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 00373 to the memory before getting the first data. 00374 The parameter value depends on the memory type as shown below: 00375 - It must be set to 0 in case of a CRAM 00376 - It is don't care in asynchronous NOR, SRAM or ROM accesses 00377 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories 00378 with synchronous burst mode enable */ 00379 00380 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 00381 This parameter can be a value of @ref FMC_Access_Mode */ 00382 }FMC_NORSRAM_TimingTypeDef; 00383 00384 /** 00385 * @brief FMC_NAND Configuration Structure definition 00386 */ 00387 typedef struct 00388 { 00389 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 00390 This parameter can be a value of @ref FMC_NAND_Bank */ 00391 00392 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 00393 This parameter can be any value of @ref FMC_Wait_feature */ 00394 00395 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 00396 This parameter can be any value of @ref FMC_NAND_Data_Width */ 00397 00398 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 00399 This parameter can be any value of @ref FMC_ECC */ 00400 00401 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 00402 This parameter can be any value of @ref FMC_ECC_Page_Size */ 00403 00404 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 00405 delay between CLE low and RE low. 00406 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 00407 00408 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 00409 delay between ALE low and RE low. 00410 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 00411 }FMC_NAND_InitTypeDef; 00412 00413 /** 00414 * @brief FMC_NAND Timing parameters structure definition 00415 */ 00416 typedef struct 00417 { 00418 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 00419 the command assertion for NAND-Flash read or write access 00420 to common/Attribute or I/O memory space (depending on 00421 the memory space timing to be configured). 00422 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 00423 00424 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 00425 command for NAND-Flash read or write access to 00426 common/Attribute or I/O memory space (depending on the 00427 memory space timing to be configured). 00428 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 00429 00430 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 00431 (and data for write access) after the command de-assertion 00432 for NAND-Flash read or write access to common/Attribute 00433 or I/O memory space (depending on the memory space timing 00434 to be configured). 00435 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 00436 00437 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 00438 data bus is kept in HiZ after the start of a NAND-Flash 00439 write access to common/Attribute or I/O memory space (depending 00440 on the memory space timing to be configured). 00441 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 00442 }FMC_NAND_PCC_TimingTypeDef; 00443 00444 /** 00445 * @} 00446 */ 00447 00448 /* Exported constants --------------------------------------------------------*/ 00449 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 00450 * @{ 00451 */ 00452 00453 /** @defgroup FMC_NOR_SRAM_Exported_constants FMC NOR/SRAM Exported constants 00454 * @{ 00455 */ 00456 00457 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 00458 * @{ 00459 */ 00460 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) 00461 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) 00462 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) 00463 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) 00464 /** 00465 * @} 00466 */ 00467 00468 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 00469 * @{ 00470 */ 00471 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) 00472 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN) 00473 /** 00474 * @} 00475 */ 00476 00477 /** @defgroup FMC_Memory_Type FMC Memory Type 00478 * @{ 00479 */ 00480 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) 00481 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0) 00482 #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1) 00483 /** 00484 * @} 00485 */ 00486 00487 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 00488 * @{ 00489 */ 00490 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) 00491 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0) 00492 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1) 00493 /** 00494 * @} 00495 */ 00496 00497 /** @defgroup FMC_NORSRAM_Flash_Access FMC NORSRAM Flash Access 00498 * @{ 00499 */ 00500 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN) 00501 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) 00502 /** 00503 * @} 00504 */ 00505 00506 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 00507 * @{ 00508 */ 00509 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) 00510 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN) 00511 /** 00512 * @} 00513 */ 00514 00515 00516 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 00517 * @{ 00518 */ 00519 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) 00520 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL) 00521 /** 00522 * @} 00523 */ 00524 00525 /** @defgroup FMC_Wait_Timing FMC Wait Timing 00526 * @{ 00527 */ 00528 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) 00529 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG) 00530 00531 /** 00532 * @} 00533 */ 00534 00535 /** @defgroup FMC_Write_Operation FMC Write Operation 00536 * @{ 00537 */ 00538 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) 00539 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN) 00540 /** 00541 * @} 00542 */ 00543 00544 /** @defgroup FMC_Wait_Signal FMC Wait Signal 00545 * @{ 00546 */ 00547 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) 00548 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN) 00549 /** 00550 * @} 00551 */ 00552 00553 /** @defgroup FMC_Extended_Mode FMC Extended Mode 00554 * @{ 00555 */ 00556 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) 00557 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD) 00558 /** 00559 * @} 00560 */ 00561 00562 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 00563 * @{ 00564 */ 00565 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) 00566 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT) 00567 /** 00568 * @} 00569 */ 00570 00571 /** @defgroup FMC_Page_Size FMC Page Size 00572 * @{ 00573 */ 00574 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) 00575 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) 00576 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) 00577 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) 00578 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2) 00579 /** 00580 * @} 00581 */ 00582 00583 /** @defgroup FMC_Write_Burst FMC Write Burst 00584 * @{ 00585 */ 00586 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) 00587 #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW) 00588 /** 00589 * @} 00590 */ 00591 00592 /** @defgroup FMC_Continous_Clock FMC Continous Clock 00593 * @{ 00594 */ 00595 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) 00596 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN) 00597 /** 00598 * @} 00599 */ 00600 00601 /** @defgroup FMC_Access_Mode FMC Access Mode 00602 * @{ 00603 */ 00604 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) 00605 #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0) 00606 #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1) 00607 #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0|FMC_BTRx_ACCMOD_1)) 00608 /** 00609 * @} 00610 */ 00611 00612 /** 00613 * @} 00614 */ 00615 00616 /** 00617 * @} 00618 */ 00619 00620 /** @defgroup FMC_NAND_Controller FMC NAND Exported constants 00621 * @{ 00622 */ 00623 00624 /** @defgroup FMC_NAND_Bank FMC NAND Bank 00625 * @{ 00626 */ 00627 #define FMC_NAND_BANK3 ((uint32_t)0x00000100) 00628 /** 00629 * @} 00630 */ 00631 00632 /** @defgroup FMC_Wait_feature FMC Wait feature 00633 * @{ 00634 */ 00635 #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) 00636 #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCR_PWAITEN) 00637 /** 00638 * @} 00639 */ 00640 00641 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 00642 * @{ 00643 */ 00644 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCR_PTYP) 00645 /** 00646 * @} 00647 */ 00648 00649 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 00650 * @{ 00651 */ 00652 #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) 00653 #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCR_PWID_0) 00654 /** 00655 * @} 00656 */ 00657 00658 /** @defgroup FMC_ECC FMC NAND ECC 00659 * @{ 00660 */ 00661 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) 00662 #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCR_ECCEN) 00663 /** 00664 * @} 00665 */ 00666 00667 /** @defgroup FMC_ECC_Page_Size FMC NAND ECC Page Size 00668 * @{ 00669 */ 00670 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) 00671 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCR_ECCPS_0) 00672 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCR_ECCPS_1) 00673 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1) 00674 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCR_ECCPS_2) 00675 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2) 00676 /** 00677 * @} 00678 */ 00679 00680 /** 00681 * @} 00682 */ 00683 00684 /** 00685 * @} 00686 */ 00687 00688 /** @defgroup FMC_Interrupt_definition FMC Interrupt definition 00689 * @brief FMC Interrupt definition 00690 * @{ 00691 */ 00692 #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) 00693 #define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) 00694 #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) 00695 /** 00696 * @} 00697 */ 00698 00699 /** @defgroup FMC_Flag_definition FMC Flag definition 00700 * @brief FMC Flag definition 00701 * @{ 00702 */ 00703 #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS) 00704 #define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS) 00705 #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS) 00706 #define FMC_FLAG_FEMPT ((uint32_t)FMC_SR_FEMPT) 00707 /** 00708 * @} 00709 */ 00710 00711 /* Exported macro ------------------------------------------------------------*/ 00712 00713 /** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros 00714 * @{ 00715 */ 00716 00717 /** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros 00718 * @brief macros to handle NOR device enable/disable and read/write operations 00719 * @{ 00720 */ 00721 00722 /** 00723 * @brief Enable the NORSRAM device access. 00724 * @param __INSTANCE__: FMC_NORSRAM Instance 00725 * @param __BANK__: FMC_NORSRAM Bank 00726 * @retval none 00727 */ 00728 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) 00729 00730 /** 00731 * @brief Disable the NORSRAM device access. 00732 * @param __INSTANCE__: FMC_NORSRAM Instance 00733 * @param __BANK__: FMC_NORSRAM Bank 00734 * @retval none 00735 */ 00736 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) 00737 00738 /** 00739 * @} 00740 */ 00741 00742 /** @defgroup FMC_NAND_Macros FMC NAND Macros 00743 * @brief macros to handle NAND device enable/disable 00744 * @{ 00745 */ 00746 00747 /** 00748 * @brief Enable the NAND device access. 00749 * @param __INSTANCE__: FMC_NAND Instance 00750 * @param __BANK__: FMC_NAND Bank 00751 * @retval none 00752 */ 00753 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 00754 00755 /** 00756 * @brief Disable the NAND device access. 00757 * @param __INSTANCE__: FMC_NAND Instance 00758 * @param __BANK__: FMC_NAND Bank 00759 * @retval None 00760 */ 00761 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 00762 00763 /** 00764 * @} 00765 */ 00766 00767 /** @defgroup FMC_Interrupt FMC Interrupt 00768 * @brief macros to handle FMC interrupts 00769 * @{ 00770 */ 00771 00772 /** 00773 * @brief Enable the NAND device interrupt. 00774 * @param __INSTANCE__: FMC_NAND Instance 00775 * @param __BANK__: FMC_NAND Bank 00776 * @param __INTERRUPT__: FMC_NAND interrupt 00777 * This parameter can be any combination of the following values: 00778 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 00779 * @arg FMC_IT_LEVEL: Interrupt level. 00780 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 00781 * @retval None 00782 */ 00783 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) 00784 00785 /** 00786 * @brief Disable the NAND device interrupt. 00787 * @param __INSTANCE__: FMC_NAND Instance 00788 * @param __BANK__: FMC_NAND Bank 00789 * @param __INTERRUPT__: FMC_NAND interrupt 00790 * This parameter can be any combination of the following values: 00791 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 00792 * @arg FMC_IT_LEVEL: Interrupt level. 00793 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 00794 * @retval None 00795 */ 00796 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) 00797 00798 /** 00799 * @brief Get flag status of the NAND device. 00800 * @param __INSTANCE__: FMC_NAND Instance 00801 * @param __BANK__: FMC_NAND Bank 00802 * @param __FLAG__: FMC_NAND flag 00803 * This parameter can be any combination of the following values: 00804 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 00805 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 00806 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 00807 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 00808 * @retval The state of FLAG (SET or RESET). 00809 */ 00810 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 00811 00812 /** 00813 * @brief Clear flag status of the NAND device. 00814 * @param __INSTANCE__: FMC_NAND Instance 00815 * @param __BANK__: FMC_NAND Bank 00816 * @param __FLAG__: FMC_NAND flag 00817 * This parameter can be any combination of the following values: 00818 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 00819 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 00820 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 00821 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 00822 * @retval None 00823 */ 00824 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__)) 00825 00826 00827 /* Exported functions --------------------------------------------------------*/ 00828 /** @addgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions 00829 * @{ 00830 */ 00831 00832 /* FMC_LL_NORSRAM Controller functions *******************************************/ 00833 /** @addgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions 00834 * @{ 00835 */ 00836 /* Initialization/de-initialization functions */ 00837 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); 00838 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 00839 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); 00840 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 00841 /** 00842 * @} 00843 */ 00844 00845 /** @addtogroup FMC_LL_NORSRAM_Exported_Functions_Group2 Peripheral Control functions 00846 * @{ 00847 */ 00848 /* FMC_NORSRAM Control functions */ 00849 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 00850 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 00851 /** 00852 * @} 00853 */ 00854 00855 /* FMC_NAND Controller functions **********************************************/ 00856 /** @addtogroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions 00857 * @{ 00858 */ 00859 /* Initialization/de-initialization functions */ 00860 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 00861 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 00862 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 00863 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 00864 /** 00865 * @} 00866 */ 00867 00868 /** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions 00869 * @{ 00870 */ 00871 /* FMC_NAND Control functions */ 00872 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 00873 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 00874 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); 00875 /** 00876 * @} 00877 */ 00878 00879 /** 00880 * @} 00881 */ 00882 00883 /** 00884 * @} 00885 */ 00886 00887 /** 00888 * @} 00889 */ 00890 00891 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ 00892 00893 #ifdef __cplusplus 00894 } 00895 #endif 00896 00897 #endif /* __STM32L4xx_LL_FMC_H */ 00898 00899 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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