TUKS MCU Introductory course
/
TUKS-COURSE-THERMOMETER
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
TUKS-COURSE-TIMER
by 
TUKS MCU Introductory course
Embed:
(wiki syntax)
Show/hide line numbers
stm32l4xx_ll_dma.h
Go to the documentation of this file.
00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_dma.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of DMA LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_DMA_H 00040 #define __STM32L4xx_LL_DMA_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined (DMA1) || defined (DMA2) 00054 00055 /** @defgroup DMA_LL DMA 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 /** @defgroup DMA_LL_Private_Variables DMA Private Variables 00062 * @{ 00063 */ 00064 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ 00065 static const uint8_t CHANNEL_OFFSET_TAB[] = 00066 { 00067 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 00068 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 00069 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 00070 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 00071 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 00072 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 00073 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) 00074 }; 00075 /** 00076 * @} 00077 */ 00078 00079 /* Private constants ---------------------------------------------------------*/ 00080 /** @defgroup DMA_LL_Private_Constants DMA Private Constants 00081 * @{ 00082 */ 00083 /* Define used to get CSELR register offset */ 00084 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) 00085 00086 /* Defines used for the bit position in the register and perform offsets */ 00087 #define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U)) 00088 /** 00089 * @} 00090 */ 00091 00092 /* Private macros ------------------------------------------------------------*/ 00093 #if defined(USE_FULL_LL_DRIVER) 00094 /** @defgroup DMA_LL_Private_Macros DMA Private Macros 00095 * @{ 00096 */ 00097 /** 00098 * @} 00099 */ 00100 #endif /*USE_FULL_LL_DRIVER*/ 00101 00102 /* Exported types ------------------------------------------------------------*/ 00103 #if defined(USE_FULL_LL_DRIVER) 00104 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 00105 * @{ 00106 */ 00107 typedef struct 00108 { 00109 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 00110 or as Source base address in case of memory to memory transfer direction. 00111 00112 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00113 00114 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 00115 or as Destination base address in case of memory to memory transfer direction. 00116 00117 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00118 00119 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00120 from memory to memory or from peripheral to memory. 00121 This parameter can be a value of @ref DMA_LL_EC_DIRECTION 00122 00123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ 00124 00125 uint32_t Mode; /*!< Specifies the normal or circular operation mode. 00126 This parameter can be a value of @ref DMA_LL_EC_MODE 00127 @note: The circular buffer mode cannot be used if the memory to memory 00128 data transfer direction is configured on the selected Channel 00129 00130 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ 00131 00132 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction 00133 is incremented or not. 00134 This parameter can be a value of @ref DMA_LL_EC_PERIPH 00135 00136 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ 00137 00138 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction 00139 is incremented or not. 00140 This parameter can be a value of @ref DMA_LL_EC_MEMORY 00141 00142 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ 00143 00144 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) 00145 in case of memory to memory transfer direction. 00146 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 00147 00148 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ 00149 00150 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) 00151 in case of memory to memory transfer direction. 00152 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 00153 00154 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ 00155 00156 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 00157 The data unit is equal to the source buffer configuration set in PeripheralSize 00158 or MemorySize parameters depending in the transfer direction. 00159 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF 00160 00161 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ 00162 00163 uint32_t PeriphRequest; /*!< Specifies the peripheral request. 00164 This parameter can be a value of @ref DMA_LL_EC_REQUEST 00165 00166 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ 00167 00168 uint32_t Priority; /*!< Specifies the channel priority level. 00169 This parameter can be a value of @ref DMA_LL_EC_PRIORITY 00170 00171 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ 00172 00173 } LL_DMA_InitTypeDef; 00174 /** 00175 * @} 00176 */ 00177 #endif /*USE_FULL_LL_DRIVER*/ 00178 00179 /* Exported constants --------------------------------------------------------*/ 00180 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 00181 * @{ 00182 */ 00183 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines 00184 * @brief Flags defines which can be used with LL_DMA_WriteReg function 00185 * @{ 00186 */ 00187 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ 00188 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ 00189 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ 00190 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ 00191 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ 00192 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ 00193 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ 00194 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ 00195 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ 00196 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ 00197 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ 00198 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ 00199 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ 00200 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ 00201 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ 00202 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ 00203 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ 00204 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ 00205 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ 00206 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ 00207 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ 00208 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ 00209 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ 00210 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ 00211 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ 00212 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ 00213 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ 00214 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ 00215 /** 00216 * @} 00217 */ 00218 00219 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines 00220 * @brief Flags defines which can be used with LL_DMA_ReadReg function 00221 * @{ 00222 */ 00223 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ 00224 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ 00225 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ 00226 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ 00227 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ 00228 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ 00229 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ 00230 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ 00231 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ 00232 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ 00233 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ 00234 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ 00235 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ 00236 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ 00237 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ 00238 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ 00239 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ 00240 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ 00241 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ 00242 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ 00243 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ 00244 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ 00245 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ 00246 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ 00247 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ 00248 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ 00249 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ 00250 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ 00251 /** 00252 * @} 00253 */ 00254 00255 /** @defgroup DMA_LL_EC_IT IT Defines 00256 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions 00257 * @{ 00258 */ 00259 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ 00260 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ 00261 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ 00262 /** 00263 * @} 00264 */ 00265 00266 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 00267 * @{ 00268 */ 00269 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */ 00270 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */ 00271 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */ 00272 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */ 00273 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */ 00274 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */ 00275 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */ 00276 #if defined(USE_FULL_LL_DRIVER) 00277 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ 00278 #endif /*USE_FULL_LL_DRIVER*/ 00279 /** 00280 * @} 00281 */ 00282 00283 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction 00284 * @{ 00285 */ 00286 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ 00287 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 00288 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 00289 /** 00290 * @} 00291 */ 00292 00293 /** @defgroup DMA_LL_EC_MODE Transfer mode 00294 * @{ 00295 */ 00296 #define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ 00297 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ 00298 /** 00299 * @} 00300 */ 00301 00302 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode 00303 * @{ 00304 */ 00305 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 00306 #define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ 00307 /** 00308 * @} 00309 */ 00310 00311 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode 00312 * @{ 00313 */ 00314 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ 00315 #define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ 00316 /** 00317 * @} 00318 */ 00319 00320 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment 00321 * @{ 00322 */ 00323 #define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ 00324 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 00325 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 00326 /** 00327 * @} 00328 */ 00329 00330 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment 00331 * @{ 00332 */ 00333 #define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ 00334 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 00335 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 00336 /** 00337 * @} 00338 */ 00339 00340 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level 00341 * @{ 00342 */ 00343 #define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ 00344 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 00345 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 00346 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ 00347 /** 00348 * @} 00349 */ 00350 00351 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request 00352 * @{ 00353 */ 00354 #define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /*!< DMA peripheral request 0 */ 00355 #define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /*!< DMA peripheral request 1 */ 00356 #define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /*!< DMA peripheral request 2 */ 00357 #define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /*!< DMA peripheral request 3 */ 00358 #define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /*!< DMA peripheral request 4 */ 00359 #define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /*!< DMA peripheral request 5 */ 00360 #define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /*!< DMA peripheral request 6 */ 00361 #define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /*!< DMA peripheral request 7 */ 00362 /** 00363 * @} 00364 */ 00365 00366 /** 00367 * @} 00368 */ 00369 00370 /* Exported macro ------------------------------------------------------------*/ 00371 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 00372 * @{ 00373 */ 00374 00375 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 00376 * @{ 00377 */ 00378 /** 00379 * @brief Write a value in DMA register 00380 * @param __INSTANCE__ DMA Instance 00381 * @param __REG__ Register to be written 00382 * @param __VALUE__ Value to be written in the register 00383 * @retval None 00384 */ 00385 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00386 00387 /** 00388 * @brief Read a value in DMA register 00389 * @param __INSTANCE__ DMA Instance 00390 * @param __REG__ Register to be read 00391 * @retval Register value 00392 */ 00393 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00394 /** 00395 * @} 00396 */ 00397 00398 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely 00399 * @{ 00400 */ 00401 /** 00402 * @brief Convert DMAx_Channely into DMAx 00403 * @param __CHANNEL_INSTANCE__ DMAx_Channely 00404 * @retval DMAx 00405 */ 00406 #if defined(DMA2) 00407 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ 00408 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) 00409 #else 00410 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) 00411 #endif 00412 00413 /** 00414 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y 00415 * @param __CHANNEL_INSTANCE__ DMAx_Channely 00416 * @retval LL_DMA_CHANNEL_y 00417 */ 00418 #if defined (DMA2) 00419 #if defined (DMA2_Channel6) && defined (DMA2_Channel7) 00420 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 00421 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00424 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00425 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00426 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00427 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00428 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00429 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00430 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00431 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 00432 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ 00433 LL_DMA_CHANNEL_7) 00434 #else 00435 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 00436 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00437 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00438 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00442 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00443 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00444 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00445 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00446 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 00447 LL_DMA_CHANNEL_7) 00448 #endif 00449 #else 00450 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 00451 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00452 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00453 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00454 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00455 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00456 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 00457 LL_DMA_CHANNEL_7) 00458 #endif 00459 00460 /** 00461 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely 00462 * @param __DMA_INSTANCE__ DMAx 00463 * @param __CHANNEL__ LL_DMA_CHANNEL_y 00464 * @retval DMAx_Channely 00465 */ 00466 #if defined (DMA2) 00467 #if defined (DMA2_Channel6) && defined (DMA2_Channel7) 00468 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ 00469 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ 00470 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ 00471 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ 00472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ 00473 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ 00474 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ 00475 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ 00476 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ 00477 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ 00478 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ 00479 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ 00480 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ 00481 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ 00482 DMA2_Channel7) 00483 #else 00484 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ 00485 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ 00486 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ 00487 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ 00488 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ 00489 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ 00490 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ 00491 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ 00492 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ 00493 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ 00494 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ 00495 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ 00496 DMA1_Channel7) 00497 #endif 00498 #else 00499 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ 00500 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ 00501 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ 00502 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ 00503 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ 00504 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ 00505 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ 00506 DMA1_Channel7) 00507 #endif 00508 00509 /** 00510 * @} 00511 */ 00512 00513 /** 00514 * @} 00515 */ 00516 00517 /* Exported functions --------------------------------------------------------*/ 00518 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 00519 * @{ 00520 */ 00521 00522 /** @defgroup DMA_LL_EF_Configuration Configuration 00523 * @{ 00524 */ 00525 /** 00526 * @brief Enable DMA channel. 00527 * @rmtoll CCR EN LL_DMA_EnableChannel 00528 * @param DMAx DMAx Instance 00529 * @param Channel This parameter can be one of the following values: 00530 * @arg @ref LL_DMA_CHANNEL_1 00531 * @arg @ref LL_DMA_CHANNEL_2 00532 * @arg @ref LL_DMA_CHANNEL_3 00533 * @arg @ref LL_DMA_CHANNEL_4 00534 * @arg @ref LL_DMA_CHANNEL_5 00535 * @arg @ref LL_DMA_CHANNEL_6 00536 * @arg @ref LL_DMA_CHANNEL_7 00537 * @retval None 00538 */ 00539 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) 00540 { 00541 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); 00542 } 00543 00544 /** 00545 * @brief Disable DMA channel. 00546 * @rmtoll CCR EN LL_DMA_DisableChannel 00547 * @param DMAx DMAx Instance 00548 * @param Channel This parameter can be one of the following values: 00549 * @arg @ref LL_DMA_CHANNEL_1 00550 * @arg @ref LL_DMA_CHANNEL_2 00551 * @arg @ref LL_DMA_CHANNEL_3 00552 * @arg @ref LL_DMA_CHANNEL_4 00553 * @arg @ref LL_DMA_CHANNEL_5 00554 * @arg @ref LL_DMA_CHANNEL_6 00555 * @arg @ref LL_DMA_CHANNEL_7 00556 * @retval None 00557 */ 00558 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) 00559 { 00560 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); 00561 } 00562 00563 /** 00564 * @brief Check if DMA channel is enabled or disabled. 00565 * @rmtoll CCR EN LL_DMA_IsEnabledChannel 00566 * @param DMAx DMAx Instance 00567 * @param Channel This parameter can be one of the following values: 00568 * @arg @ref LL_DMA_CHANNEL_1 00569 * @arg @ref LL_DMA_CHANNEL_2 00570 * @arg @ref LL_DMA_CHANNEL_3 00571 * @arg @ref LL_DMA_CHANNEL_4 00572 * @arg @ref LL_DMA_CHANNEL_5 00573 * @arg @ref LL_DMA_CHANNEL_6 00574 * @arg @ref LL_DMA_CHANNEL_7 00575 * @retval State of bit (1 or 0). 00576 */ 00577 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) 00578 { 00579 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00580 DMA_CCR_EN) == (DMA_CCR_EN)); 00581 } 00582 00583 /** 00584 * @brief Configure all parameters link to DMA transfer. 00585 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n 00586 * CCR MEM2MEM LL_DMA_ConfigTransfer\n 00587 * CCR CIRC LL_DMA_ConfigTransfer\n 00588 * CCR PINC LL_DMA_ConfigTransfer\n 00589 * CCR MINC LL_DMA_ConfigTransfer\n 00590 * CCR PSIZE LL_DMA_ConfigTransfer\n 00591 * CCR MSIZE LL_DMA_ConfigTransfer\n 00592 * CCR PL LL_DMA_ConfigTransfer 00593 * @param DMAx DMAx Instance 00594 * @param Channel This parameter can be one of the following values: 00595 * @arg @ref LL_DMA_CHANNEL_1 00596 * @arg @ref LL_DMA_CHANNEL_2 00597 * @arg @ref LL_DMA_CHANNEL_3 00598 * @arg @ref LL_DMA_CHANNEL_4 00599 * @arg @ref LL_DMA_CHANNEL_5 00600 * @arg @ref LL_DMA_CHANNEL_6 00601 * @arg @ref LL_DMA_CHANNEL_7 00602 * @param Configuration This parameter must be a combination of all the following values: 00603 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00604 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR 00605 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 00606 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 00607 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD 00608 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD 00609 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH 00610 * @retval None 00611 */ 00612 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) 00613 { 00614 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00615 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, 00616 Configuration); 00617 } 00618 00619 /** 00620 * @brief Set Data transfer direction (read from peripheral or from memory). 00621 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n 00622 * CCR MEM2MEM LL_DMA_SetDataTransferDirection 00623 * @param DMAx DMAx Instance 00624 * @param Channel This parameter can be one of the following values: 00625 * @arg @ref LL_DMA_CHANNEL_1 00626 * @arg @ref LL_DMA_CHANNEL_2 00627 * @arg @ref LL_DMA_CHANNEL_3 00628 * @arg @ref LL_DMA_CHANNEL_4 00629 * @arg @ref LL_DMA_CHANNEL_5 00630 * @arg @ref LL_DMA_CHANNEL_6 00631 * @arg @ref LL_DMA_CHANNEL_7 00632 * @param Direction This parameter can be one of the following values: 00633 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00634 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00635 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00636 * @retval None 00637 */ 00638 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) 00639 { 00640 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00641 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); 00642 } 00643 00644 /** 00645 * @brief Get Data transfer direction (read from peripheral or from memory). 00646 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n 00647 * CCR MEM2MEM LL_DMA_GetDataTransferDirection 00648 * @param DMAx DMAx Instance 00649 * @param Channel This parameter can be one of the following values: 00650 * @arg @ref LL_DMA_CHANNEL_1 00651 * @arg @ref LL_DMA_CHANNEL_2 00652 * @arg @ref LL_DMA_CHANNEL_3 00653 * @arg @ref LL_DMA_CHANNEL_4 00654 * @arg @ref LL_DMA_CHANNEL_5 00655 * @arg @ref LL_DMA_CHANNEL_6 00656 * @arg @ref LL_DMA_CHANNEL_7 00657 * @retval Returned value can be one of the following values: 00658 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00659 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00660 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00661 */ 00662 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) 00663 { 00664 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00665 DMA_CCR_DIR | DMA_CCR_MEM2MEM)); 00666 } 00667 00668 /** 00669 * @brief Set DMA mode circular or normal. 00670 * @note The circular buffer mode cannot be used if the memory-to-memory 00671 * data transfer is configured on the selected Channel. 00672 * @rmtoll CCR CIRC LL_DMA_SetMode 00673 * @param DMAx DMAx Instance 00674 * @param Channel This parameter can be one of the following values: 00675 * @arg @ref LL_DMA_CHANNEL_1 00676 * @arg @ref LL_DMA_CHANNEL_2 00677 * @arg @ref LL_DMA_CHANNEL_3 00678 * @arg @ref LL_DMA_CHANNEL_4 00679 * @arg @ref LL_DMA_CHANNEL_5 00680 * @arg @ref LL_DMA_CHANNEL_6 00681 * @arg @ref LL_DMA_CHANNEL_7 00682 * @param Mode This parameter can be one of the following values: 00683 * @arg @ref LL_DMA_MODE_NORMAL 00684 * @arg @ref LL_DMA_MODE_CIRCULAR 00685 * @retval None 00686 */ 00687 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) 00688 { 00689 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, 00690 Mode); 00691 } 00692 00693 /** 00694 * @brief Get DMA mode circular or normal. 00695 * @rmtoll CCR CIRC LL_DMA_GetMode 00696 * @param DMAx DMAx Instance 00697 * @param Channel This parameter can be one of the following values: 00698 * @arg @ref LL_DMA_CHANNEL_1 00699 * @arg @ref LL_DMA_CHANNEL_2 00700 * @arg @ref LL_DMA_CHANNEL_3 00701 * @arg @ref LL_DMA_CHANNEL_4 00702 * @arg @ref LL_DMA_CHANNEL_5 00703 * @arg @ref LL_DMA_CHANNEL_6 00704 * @arg @ref LL_DMA_CHANNEL_7 00705 * @retval Returned value can be one of the following values: 00706 * @arg @ref LL_DMA_MODE_NORMAL 00707 * @arg @ref LL_DMA_MODE_CIRCULAR 00708 */ 00709 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) 00710 { 00711 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00712 DMA_CCR_CIRC)); 00713 } 00714 00715 /** 00716 * @brief Set Peripheral increment mode. 00717 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode 00718 * @param DMAx DMAx Instance 00719 * @param Channel This parameter can be one of the following values: 00720 * @arg @ref LL_DMA_CHANNEL_1 00721 * @arg @ref LL_DMA_CHANNEL_2 00722 * @arg @ref LL_DMA_CHANNEL_3 00723 * @arg @ref LL_DMA_CHANNEL_4 00724 * @arg @ref LL_DMA_CHANNEL_5 00725 * @arg @ref LL_DMA_CHANNEL_6 00726 * @arg @ref LL_DMA_CHANNEL_7 00727 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: 00728 * @arg @ref LL_DMA_PERIPH_INCREMENT 00729 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00730 * @retval None 00731 */ 00732 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) 00733 { 00734 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, 00735 PeriphOrM2MSrcIncMode); 00736 } 00737 00738 /** 00739 * @brief Get Peripheral increment mode. 00740 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode 00741 * @param DMAx DMAx Instance 00742 * @param Channel This parameter can be one of the following values: 00743 * @arg @ref LL_DMA_CHANNEL_1 00744 * @arg @ref LL_DMA_CHANNEL_2 00745 * @arg @ref LL_DMA_CHANNEL_3 00746 * @arg @ref LL_DMA_CHANNEL_4 00747 * @arg @ref LL_DMA_CHANNEL_5 00748 * @arg @ref LL_DMA_CHANNEL_6 00749 * @arg @ref LL_DMA_CHANNEL_7 00750 * @retval Returned value can be one of the following values: 00751 * @arg @ref LL_DMA_PERIPH_INCREMENT 00752 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00753 */ 00754 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) 00755 { 00756 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00757 DMA_CCR_PINC)); 00758 } 00759 00760 /** 00761 * @brief Set Memory increment mode. 00762 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode 00763 * @param DMAx DMAx Instance 00764 * @param Channel This parameter can be one of the following values: 00765 * @arg @ref LL_DMA_CHANNEL_1 00766 * @arg @ref LL_DMA_CHANNEL_2 00767 * @arg @ref LL_DMA_CHANNEL_3 00768 * @arg @ref LL_DMA_CHANNEL_4 00769 * @arg @ref LL_DMA_CHANNEL_5 00770 * @arg @ref LL_DMA_CHANNEL_6 00771 * @arg @ref LL_DMA_CHANNEL_7 00772 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: 00773 * @arg @ref LL_DMA_MEMORY_INCREMENT 00774 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00775 * @retval None 00776 */ 00777 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) 00778 { 00779 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, 00780 MemoryOrM2MDstIncMode); 00781 } 00782 00783 /** 00784 * @brief Get Memory increment mode. 00785 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode 00786 * @param DMAx DMAx Instance 00787 * @param Channel This parameter can be one of the following values: 00788 * @arg @ref LL_DMA_CHANNEL_1 00789 * @arg @ref LL_DMA_CHANNEL_2 00790 * @arg @ref LL_DMA_CHANNEL_3 00791 * @arg @ref LL_DMA_CHANNEL_4 00792 * @arg @ref LL_DMA_CHANNEL_5 00793 * @arg @ref LL_DMA_CHANNEL_6 00794 * @arg @ref LL_DMA_CHANNEL_7 00795 * @retval Returned value can be one of the following values: 00796 * @arg @ref LL_DMA_MEMORY_INCREMENT 00797 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00798 */ 00799 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) 00800 { 00801 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00802 DMA_CCR_MINC)); 00803 } 00804 00805 /** 00806 * @brief Set Peripheral size. 00807 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize 00808 * @param DMAx DMAx Instance 00809 * @param Channel This parameter can be one of the following values: 00810 * @arg @ref LL_DMA_CHANNEL_1 00811 * @arg @ref LL_DMA_CHANNEL_2 00812 * @arg @ref LL_DMA_CHANNEL_3 00813 * @arg @ref LL_DMA_CHANNEL_4 00814 * @arg @ref LL_DMA_CHANNEL_5 00815 * @arg @ref LL_DMA_CHANNEL_6 00816 * @arg @ref LL_DMA_CHANNEL_7 00817 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: 00818 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00819 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00820 * @arg @ref LL_DMA_PDATAALIGN_WORD 00821 * @retval None 00822 */ 00823 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) 00824 { 00825 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, 00826 PeriphOrM2MSrcDataSize); 00827 } 00828 00829 /** 00830 * @brief Get Peripheral size. 00831 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize 00832 * @param DMAx DMAx Instance 00833 * @param Channel This parameter can be one of the following values: 00834 * @arg @ref LL_DMA_CHANNEL_1 00835 * @arg @ref LL_DMA_CHANNEL_2 00836 * @arg @ref LL_DMA_CHANNEL_3 00837 * @arg @ref LL_DMA_CHANNEL_4 00838 * @arg @ref LL_DMA_CHANNEL_5 00839 * @arg @ref LL_DMA_CHANNEL_6 00840 * @arg @ref LL_DMA_CHANNEL_7 00841 * @retval Returned value can be one of the following values: 00842 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00843 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00844 * @arg @ref LL_DMA_PDATAALIGN_WORD 00845 */ 00846 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) 00847 { 00848 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00849 DMA_CCR_PSIZE)); 00850 } 00851 00852 /** 00853 * @brief Set Memory size. 00854 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize 00855 * @param DMAx DMAx Instance 00856 * @param Channel This parameter can be one of the following values: 00857 * @arg @ref LL_DMA_CHANNEL_1 00858 * @arg @ref LL_DMA_CHANNEL_2 00859 * @arg @ref LL_DMA_CHANNEL_3 00860 * @arg @ref LL_DMA_CHANNEL_4 00861 * @arg @ref LL_DMA_CHANNEL_5 00862 * @arg @ref LL_DMA_CHANNEL_6 00863 * @arg @ref LL_DMA_CHANNEL_7 00864 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: 00865 * @arg @ref LL_DMA_MDATAALIGN_BYTE 00866 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 00867 * @arg @ref LL_DMA_MDATAALIGN_WORD 00868 * @retval None 00869 */ 00870 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) 00871 { 00872 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, 00873 MemoryOrM2MDstDataSize); 00874 } 00875 00876 /** 00877 * @brief Get Memory size. 00878 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize 00879 * @param DMAx DMAx Instance 00880 * @param Channel This parameter can be one of the following values: 00881 * @arg @ref LL_DMA_CHANNEL_1 00882 * @arg @ref LL_DMA_CHANNEL_2 00883 * @arg @ref LL_DMA_CHANNEL_3 00884 * @arg @ref LL_DMA_CHANNEL_4 00885 * @arg @ref LL_DMA_CHANNEL_5 00886 * @arg @ref LL_DMA_CHANNEL_6 00887 * @arg @ref LL_DMA_CHANNEL_7 00888 * @retval Returned value can be one of the following values: 00889 * @arg @ref LL_DMA_MDATAALIGN_BYTE 00890 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 00891 * @arg @ref LL_DMA_MDATAALIGN_WORD 00892 */ 00893 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) 00894 { 00895 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00896 DMA_CCR_MSIZE)); 00897 } 00898 00899 /** 00900 * @brief Set Channel priority level. 00901 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel 00902 * @param DMAx DMAx Instance 00903 * @param Channel This parameter can be one of the following values: 00904 * @arg @ref LL_DMA_CHANNEL_1 00905 * @arg @ref LL_DMA_CHANNEL_2 00906 * @arg @ref LL_DMA_CHANNEL_3 00907 * @arg @ref LL_DMA_CHANNEL_4 00908 * @arg @ref LL_DMA_CHANNEL_5 00909 * @arg @ref LL_DMA_CHANNEL_6 00910 * @arg @ref LL_DMA_CHANNEL_7 00911 * @param Priority This parameter can be one of the following values: 00912 * @arg @ref LL_DMA_PRIORITY_LOW 00913 * @arg @ref LL_DMA_PRIORITY_MEDIUM 00914 * @arg @ref LL_DMA_PRIORITY_HIGH 00915 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 00916 * @retval None 00917 */ 00918 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) 00919 { 00920 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, 00921 Priority); 00922 } 00923 00924 /** 00925 * @brief Get Channel priority level. 00926 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel 00927 * @param DMAx DMAx Instance 00928 * @param Channel This parameter can be one of the following values: 00929 * @arg @ref LL_DMA_CHANNEL_1 00930 * @arg @ref LL_DMA_CHANNEL_2 00931 * @arg @ref LL_DMA_CHANNEL_3 00932 * @arg @ref LL_DMA_CHANNEL_4 00933 * @arg @ref LL_DMA_CHANNEL_5 00934 * @arg @ref LL_DMA_CHANNEL_6 00935 * @arg @ref LL_DMA_CHANNEL_7 00936 * @retval Returned value can be one of the following values: 00937 * @arg @ref LL_DMA_PRIORITY_LOW 00938 * @arg @ref LL_DMA_PRIORITY_MEDIUM 00939 * @arg @ref LL_DMA_PRIORITY_HIGH 00940 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 00941 */ 00942 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) 00943 { 00944 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00945 DMA_CCR_PL)); 00946 } 00947 00948 /** 00949 * @brief Set Number of data to transfer. 00950 * @note This action has no effect if 00951 * channel is enabled. 00952 * @rmtoll CNDTR NDT LL_DMA_SetDataLength 00953 * @param DMAx DMAx Instance 00954 * @param Channel This parameter can be one of the following values: 00955 * @arg @ref LL_DMA_CHANNEL_1 00956 * @arg @ref LL_DMA_CHANNEL_2 00957 * @arg @ref LL_DMA_CHANNEL_3 00958 * @arg @ref LL_DMA_CHANNEL_4 00959 * @arg @ref LL_DMA_CHANNEL_5 00960 * @arg @ref LL_DMA_CHANNEL_6 00961 * @arg @ref LL_DMA_CHANNEL_7 00962 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF 00963 * @retval None 00964 */ 00965 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) 00966 { 00967 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, 00968 DMA_CNDTR_NDT, NbData); 00969 } 00970 00971 /** 00972 * @brief Get Number of data to transfer. 00973 * @note Once the channel is enabled, the return value indicate the 00974 * remaining bytes to be transmitted. 00975 * @rmtoll CNDTR NDT LL_DMA_GetDataLength 00976 * @param DMAx DMAx Instance 00977 * @param Channel This parameter can be one of the following values: 00978 * @arg @ref LL_DMA_CHANNEL_1 00979 * @arg @ref LL_DMA_CHANNEL_2 00980 * @arg @ref LL_DMA_CHANNEL_3 00981 * @arg @ref LL_DMA_CHANNEL_4 00982 * @arg @ref LL_DMA_CHANNEL_5 00983 * @arg @ref LL_DMA_CHANNEL_6 00984 * @arg @ref LL_DMA_CHANNEL_7 00985 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 00986 */ 00987 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) 00988 { 00989 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, 00990 DMA_CNDTR_NDT)); 00991 } 00992 00993 /** 00994 * @brief Configure the Source and Destination addresses. 00995 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr) 00996 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n 00997 * CMAR MA LL_DMA_ConfigAddresses 00998 * @param DMAx DMAx Instance 00999 * @param Channel This parameter can be one of the following values: 01000 * @arg @ref LL_DMA_CHANNEL_1 01001 * @arg @ref LL_DMA_CHANNEL_2 01002 * @arg @ref LL_DMA_CHANNEL_3 01003 * @arg @ref LL_DMA_CHANNEL_4 01004 * @arg @ref LL_DMA_CHANNEL_5 01005 * @arg @ref LL_DMA_CHANNEL_6 01006 * @arg @ref LL_DMA_CHANNEL_7 01007 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01008 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01009 * @param Direction This parameter can be one of the following values: 01010 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 01011 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 01012 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 01013 * @retval None 01014 */ 01015 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, 01016 uint32_t DstAddress, uint32_t Direction) 01017 { 01018 /* Direction Memory to Periph */ 01019 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 01020 { 01021 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, 01022 SrcAddress); 01023 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, 01024 DstAddress); 01025 } 01026 /* Direction Periph to Memory and Memory to Memory */ 01027 else 01028 { 01029 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, 01030 SrcAddress); 01031 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, 01032 DstAddress); 01033 } 01034 } 01035 01036 /** 01037 * @brief Set the Memory address. 01038 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01039 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress 01040 * @param DMAx DMAx Instance 01041 * @param Channel This parameter can be one of the following values: 01042 * @arg @ref LL_DMA_CHANNEL_1 01043 * @arg @ref LL_DMA_CHANNEL_2 01044 * @arg @ref LL_DMA_CHANNEL_3 01045 * @arg @ref LL_DMA_CHANNEL_4 01046 * @arg @ref LL_DMA_CHANNEL_5 01047 * @arg @ref LL_DMA_CHANNEL_6 01048 * @arg @ref LL_DMA_CHANNEL_7 01049 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01050 * @retval None 01051 */ 01052 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) 01053 { 01054 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, 01055 MemoryAddress); 01056 } 01057 01058 /** 01059 * @brief Set the Peripheral address. 01060 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01061 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress 01062 * @param DMAx DMAx Instance 01063 * @param Channel This parameter can be one of the following values: 01064 * @arg @ref LL_DMA_CHANNEL_1 01065 * @arg @ref LL_DMA_CHANNEL_2 01066 * @arg @ref LL_DMA_CHANNEL_3 01067 * @arg @ref LL_DMA_CHANNEL_4 01068 * @arg @ref LL_DMA_CHANNEL_5 01069 * @arg @ref LL_DMA_CHANNEL_6 01070 * @arg @ref LL_DMA_CHANNEL_7 01071 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01072 * @retval None 01073 */ 01074 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) 01075 { 01076 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, 01077 PeriphAddress); 01078 } 01079 01080 /** 01081 * @brief Get Memory address. 01082 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01083 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress 01084 * @param DMAx DMAx Instance 01085 * @param Channel This parameter can be one of the following values: 01086 * @arg @ref LL_DMA_CHANNEL_1 01087 * @arg @ref LL_DMA_CHANNEL_2 01088 * @arg @ref LL_DMA_CHANNEL_3 01089 * @arg @ref LL_DMA_CHANNEL_4 01090 * @arg @ref LL_DMA_CHANNEL_5 01091 * @arg @ref LL_DMA_CHANNEL_6 01092 * @arg @ref LL_DMA_CHANNEL_7 01093 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01094 */ 01095 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) 01096 { 01097 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, 01098 DMA_CMAR_MA)); 01099 } 01100 01101 /** 01102 * @brief Get Peripheral address. 01103 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01104 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress 01105 * @param DMAx DMAx Instance 01106 * @param Channel This parameter can be one of the following values: 01107 * @arg @ref LL_DMA_CHANNEL_1 01108 * @arg @ref LL_DMA_CHANNEL_2 01109 * @arg @ref LL_DMA_CHANNEL_3 01110 * @arg @ref LL_DMA_CHANNEL_4 01111 * @arg @ref LL_DMA_CHANNEL_5 01112 * @arg @ref LL_DMA_CHANNEL_6 01113 * @arg @ref LL_DMA_CHANNEL_7 01114 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01115 */ 01116 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) 01117 { 01118 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, 01119 DMA_CPAR_PA)); 01120 } 01121 01122 /** 01123 * @brief Set the Memory to Memory Source address. 01124 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01125 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress 01126 * @param DMAx DMAx Instance 01127 * @param Channel This parameter can be one of the following values: 01128 * @arg @ref LL_DMA_CHANNEL_1 01129 * @arg @ref LL_DMA_CHANNEL_2 01130 * @arg @ref LL_DMA_CHANNEL_3 01131 * @arg @ref LL_DMA_CHANNEL_4 01132 * @arg @ref LL_DMA_CHANNEL_5 01133 * @arg @ref LL_DMA_CHANNEL_6 01134 * @arg @ref LL_DMA_CHANNEL_7 01135 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01136 * @retval None 01137 */ 01138 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) 01139 { 01140 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, 01141 MemoryAddress); 01142 } 01143 01144 /** 01145 * @brief Set the Memory to Memory Destination address. 01146 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01147 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress 01148 * @param DMAx DMAx Instance 01149 * @param Channel This parameter can be one of the following values: 01150 * @arg @ref LL_DMA_CHANNEL_1 01151 * @arg @ref LL_DMA_CHANNEL_2 01152 * @arg @ref LL_DMA_CHANNEL_3 01153 * @arg @ref LL_DMA_CHANNEL_4 01154 * @arg @ref LL_DMA_CHANNEL_5 01155 * @arg @ref LL_DMA_CHANNEL_6 01156 * @arg @ref LL_DMA_CHANNEL_7 01157 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01158 * @retval None 01159 */ 01160 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) 01161 { 01162 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, 01163 MemoryAddress); 01164 } 01165 01166 /** 01167 * @brief Get the Memory to Memory Source address. 01168 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01169 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress 01170 * @param DMAx DMAx Instance 01171 * @param Channel This parameter can be one of the following values: 01172 * @arg @ref LL_DMA_CHANNEL_1 01173 * @arg @ref LL_DMA_CHANNEL_2 01174 * @arg @ref LL_DMA_CHANNEL_3 01175 * @arg @ref LL_DMA_CHANNEL_4 01176 * @arg @ref LL_DMA_CHANNEL_5 01177 * @arg @ref LL_DMA_CHANNEL_6 01178 * @arg @ref LL_DMA_CHANNEL_7 01179 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01180 */ 01181 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) 01182 { 01183 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, 01184 DMA_CPAR_PA)); 01185 } 01186 01187 /** 01188 * @brief Get the Memory to Memory Destination address. 01189 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01190 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress 01191 * @param DMAx DMAx Instance 01192 * @param Channel This parameter can be one of the following values: 01193 * @arg @ref LL_DMA_CHANNEL_1 01194 * @arg @ref LL_DMA_CHANNEL_2 01195 * @arg @ref LL_DMA_CHANNEL_3 01196 * @arg @ref LL_DMA_CHANNEL_4 01197 * @arg @ref LL_DMA_CHANNEL_5 01198 * @arg @ref LL_DMA_CHANNEL_6 01199 * @arg @ref LL_DMA_CHANNEL_7 01200 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01201 */ 01202 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) 01203 { 01204 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, 01205 DMA_CMAR_MA)); 01206 } 01207 01208 /** 01209 * @brief Set DMA request for DMA instance on Channel x. 01210 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. 01211 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n 01212 * CSELR C2S LL_DMA_SetPeriphRequest\n 01213 * CSELR C3S LL_DMA_SetPeriphRequest\n 01214 * CSELR C4S LL_DMA_SetPeriphRequest\n 01215 * CSELR C5S LL_DMA_SetPeriphRequest\n 01216 * CSELR C6S LL_DMA_SetPeriphRequest\n 01217 * CSELR C7S LL_DMA_SetPeriphRequest 01218 * @param DMAx DMAx Instance 01219 * @param Channel This parameter can be one of the following values: 01220 * @arg @ref LL_DMA_CHANNEL_1 01221 * @arg @ref LL_DMA_CHANNEL_2 01222 * @arg @ref LL_DMA_CHANNEL_3 01223 * @arg @ref LL_DMA_CHANNEL_4 01224 * @arg @ref LL_DMA_CHANNEL_5 01225 * @arg @ref LL_DMA_CHANNEL_6 01226 * @arg @ref LL_DMA_CHANNEL_7 01227 * @param PeriphRequest This parameter can be one of the following values: 01228 * @arg @ref LL_DMA_REQUEST_0 01229 * @arg @ref LL_DMA_REQUEST_1 01230 * @arg @ref LL_DMA_REQUEST_2 01231 * @arg @ref LL_DMA_REQUEST_3 01232 * @arg @ref LL_DMA_REQUEST_4 01233 * @arg @ref LL_DMA_REQUEST_5 01234 * @arg @ref LL_DMA_REQUEST_6 01235 * @arg @ref LL_DMA_REQUEST_7 01236 * @retval None 01237 */ 01238 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) 01239 { 01240 MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, 01241 DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); 01242 } 01243 01244 /** 01245 * @brief Get DMA request for DMA instance on Channel x. 01246 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n 01247 * CSELR C2S LL_DMA_GetPeriphRequest\n 01248 * CSELR C3S LL_DMA_GetPeriphRequest\n 01249 * CSELR C4S LL_DMA_GetPeriphRequest\n 01250 * CSELR C5S LL_DMA_GetPeriphRequest\n 01251 * CSELR C6S LL_DMA_GetPeriphRequest\n 01252 * CSELR C7S LL_DMA_GetPeriphRequest 01253 * @param DMAx DMAx Instance 01254 * @param Channel This parameter can be one of the following values: 01255 * @arg @ref LL_DMA_CHANNEL_1 01256 * @arg @ref LL_DMA_CHANNEL_2 01257 * @arg @ref LL_DMA_CHANNEL_3 01258 * @arg @ref LL_DMA_CHANNEL_4 01259 * @arg @ref LL_DMA_CHANNEL_5 01260 * @arg @ref LL_DMA_CHANNEL_6 01261 * @arg @ref LL_DMA_CHANNEL_7 01262 * @retval Returned value can be one of the following values: 01263 * @arg @ref LL_DMA_REQUEST_0 01264 * @arg @ref LL_DMA_REQUEST_1 01265 * @arg @ref LL_DMA_REQUEST_2 01266 * @arg @ref LL_DMA_REQUEST_3 01267 * @arg @ref LL_DMA_REQUEST_4 01268 * @arg @ref LL_DMA_REQUEST_5 01269 * @arg @ref LL_DMA_REQUEST_6 01270 * @arg @ref LL_DMA_REQUEST_7 01271 */ 01272 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) 01273 { 01274 return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, 01275 DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); 01276 } 01277 01278 /** 01279 * @} 01280 */ 01281 01282 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 01283 * @{ 01284 */ 01285 01286 /** 01287 * @brief Get Channel 1 global interrupt flag. 01288 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 01289 * @param DMAx DMAx Instance 01290 * @retval State of bit (1 or 0). 01291 */ 01292 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) 01293 { 01294 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); 01295 } 01296 01297 /** 01298 * @brief Get Channel 2 global interrupt flag. 01299 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 01300 * @param DMAx DMAx Instance 01301 * @retval State of bit (1 or 0). 01302 */ 01303 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) 01304 { 01305 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); 01306 } 01307 01308 /** 01309 * @brief Get Channel 3 global interrupt flag. 01310 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 01311 * @param DMAx DMAx Instance 01312 * @retval State of bit (1 or 0). 01313 */ 01314 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) 01315 { 01316 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); 01317 } 01318 01319 /** 01320 * @brief Get Channel 4 global interrupt flag. 01321 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 01322 * @param DMAx DMAx Instance 01323 * @retval State of bit (1 or 0). 01324 */ 01325 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) 01326 { 01327 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); 01328 } 01329 01330 /** 01331 * @brief Get Channel 5 global interrupt flag. 01332 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 01333 * @param DMAx DMAx Instance 01334 * @retval State of bit (1 or 0). 01335 */ 01336 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) 01337 { 01338 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); 01339 } 01340 01341 /** 01342 * @brief Get Channel 6 global interrupt flag. 01343 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 01344 * @param DMAx DMAx Instance 01345 * @retval State of bit (1 or 0). 01346 */ 01347 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) 01348 { 01349 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); 01350 } 01351 01352 /** 01353 * @brief Get Channel 7 global interrupt flag. 01354 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 01355 * @param DMAx DMAx Instance 01356 * @retval State of bit (1 or 0). 01357 */ 01358 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) 01359 { 01360 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); 01361 } 01362 01363 /** 01364 * @brief Get Channel 1 transfer complete flag. 01365 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 01366 * @param DMAx DMAx Instance 01367 * @retval State of bit (1 or 0). 01368 */ 01369 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 01370 { 01371 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); 01372 } 01373 01374 /** 01375 * @brief Get Channel 2 transfer complete flag. 01376 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 01377 * @param DMAx DMAx Instance 01378 * @retval State of bit (1 or 0). 01379 */ 01380 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 01381 { 01382 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); 01383 } 01384 01385 /** 01386 * @brief Get Channel 3 transfer complete flag. 01387 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 01388 * @param DMAx DMAx Instance 01389 * @retval State of bit (1 or 0). 01390 */ 01391 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 01392 { 01393 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); 01394 } 01395 01396 /** 01397 * @brief Get Channel 4 transfer complete flag. 01398 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 01399 * @param DMAx DMAx Instance 01400 * @retval State of bit (1 or 0). 01401 */ 01402 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 01403 { 01404 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); 01405 } 01406 01407 /** 01408 * @brief Get Channel 5 transfer complete flag. 01409 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 01410 * @param DMAx DMAx Instance 01411 * @retval State of bit (1 or 0). 01412 */ 01413 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 01414 { 01415 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); 01416 } 01417 01418 /** 01419 * @brief Get Channel 6 transfer complete flag. 01420 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 01421 * @param DMAx DMAx Instance 01422 * @retval State of bit (1 or 0). 01423 */ 01424 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 01425 { 01426 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); 01427 } 01428 01429 /** 01430 * @brief Get Channel 7 transfer complete flag. 01431 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 01432 * @param DMAx DMAx Instance 01433 * @retval State of bit (1 or 0). 01434 */ 01435 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 01436 { 01437 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); 01438 } 01439 01440 /** 01441 * @brief Get Channel 1 half transfer flag. 01442 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 01443 * @param DMAx DMAx Instance 01444 * @retval State of bit (1 or 0). 01445 */ 01446 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 01447 { 01448 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); 01449 } 01450 01451 /** 01452 * @brief Get Channel 2 half transfer flag. 01453 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 01454 * @param DMAx DMAx Instance 01455 * @retval State of bit (1 or 0). 01456 */ 01457 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 01458 { 01459 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); 01460 } 01461 01462 /** 01463 * @brief Get Channel 3 half transfer flag. 01464 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 01465 * @param DMAx DMAx Instance 01466 * @retval State of bit (1 or 0). 01467 */ 01468 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 01469 { 01470 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); 01471 } 01472 01473 /** 01474 * @brief Get Channel 4 half transfer flag. 01475 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 01476 * @param DMAx DMAx Instance 01477 * @retval State of bit (1 or 0). 01478 */ 01479 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 01480 { 01481 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); 01482 } 01483 01484 /** 01485 * @brief Get Channel 5 half transfer flag. 01486 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 01487 * @param DMAx DMAx Instance 01488 * @retval State of bit (1 or 0). 01489 */ 01490 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 01491 { 01492 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); 01493 } 01494 01495 /** 01496 * @brief Get Channel 6 half transfer flag. 01497 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 01498 * @param DMAx DMAx Instance 01499 * @retval State of bit (1 or 0). 01500 */ 01501 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 01502 { 01503 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); 01504 } 01505 01506 /** 01507 * @brief Get Channel 7 half transfer flag. 01508 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 01509 * @param DMAx DMAx Instance 01510 * @retval State of bit (1 or 0). 01511 */ 01512 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 01513 { 01514 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); 01515 } 01516 01517 /** 01518 * @brief Get Channel 1 transfer error flag. 01519 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 01520 * @param DMAx DMAx Instance 01521 * @retval State of bit (1 or 0). 01522 */ 01523 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 01524 { 01525 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); 01526 } 01527 01528 /** 01529 * @brief Get Channel 2 transfer error flag. 01530 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 01531 * @param DMAx DMAx Instance 01532 * @retval State of bit (1 or 0). 01533 */ 01534 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 01535 { 01536 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); 01537 } 01538 01539 /** 01540 * @brief Get Channel 3 transfer error flag. 01541 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 01542 * @param DMAx DMAx Instance 01543 * @retval State of bit (1 or 0). 01544 */ 01545 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 01546 { 01547 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); 01548 } 01549 01550 /** 01551 * @brief Get Channel 4 transfer error flag. 01552 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 01553 * @param DMAx DMAx Instance 01554 * @retval State of bit (1 or 0). 01555 */ 01556 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 01557 { 01558 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); 01559 } 01560 01561 /** 01562 * @brief Get Channel 5 transfer error flag. 01563 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 01564 * @param DMAx DMAx Instance 01565 * @retval State of bit (1 or 0). 01566 */ 01567 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 01568 { 01569 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); 01570 } 01571 01572 /** 01573 * @brief Get Channel 6 transfer error flag. 01574 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 01575 * @param DMAx DMAx Instance 01576 * @retval State of bit (1 or 0). 01577 */ 01578 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 01579 { 01580 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); 01581 } 01582 01583 /** 01584 * @brief Get Channel 7 transfer error flag. 01585 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 01586 * @param DMAx DMAx Instance 01587 * @retval State of bit (1 or 0). 01588 */ 01589 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 01590 { 01591 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); 01592 } 01593 01594 /** 01595 * @brief Clear Channel 1 global interrupt flag. 01596 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 01597 * @param DMAx DMAx Instance 01598 * @retval None 01599 */ 01600 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) 01601 { 01602 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1); 01603 } 01604 01605 /** 01606 * @brief Clear Channel 2 global interrupt flag. 01607 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 01608 * @param DMAx DMAx Instance 01609 * @retval None 01610 */ 01611 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) 01612 { 01613 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2); 01614 } 01615 01616 /** 01617 * @brief Clear Channel 3 global interrupt flag. 01618 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 01619 * @param DMAx DMAx Instance 01620 * @retval None 01621 */ 01622 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) 01623 { 01624 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3); 01625 } 01626 01627 /** 01628 * @brief Clear Channel 4 global interrupt flag. 01629 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 01630 * @param DMAx DMAx Instance 01631 * @retval None 01632 */ 01633 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) 01634 { 01635 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4); 01636 } 01637 01638 /** 01639 * @brief Clear Channel 5 global interrupt flag. 01640 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 01641 * @param DMAx DMAx Instance 01642 * @retval None 01643 */ 01644 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) 01645 { 01646 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5); 01647 } 01648 01649 /** 01650 * @brief Clear Channel 6 global interrupt flag. 01651 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 01652 * @param DMAx DMAx Instance 01653 * @retval None 01654 */ 01655 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) 01656 { 01657 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6); 01658 } 01659 01660 /** 01661 * @brief Clear Channel 7 global interrupt flag. 01662 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 01663 * @param DMAx DMAx Instance 01664 * @retval None 01665 */ 01666 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) 01667 { 01668 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7); 01669 } 01670 01671 /** 01672 * @brief Clear Channel 1 transfer complete flag. 01673 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 01674 * @param DMAx DMAx Instance 01675 * @retval None 01676 */ 01677 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 01678 { 01679 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1); 01680 } 01681 01682 /** 01683 * @brief Clear Channel 2 transfer complete flag. 01684 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 01685 * @param DMAx DMAx Instance 01686 * @retval None 01687 */ 01688 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 01689 { 01690 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2); 01691 } 01692 01693 /** 01694 * @brief Clear Channel 3 transfer complete flag. 01695 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 01696 * @param DMAx DMAx Instance 01697 * @retval None 01698 */ 01699 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 01700 { 01701 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3); 01702 } 01703 01704 /** 01705 * @brief Clear Channel 4 transfer complete flag. 01706 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 01707 * @param DMAx DMAx Instance 01708 * @retval None 01709 */ 01710 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 01711 { 01712 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4); 01713 } 01714 01715 /** 01716 * @brief Clear Channel 5 transfer complete flag. 01717 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 01718 * @param DMAx DMAx Instance 01719 * @retval None 01720 */ 01721 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 01722 { 01723 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5); 01724 } 01725 01726 /** 01727 * @brief Clear Channel 6 transfer complete flag. 01728 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 01729 * @param DMAx DMAx Instance 01730 * @retval None 01731 */ 01732 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 01733 { 01734 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6); 01735 } 01736 01737 /** 01738 * @brief Clear Channel 7 transfer complete flag. 01739 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 01740 * @param DMAx DMAx Instance 01741 * @retval None 01742 */ 01743 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 01744 { 01745 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7); 01746 } 01747 01748 /** 01749 * @brief Clear Channel 1 half transfer flag. 01750 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 01751 * @param DMAx DMAx Instance 01752 * @retval None 01753 */ 01754 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 01755 { 01756 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1); 01757 } 01758 01759 /** 01760 * @brief Clear Channel 2 half transfer flag. 01761 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 01762 * @param DMAx DMAx Instance 01763 * @retval None 01764 */ 01765 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 01766 { 01767 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2); 01768 } 01769 01770 /** 01771 * @brief Clear Channel 3 half transfer flag. 01772 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 01773 * @param DMAx DMAx Instance 01774 * @retval None 01775 */ 01776 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 01777 { 01778 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3); 01779 } 01780 01781 /** 01782 * @brief Clear Channel 4 half transfer flag. 01783 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 01784 * @param DMAx DMAx Instance 01785 * @retval None 01786 */ 01787 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 01788 { 01789 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4); 01790 } 01791 01792 /** 01793 * @brief Clear Channel 5 half transfer flag. 01794 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 01795 * @param DMAx DMAx Instance 01796 * @retval None 01797 */ 01798 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 01799 { 01800 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5); 01801 } 01802 01803 /** 01804 * @brief Clear Channel 6 half transfer flag. 01805 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 01806 * @param DMAx DMAx Instance 01807 * @retval None 01808 */ 01809 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 01810 { 01811 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6); 01812 } 01813 01814 /** 01815 * @brief Clear Channel 7 half transfer flag. 01816 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 01817 * @param DMAx DMAx Instance 01818 * @retval None 01819 */ 01820 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 01821 { 01822 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7); 01823 } 01824 01825 /** 01826 * @brief Clear Channel 1 transfer error flag. 01827 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 01828 * @param DMAx DMAx Instance 01829 * @retval None 01830 */ 01831 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 01832 { 01833 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1); 01834 } 01835 01836 /** 01837 * @brief Clear Channel 2 transfer error flag. 01838 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 01839 * @param DMAx DMAx Instance 01840 * @retval None 01841 */ 01842 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 01843 { 01844 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2); 01845 } 01846 01847 /** 01848 * @brief Clear Channel 3 transfer error flag. 01849 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 01850 * @param DMAx DMAx Instance 01851 * @retval None 01852 */ 01853 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 01854 { 01855 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3); 01856 } 01857 01858 /** 01859 * @brief Clear Channel 4 transfer error flag. 01860 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 01861 * @param DMAx DMAx Instance 01862 * @retval None 01863 */ 01864 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 01865 { 01866 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4); 01867 } 01868 01869 /** 01870 * @brief Clear Channel 5 transfer error flag. 01871 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 01872 * @param DMAx DMAx Instance 01873 * @retval None 01874 */ 01875 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 01876 { 01877 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5); 01878 } 01879 01880 /** 01881 * @brief Clear Channel 6 transfer error flag. 01882 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 01883 * @param DMAx DMAx Instance 01884 * @retval None 01885 */ 01886 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 01887 { 01888 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6); 01889 } 01890 01891 /** 01892 * @brief Clear Channel 7 transfer error flag. 01893 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 01894 * @param DMAx DMAx Instance 01895 * @retval None 01896 */ 01897 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 01898 { 01899 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7); 01900 } 01901 01902 /** 01903 * @} 01904 */ 01905 01906 /** @defgroup DMA_LL_EF_IT_Management IT_Management 01907 * @{ 01908 */ 01909 /** 01910 * @brief Enable Transfer complete interrupt. 01911 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC 01912 * @param DMAx DMAx Instance 01913 * @param Channel This parameter can be one of the following values: 01914 * @arg @ref LL_DMA_CHANNEL_1 01915 * @arg @ref LL_DMA_CHANNEL_2 01916 * @arg @ref LL_DMA_CHANNEL_3 01917 * @arg @ref LL_DMA_CHANNEL_4 01918 * @arg @ref LL_DMA_CHANNEL_5 01919 * @arg @ref LL_DMA_CHANNEL_6 01920 * @arg @ref LL_DMA_CHANNEL_7 01921 * @retval None 01922 */ 01923 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 01924 { 01925 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); 01926 } 01927 01928 /** 01929 * @brief Enable Half transfer interrupt. 01930 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT 01931 * @param DMAx DMAx Instance 01932 * @param Channel This parameter can be one of the following values: 01933 * @arg @ref LL_DMA_CHANNEL_1 01934 * @arg @ref LL_DMA_CHANNEL_2 01935 * @arg @ref LL_DMA_CHANNEL_3 01936 * @arg @ref LL_DMA_CHANNEL_4 01937 * @arg @ref LL_DMA_CHANNEL_5 01938 * @arg @ref LL_DMA_CHANNEL_6 01939 * @arg @ref LL_DMA_CHANNEL_7 01940 * @retval None 01941 */ 01942 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 01943 { 01944 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); 01945 } 01946 01947 /** 01948 * @brief Enable Transfer error interrupt. 01949 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE 01950 * @param DMAx DMAx Instance 01951 * @param Channel This parameter can be one of the following values: 01952 * @arg @ref LL_DMA_CHANNEL_1 01953 * @arg @ref LL_DMA_CHANNEL_2 01954 * @arg @ref LL_DMA_CHANNEL_3 01955 * @arg @ref LL_DMA_CHANNEL_4 01956 * @arg @ref LL_DMA_CHANNEL_5 01957 * @arg @ref LL_DMA_CHANNEL_6 01958 * @arg @ref LL_DMA_CHANNEL_7 01959 * @retval None 01960 */ 01961 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 01962 { 01963 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); 01964 } 01965 01966 /** 01967 * @brief Disable Transfer complete interrupt. 01968 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC 01969 * @param DMAx DMAx Instance 01970 * @param Channel This parameter can be one of the following values: 01971 * @arg @ref LL_DMA_CHANNEL_1 01972 * @arg @ref LL_DMA_CHANNEL_2 01973 * @arg @ref LL_DMA_CHANNEL_3 01974 * @arg @ref LL_DMA_CHANNEL_4 01975 * @arg @ref LL_DMA_CHANNEL_5 01976 * @arg @ref LL_DMA_CHANNEL_6 01977 * @arg @ref LL_DMA_CHANNEL_7 01978 * @retval None 01979 */ 01980 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 01981 { 01982 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); 01983 } 01984 01985 /** 01986 * @brief Disable Half transfer interrupt. 01987 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT 01988 * @param DMAx DMAx Instance 01989 * @param Channel This parameter can be one of the following values: 01990 * @arg @ref LL_DMA_CHANNEL_1 01991 * @arg @ref LL_DMA_CHANNEL_2 01992 * @arg @ref LL_DMA_CHANNEL_3 01993 * @arg @ref LL_DMA_CHANNEL_4 01994 * @arg @ref LL_DMA_CHANNEL_5 01995 * @arg @ref LL_DMA_CHANNEL_6 01996 * @arg @ref LL_DMA_CHANNEL_7 01997 * @retval None 01998 */ 01999 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 02000 { 02001 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); 02002 } 02003 02004 /** 02005 * @brief Disable Transfer error interrupt. 02006 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE 02007 * @param DMAx DMAx Instance 02008 * @param Channel This parameter can be one of the following values: 02009 * @arg @ref LL_DMA_CHANNEL_1 02010 * @arg @ref LL_DMA_CHANNEL_2 02011 * @arg @ref LL_DMA_CHANNEL_3 02012 * @arg @ref LL_DMA_CHANNEL_4 02013 * @arg @ref LL_DMA_CHANNEL_5 02014 * @arg @ref LL_DMA_CHANNEL_6 02015 * @arg @ref LL_DMA_CHANNEL_7 02016 * @retval None 02017 */ 02018 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 02019 { 02020 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); 02021 } 02022 02023 /** 02024 * @brief Check if Transfer complete Interrupt is enabled. 02025 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC 02026 * @param DMAx DMAx Instance 02027 * @param Channel This parameter can be one of the following values: 02028 * @arg @ref LL_DMA_CHANNEL_1 02029 * @arg @ref LL_DMA_CHANNEL_2 02030 * @arg @ref LL_DMA_CHANNEL_3 02031 * @arg @ref LL_DMA_CHANNEL_4 02032 * @arg @ref LL_DMA_CHANNEL_5 02033 * @arg @ref LL_DMA_CHANNEL_6 02034 * @arg @ref LL_DMA_CHANNEL_7 02035 * @retval State of bit (1 or 0). 02036 */ 02037 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 02038 { 02039 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 02040 DMA_CCR_TCIE) == (DMA_CCR_TCIE)); 02041 } 02042 02043 /** 02044 * @brief Check if Half transfer Interrupt is enabled. 02045 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT 02046 * @param DMAx DMAx Instance 02047 * @param Channel This parameter can be one of the following values: 02048 * @arg @ref LL_DMA_CHANNEL_1 02049 * @arg @ref LL_DMA_CHANNEL_2 02050 * @arg @ref LL_DMA_CHANNEL_3 02051 * @arg @ref LL_DMA_CHANNEL_4 02052 * @arg @ref LL_DMA_CHANNEL_5 02053 * @arg @ref LL_DMA_CHANNEL_6 02054 * @arg @ref LL_DMA_CHANNEL_7 02055 * @retval State of bit (1 or 0). 02056 */ 02057 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 02058 { 02059 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 02060 DMA_CCR_HTIE) == (DMA_CCR_HTIE)); 02061 } 02062 02063 /** 02064 * @brief Check if Transfer error Interrupt is enabled. 02065 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE 02066 * @param DMAx DMAx Instance 02067 * @param Channel This parameter can be one of the following values: 02068 * @arg @ref LL_DMA_CHANNEL_1 02069 * @arg @ref LL_DMA_CHANNEL_2 02070 * @arg @ref LL_DMA_CHANNEL_3 02071 * @arg @ref LL_DMA_CHANNEL_4 02072 * @arg @ref LL_DMA_CHANNEL_5 02073 * @arg @ref LL_DMA_CHANNEL_6 02074 * @arg @ref LL_DMA_CHANNEL_7 02075 * @retval State of bit (1 or 0). 02076 */ 02077 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 02078 { 02079 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 02080 DMA_CCR_TEIE) == (DMA_CCR_TEIE)); 02081 } 02082 02083 /** 02084 * @} 02085 */ 02086 02087 #if defined(USE_FULL_LL_DRIVER) 02088 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions 02089 * @{ 02090 */ 02091 02092 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); 02093 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); 02094 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); 02095 02096 /** 02097 * @} 02098 */ 02099 #endif /* USE_FULL_LL_DRIVER */ 02100 02101 /** 02102 * @} 02103 */ 02104 02105 /** 02106 * @} 02107 */ 02108 02109 #endif /* DMA1 || DMA2 */ 02110 02111 /** 02112 * @} 02113 */ 02114 02115 #ifdef __cplusplus 02116 } 02117 #endif 02118 02119 #endif /* __STM32L4xx_LL_DMA_H */ 02120 02121 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jul 12 2022 17:38:50 by
1.7.2