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stm32l4xx_ll_dma.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_dma.c 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief DMA LL module driver. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 #if defined(USE_FULL_LL_DRIVER) 00038 00039 /* Includes ------------------------------------------------------------------*/ 00040 #include "stm32l4xx_ll_dma.h" 00041 #include "stm32l4xx_ll_bus.h" 00042 #ifdef USE_FULL_ASSERT 00043 #include "stm32_assert.h" 00044 #else 00045 #define assert_param(expr) ((void)0U) 00046 #endif 00047 00048 /** @addtogroup STM32L4xx_LL_Driver 00049 * @{ 00050 */ 00051 00052 #if defined (DMA1) || defined (DMA2) 00053 00054 /** @defgroup DMA_LL DMA 00055 * @{ 00056 */ 00057 00058 /* Private types -------------------------------------------------------------*/ 00059 /* Private variables ---------------------------------------------------------*/ 00060 /* Private constants ---------------------------------------------------------*/ 00061 /* Private macros ------------------------------------------------------------*/ 00062 /** @addtogroup DMA_LL_Private_Macros 00063 * @{ 00064 */ 00065 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ 00066 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ 00067 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) 00068 00069 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ 00070 ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) 00071 00072 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ 00073 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) 00074 00075 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ 00076 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) 00077 00078 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ 00079 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ 00080 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) 00081 00082 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ 00083 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ 00084 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) 00085 00086 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU) 00087 00088 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \ 00089 ((__VALUE__) == LL_DMA_REQUEST_1) || \ 00090 ((__VALUE__) == LL_DMA_REQUEST_2) || \ 00091 ((__VALUE__) == LL_DMA_REQUEST_3) || \ 00092 ((__VALUE__) == LL_DMA_REQUEST_4) || \ 00093 ((__VALUE__) == LL_DMA_REQUEST_5) || \ 00094 ((__VALUE__) == LL_DMA_REQUEST_6) || \ 00095 ((__VALUE__) == LL_DMA_REQUEST_7)) 00096 00097 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ 00098 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ 00099 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ 00100 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) 00101 00102 #if defined (DMA2) 00103 #if defined (DMA2_Channel6) && defined (DMA2_Channel7) 00104 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ 00105 (((CHANNEL) == LL_DMA_CHANNEL_1) || \ 00106 ((CHANNEL) == LL_DMA_CHANNEL_2) || \ 00107 ((CHANNEL) == LL_DMA_CHANNEL_3) || \ 00108 ((CHANNEL) == LL_DMA_CHANNEL_4) || \ 00109 ((CHANNEL) == LL_DMA_CHANNEL_5) || \ 00110 ((CHANNEL) == LL_DMA_CHANNEL_6) || \ 00111 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ 00112 (((INSTANCE) == DMA2) && \ 00113 (((CHANNEL) == LL_DMA_CHANNEL_1) || \ 00114 ((CHANNEL) == LL_DMA_CHANNEL_2) || \ 00115 ((CHANNEL) == LL_DMA_CHANNEL_3) || \ 00116 ((CHANNEL) == LL_DMA_CHANNEL_4) || \ 00117 ((CHANNEL) == LL_DMA_CHANNEL_5) || \ 00118 ((CHANNEL) == LL_DMA_CHANNEL_6) || \ 00119 ((CHANNEL) == LL_DMA_CHANNEL_7)))) 00120 #else 00121 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ 00122 (((CHANNEL) == LL_DMA_CHANNEL_1) || \ 00123 ((CHANNEL) == LL_DMA_CHANNEL_2) || \ 00124 ((CHANNEL) == LL_DMA_CHANNEL_3) || \ 00125 ((CHANNEL) == LL_DMA_CHANNEL_4) || \ 00126 ((CHANNEL) == LL_DMA_CHANNEL_5) || \ 00127 ((CHANNEL) == LL_DMA_CHANNEL_6) || \ 00128 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ 00129 (((INSTANCE) == DMA2) && \ 00130 (((CHANNEL) == LL_DMA_CHANNEL_1) || \ 00131 ((CHANNEL) == LL_DMA_CHANNEL_2) || \ 00132 ((CHANNEL) == LL_DMA_CHANNEL_3) || \ 00133 ((CHANNEL) == LL_DMA_CHANNEL_4) || \ 00134 ((CHANNEL) == LL_DMA_CHANNEL_5)))) 00135 #endif 00136 #else 00137 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ 00138 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ 00139 ((CHANNEL) == LL_DMA_CHANNEL_2) || \ 00140 ((CHANNEL) == LL_DMA_CHANNEL_3) || \ 00141 ((CHANNEL) == LL_DMA_CHANNEL_4) || \ 00142 ((CHANNEL) == LL_DMA_CHANNEL_5) || \ 00143 ((CHANNEL) == LL_DMA_CHANNEL_6) || \ 00144 ((CHANNEL) == LL_DMA_CHANNEL_7)))) 00145 #endif 00146 /** 00147 * @} 00148 */ 00149 00150 /* Private function prototypes -----------------------------------------------*/ 00151 00152 /* Exported functions --------------------------------------------------------*/ 00153 /** @addtogroup DMA_LL_Exported_Functions 00154 * @{ 00155 */ 00156 00157 /** @addtogroup DMA_LL_EF_Init 00158 * @{ 00159 */ 00160 00161 /** 00162 * @brief De-initialize the DMA registers to their default reset values. 00163 * @param DMAx DMAx Instance 00164 * @param Channel This parameter can be one of the following values: 00165 * @arg @ref LL_DMA_CHANNEL_1 00166 * @arg @ref LL_DMA_CHANNEL_2 00167 * @arg @ref LL_DMA_CHANNEL_3 00168 * @arg @ref LL_DMA_CHANNEL_4 00169 * @arg @ref LL_DMA_CHANNEL_5 00170 * @arg @ref LL_DMA_CHANNEL_6 00171 * @arg @ref LL_DMA_CHANNEL_7 00172 * @arg @ref LL_DMA_CHANNEL_ALL 00173 * @retval An ErrorStatus enumeration value: 00174 * - SUCCESS: DMA registers are de-initialized 00175 * - ERROR: DMA registers are not de-initialized 00176 */ 00177 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) 00178 { 00179 DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; 00180 ErrorStatus status = SUCCESS; 00181 00182 /* Check the DMA Instance DMAx and Channel parameters*/ 00183 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL)); 00184 00185 if (Channel == LL_DMA_CHANNEL_ALL) 00186 { 00187 if (DMAx == DMA1) 00188 { 00189 /* Force reset of DMA clock */ 00190 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); 00191 00192 /* Release reset of DMA clock */ 00193 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); 00194 } 00195 #if defined(DMA2) 00196 else if (DMAx == DMA2) 00197 { 00198 /* Force reset of DMA clock */ 00199 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); 00200 00201 /* Release reset of DMA clock */ 00202 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); 00203 } 00204 #endif 00205 else 00206 { 00207 status = ERROR; 00208 } 00209 } 00210 else 00211 { 00212 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); 00213 00214 /* Disable the selected DMAx_Channely */ 00215 CLEAR_BIT(tmp->CCR, DMA_CCR_EN); 00216 00217 /* Reset DMAx_Channely control register */ 00218 LL_DMA_WriteReg(tmp, CCR, 0U); 00219 00220 /* Reset DMAx_Channely remaining bytes register */ 00221 LL_DMA_WriteReg(tmp, CNDTR, 0U); 00222 00223 /* Reset DMAx_Channely peripheral address register */ 00224 LL_DMA_WriteReg(tmp, CPAR, 0U); 00225 00226 /* Reset DMAx_Channely memory address register */ 00227 LL_DMA_WriteReg(tmp, CMAR, 0U); 00228 00229 /* Reset Request register field for DMAx Channel */ 00230 LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0); 00231 00232 if (Channel == LL_DMA_CHANNEL_1) 00233 { 00234 /* Reset interrupt pending bits for DMAx Channel1 */ 00235 LL_DMA_ClearFlag_GI1(DMAx); 00236 } 00237 else if (Channel == LL_DMA_CHANNEL_2) 00238 { 00239 /* Reset interrupt pending bits for DMAx Channel2 */ 00240 LL_DMA_ClearFlag_GI2(DMAx); 00241 } 00242 else if (Channel == LL_DMA_CHANNEL_3) 00243 { 00244 /* Reset interrupt pending bits for DMAx Channel3 */ 00245 LL_DMA_ClearFlag_GI3(DMAx); 00246 } 00247 else if (Channel == LL_DMA_CHANNEL_4) 00248 { 00249 /* Reset interrupt pending bits for DMAx Channel4 */ 00250 LL_DMA_ClearFlag_GI4(DMAx); 00251 } 00252 else if (Channel == LL_DMA_CHANNEL_5) 00253 { 00254 /* Reset interrupt pending bits for DMAx Channel5 */ 00255 LL_DMA_ClearFlag_GI5(DMAx); 00256 } 00257 00258 else if (Channel == LL_DMA_CHANNEL_6) 00259 { 00260 /* Reset interrupt pending bits for DMAx Channel6 */ 00261 LL_DMA_ClearFlag_GI6(DMAx); 00262 } 00263 else if (Channel == LL_DMA_CHANNEL_7) 00264 { 00265 /* Reset interrupt pending bits for DMAx Channel7 */ 00266 LL_DMA_ClearFlag_GI7(DMAx); 00267 } 00268 else 00269 { 00270 status = ERROR; 00271 } 00272 } 00273 00274 return status; 00275 } 00276 00277 /** 00278 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. 00279 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : 00280 * @arg @ref __LL_DMA_GET_INSTANCE 00281 * @arg @ref __LL_DMA_GET_CHANNEL 00282 * @param DMAx DMAx Instance 00283 * @param Channel This parameter can be one of the following values: 00284 * @arg @ref LL_DMA_CHANNEL_1 00285 * @arg @ref LL_DMA_CHANNEL_2 00286 * @arg @ref LL_DMA_CHANNEL_3 00287 * @arg @ref LL_DMA_CHANNEL_4 00288 * @arg @ref LL_DMA_CHANNEL_5 00289 * @arg @ref LL_DMA_CHANNEL_6 00290 * @arg @ref LL_DMA_CHANNEL_7 00291 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. 00292 * @retval An ErrorStatus enumeration value: 00293 * - SUCCESS: DMA registers are initialized 00294 * - ERROR: Not applicable 00295 */ 00296 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) 00297 { 00298 /* Check the DMA Instance DMAx and Channel parameters*/ 00299 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); 00300 00301 /* Check the DMA parameters from DMA_InitStruct */ 00302 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); 00303 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); 00304 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); 00305 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); 00306 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); 00307 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); 00308 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); 00309 assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest)); 00310 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); 00311 00312 /*---------------------------- DMAx CCR Configuration ------------------------ 00313 * Configure DMAx_Channely: data transfer direction, data transfer mode, 00314 * peripheral and memory increment mode, 00315 * data size alignment and priority level with parameters : 00316 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits 00317 * - Mode: DMA_CCR_CIRC bit 00318 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit 00319 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit 00320 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits 00321 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits 00322 * - Priority: DMA_CCR_PL[1:0] bits 00323 */ 00324 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ 00325 DMA_InitStruct->Mode | \ 00326 DMA_InitStruct->PeriphOrM2MSrcIncMode | \ 00327 DMA_InitStruct->MemoryOrM2MDstIncMode | \ 00328 DMA_InitStruct->PeriphOrM2MSrcDataSize | \ 00329 DMA_InitStruct->MemoryOrM2MDstDataSize | \ 00330 DMA_InitStruct->Priority); 00331 00332 /*-------------------------- DMAx CMAR Configuration ------------------------- 00333 * Configure the memory or destination base address with parameter : 00334 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits 00335 */ 00336 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); 00337 00338 /*-------------------------- DMAx CPAR Configuration ------------------------- 00339 * Configure the peripheral or source base address with parameter : 00340 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits 00341 */ 00342 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); 00343 00344 /*--------------------------- DMAx CNDTR Configuration ----------------------- 00345 * Configure the peripheral base address with parameter : 00346 * - NbData: DMA_CNDTR_NDT[15:0] bits 00347 */ 00348 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); 00349 00350 /*--------------------------- DMAx CSELR Configuration ----------------------- 00351 * Configure the peripheral base address with parameter : 00352 * - PeriphRequest: DMA_CSELR[31:0] bits 00353 */ 00354 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); 00355 00356 return SUCCESS; 00357 } 00358 00359 /** 00360 * @brief Set each @ref LL_DMA_InitTypeDef field to default value. 00361 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. 00362 * @retval None 00363 */ 00364 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) 00365 { 00366 /* Set DMA_InitStruct fields to default values */ 00367 DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U; 00368 DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U; 00369 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; 00370 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; 00371 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; 00372 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; 00373 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; 00374 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; 00375 DMA_InitStruct->NbData = (uint32_t)0x00000000U; 00376 DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; 00377 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; 00378 } 00379 00380 /** 00381 * @} 00382 */ 00383 00384 /** 00385 * @} 00386 */ 00387 00388 /** 00389 * @} 00390 */ 00391 00392 #endif /* DMA1 || DMA2 */ 00393 00394 /** 00395 * @} 00396 */ 00397 00398 #endif /* USE_FULL_LL_DRIVER */ 00399 00400 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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