stm32l4xx_ll_dac.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_dac.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of DAC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_DAC_H
00040 #define __STM32L4xx_LL_DAC_H
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048 
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052 
00053 #if defined (DAC1)
00054 
00055 /** @defgroup DAC_LL DAC
00056   * @{
00057   */
00058 
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
00064   * @{
00065   */
00066 
00067 /* Internal masks for DAC channels definition */
00068 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
00069 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR            */
00070 /* - channel bits position into register SWTRIG                               */
00071 /* - channel register offset of data holding register DHRx                    */
00072 /* - channel register offset of data output register DORx                     */
00073 /* - channel register offset of sample-and-hold sample time register SHSRx    */
00074 
00075 #define DAC_CR_CH1_BITOFFSET           ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
00076 #define DAC_CR_CH2_BITOFFSET           ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
00077 #define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
00078 
00079 #define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
00080 #define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
00081 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
00082 
00083 #define DAC_REG_DHR12R1_REGOFFSET      ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
00084 #define DAC_REG_DHR12L1_REGOFFSET      ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00085 #define DAC_REG_DHR8R1_REGOFFSET       ((uint32_t)0x02000000U) /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00086 #define DAC_REG_DHR12R2_REGOFFSET      ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
00087 #define DAC_REG_DHR12L2_REGOFFSET      ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00088 #define DAC_REG_DHR8R2_REGOFFSET       ((uint32_t)0x05000000U) /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00089 #define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
00090 #define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
00091 #define DAC_REG_DHR8RX_REGOFFSET_MASK  ((uint32_t)0x0F000000U)
00092 #define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
00093 
00094 #define DAC_REG_DOR1_REGOFFSET         ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
00095 #define DAC_REG_DOR2_REGOFFSET         ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
00096 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
00097 
00098 #define DAC_REG_SHSR1_REGOFFSET        ((uint32_t)0x00000000U) /* Register SHSRx channel 1 taken as reference */
00099 #define DAC_REG_SHSR2_REGOFFSET        ((uint32_t)0x00001000U) /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */
00100 #define DAC_REG_SHSRX_REGOFFSET_MASK   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
00101 
00102 /* DAC registers bits positions */
00103 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
00104 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
00105 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS  ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
00106 
00107 /* Miscellaneous data */
00108 #define DAC_DIGITAL_SCALE_12BITS           ((uint32_t)4095U)                     /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
00109 
00110 /**
00111   * @}
00112   */
00113 
00114 
00115 /* Private macros ------------------------------------------------------------*/
00116 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
00117   * @{
00118   */
00119 
00120 /**
00121   * @brief  Driver macro reserved for internal use: isolate bits with the
00122   *         selected mask and shift them to the register LSB
00123   *         (shift mask on register position bit 0).
00124   * @param  __BITS__ Bits in register 32 bits
00125   * @param  __MASK__ Mask in register 32 bits
00126   * @retval Bits in register 32 bits
00127 */
00128 #define __DAC_MASK_SHIFT(__BITS__, __MASK__)                                   \
00129   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
00130 
00131 /**
00132   * @brief  Driver macro reserved for internal use: set a pointer to
00133   *         a register from a register basis from which an offset
00134   *         is applied.
00135   * @param  __REG__ Register basis from which the offset is applied.
00136   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00137   * @retval Pointer to register address
00138 */
00139 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00140  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
00141 
00142 /**
00143   * @}
00144   */
00145 
00146 
00147 /* Exported types ------------------------------------------------------------*/
00148 #if defined(USE_FULL_LL_DRIVER)
00149 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
00150   * @{
00151   */
00152 
00153 /**
00154   * @brief  Structure definition of some features of DAC instance.
00155   */
00156 typedef struct
00157 {
00158   uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
00159                                              This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
00160                                              
00161                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
00162 
00163   uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
00164                                              This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
00165                                              
00166                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
00167 
00168   uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
00169                                              If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
00170                                              If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
00171                                              @note If waveform automatic generation mode is disabled, this parameter is discarded.
00172                                              
00173                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
00174 
00175   uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
00176                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
00177                                              
00178                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
00179 
00180   uint32_t OutputConnection;            /*!< Set the output connection for the selected DAC channel.
00181                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
00182                                              
00183                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
00184 
00185   uint32_t OutputMode;                  /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
00186                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
00187                                              
00188                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
00189 
00190 } LL_DAC_InitTypeDef;
00191 
00192 /**
00193   * @}
00194   */
00195 #endif /* USE_FULL_LL_DRIVER */
00196 
00197 /* Exported constants --------------------------------------------------------*/
00198 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
00199   * @{
00200   */
00201 
00202 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
00203   * @brief    Flags defines which can be used with LL_DAC_ReadReg function
00204   * @{
00205   */
00206 /* DAC channel 1 flags */
00207 #define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
00208 #define LL_DAC_FLAG_CAL1                   (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
00209 #define LL_DAC_FLAG_BWST1                  (DAC_SR_BWST1)     /*!< DAC channel 1 flag busy writing sample time */
00210 
00211 /* DAC channel 2 flags */
00212 #define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
00213 #define LL_DAC_FLAG_CAL2                   (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
00214 #define LL_DAC_FLAG_BWST2                  (DAC_SR_BWST2)     /*!< DAC channel 2 flag busy writing sample time */
00215 /**
00216   * @}
00217   */
00218 
00219 /** @defgroup DAC_LL_EC_IT DAC interruptions
00220   * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
00221   * @{
00222   */
00223 #define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
00224 #define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
00225 /**
00226   * @}
00227   */
00228 
00229 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
00230   * @{
00231   */
00232 #define LL_DAC_CHANNEL_1                   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
00233 #define LL_DAC_CHANNEL_2                   (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
00234 /**
00235   * @}
00236   */
00237 
00238 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
00239   * @{
00240   */
00241 #define LL_DAC_MODE_NORMAL_OPERATION       ((uint32_t)0x00000000U) /*!< DAC channel in mode normal operation */
00242 #define LL_DAC_MODE_CALIBRATION            (DAC_CR_CEN1)           /*!< DAC channel in mode calibration */
00243 /**
00244   * @}
00245   */
00246 
00247 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
00248   * @{
00249   */
00250 #define LL_DAC_TRIG_SOFTWARE               (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
00251 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
00252 #define LL_DAC_TRIG_EXT_TIM4_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
00253 #define LL_DAC_TRIG_EXT_TIM5_TRGO          (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
00254 #define LL_DAC_TRIG_EXT_TIM6_TRGO          ((uint32_t)0x00000000U)                            /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
00255 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
00256 #define LL_DAC_TRIG_EXT_TIM8_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
00257 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
00258 /**
00259   * @}
00260   */
00261 
00262 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
00263   * @{
00264   */
00265 #define LL_DAC_WAVE_AUTO_GENERATION_NONE     ((uint32_t)0x00000000U) /*!< DAC channel wave auto generation mode disabled. */
00266 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (DAC_CR_WAVE1_0)        /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
00267 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)        /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
00268 /**
00269   * @}
00270   */
00271 
00272 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
00273   * @{
00274   */
00275 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0      ((uint32_t)0x00000000U)                                             /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
00276 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
00277 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
00278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
00279 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
00280 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
00281 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
00282 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
00283 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
00284 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
00285 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
00286 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
00287 /**
00288   * @}
00289   */
00290 
00291 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
00292   * @{
00293   */
00294 #define LL_DAC_TRIANGLE_AMPLITUDE_1        ((uint32_t)0x00000000U)                                             /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
00295 #define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
00296 #define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
00297 #define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
00298 #define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
00299 #define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
00300 #define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
00301 #define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
00302 #define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
00303 #define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
00304 #define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
00305 #define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
00306 /**
00307   * @}
00308   */
00309 
00310 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
00311   * @{
00312   */
00313 #define LL_DAC_OUTPUT_MODE_NORMAL          ((uint32_t)0x00000000U) /*!< The selected DAC channel output is on mode normal. */
00314 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)       /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
00315 /**
00316   * @}
00317   */
00318 
00319 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
00320   * @{
00321   */
00322 #define LL_DAC_OUTPUT_BUFFER_ENABLE        ((uint32_t)0x00000000U) /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
00323 #define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_MCR_MODE1_1)       /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
00324 /**
00325   * @}
00326   */
00327 
00328 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
00329   * @{
00330   */
00331 #define LL_DAC_OUTPUT_CONNECT_GPIO         ((uint32_t)0x00000000U) /*!< The selected DAC channel output is connected to external pin */
00332 #define LL_DAC_OUTPUT_CONNECT_INTERNAL     (DAC_MCR_MODE1_0)       /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
00333 /**
00334   * @}
00335   */
00336 
00337 /** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming
00338   * @{
00339   */
00340 #define LL_DAC_TRIGGER_SOFTWARE            (LL_DAC_TRIG_SOFTWARE)
00341 #define LL_DAC_TRIGGER_TIM2_TRGO           (LL_DAC_TRIG_EXT_TIM2_TRGO)
00342 #define LL_DAC_TRIGGER_TIM4_TRGO           (LL_DAC_TRIG_EXT_TIM4_TRGO)
00343 #define LL_DAC_TRIGGER_TIM5_TRGO           (LL_DAC_TRIG_EXT_TIM5_TRGO)
00344 #define LL_DAC_TRIGGER_TIM6_TRGO           (LL_DAC_TRIG_EXT_TIM6_TRGO)
00345 #define LL_DAC_TRIGGER_TIM7_TRGO           (LL_DAC_TRIG_EXT_TIM7_TRGO)
00346 #define LL_DAC_TRIGGER_TIM8_TRGO           (LL_DAC_TRIG_EXT_TIM8_TRGO)
00347 #define LL_DAC_TRIGGER_EXT_IT9             (LL_DAC_TRIG_EXT_EXTI_LINE9)
00348 
00349 #define LL_DAC_WAVEGENERATION_NONE         (LL_DAC_WAVE_AUTO_GENERATION_NONE)
00350 #define LL_DAC_WAVEGENERATION_NOISE        (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
00351 #define LL_DAC_WAVEGENERATION_TRIANGLE     (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
00352 
00353 #define LL_DAC_CONNECT_GPIO                (LL_DAC_OUTPUT_CONNECT_GPIO)
00354 #define LL_DAC_CONNECT_INTERNAL            (LL_DAC_OUTPUT_CONNECT_INTERNAL)
00355 /**
00356   * @}
00357   */
00358 
00359 
00360 /** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
00361   * @{
00362   */
00363 #define LL_DAC_RESOLUTION_12B              ((uint32_t)0x00000000U) /*!< DAC channel resolution 12 bits */
00364 #define LL_DAC_RESOLUTION_8B               ((uint32_t)0x00000002U) /*!< DAC channel resolution 8 bits */
00365 /**
00366   * @}
00367   */
00368 
00369 /** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
00370   * @{
00371   */
00372 /* List of DAC registers intended to be used (most commonly) with             */
00373 /* DMA transfer.                                                              */
00374 /* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
00375 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
00376 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
00377 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_MASK  /*!< DAC channel data holding register 8 bits right aligned */
00378 /**
00379   * @}
00380   */
00381 
00382 /** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
00383   * @note   Only DAC IP HW delays are defined in DAC LL driver driver,
00384   *         not timeout values.
00385   *         For details on delays values, refer to descriptions in source code
00386   *         above each literal definition.
00387   * @{
00388   */
00389 
00390 /* Delay for DAC channel voltage settling time from DAC channel startup       */
00391 /* (transition from disable to enable).                                       */
00392 /* Note: DAC channel startup time depends on board application environment:   */
00393 /*       impedance connected to DAC channel output.                           */
00394 /*       The delay below is specified under conditions:                       */
00395 /*        - voltage maximum transition (lowest to highest value)              */
00396 /*        - until voltage reaches final value +-1LSB                          */
00397 /*        - DAC channel output buffer enabled                                 */
00398 /*        - load impedance of 5kOhm (min), 50pF (max)                         */
00399 /* Literal set to maximum value (refer to device datasheet,                   */
00400 /* parameter "tWAKEUP").                                                      */
00401 /* Unit: us                                                                   */
00402 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t)  8U)  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
00403 
00404 
00405 /* Delay for DAC channel voltage settling time.                               */
00406 /* Note: DAC channel startup time depends on board application environment:   */
00407 /*       impedance connected to DAC channel output.                           */
00408 /*       The delay below is specified under conditions:                       */
00409 /*        - voltage maximum transition (lowest to highest value)              */
00410 /*        - until voltage reaches final value +-1LSB                          */
00411 /*        - DAC channel output buffer enabled                                 */
00412 /*        - load impedance of 5kOhm min, 50pF max                             */
00413 /* Literal set to maximum value (refer to device datasheet,                   */
00414 /* parameter "tSETTLING").                                                    */
00415 /* Unit: us                                                                   */
00416 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US  ((uint32_t)  2U)  /*!< Delay for DAC channel voltage settling time */
00417 
00418 /**
00419   * @}
00420   */
00421 
00422 /**
00423   * @}
00424   */
00425 
00426 /* Exported macro ------------------------------------------------------------*/
00427 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
00428   * @{
00429   */
00430 
00431 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
00432   * @{
00433   */
00434 
00435 /**
00436   * @brief  Write a value in DAC register
00437   * @param  __INSTANCE__ DAC Instance
00438   * @param  __REG__ Register to be written
00439   * @param  __VALUE__ Value to be written in the register
00440   * @retval None
00441   */
00442 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00443 
00444 /**
00445   * @brief  Read a value in DAC register
00446   * @param  __INSTANCE__ DAC Instance
00447   * @param  __REG__ Register to be read
00448   * @retval Register value
00449   */
00450 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00451 
00452 /**
00453   * @}
00454   */
00455 
00456 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
00457   * @{
00458   */
00459 
00460 /**
00461   * @brief  Helper macro to get DAC channel number in decimal format
00462   *         from literals LL_DAC_CHANNEL_x.
00463   *         Example:
00464   *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
00465   *            will return decimal number "1".
00466   * @note   The input can be a value from functions where a channel
00467   *         number is returned.
00468   * @param  __CHANNEL__ This parameter can be one of the following values:
00469   *         @arg @ref LL_DAC_CHANNEL_1
00470   *         @arg @ref LL_DAC_CHANNEL_2
00471   * @retval 1...2
00472   */
00473 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
00474   ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
00475 
00476 /**
00477   * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
00478   *         from number in decimal format.
00479   *         Example:
00480   *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
00481   *           will return a data equivalent to "LL_DAC_CHANNEL_1".
00482   * @note  If the input parameter does not correspond to a DAC channel,
00483   *        this macro returns value '0'.
00484   * @param  __DECIMAL_NB__ 1...2
00485   * @retval Returned value can be one of the following values:
00486   *         @arg @ref LL_DAC_CHANNEL_1
00487   *         @arg @ref LL_DAC_CHANNEL_2
00488   */
00489 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
00490   (((__DECIMAL_NB__) == 1U)                                                     \
00491     ? (                                                                        \
00492        LL_DAC_CHANNEL_1                                                        \
00493       )                                                                        \
00494       :                                                                        \
00495       (((__DECIMAL_NB__) == 2U)                                                 \
00496         ? (                                                                    \
00497            LL_DAC_CHANNEL_2                                                    \
00498           )                                                                    \
00499           :                                                                    \
00500           (                                                                    \
00501            0                                                                   \
00502           )                                                                    \
00503       )                                                                        \
00504   )
00505 
00506 /**
00507   * @brief  Helper macro to define the DAC conversion data full-scale digital
00508   *         value corresponding to the selected DAC resolution.
00509   * @note   DAC conversion data full-scale corresponds to voltage range
00510   *         determined by analog voltage references Vref+ and Vref-
00511   *         (refer to reference manual).
00512   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00513   *         @arg @ref LL_DAC_RESOLUTION_12B
00514   *         @arg @ref LL_DAC_RESOLUTION_8B
00515   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
00516   */
00517 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
00518   (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
00519 
00520 /**
00521   * @brief  Helper macro to calculate the DAC conversion data (unit: digital
00522   *         value) corresponding to a voltage (unit: mVolt).
00523   * @note   This helper macro is intended to provide input data in voltage
00524   *         rather than digital value,
00525   *         to be used with LL DAC functions such as
00526   *         @ref LL_DAC_ConvertData12RightAligned().
00527   * @note   Analog reference voltage (Vref+) must be either known from
00528   *         user board environment or can be calculated using ADC measurement
00529   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
00530   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
00531   * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
00532   *                         (unit: mVolt).
00533   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00534   *         @arg @ref LL_DAC_RESOLUTION_12B
00535   *         @arg @ref LL_DAC_RESOLUTION_8B
00536   * @retval DAC conversion data (unit: digital value)
00537   */
00538 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
00539                                       __DAC_VOLTAGE__,\
00540                                       __DAC_RESOLUTION__)                      \
00541   ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
00542    / (__VREFANALOG_VOLTAGE__)                                                  \
00543   )
00544 
00545 /**
00546   * @}
00547   */
00548 
00549 /**
00550   * @}
00551   */
00552 
00553 
00554 /* Exported functions --------------------------------------------------------*/
00555 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
00556   * @{
00557   */
00558 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
00559   * @{
00560   */
00561 
00562 /**
00563   * @brief  Set the operating mode for the selected DAC channel:
00564   *         calibration or normal operating mode.
00565   * @rmtoll CR       CEN1           LL_DAC_SetMode\n
00566   *         CR       CEN2           LL_DAC_SetMode
00567   * @param  DACx DAC instance
00568   * @param  DAC_Channel This parameter can be one of the following values:
00569   *         @arg @ref LL_DAC_CHANNEL_1
00570   *         @arg @ref LL_DAC_CHANNEL_2
00571   * @param  ChannelMode This parameter can be one of the following values:
00572   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
00573   *         @arg @ref LL_DAC_MODE_CALIBRATION
00574   * @retval None
00575   */
00576 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
00577 {
00578   MODIFY_REG(DACx->CR,
00579              DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00580              ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00581 }
00582 
00583 /**
00584   * @brief  Get the operating mode for the selected DAC channel:
00585   *         calibration or normal operating mode.
00586   * @rmtoll CR       CEN1           LL_DAC_GetMode\n
00587   *         CR       CEN2           LL_DAC_GetMode
00588   * @param  DACx DAC instance
00589   * @param  DAC_Channel This parameter can be one of the following values:
00590   *         @arg @ref LL_DAC_CHANNEL_1
00591   *         @arg @ref LL_DAC_CHANNEL_2
00592   * @retval Returned value can be one of the following values:
00593   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
00594   *         @arg @ref LL_DAC_MODE_CALIBRATION
00595   */
00596 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00597 {
00598   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00599                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00600                    );
00601 }
00602 
00603 /**
00604   * @brief  Set the offset trimming value for the selected DAC channel.
00605   *         Trimming has an impact when output buffer is enabled
00606   *         and is intended to replace factory calibration default values.
00607   * @rmtoll CCR      OTRIM1         LL_DAC_SetTrimmingValue\n
00608   *         CCR      OTRIM2         LL_DAC_SetTrimmingValue
00609   * @param  DACx DAC instance
00610   * @param  DAC_Channel This parameter can be one of the following values:
00611   *         @arg @ref LL_DAC_CHANNEL_1
00612   *         @arg @ref LL_DAC_CHANNEL_2
00613   * @param  TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
00617 {
00618   MODIFY_REG(DACx->CCR,
00619              DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00620              TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00621 }
00622 
00623 /**
00624   * @brief  Get the offset trimming value for the selected DAC channel.
00625   *         Trimming has an impact when output buffer is enabled
00626   *         and is intended to replace factory calibration default values.
00627   * @rmtoll CCR      OTRIM1         LL_DAC_GetTrimmingValue\n
00628   *         CCR      OTRIM2         LL_DAC_GetTrimmingValue
00629   * @param  DACx DAC instance
00630   * @param  DAC_Channel This parameter can be one of the following values:
00631   *         @arg @ref LL_DAC_CHANNEL_1
00632   *         @arg @ref LL_DAC_CHANNEL_2
00633   * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
00634   */
00635 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00636 {
00637   return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00638                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00639                    );
00640 }
00641 
00642 /**
00643   * @brief  Set the conversion trigger source for the selected DAC channel.
00644   * @note   For conversion trigger source to be effective, DAC trigger
00645   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00646   * @note   To set conversion trigger source, DAC channel must be disabled.
00647   *         Otherwise, the setting is discarded.
00648   * @note   Availability of parameters of trigger sources from timer
00649   *         depends on timers availability on the selected device.
00650   * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
00651   *         CR       TSEL2          LL_DAC_SetTriggerSource
00652   * @param  DACx DAC instance
00653   * @param  DAC_Channel This parameter can be one of the following values:
00654   *         @arg @ref LL_DAC_CHANNEL_1
00655   *         @arg @ref LL_DAC_CHANNEL_2
00656   * @param  TriggerSource This parameter can be one of the following values:
00657   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00658   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00659   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
00660   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
00661   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00662   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00663   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
00664   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
00668 {
00669   MODIFY_REG(DACx->CR,
00670              DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00671              TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00672 }
00673 
00674 /**
00675   * @brief  Get the conversion trigger source for the selected DAC channel.
00676   * @note   For conversion trigger source to be effective, DAC trigger
00677   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00678   * @note   Availability of parameters of trigger sources from timer
00679   *         depends on timers availability on the selected device.
00680   * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
00681   *         CR       TSEL2          LL_DAC_GetTriggerSource
00682   * @param  DACx DAC instance
00683   * @param  DAC_Channel This parameter can be one of the following values:
00684   *         @arg @ref LL_DAC_CHANNEL_1
00685   *         @arg @ref LL_DAC_CHANNEL_2
00686   * @retval Returned value can be one of the following values:
00687   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00688   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00689   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
00690   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
00691   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00692   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00693   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
00694   *         @arg @ref LL_DAC_TRIGGER_EXT_IT9
00695   */
00696 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00697 {
00698   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00699                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00700                    );
00701 }
00702 
00703 /**
00704   * @brief  Set the waveform automatic generation mode
00705   *         for the selected DAC channel.
00706   * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
00707   *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
00708   * @param  DACx DAC instance
00709   * @param  DAC_Channel This parameter can be one of the following values:
00710   *         @arg @ref LL_DAC_CHANNEL_1
00711   *         @arg @ref LL_DAC_CHANNEL_2
00712   * @param  WaveAutoGeneration This parameter can be one of the following values:
00713   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00714   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00715   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00716   * @retval None
00717   */
00718 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
00719 {
00720   MODIFY_REG(DACx->CR,
00721              DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00722              WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00723 }
00724 
00725 /**
00726   * @brief  Get the waveform automatic generation mode
00727   *         for the selected DAC channel.
00728   * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
00729   *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
00730   * @param  DACx DAC instance
00731   * @param  DAC_Channel This parameter can be one of the following values:
00732   *         @arg @ref LL_DAC_CHANNEL_1
00733   *         @arg @ref LL_DAC_CHANNEL_2
00734   * @retval Returned value can be one of the following values:
00735   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00736   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00737   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00738   */
00739 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00740 {
00741   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00742                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00743                    );
00744 }
00745 
00746 /**
00747   * @brief  Set the noise waveform generation for the selected DAC channel:
00748   *         Noise mode and parameters LFSR (linear feedback shift register).
00749   * @note   For wave generation to be effective, DAC channel
00750   *         wave generation mode must be enabled using
00751   *         function @ref LL_DAC_SetWaveAutoGeneration().
00752   * @note   This setting can be set when the selected DAC channel is disabled
00753   *         (otherwise, the setting operation is ignored).
00754   * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
00755   *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
00756   * @param  DACx DAC instance
00757   * @param  DAC_Channel This parameter can be one of the following values:
00758   *         @arg @ref LL_DAC_CHANNEL_1
00759   *         @arg @ref LL_DAC_CHANNEL_2
00760   * @param  NoiseLFSRMask This parameter can be one of the following values:
00761   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00762   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00763   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00764   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00765   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00766   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00767   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00768   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00769   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00770   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00771   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00772   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00773   * @retval None
00774   */
00775 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
00776 {
00777   MODIFY_REG(DACx->CR,
00778              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00779              NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00780 }
00781 
00782 /**
00783   * @brief  Set the noise waveform generation for the selected DAC channel:
00784   *         Noise mode and parameters LFSR (linear feedback shift register).
00785   * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
00786   *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
00787   * @param  DACx DAC instance
00788   * @param  DAC_Channel This parameter can be one of the following values:
00789   *         @arg @ref LL_DAC_CHANNEL_1
00790   *         @arg @ref LL_DAC_CHANNEL_2
00791   * @retval Returned value can be one of the following values:
00792   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00793   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00794   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00795   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00796   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00797   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00798   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00799   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00800   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00801   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00802   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00803   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00804   */
00805 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00806 {
00807   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00808                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00809                    );
00810 }
00811 
00812 /**
00813   * @brief  Set the triangle waveform generation for the selected DAC channel:
00814   *         triangle mode and amplitude.
00815   * @note   For wave generation to be effective, DAC channel
00816   *         wave generation mode must be enabled using
00817   *         function @ref LL_DAC_SetWaveAutoGeneration().
00818   * @note   This setting can be set when the selected DAC channel is disabled
00819   *         (otherwise, the setting operation is ignored).
00820   * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
00821   *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
00822   * @param  DACx DAC instance
00823   * @param  DAC_Channel This parameter can be one of the following values:
00824   *         @arg @ref LL_DAC_CHANNEL_1
00825   *         @arg @ref LL_DAC_CHANNEL_2
00826   * @param  TriangleAmplitude This parameter can be one of the following values:
00827   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00828   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00829   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00830   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00831   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00832   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00833   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00834   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00835   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00836   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00837   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00838   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00839   * @retval None
00840   */
00841 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
00842 {
00843   MODIFY_REG(DACx->CR,
00844              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00845              TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00846 }
00847 
00848 /**
00849   * @brief  Set the triangle waveform generation for the selected DAC channel:
00850   *         triangle mode and amplitude.
00851   * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
00852   *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
00853   * @param  DACx DAC instance
00854   * @param  DAC_Channel This parameter can be one of the following values:
00855   *         @arg @ref LL_DAC_CHANNEL_1
00856   *         @arg @ref LL_DAC_CHANNEL_2
00857   * @retval Returned value can be one of the following values:
00858   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00859   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00860   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00861   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00862   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00863   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00864   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00865   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00866   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00867   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00868   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00869   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00870   */
00871 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00872 {
00873   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00874                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00875                    );
00876 }
00877 
00878 /**
00879   * @brief  Set the output for the selected DAC channel.
00880   * @note   This function set several features:
00881   *         - mode normal or sample-and-hold
00882   *         - buffer
00883   *         - connection to GPIO or internal path.
00884   *         These features can also be set individually using
00885   *         dedicated functions:
00886   *         - @ref LL_DAC_SetOutputBuffer()
00887   *         - @ref LL_DAC_SetOutputMode()
00888   *         - @ref LL_DAC_SetOutputConnection()
00889   * @note   On this STM32 serie, output connection depends on output mode
00890   *         (normal or sample and hold) and output buffer state.
00891   *         - if output connection is set to internal path and output buffer
00892   *           is enabled (whatever output mode):
00893   *           output connection is also connected to GPIO pin
00894   *           (both connections to GPIO pin and internal path).
00895   *         - if output connection is set to GPIO pin, output buffer
00896   *           is disabled, output mode set to sample and hold:
00897   *           output connection is also connected to internal path
00898   *           (both connections to GPIO pin and internal path).
00899   * @note   Mode sample-and-hold requires an external capacitor
00900   *         to be connected between DAC channel output and ground.
00901   *         Capacitor value depends on load on DAC channel output and 
00902   *         sample-and-hold timings configured.
00903   *         As indication, capacitor typical value is 100nF
00904   *         (refer to device datasheet, parameter "CSH").
00905   * @rmtoll CR       MODE1          LL_DAC_ConfigOutput\n
00906   *         CR       MODE2          LL_DAC_ConfigOutput
00907   * @param  DACx DAC instance
00908   * @param  DAC_Channel This parameter can be one of the following values:
00909   *         @arg @ref LL_DAC_CHANNEL_1
00910   *         @arg @ref LL_DAC_CHANNEL_2
00911   * @param  OutputMode This parameter can be one of the following values:
00912   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00913   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00914   * @param  OutputBuffer This parameter can be one of the following values:
00915   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00916   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00917   * @param  OutputConnection This parameter can be one of the following values:
00918   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
00919   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
00920   * @retval None
00921   */
00922 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
00923 {
00924   MODIFY_REG(DACx->MCR,
00925              (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00926              (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00927 }
00928 
00929 /**
00930   * @brief  Set the output mode normal or sample-and-hold
00931   *         for the selected DAC channel.
00932   * @note   Mode sample-and-hold requires an external capacitor
00933   *         to be connected between DAC channel output and ground.
00934   *         Capacitor value depends on load on DAC channel output and 
00935   *         sample-and-hold timings configured.
00936   *         As indication, capacitor typical value is 100nF
00937   *         (refer to device datasheet, parameter "CSH").
00938   * @rmtoll CR       MODE1          LL_DAC_SetOutputMode\n
00939   *         CR       MODE2          LL_DAC_SetOutputMode
00940   * @param  DACx DAC instance
00941   * @param  DAC_Channel This parameter can be one of the following values:
00942   *         @arg @ref LL_DAC_CHANNEL_1
00943   *         @arg @ref LL_DAC_CHANNEL_2
00944   * @param  OutputMode This parameter can be one of the following values:
00945   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00946   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00947   * @retval None
00948   */
00949 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
00950 {
00951   MODIFY_REG(DACx->MCR,
00952              DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00953              OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00954 }
00955 
00956 /**
00957   * @brief  Get the output mode normal or sample-and-hold for the selected DAC channel.
00958   * @rmtoll CR       MODE1          LL_DAC_GetOutputMode\n
00959   *         CR       MODE2          LL_DAC_GetOutputMode
00960   * @param  DACx DAC instance
00961   * @param  DAC_Channel This parameter can be one of the following values:
00962   *         @arg @ref LL_DAC_CHANNEL_1
00963   *         @arg @ref LL_DAC_CHANNEL_2
00964   * @retval Returned value can be one of the following values:
00965   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
00966   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
00967   */
00968 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00969 {
00970   return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00971                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00972                    );
00973 }
00974 
00975 /**
00976   * @brief  Set the output buffer for the selected DAC channel.
00977   * @note   On this STM32 serie, when buffer is enabled, its offset can be
00978   *         trimmed: factory calibration default values can be
00979   *         replaced by user trimming values, using function
00980   *         @ref LL_DAC_SetTrimmingValue().
00981   * @rmtoll CR       MODE1          LL_DAC_SetOutputBuffer\n
00982   *         CR       MODE2          LL_DAC_SetOutputBuffer
00983   * @param  DACx DAC instance
00984   * @param  DAC_Channel This parameter can be one of the following values:
00985   *         @arg @ref LL_DAC_CHANNEL_1
00986   *         @arg @ref LL_DAC_CHANNEL_2
00987   * @param  OutputBuffer This parameter can be one of the following values:
00988   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00989   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00990   * @retval None
00991   */
00992 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
00993 {
00994   MODIFY_REG(DACx->MCR,
00995              DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00996              OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00997 }
00998 
00999 /**
01000   * @brief  Get the output buffer state for the selected DAC channel.
01001   * @rmtoll CR       MODE1          LL_DAC_GetOutputBuffer\n
01002   *         CR       MODE2          LL_DAC_GetOutputBuffer
01003   * @param  DACx DAC instance
01004   * @param  DAC_Channel This parameter can be one of the following values:
01005   *         @arg @ref LL_DAC_CHANNEL_1
01006   *         @arg @ref LL_DAC_CHANNEL_2
01007   * @retval Returned value can be one of the following values:
01008   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
01009   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
01010   */
01011 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01012 {
01013   return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01014                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01015                    );
01016 }
01017 
01018 /**
01019   * @brief  Set the output connection for the selected DAC channel.
01020   * @note   On this STM32 serie, output connection depends on output mode (normal or
01021   *         sample and hold) and output buffer state.
01022   *         - if output connection is set to internal path and output buffer
01023   *           is enabled (whatever output mode):
01024   *           output connection is also connected to GPIO pin
01025   *           (both connections to GPIO pin and internal path).
01026   *         - if output connection is set to GPIO pin, output buffer
01027   *           is disabled, output mode set to sample and hold:
01028   *           output connection is also connected to internal path
01029   *           (both connections to GPIO pin and internal path).
01030   * @rmtoll CR       MODE1          LL_DAC_SetOutputConnection\n
01031   *         CR       MODE2          LL_DAC_SetOutputConnection
01032   * @param  DACx DAC instance
01033   * @param  DAC_Channel This parameter can be one of the following values:
01034   *         @arg @ref LL_DAC_CHANNEL_1
01035   *         @arg @ref LL_DAC_CHANNEL_2
01036   * @param  OutputConnection This parameter can be one of the following values:
01037   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01038   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01039   * @retval None
01040   */
01041 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
01042 {
01043   MODIFY_REG(DACx->MCR,
01044              DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01045              OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01046 }
01047 
01048 /**
01049   * @brief  Get the output connection for the selected DAC channel.
01050   * @note   On this STM32 serie, output connection depends on output mode (normal or
01051   *         sample and hold) and output buffer state.
01052   *         - if output connection is set to internal path and output buffer
01053   *           is enabled (whatever output mode):
01054   *           output connection is also connected to GPIO pin
01055   *           (both connections to GPIO pin and internal path).
01056   *         - if output connection is set to GPIO pin, output buffer
01057   *           is disabled, output mode set to sample and hold:
01058   *           output connection is also connected to internal path
01059   *           (both connections to GPIO pin and internal path).
01060   * @rmtoll CR       MODE1          LL_DAC_GetOutputConnection\n
01061   *         CR       MODE2          LL_DAC_GetOutputConnection
01062   * @param  DACx DAC instance
01063   * @param  DAC_Channel This parameter can be one of the following values:
01064   *         @arg @ref LL_DAC_CHANNEL_1
01065   *         @arg @ref LL_DAC_CHANNEL_2
01066   * @retval Returned value can be one of the following values:
01067   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
01068   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
01069   */
01070 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01071 {
01072   return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01073                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01074                    );
01075 }
01076 
01077 /**
01078   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01079   *         sample time
01080   * @note   Sample time must be set when DAC channel is disabled
01081   *         or during DAC operation when DAC channel flag BWSTx is reset,
01082   *         otherwise the setting is ignored.
01083   *         Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
01084   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_SetSampleAndHoldSampleTime\n
01085   *         SHSR2    TSAMPLE2       LL_DAC_SetSampleAndHoldSampleTime
01086   * @param  DACx DAC instance
01087   * @param  DAC_Channel This parameter can be one of the following values:
01088   *         @arg @ref LL_DAC_CHANNEL_1
01089   *         @arg @ref LL_DAC_CHANNEL_2
01090   * @param  SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
01091   * @retval None
01092   */
01093 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
01094 {
01095   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK));
01096   
01097   MODIFY_REG(*preg,
01098              DAC_SHSR1_TSAMPLE1,
01099              SampleTime);
01100 }
01101 
01102 /**
01103   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01104   *         sample time
01105   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_GetSampleAndHoldSampleTime\n
01106   *         SHSR2    TSAMPLE2       LL_DAC_GetSampleAndHoldSampleTime
01107   * @param  DACx DAC instance
01108   * @param  DAC_Channel This parameter can be one of the following values:
01109   *         @arg @ref LL_DAC_CHANNEL_1
01110   *         @arg @ref LL_DAC_CHANNEL_2
01111   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
01112   */
01113 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01114 {
01115   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK));
01116   
01117   return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
01118 }
01119 
01120 /**
01121   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01122   *         hold time
01123   * @rmtoll SHHR     THOLD1         LL_DAC_SetSampleAndHoldHoldTime\n
01124   *         SHHR     THOLD2         LL_DAC_SetSampleAndHoldHoldTime
01125   * @param  DACx DAC instance
01126   * @param  DAC_Channel This parameter can be one of the following values:
01127   *         @arg @ref LL_DAC_CHANNEL_1
01128   *         @arg @ref LL_DAC_CHANNEL_2
01129   * @param  HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
01130   * @retval None
01131   */
01132 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
01133 {
01134   MODIFY_REG(DACx->SHHR,
01135              DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01136              HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01137 }
01138 
01139 /**
01140   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01141   *         hold time
01142   * @rmtoll SHHR     THOLD1         LL_DAC_GetSampleAndHoldHoldTime\n
01143   *         SHHR     THOLD2         LL_DAC_GetSampleAndHoldHoldTime
01144   * @param  DACx DAC instance
01145   * @param  DAC_Channel This parameter can be one of the following values:
01146   *         @arg @ref LL_DAC_CHANNEL_1
01147   *         @arg @ref LL_DAC_CHANNEL_2
01148   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
01149   */
01150 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01151 {
01152   return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01153                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01154                    );
01155 }
01156 
01157 /**
01158   * @brief  Set the sample-and-hold timing for the selected DAC channel:
01159   *         refresh time
01160   * @rmtoll SHRR     TREFRESH1      LL_DAC_SetSampleAndHoldRefreshTime\n
01161   *         SHRR     TREFRESH2      LL_DAC_SetSampleAndHoldRefreshTime
01162   * @param  DACx DAC instance
01163   * @param  DAC_Channel This parameter can be one of the following values:
01164   *         @arg @ref LL_DAC_CHANNEL_1
01165   *         @arg @ref LL_DAC_CHANNEL_2
01166   * @param  RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
01167   * @retval None
01168   */
01169 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
01170 {
01171   MODIFY_REG(DACx->SHRR,
01172              DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
01173              RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01174 }
01175 
01176 /**
01177   * @brief  Get the sample-and-hold timing for the selected DAC channel:
01178   *         refresh time
01179   * @rmtoll SHRR     TREFRESH1      LL_DAC_GetSampleAndHoldRefreshTime\n
01180   *         SHRR     TREFRESH2      LL_DAC_GetSampleAndHoldRefreshTime
01181   * @param  DACx DAC instance
01182   * @param  DAC_Channel This parameter can be one of the following values:
01183   *         @arg @ref LL_DAC_CHANNEL_1
01184   *         @arg @ref LL_DAC_CHANNEL_2
01185   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01186   */
01187 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01188 {
01189   return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01190                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
01191                    );
01192 }
01193 
01194 /**
01195   * @}
01196   */
01197 
01198 /** @defgroup DAC_LL_EF_Configuration_Legacy_Functions DAC configuration, legacy functions name
01199   * @{
01200   */
01201 /* Old functions name kept for legacy purpose, to be replaced by the          */
01202 /* current functions name.                                                    */
01203 __STATIC_INLINE void LL_DAC_SetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveMode)
01204 {
01205   LL_DAC_SetWaveAutoGeneration(DACx, DAC_Channel, WaveMode);
01206 }
01207 __STATIC_INLINE uint32_t LL_DAC_GetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01208 {
01209   return LL_DAC_GetWaveAutoGeneration(DACx, DAC_Channel);
01210 }
01211 
01212 /**
01213   * @}
01214   */
01215 
01216 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
01217   * @{
01218   */
01219 
01220 /**
01221   * @brief  Enable DAC DMA transfer request of the selected channel.
01222   * @note   To configure DMA source address (peripheral address),
01223   *         use function @ref LL_DAC_DMA_GetRegAddr().
01224   * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
01225   *         CR       DMAEN2         LL_DAC_EnableDMAReq
01226   * @param  DACx DAC instance
01227   * @param  DAC_Channel This parameter can be one of the following values:
01228   *         @arg @ref LL_DAC_CHANNEL_1
01229   *         @arg @ref LL_DAC_CHANNEL_2
01230   * @retval None
01231   */
01232 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01233 {
01234   SET_BIT(DACx->CR,
01235           DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01236 }
01237 
01238 /**
01239   * @brief  Disable DAC DMA transfer request of the selected channel.
01240   * @note   To configure DMA source address (peripheral address),
01241   *         use function @ref LL_DAC_DMA_GetRegAddr().
01242   * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
01243   *         CR       DMAEN2         LL_DAC_DisableDMAReq
01244   * @param  DACx DAC instance
01245   * @param  DAC_Channel This parameter can be one of the following values:
01246   *         @arg @ref LL_DAC_CHANNEL_1
01247   *         @arg @ref LL_DAC_CHANNEL_2
01248   * @retval None
01249   */
01250 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01251 {
01252   CLEAR_BIT(DACx->CR,
01253             DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01254 }
01255 
01256 /**
01257   * @brief  Get DAC DMA transfer request state of the selected channel.
01258   *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
01259   * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
01260   *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
01261   * @param  DACx DAC instance
01262   * @param  DAC_Channel This parameter can be one of the following values:
01263   *         @arg @ref LL_DAC_CHANNEL_1
01264   *         @arg @ref LL_DAC_CHANNEL_2
01265   * @retval State of bit (1 or 0).
01266   */
01267 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01268 {
01269   return (READ_BIT(DACx->CR,
01270                    DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01271           == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
01272 }
01273 
01274 /**
01275   * @brief  Function to help to configure DMA transfer to DAC: retrieve the
01276   *         DAC register address from DAC instance and a list of DAC registers
01277   *         intended to be used (most commonly) with DMA transfer.
01278   * @note   These DAC registers are data holding registers:
01279   *         when DAC conversion is requested, DAC generates a DMA transfer
01280   *         request to have data available in DAC data holding registers.
01281   * @note   This macro is intended to be used with LL DMA driver, refer to
01282   *         function "LL_DMA_ConfigAddresses()".
01283   *         Example:
01284   *           LL_DMA_ConfigAddresses(DMA1,
01285   *                                  LL_DMA_CHANNEL_1,
01286   *                                  (uint32_t)&< array or variable >,
01287   *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
01288   *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
01289   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01290   *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01291   *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
01292   *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
01293   *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
01294   *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
01295   * @param  DACx DAC instance
01296   * @param  DAC_Channel This parameter can be one of the following values:
01297   *         @arg @ref LL_DAC_CHANNEL_1
01298   *         @arg @ref LL_DAC_CHANNEL_2
01299   * @param  Register This parameter can be one of the following values:
01300   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
01301   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
01302   *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
01303   * @retval DAC register address
01304   */
01305 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
01306 {
01307   /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
01308   /* DAC channel selected.                                                    */
01309   return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
01310 }
01311 /**
01312   * @}
01313   */
01314 
01315 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
01316   * @{
01317   */
01318 
01319 /**
01320   * @brief  Enable DAC selected channel.
01321   * @rmtoll CR       EN1            LL_DAC_Enable\n
01322   *         CR       EN2            LL_DAC_Enable
01323   * @note   After enable from off state, DAC channel requires a delay
01324   *         for output voltage to reach accuracy +/- 1 LSB.
01325   *         Refer to device datasheet, parameter "tWAKEUP".
01326   * @param  DACx DAC instance
01327   * @param  DAC_Channel This parameter can be one of the following values:
01328   *         @arg @ref LL_DAC_CHANNEL_1
01329   *         @arg @ref LL_DAC_CHANNEL_2
01330   * @retval None
01331   */
01332 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01333 {
01334   SET_BIT(DACx->CR,
01335           DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01336 }
01337 
01338 /**
01339   * @brief  Disable DAC selected channel.
01340   * @rmtoll CR       EN1            LL_DAC_Disable\n
01341   *         CR       EN2            LL_DAC_Disable
01342   * @param  DACx DAC instance
01343   * @param  DAC_Channel This parameter can be one of the following values:
01344   *         @arg @ref LL_DAC_CHANNEL_1
01345   *         @arg @ref LL_DAC_CHANNEL_2
01346   * @retval None
01347   */
01348 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01349 {
01350   CLEAR_BIT(DACx->CR,
01351             DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01352 }
01353 
01354 /**
01355   * @brief  Get DAC enable state of the selected channel.
01356   *         (0: DAC channel is disabled, 1: DAC channel is enabled)
01357   * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
01358   *         CR       EN2            LL_DAC_IsEnabled
01359   * @param  DACx DAC instance
01360   * @param  DAC_Channel This parameter can be one of the following values:
01361   *         @arg @ref LL_DAC_CHANNEL_1
01362   *         @arg @ref LL_DAC_CHANNEL_2
01363   * @retval State of bit (1 or 0).
01364   */
01365 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01366 {
01367   return (READ_BIT(DACx->CR,
01368                    DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01369           == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
01370 }
01371 
01372 /**
01373   * @brief  Enable DAC trigger of the selected channel.
01374   * @note   - If DAC trigger is disabled, DAC conversion is performed
01375   *           automatically once the data holding register is updated,
01376   *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01377   *           @ref LL_DAC_ConvertData12RightAligned(), ...
01378   *         - If DAC trigger is enabled, DAC conversion is performed
01379   *           only when a hardware of software trigger event is occurring.
01380   *           Select trigger source using
01381   *           function @ref LL_DAC_SetTriggerSource().
01382   * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
01383   *         CR       TEN2           LL_DAC_EnableTrigger
01384   * @param  DACx DAC instance
01385   * @param  DAC_Channel This parameter can be one of the following values:
01386   *         @arg @ref LL_DAC_CHANNEL_1
01387   *         @arg @ref LL_DAC_CHANNEL_2
01388   * @retval None
01389   */
01390 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01391 {
01392   SET_BIT(DACx->CR,
01393           DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01394 }
01395 
01396 /**
01397   * @brief  Disable DAC trigger of the selected channel.
01398   * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
01399   *         CR       TEN2           LL_DAC_DisableTrigger
01400   * @param  DACx DAC instance
01401   * @param  DAC_Channel This parameter can be one of the following values:
01402   *         @arg @ref LL_DAC_CHANNEL_1
01403   *         @arg @ref LL_DAC_CHANNEL_2
01404   * @retval None
01405   */
01406 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01407 {
01408   CLEAR_BIT(DACx->CR,
01409             DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
01410 }
01411 
01412 /**
01413   * @brief  Get DAC trigger state of the selected channel.
01414   *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
01415   * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
01416   *         CR       TEN2           LL_DAC_IsTriggerEnabled
01417   * @param  DACx DAC instance
01418   * @param  DAC_Channel This parameter can be one of the following values:
01419   *         @arg @ref LL_DAC_CHANNEL_1
01420   *         @arg @ref LL_DAC_CHANNEL_2
01421   * @retval State of bit (1 or 0).
01422   */
01423 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01424 {
01425   return (READ_BIT(DACx->CR,
01426                    DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
01427           == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
01428 }
01429 
01430 /**
01431   * @brief  Trig DAC conversion by software for the selected DAC channel.
01432   * @note   Preliminarily, DAC trigger must be set to software trigger
01433   *         using function @ref LL_DAC_SetTriggerSource()
01434   *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
01435   *         and DAC trigger must be enabled using
01436   *         function @ref LL_DAC_EnableTrigger().
01437   * @note   For devices featuring DAC with 2 channels: this function
01438   *         can perform a SW start of both DAC channels simultaneously.
01439   *         Two channels can be selected as parameter.
01440   *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
01441   * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
01442   *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
01443   * @param  DACx DAC instance
01444   * @param  DAC_Channel  This parameter can a combination of the following values:
01445   *         @arg @ref LL_DAC_CHANNEL_1
01446   *         @arg @ref LL_DAC_CHANNEL_2
01447   * @retval None
01448   */
01449 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01450 {
01451   SET_BIT(DACx->SWTRIGR,
01452           (DAC_Channel & DAC_SWTR_CHX_MASK));
01453 }
01454 
01455 /**
01456   * @brief  Set the data to be loaded in the data holding register
01457   *         in format 12 bits left alignment (LSB aligned on bit 0),
01458   *         for the selected DAC channel.
01459   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
01460   *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
01461   * @param  DACx DAC instance
01462   * @param  DAC_Channel This parameter can be one of the following values:
01463   *         @arg @ref LL_DAC_CHANNEL_1
01464   *         @arg @ref LL_DAC_CHANNEL_2
01465   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01466   * @retval None
01467   */
01468 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01469 {
01470   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
01471   
01472   MODIFY_REG(*preg,
01473              DAC_DHR12R1_DACC1DHR,
01474              Data);
01475 }
01476 
01477 /**
01478   * @brief  Set the data to be loaded in the data holding register
01479   *         in format 12 bits left alignment (MSB aligned on bit 15),
01480   *         for the selected DAC channel.
01481   * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
01482   *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
01483   * @param  DACx DAC instance
01484   * @param  DAC_Channel This parameter can be one of the following values:
01485   *         @arg @ref LL_DAC_CHANNEL_1
01486   *         @arg @ref LL_DAC_CHANNEL_2
01487   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01488   * @retval None
01489   */
01490 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01491 {
01492   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
01493   
01494   MODIFY_REG(*preg,
01495              DAC_DHR12L1_DACC1DHR,
01496              Data);
01497 }
01498 
01499 /**
01500   * @brief  Set the data to be loaded in the data holding register
01501   *         in format 8 bits left alignment (LSB aligned on bit 0),
01502   *         for the selected DAC channel.
01503   * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
01504   *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
01505   * @param  DACx DAC instance
01506   * @param  DAC_Channel This parameter can be one of the following values:
01507   *         @arg @ref LL_DAC_CHANNEL_1
01508   *         @arg @ref LL_DAC_CHANNEL_2
01509   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
01510   * @retval None
01511   */
01512 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01513 {
01514   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
01515   
01516   MODIFY_REG(*preg,
01517              DAC_DHR8R1_DACC1DHR,
01518              Data);
01519 }
01520 
01521 /**
01522   * @brief  Set the data to be loaded in the data holding register
01523   *         in format 12 bits left alignment (LSB aligned on bit 0),
01524   *         for both DAC channels.
01525   * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
01526   *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
01527   * @param  DACx DAC instance
01528   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01529   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01530   * @retval None
01531   */
01532 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01533 {
01534   MODIFY_REG(DACx->DHR12RD,
01535              (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
01536              ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01537 }
01538 
01539 /**
01540   * @brief  Set the data to be loaded in the data holding register
01541   *         in format 12 bits left alignment (MSB aligned on bit 15),
01542   *         for both DAC channels.
01543   * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
01544   *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
01545   * @param  DACx DAC instance
01546   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01547   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01548   * @retval None
01549   */
01550 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01551 {
01552   /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
01553   /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
01554   /*       the 4 LSB must be taken into account for the shift value.          */
01555   MODIFY_REG(DACx->DHR12LD,
01556              (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
01557              ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
01558 }
01559 
01560 /**
01561   * @brief  Set the data to be loaded in the data holding register
01562   *         in format 8 bits left alignment (LSB aligned on bit 0),
01563   *         for both DAC channels.
01564   * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
01565   *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
01566   * @param  DACx DAC instance
01567   * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
01568   * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
01569   * @retval None
01570   */
01571 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01572 {
01573   MODIFY_REG(DACx->DHR8RD,
01574              (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
01575              ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01576 }
01577 
01578 /**
01579   * @brief  Retrieve output data currently generated for the selected DAC channel.
01580   * @note   Whatever alignment and resolution settings
01581   *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01582   *         @ref LL_DAC_ConvertData12RightAligned(), ...),
01583   *         output data format is 12 bits right aligned (LSB aligned on bit 0).
01584   * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
01585   *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
01586   * @param  DACx DAC instance
01587   * @param  DAC_Channel This parameter can be one of the following values:
01588   *         @arg @ref LL_DAC_CHANNEL_1
01589   *         @arg @ref LL_DAC_CHANNEL_2
01590   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01591   */
01592 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01593 {
01594   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
01595   
01596   return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
01597 }
01598 
01599 /**
01600   * @}
01601   */
01602 
01603 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
01604   * @{
01605   */
01606 /**
01607   * @brief  Get DAC calibration offset flag for DAC channel 1
01608   * @rmtoll SR       CAL_FLAG1      LL_DAC_IsActiveFlag_CAL1
01609   * @param  DACx DAC instance
01610   * @retval State of bit (1 or 0).
01611   */
01612 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
01613 {
01614   return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1));
01615 }
01616 
01617 /**
01618   * @brief  Get DAC calibration offset flag for DAC channel 2
01619   * @rmtoll SR       CAL_FLAG2      LL_DAC_IsActiveFlag_CAL2
01620   * @param  DACx DAC instance
01621   * @retval State of bit (1 or 0).
01622   */
01623 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
01624 {
01625   return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2));
01626 }
01627 
01628 /**
01629   * @brief  Get DAC busy writing sample time flag for DAC channel 1
01630   * @rmtoll SR       BWST1          LL_DAC_IsActiveFlag_BWST1
01631   * @param  DACx DAC instance
01632   * @retval State of bit (1 or 0).
01633   */
01634 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
01635 {
01636   return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1));
01637 }
01638 
01639 /**
01640   * @brief  Get DAC busy writing sample time flag for DAC channel 2
01641   * @rmtoll SR       BWST2          LL_DAC_IsActiveFlag_BWST2
01642   * @param  DACx DAC instance
01643   * @retval State of bit (1 or 0).
01644   */
01645 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
01646 {
01647   return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2));
01648 }
01649 
01650 /**
01651   * @brief  Get DAC underrun flag for DAC channel 1
01652   * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
01653   * @param  DACx DAC instance
01654   * @retval State of bit (1 or 0).
01655   */
01656 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
01657 {
01658   return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
01659 }
01660 
01661 /**
01662   * @brief  Get DAC underrun flag for DAC channel 2
01663   * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
01664   * @param  DACx DAC instance
01665   * @retval State of bit (1 or 0).
01666   */
01667 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
01668 {
01669   return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
01670 }
01671 
01672 /**
01673   * @brief  Clear DAC underrun flag for DAC channel 1
01674   * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
01675   * @param  DACx DAC instance
01676   * @retval None
01677   */
01678 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
01679 {
01680   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
01681 }
01682 
01683 /**
01684   * @brief  Clear DAC underrun flag for DAC channel 2
01685   * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
01686   * @param  DACx DAC instance
01687   * @retval None
01688   */
01689 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
01690 {
01691   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
01692 }
01693 
01694 /**
01695   * @}
01696   */
01697 
01698 /** @defgroup DAC_LL_EF_IT_Management IT management
01699   * @{
01700   */
01701 
01702 /**
01703   * @brief  Enable DMA underrun interrupt for DAC channel 1
01704   * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
01705   * @param  DACx DAC instance
01706   * @retval None
01707   */
01708 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
01709 {
01710   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01711 }
01712 
01713 /**
01714   * @brief  Enable DMA underrun interrupt for DAC channel 2
01715   * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
01716   * @param  DACx DAC instance
01717   * @retval None
01718   */
01719 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
01720 {
01721   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01722 }
01723 
01724 /**
01725   * @brief  Disable DMA underrun interrupt for DAC channel 1
01726   * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
01727   * @param  DACx DAC instance
01728   * @retval None
01729   */
01730 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
01731 {
01732   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01733 }
01734 
01735 /**
01736   * @brief  Disable DMA underrun interrupt for DAC channel 2
01737   * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
01738   * @param  DACx DAC instance
01739   * @retval None
01740   */
01741 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
01742 {
01743   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01744 }
01745 
01746 /**
01747   * @brief  Get DMA underrun interrupt for DAC channel 1
01748   * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
01749   * @param  DACx DAC instance
01750   * @retval State of bit (1 or 0).
01751   */
01752 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
01753 {
01754   return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
01755 }
01756 
01757 /**
01758   * @brief  Get DMA underrun interrupt for DAC channel 2
01759   * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
01760   * @param  DACx DAC instance
01761   * @retval State of bit (1 or 0).
01762   */
01763 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
01764 {
01765   return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
01766 }
01767 
01768 /**
01769   * @}
01770   */
01771 
01772 #if defined(USE_FULL_LL_DRIVER)
01773 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
01774   * @{
01775   */
01776 
01777 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
01778 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
01779 void        LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
01780 
01781 /**
01782   * @}
01783   */
01784 #endif /* USE_FULL_LL_DRIVER */
01785 
01786 /**
01787   * @}
01788   */
01789 
01790 /**
01791   * @}
01792   */
01793 
01794 #endif /* DAC1 */
01795 
01796 /**
01797   * @}
01798   */
01799 
01800 #ifdef __cplusplus
01801 }
01802 #endif
01803 
01804 #endif /* __STM32L4xx_LL_DAC_H */
01805 
01806 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/