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stm32l4xx_ll_adc.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_adc.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of ADC LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_ADC_H 00040 #define __STM32L4xx_LL_ADC_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 00054 00055 /** @defgroup ADC_LL ADC 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 00062 /* Private constants ---------------------------------------------------------*/ 00063 /** @defgroup ADC_LL_Private_Constants ADC Private Constants 00064 * @{ 00065 */ 00066 00067 /* Internal mask for ADC group regular sequencer: */ 00068 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ 00069 /* - sequencer register offset */ 00070 /* - sequencer rank bits position into the selected register */ 00071 00072 /* Internal register offset for ADC group regular sequencer configuration */ 00073 /* (offset placed into a spare area of literal definition) */ 00074 #define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U) 00075 #define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U) 00076 #define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U) 00077 #define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U) 00078 00079 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) 00080 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00081 00082 /* Definition of ADC group regular sequencer bits information to be inserted */ 00083 /* into ADC group regular sequencer ranks literals definition. */ 00084 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */ 00085 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */ 00086 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */ 00087 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */ 00088 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */ 00089 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */ 00090 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ 00091 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ 00092 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ 00093 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */ 00094 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */ 00095 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */ 00096 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */ 00097 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */ 00098 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */ 00099 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */ 00100 00101 00102 00103 /* Internal mask for ADC group injected sequencer: */ 00104 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ 00105 /* - data register offset */ 00106 /* - sequencer rank bits position into the selected register */ 00107 00108 /* Internal register offset for ADC group injected data register */ 00109 /* (offset placed into a spare area of literal definition) */ 00110 #define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U) 00111 #define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U) 00112 #define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U) 00113 #define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U) 00114 00115 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) 00116 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00117 00118 /* Definition of ADC group injected sequencer bits information to be inserted */ 00119 /* into ADC group injected sequencer ranks literals definition. */ 00120 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */ 00121 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */ 00122 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */ 00123 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */ 00124 00125 00126 00127 /* Internal mask for ADC group regular trigger: */ 00128 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ 00129 /* - regular trigger source */ 00130 /* - regular trigger edge */ 00131 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ 00132 00133 /* Mask containing trigger source masks for each of possible */ 00134 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00135 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00136 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \ 00137 ((ADC_CFGR_EXTSEL) << (4U * 1U)) | \ 00138 ((ADC_CFGR_EXTSEL) << (4U * 2U)) | \ 00139 ((ADC_CFGR_EXTSEL) << (4U * 3U)) ) 00140 00141 /* Mask containing trigger edge masks for each of possible */ 00142 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00143 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00144 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \ 00145 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \ 00146 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \ 00147 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) 00148 00149 /* Definition of ADC group regular trigger bits information. */ 00150 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */ 00151 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */ 00152 00153 00154 00155 /* Internal mask for ADC group injected trigger: */ 00156 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ 00157 /* - injected trigger source */ 00158 /* - injected trigger edge */ 00159 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ 00160 00161 /* Mask containing trigger source masks for each of possible */ 00162 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00163 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00164 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \ 00165 ((ADC_JSQR_JEXTSEL) << (4U * 1U)) | \ 00166 ((ADC_JSQR_JEXTSEL) << (4U * 2U)) | \ 00167 ((ADC_JSQR_JEXTSEL) << (4U * 3U)) ) 00168 00169 /* Mask containing trigger edge masks for each of possible */ 00170 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00171 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00172 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \ 00173 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \ 00174 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \ 00175 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) 00176 00177 /* Definition of ADC group injected trigger bits information. */ 00178 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */ 00179 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */ 00180 00181 00182 00183 00184 00185 00186 /* Internal mask for ADC channel: */ 00187 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ 00188 /* - channel identifier defined by number */ 00189 /* - channel identifier defined by bitfield */ 00190 /* - channel differentiation between external channels (connected to */ 00191 /* GPIO pins) and internal channels (connected to internal paths) */ 00192 /* - channel sampling time defined by SMPRx register offset */ 00193 /* and SMPx bits positions into SMPRx register */ 00194 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) 00195 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) 00196 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ 00197 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) 00198 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ 00199 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ 00200 00201 /* Channel differentiation between external and internal channels */ 00202 #define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */ 00203 #define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ 00204 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) 00205 00206 /* Internal register offset for ADC channel sampling time configuration */ 00207 /* (offset placed into a spare area of literal definition) */ 00208 #define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U) 00209 #define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U) 00210 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) 00211 00212 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U) 00213 #define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ 00214 00215 /* Definition of channels ID number information to be inserted into */ 00216 /* channels literals definition. */ 00217 #define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U) 00218 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0) 00219 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 ) 00220 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) 00221 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 ) 00222 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) 00223 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 ) 00224 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) 00225 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 ) 00226 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) 00227 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 ) 00228 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) 00229 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 ) 00230 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) 00231 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 ) 00232 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) 00233 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 ) 00234 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) 00235 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 ) 00236 00237 /* Definition of channels ID bitfield information to be inserted into */ 00238 /* channels literals definition. */ 00239 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0) 00240 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1) 00241 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2) 00242 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3) 00243 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4) 00244 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5) 00245 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6) 00246 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7) 00247 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8) 00248 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9) 00249 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10) 00250 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11) 00251 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12) 00252 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13) 00253 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14) 00254 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15) 00255 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16) 00256 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17) 00257 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18) 00258 00259 /* Definition of channels sampling time information to be inserted into */ 00260 /* channels literals definition. */ 00261 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */ 00262 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */ 00263 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */ 00264 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */ 00265 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */ 00266 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */ 00267 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */ 00268 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */ 00269 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */ 00270 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */ 00271 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */ 00272 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */ 00273 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */ 00274 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */ 00275 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */ 00276 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */ 00277 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */ 00278 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */ 00279 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */ 00280 00281 00282 /* Internal mask for ADC mode single or differential ended: */ 00283 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */ 00284 /* the relevant bits for: */ 00285 /* (concatenation of multiple bits used in different registers) */ 00286 /* - ADC calibration: calibration start, calibration factor get or set */ 00287 /* - ADC channels: set each ADC channel ending mode */ 00288 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF) 00289 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) 00290 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ 00291 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ 00292 00293 00294 /* Internal mask for ADC analog watchdog: */ 00295 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ 00296 /* (concatenation of multiple bits used in different analog watchdogs, */ 00297 /* (feature of several watchdogs not available on all STM32 families)). */ 00298 /* - analog watchdog 1: monitored channel defined by number, */ 00299 /* selection of ADC group (ADC groups regular and-or injected). */ 00300 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ 00301 /* selection on groups. */ 00302 00303 /* Internal register offset for ADC analog watchdog channel configuration */ 00304 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U) 00305 #define ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00100000U) 00306 #define ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00200000U) 00307 00308 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ 00309 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ 00310 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) 00311 #define ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024U) 00312 00313 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) 00314 00315 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) 00316 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) 00317 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) 00318 00319 /* Internal register offset for ADC analog watchdog threshold configuration */ 00320 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) 00321 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) 00322 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) 00323 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) 00324 00325 00326 /* Internal mask for ADC offset: */ 00327 /* Internal register offset for ADC offset number configuration */ 00328 #define ADC_OFR1_REGOFFSET ((uint32_t)0x00000000U) 00329 #define ADC_OFR2_REGOFFSET ((uint32_t)0x00000001U) 00330 #define ADC_OFR3_REGOFFSET ((uint32_t)0x00000002U) 00331 #define ADC_OFR4_REGOFFSET ((uint32_t)0x00000003U) 00332 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) 00333 00334 00335 /* ADC registers bits positions */ 00336 #define ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */ 00337 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */ 00338 #define ADC_CFGR_AWD1EN_BITOFFSET_POS ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */ 00339 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */ 00340 #define ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */ 00341 00342 00343 /* ADC registers bits groups */ 00344 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ 00345 00346 00347 /* ADC internal channels related definitions */ 00348 /* Internal voltage reference VrefInt */ 00349 #define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 00350 #define VREFINT_CAL_VREF ((uint32_t) 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ 00351 /* Temperature sensor */ 00352 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 00353 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 00354 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ 00355 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ 00356 #define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ 00357 00358 00359 /** 00360 * @} 00361 */ 00362 00363 00364 /* Private macros ------------------------------------------------------------*/ 00365 /** @defgroup ADC_LL_Private_Macros ADC Private Macros 00366 * @{ 00367 */ 00368 00369 /** 00370 * @brief Driver macro reserved for internal use: isolate bits with the 00371 * selected mask and shift them to the register LSB 00372 * (shift mask on register position bit 0). 00373 * @param __BITS__ Bits in register 32 bits 00374 * @param __MASK__ Mask in register 32 bits 00375 * @retval Bits in register 32 bits 00376 */ 00377 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ 00378 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) 00379 00380 /** 00381 * @brief Driver macro reserved for internal use: set a pointer to 00382 * a register from a register basis from which an offset 00383 * is applied. 00384 * @param __REG__ Register basis from which the offset is applied. 00385 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). 00386 * @retval Pointer to register address 00387 */ 00388 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00389 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) 00390 00391 /** 00392 * @} 00393 */ 00394 00395 00396 /* Exported types ------------------------------------------------------------*/ 00397 #if defined(USE_FULL_LL_DRIVER) 00398 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure 00399 * @{ 00400 */ 00401 00402 /** 00403 * @brief Structure definition of some features of ADC common parameters 00404 * and multimode 00405 * (all ADC instances belonging to the same ADC common instance). 00406 * @note The setting of these parameters by function @ref LL_ADC_CommonInit() 00407 * is conditioned to ADC instances state (all ADC instances 00408 * sharing the same ADC common instance): 00409 * All ADC instances sharing the same ADC common instance must be 00410 * disabled. 00411 */ 00412 typedef struct 00413 { 00414 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. 00415 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE 00416 @note On this STM32 serie, if ADC group injected is used, some 00417 clock ratio constraints between ADC clock and AHB clock 00418 must be respected. Refer to reference manual. 00419 00420 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ 00421 00422 #if defined(ADC_MULTIMODE_SUPPORT) 00423 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). 00424 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE 00425 00426 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ 00427 00428 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. 00429 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER 00430 00431 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ 00432 00433 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. 00434 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY 00435 00436 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ 00437 #endif /* ADC_MULTIMODE_SUPPORT */ 00438 00439 } LL_ADC_CommonInitTypeDef; 00440 00441 /** 00442 * @brief Structure definition of some features of ADC instance. 00443 * @note These parameters have an impact on ADC scope: ADC instance. 00444 * Affects both group regular and group injected (availability 00445 * of ADC group injected depends on STM32 families). 00446 * Refer to corresponding unitary functions into 00447 * @ref ADC_LL_EF_Configuration_ADC_Instance . 00448 * @note The setting of these parameters by function @ref LL_ADC_Init() 00449 * is conditioned to ADC state: 00450 * ADC instance must be disabled. 00451 * This condition is applied to all ADC features, for efficiency 00452 * and compatibility over all STM32 families. However, the different 00453 * features can be set under different ADC state conditions 00454 * (setting possible with ADC enabled without conversion on going, 00455 * ADC enabled with conversion on going, ...) 00456 * Each feature can be updated afterwards with a unitary function 00457 * and potentially with ADC in a different state than disabled, 00458 * refer to description of each function for setting 00459 * conditioned to ADC state. 00460 */ 00461 typedef struct 00462 { 00463 uint32_t Resolution; /*!< Set ADC resolution. 00464 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION 00465 00466 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ 00467 00468 uint32_t DataAlignment; /*!< Set ADC conversion data alignment. 00469 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN 00470 00471 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ 00472 00473 uint32_t LowPowerMode; /*!< Set ADC low power mode. 00474 This parameter can be a value of @ref ADC_LL_EC_LP_MODE 00475 00476 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ 00477 00478 } LL_ADC_InitTypeDef; 00479 00480 /** 00481 * @brief Structure definition of some features of ADC group regular. 00482 * @note These parameters have an impact on ADC scope: ADC group regular. 00483 * Refer to corresponding unitary functions into 00484 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00485 * (functions with prefix "REG"). 00486 * @note The setting of these parameters by function @ref LL_ADC_REG_Init() 00487 * is conditioned to ADC state: 00488 * ADC instance must be disabled. 00489 * This condition is applied to all ADC features, for efficiency 00490 * and compatibility over all STM32 families. However, the different 00491 * features can be set under different ADC state conditions 00492 * (setting possible with ADC enabled without conversion on going, 00493 * ADC enabled with conversion on going, ...) 00494 * Each feature can be updated afterwards with a unitary function 00495 * and potentially with ADC in a different state than disabled, 00496 * refer to description of each function for setting 00497 * conditioned to ADC state. 00498 */ 00499 typedef struct 00500 { 00501 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 00502 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE 00503 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge 00504 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). 00505 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). 00506 00507 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ 00508 00509 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. 00510 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH 00511 00512 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ 00513 00514 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 00515 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE 00516 @note This parameter has an effect only if group regular sequencer is enabled 00517 (scan length of 2 ranks or more). 00518 00519 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ 00520 00521 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). 00522 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE 00523 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. 00524 00525 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ 00526 00527 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. 00528 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER 00529 00530 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ 00531 00532 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: 00533 data preserved or overwritten. 00534 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR 00535 00536 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ 00537 00538 } LL_ADC_REG_InitTypeDef; 00539 00540 /** 00541 * @brief Structure definition of some features of ADC group injected. 00542 * @note These parameters have an impact on ADC scope: ADC group injected. 00543 * Refer to corresponding unitary functions into 00544 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00545 * (functions with prefix "INJ"). 00546 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() 00547 * is conditioned to ADC state: 00548 * ADC instance must be disabled. 00549 * This condition is applied to all ADC features, for efficiency 00550 * and compatibility over all STM32 families. However, the different 00551 * features can be set under different ADC state conditions 00552 * (setting possible with ADC enabled without conversion on going, 00553 * ADC enabled with conversion on going, ...) 00554 * Each feature can be updated afterwards with a unitary function 00555 * and potentially with ADC in a different state than disabled, 00556 * refer to description of each function for setting 00557 * conditioned to ADC state. 00558 */ 00559 typedef struct 00560 { 00561 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 00562 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE 00563 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge 00564 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). 00565 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). 00566 00567 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ 00568 00569 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. 00570 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH 00571 00572 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ 00573 00574 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 00575 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE 00576 @note This parameter has an effect only if group injected sequencer is enabled 00577 (scan length of 2 ranks or more). 00578 00579 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ 00580 00581 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. 00582 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO 00583 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. 00584 00585 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ 00586 00587 } LL_ADC_INJ_InitTypeDef; 00588 00589 /** 00590 * @} 00591 */ 00592 #endif /* USE_FULL_LL_DRIVER */ 00593 00594 /* Exported constants --------------------------------------------------------*/ 00595 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants 00596 * @{ 00597 */ 00598 00599 /** @defgroup ADC_LL_EC_FLAG ADC flags 00600 * @brief Flags defines which can be used with LL_ADC_ReadReg function 00601 * @{ 00602 */ 00603 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ 00604 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ 00605 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */ 00606 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ 00607 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ 00608 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */ 00609 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */ 00610 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */ 00611 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ 00612 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ 00613 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ 00614 #if defined(ADC_MULTIMODE_SUPPORT) 00615 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */ 00616 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */ 00617 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */ 00618 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */ 00619 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */ 00620 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */ 00621 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */ 00622 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */ 00623 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */ 00624 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */ 00625 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */ 00626 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */ 00627 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */ 00628 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */ 00629 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */ 00630 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */ 00631 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ 00632 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */ 00633 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */ 00634 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */ 00635 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */ 00636 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */ 00637 #endif 00638 /** 00639 * @} 00640 */ 00641 00642 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) 00643 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions 00644 * @{ 00645 */ 00646 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ 00647 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ 00648 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */ 00649 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ 00650 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */ 00651 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */ 00652 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */ 00653 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */ 00654 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ 00655 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ 00656 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ 00657 /** 00658 * @} 00659 */ 00660 00661 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose 00662 * @{ 00663 */ 00664 /* List of ADC registers intended to be used (most commonly) with */ 00665 /* DMA transfer. */ 00666 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ 00667 #define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ 00668 #if defined(ADC_MULTIMODE_SUPPORT) 00669 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ 00670 #endif 00671 /** 00672 * @} 00673 */ 00674 00675 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 00676 * @{ 00677 */ 00678 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 00679 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 00680 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 00681 #define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC asynchronous clock without prescaler */ 00682 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */ 00683 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */ 00684 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */ 00685 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */ 00686 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */ 00687 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */ 00688 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */ 00689 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */ 00690 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */ 00691 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */ 00692 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */ 00693 /** 00694 * @} 00695 */ 00696 00697 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels 00698 * @{ 00699 */ 00700 /* Note: Other measurement paths to internal channels may be available */ 00701 /* (connections to other peripherals). */ 00702 /* If they are not listed below, they do not require any specific */ 00703 /* path enable. In this case, Access to measurement path is done */ 00704 /* only by selecting the corresponding ADC internal channel. */ 00705 #define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */ 00706 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ 00707 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ 00708 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ 00709 /** 00710 * @} 00711 */ 00712 00713 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution 00714 * @{ 00715 */ 00716 #define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */ 00717 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */ 00718 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */ 00719 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */ 00720 /** 00721 * @} 00722 */ 00723 00724 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment 00725 * @{ 00726 */ 00727 #define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 00728 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ 00729 /** 00730 * @} 00731 */ 00732 00733 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode 00734 * @{ 00735 */ 00736 #define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /*!< No ADC low power mode activated */ 00737 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ 00738 /** 00739 * @} 00740 */ 00741 00742 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number 00743 * @{ 00744 */ 00745 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00746 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00747 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00748 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00749 /** 00750 * @} 00751 */ 00752 00753 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state 00754 * @{ 00755 */ 00756 #define LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */ 00757 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */ 00758 /** 00759 * @} 00760 */ 00761 00762 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups 00763 * @{ 00764 */ 00765 #define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */ 00766 #define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/ 00767 #define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */ 00768 /** 00769 * @} 00770 */ 00771 00772 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number 00773 * @{ 00774 */ 00775 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 00776 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 00777 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 00778 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 00779 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 00780 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 00781 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 00782 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 00783 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 00784 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 00785 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 00786 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 00787 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 00788 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 00789 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 00790 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 00791 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 00792 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 00793 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 00794 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. */ 00795 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */ 00796 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */ 00797 #if defined(ADC1) && !defined(ADC2) 00798 #define LL_ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 00799 #define LL_ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 00800 #elif defined(ADC2) 00801 #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ 00802 #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ 00803 #if defined(ADC3) 00804 #define LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */ 00805 #define LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */ 00806 #endif 00807 #endif 00808 /** 00809 * @} 00810 */ 00811 00812 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source 00813 * @{ 00814 */ 00815 #define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ 00816 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00817 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 00818 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00819 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00820 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00821 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00822 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00823 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00824 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00825 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00826 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00827 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 00828 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00829 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 00830 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 00831 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 00832 /** 00833 * @} 00834 */ 00835 00836 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge 00837 * @{ 00838 */ 00839 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ 00840 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ 00841 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 00842 /** 00843 * @} 00844 */ 00845 00846 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode 00847 * @{ 00848 */ 00849 #define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ 00850 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ 00851 /** 00852 * @} 00853 */ 00854 00855 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data 00856 * @{ 00857 */ 00858 #define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */ 00859 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ 00860 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ 00861 /** 00862 * @} 00863 */ 00864 00865 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 00866 * @{ 00867 */ 00868 #define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */ 00869 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ 00870 /** 00871 * @} 00872 */ 00873 00874 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length 00875 * @{ 00876 */ 00877 #define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 00878 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ 00879 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ 00880 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ 00881 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ 00882 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ 00883 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ 00884 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ 00885 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ 00886 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ 00887 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ 00888 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ 00889 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ 00890 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ 00891 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ 00892 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ 00893 /** 00894 * @} 00895 */ 00896 00897 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode 00898 * @{ 00899 */ 00900 #define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ 00901 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ 00902 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ 00903 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ 00904 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ 00905 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ 00906 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ 00907 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ 00908 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ 00909 /** 00910 * @} 00911 */ 00912 00913 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 00914 * @{ 00915 */ 00916 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ 00917 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ 00918 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ 00919 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ 00920 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ 00921 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ 00922 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ 00923 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ 00924 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ 00925 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ 00926 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ 00927 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ 00928 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ 00929 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ 00930 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ 00931 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ 00932 /** 00933 * @} 00934 */ 00935 00936 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source 00937 * @{ 00938 */ 00939 #define LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */ 00940 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00941 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 00942 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00943 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00944 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00945 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00946 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00947 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00948 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00949 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00950 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 00951 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00952 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00953 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 00954 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 00955 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 00956 /** 00957 * @} 00958 */ 00959 00960 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge 00961 * @{ 00962 */ 00963 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ 00964 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ 00965 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ 00966 /** 00967 * @} 00968 */ 00969 00970 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode 00971 * @{ 00972 */ 00973 #define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ 00974 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ 00975 /** 00976 * @} 00977 */ 00978 00979 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode 00980 * @{ 00981 */ 00982 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ 00983 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */ 00984 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */ 00985 /** 00986 * @} 00987 */ 00988 00989 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length 00990 * @{ 00991 */ 00992 #define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 00993 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ 00994 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ 00995 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ 00996 /** 00997 * @} 00998 */ 00999 01000 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode 01001 * @{ 01002 */ 01003 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */ 01004 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ 01005 /** 01006 * @} 01007 */ 01008 01009 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 01010 * @{ 01011 */ 01012 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */ 01013 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */ 01014 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */ 01015 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */ 01016 /** 01017 * @} 01018 */ 01019 01020 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 01021 * @{ 01022 */ 01023 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000U) /*!< Sampling time 2.5 ADC clock cycles */ 01024 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ 01025 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */ 01026 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */ 01027 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */ 01028 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */ 01029 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */ 01030 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */ 01031 /** 01032 * @} 01033 */ 01034 01035 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 01036 * @{ 01037 */ 01038 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 01039 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 01040 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */ 01041 /** 01042 * @} 01043 */ 01044 01045 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 01046 * @{ 01047 */ 01048 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ 01049 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ 01050 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ 01051 /** 01052 * @} 01053 */ 01054 01055 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels 01056 * @{ 01057 */ 01058 #define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */ 01059 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ 01060 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ 01061 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ 01062 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ 01063 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ 01064 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ 01065 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ 01066 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ 01067 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ 01068 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ 01069 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ 01070 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ 01071 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ 01072 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ 01073 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ 01074 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ 01075 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ 01076 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ 01077 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ 01078 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ 01079 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ 01080 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ 01081 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ 01082 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ 01083 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ 01084 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ 01085 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ 01086 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ 01087 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ 01088 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ 01089 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ 01090 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ 01091 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ 01092 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ 01093 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ 01094 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ 01095 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ 01096 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ 01097 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ 01098 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ 01099 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ 01100 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ 01101 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ 01102 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ 01103 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ 01104 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ 01105 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ 01106 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ 01107 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ 01108 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ 01109 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ 01110 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ 01111 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ 01112 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ 01113 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ 01114 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ 01115 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ 01116 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ 01117 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ 01118 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ 01119 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ 01120 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ 01121 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ 01122 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ 01123 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ 01124 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ 01125 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ 01126 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ 01127 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ 01128 #if defined(ADC1) && !defined(ADC2) 01129 #define LL_ADC_AWD_CH_DAC1CH1_REG ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */ 01130 #define LL_ADC_AWD_CH_DAC1CH1_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */ 01131 #define LL_ADC_AWD_CH_DAC1CH1_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */ 01132 #define LL_ADC_AWD_CH_DAC1CH2_REG ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */ 01133 #define LL_ADC_AWD_CH_DAC1CH2_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */ 01134 #define LL_ADC_AWD_CH_DAC1CH2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */ 01135 #elif defined(ADC2) 01136 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */ 01137 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */ 01138 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */ 01139 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */ 01140 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */ 01141 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */ 01142 #if defined(ADC3) 01143 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */ 01144 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */ 01145 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */ 01146 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */ 01147 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */ 01148 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */ 01149 #endif 01150 #endif 01151 /** 01152 * @} 01153 */ 01154 01155 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds 01156 * @{ 01157 */ 01158 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */ 01159 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */ 01160 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ 01161 /** 01162 * @} 01163 */ 01164 01165 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope 01166 * @{ 01167 */ 01168 #define LL_ADC_OVS_DISABLE ((uint32_t)0x00000000U) /*!< ADC oversampling disabled. */ 01169 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ 01170 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ 01171 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */ 01172 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ 01173 /** 01174 * @} 01175 */ 01176 01177 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 01178 * @{ 01179 */ 01180 #define LL_ADC_OVS_REG_CONT ((uint32_t)0x00000000U)/*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 01181 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 01182 /** 01183 * @} 01184 */ 01185 01186 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio 01187 * @{ 01188 */ 01189 #define LL_ADC_OVS_RATIO_2 ((uint32_t)0x00000000U) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01190 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01191 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01192 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01193 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01194 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01195 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01196 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01197 /** 01198 * @} 01199 */ 01200 01201 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift 01202 * @{ 01203 */ 01204 #define LL_ADC_OVS_SHIFT_NONE ((uint32_t)0x00000000U) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 01205 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 01206 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 01207 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 01208 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 01209 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 01210 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 01211 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 01212 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 01213 /** 01214 * @} 01215 */ 01216 01217 #if defined(ADC_MULTIMODE_SUPPORT) 01218 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode 01219 * @{ 01220 */ 01221 #define LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */ 01222 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ 01223 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ 01224 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */ 01225 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 01226 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 01227 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 01228 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 01229 /** 01230 * @} 01231 */ 01232 01233 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer 01234 * @{ 01235 */ 01236 #define LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ 01237 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */ 01238 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */ 01239 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */ 01240 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */ 01241 /** 01242 * @} 01243 */ 01244 01245 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 01246 * @{ 01247 */ 01248 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 01249 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 01250 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 01251 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 01252 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 01253 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 01254 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 01255 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 01256 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 01257 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 01258 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 01259 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 01260 /** 01261 * @} 01262 */ 01263 01264 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave 01265 * @{ 01266 */ 01267 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ 01268 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ 01269 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ 01270 /** 01271 * @} 01272 */ 01273 01274 #endif /* ADC_MULTIMODE_SUPPORT */ 01275 01276 /** @defgroup ADC_LL_EC_LEGACY ADC literals legacy naming 01277 * @{ 01278 */ 01279 #define LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE) 01280 #define LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) 01281 #define LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) 01282 #define LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) 01283 #define LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) 01284 #define LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) 01285 #define LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) 01286 01287 #define LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE) 01288 #define LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) 01289 #define LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) 01290 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) 01291 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) 01292 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) 01293 #define LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) 01294 01295 #define LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) 01296 #define LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) 01297 #define LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) 01298 #define LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) 01299 #define LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) 01300 #define LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) 01301 #define LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) 01302 #define LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) 01303 #define LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) 01304 01305 /** 01306 * @} 01307 */ 01308 01309 01310 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays 01311 * @note Only ADC IP HW delays are defined in ADC LL driver driver, 01312 * not timeout values. 01313 * For details on delays values, refer to descriptions in source code 01314 * above each literal definition. 01315 * @{ 01316 */ 01317 01318 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ 01319 /* not timeout values. */ 01320 /* Timeout values for ADC operations are dependent to device clock */ 01321 /* configuration (system clock versus ADC clock), */ 01322 /* and therefore must be defined in user application. */ 01323 /* Indications for estimation of ADC timeout delays, for this */ 01324 /* STM32 serie: */ 01325 /* - ADC calibration time: maximum delay is 112/fADC. */ 01326 /* (refer to device datasheet, parameter "tCAL") */ 01327 /* - ADC enable time: maximum delay is 1 conversion cycle. */ 01328 /* (refer to device datasheet, parameter "tSTAB") */ 01329 /* - ADC disable time: maximum delay should be a few ADC clock cycles */ 01330 /* - ADC stop conversion time: maximum delay should be a few ADC clock */ 01331 /* cycles */ 01332 /* - ADC conversion time: duration depending on ADC clock and ADC */ 01333 /* configuration. */ 01334 /* (refer to device reference manual, section "Timing") */ 01335 01336 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ 01337 /* Delay set to maximum value (refer to device datasheet, */ 01338 /* parameter "tADCVREG_STUP"). */ 01339 /* Unit: us */ 01340 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ 01341 01342 /* Delay for internal voltage reference stabilization time. */ 01343 /* Delay set to maximum value (refer to device datasheet, */ 01344 /* parameter "tstart_vrefint"). */ 01345 /* Unit: us */ 01346 #define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 12U) /*!< Delay for internal voltage reference stabilization time */ 01347 01348 /* Delay for temperature sensor stabilization time. */ 01349 /* Literal set to maximum value (refer to device datasheet, */ 01350 /* parameter "tSTART"). */ 01351 /* Unit: us */ 01352 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U) /*!< Delay for temperature sensor stabilization time */ 01353 01354 /* Delay required between ADC end of calibration and ADC enable. */ 01355 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */ 01356 /* are required between ADC end of calibration and ADC enable. */ 01357 /* Wait time can be computed in user application by waiting for the */ 01358 /* equivalent number of CPU cycles, by taking into account */ 01359 /* ratio of CPU clock versus ADC clock prescalers. */ 01360 /* Unit: ADC clock cycles. */ 01361 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U) /*!< Delay required between ADC end of calibration and ADC enable */ 01362 01363 /** 01364 * @} 01365 */ 01366 01367 /** 01368 * @} 01369 */ 01370 01371 01372 /* Exported macro ------------------------------------------------------------*/ 01373 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros 01374 * @{ 01375 */ 01376 01377 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros 01378 * @{ 01379 */ 01380 01381 /** 01382 * @brief Write a value in ADC register 01383 * @param __INSTANCE__ ADC Instance 01384 * @param __REG__ Register to be written 01385 * @param __VALUE__ Value to be written in the register 01386 * @retval None 01387 */ 01388 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 01389 01390 /** 01391 * @brief Read a value in ADC register 01392 * @param __INSTANCE__ ADC Instance 01393 * @param __REG__ Register to be read 01394 * @retval Register value 01395 */ 01396 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 01397 /** 01398 * @} 01399 */ 01400 01401 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro 01402 * @{ 01403 */ 01404 01405 /** 01406 * @brief Helper macro to get ADC channel number in decimal format 01407 * from literals LL_ADC_CHANNEL_x. 01408 * @note Example: 01409 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) 01410 * will return decimal number "4". 01411 * @note The input can be a value from functions where a channel 01412 * number is returned, either defined with number 01413 * or with bitfield (only one bit must be set). 01414 * @param __CHANNEL__ This parameter can be one of the following values: 01415 * @arg @ref LL_ADC_CHANNEL_0 01416 * @arg @ref LL_ADC_CHANNEL_1 (7) 01417 * @arg @ref LL_ADC_CHANNEL_2 (7) 01418 * @arg @ref LL_ADC_CHANNEL_3 (7) 01419 * @arg @ref LL_ADC_CHANNEL_4 (7) 01420 * @arg @ref LL_ADC_CHANNEL_5 (7) 01421 * @arg @ref LL_ADC_CHANNEL_6 01422 * @arg @ref LL_ADC_CHANNEL_7 01423 * @arg @ref LL_ADC_CHANNEL_8 01424 * @arg @ref LL_ADC_CHANNEL_9 01425 * @arg @ref LL_ADC_CHANNEL_10 01426 * @arg @ref LL_ADC_CHANNEL_11 01427 * @arg @ref LL_ADC_CHANNEL_12 01428 * @arg @ref LL_ADC_CHANNEL_13 01429 * @arg @ref LL_ADC_CHANNEL_14 01430 * @arg @ref LL_ADC_CHANNEL_15 01431 * @arg @ref LL_ADC_CHANNEL_16 01432 * @arg @ref LL_ADC_CHANNEL_17 01433 * @arg @ref LL_ADC_CHANNEL_18 01434 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01435 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01436 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01437 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01438 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01439 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01440 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01441 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01442 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01443 * 01444 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01445 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01446 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01447 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01448 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01449 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01450 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01451 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01452 * @retval Value between Min_Data=0 and Max_Data=18 01453 */ 01454 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 01455 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \ 01456 ? ( \ 01457 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ 01458 ) \ 01459 : \ 01460 ( \ 01461 POSITION_VAL((__CHANNEL__)) \ 01462 ) \ 01463 ) 01464 01465 /** 01466 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x 01467 * from number in decimal format. 01468 * @note Example: 01469 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) 01470 * will return a data equivalent to "LL_ADC_CHANNEL_4". 01471 * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 01472 * @retval Returned value can be one of the following values: 01473 * @arg @ref LL_ADC_CHANNEL_0 01474 * @arg @ref LL_ADC_CHANNEL_1 (7) 01475 * @arg @ref LL_ADC_CHANNEL_2 (7) 01476 * @arg @ref LL_ADC_CHANNEL_3 (7) 01477 * @arg @ref LL_ADC_CHANNEL_4 (7) 01478 * @arg @ref LL_ADC_CHANNEL_5 (7) 01479 * @arg @ref LL_ADC_CHANNEL_6 01480 * @arg @ref LL_ADC_CHANNEL_7 01481 * @arg @ref LL_ADC_CHANNEL_8 01482 * @arg @ref LL_ADC_CHANNEL_9 01483 * @arg @ref LL_ADC_CHANNEL_10 01484 * @arg @ref LL_ADC_CHANNEL_11 01485 * @arg @ref LL_ADC_CHANNEL_12 01486 * @arg @ref LL_ADC_CHANNEL_13 01487 * @arg @ref LL_ADC_CHANNEL_14 01488 * @arg @ref LL_ADC_CHANNEL_15 01489 * @arg @ref LL_ADC_CHANNEL_16 01490 * @arg @ref LL_ADC_CHANNEL_17 01491 * @arg @ref LL_ADC_CHANNEL_18 01492 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01493 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01494 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01495 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01496 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01497 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01498 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01499 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01500 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01501 * 01502 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01503 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01504 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01505 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01506 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01507 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01508 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01509 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 01510 * (1, 2, 3, 4) For ADC channel read back from ADC register, 01511 * comparison with internal channel parameter to be done 01512 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01513 */ 01514 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 01515 (((__DECIMAL_NB__) <= 9U) \ 01516 ? ( \ 01517 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 01518 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ 01519 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 01520 ) \ 01521 : \ 01522 ( \ 01523 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 01524 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ 01525 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 01526 ) \ 01527 ) 01528 01529 /** 01530 * @brief Helper macro to determine whether the selected channel 01531 * corresponds to literal definitions of driver. 01532 * @note The different literal definitions of ADC channels are: 01533 * - ADC internal channel: 01534 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... 01535 * - ADC external channel (channel connected to a GPIO pin): 01536 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... 01537 * @note The channel parameter must be a value defined from literal 01538 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01539 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01540 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), 01541 * must not be a value from functions where a channel number is 01542 * returned from ADC registers, 01543 * because internal and external channels share the same channel 01544 * number in ADC registers. The differentiation is made only with 01545 * parameters definitions of driver. 01546 * @param __CHANNEL__ This parameter can be one of the following values: 01547 * @arg @ref LL_ADC_CHANNEL_0 01548 * @arg @ref LL_ADC_CHANNEL_1 (7) 01549 * @arg @ref LL_ADC_CHANNEL_2 (7) 01550 * @arg @ref LL_ADC_CHANNEL_3 (7) 01551 * @arg @ref LL_ADC_CHANNEL_4 (7) 01552 * @arg @ref LL_ADC_CHANNEL_5 (7) 01553 * @arg @ref LL_ADC_CHANNEL_6 01554 * @arg @ref LL_ADC_CHANNEL_7 01555 * @arg @ref LL_ADC_CHANNEL_8 01556 * @arg @ref LL_ADC_CHANNEL_9 01557 * @arg @ref LL_ADC_CHANNEL_10 01558 * @arg @ref LL_ADC_CHANNEL_11 01559 * @arg @ref LL_ADC_CHANNEL_12 01560 * @arg @ref LL_ADC_CHANNEL_13 01561 * @arg @ref LL_ADC_CHANNEL_14 01562 * @arg @ref LL_ADC_CHANNEL_15 01563 * @arg @ref LL_ADC_CHANNEL_16 01564 * @arg @ref LL_ADC_CHANNEL_17 01565 * @arg @ref LL_ADC_CHANNEL_18 01566 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01567 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01568 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01569 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01570 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01571 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01572 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01573 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01574 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01575 * 01576 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01577 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01578 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01579 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01580 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01581 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01582 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01583 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01584 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 01585 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 01586 */ 01587 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 01588 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) 01589 01590 /** 01591 * @brief Helper macro to convert a channel defined from parameter 01592 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01593 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01594 * to its equivalent parameter definition of a ADC external channel 01595 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). 01596 * @note The channel parameter can be, additionally to a value 01597 * defined from parameter definition of a ADC internal channel 01598 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), 01599 * a value defined from parameter definition of 01600 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 01601 * or a value from functions where a channel number is returned 01602 * from ADC registers. 01603 * @param __CHANNEL__ This parameter can be one of the following values: 01604 * @arg @ref LL_ADC_CHANNEL_0 01605 * @arg @ref LL_ADC_CHANNEL_1 (7) 01606 * @arg @ref LL_ADC_CHANNEL_2 (7) 01607 * @arg @ref LL_ADC_CHANNEL_3 (7) 01608 * @arg @ref LL_ADC_CHANNEL_4 (7) 01609 * @arg @ref LL_ADC_CHANNEL_5 (7) 01610 * @arg @ref LL_ADC_CHANNEL_6 01611 * @arg @ref LL_ADC_CHANNEL_7 01612 * @arg @ref LL_ADC_CHANNEL_8 01613 * @arg @ref LL_ADC_CHANNEL_9 01614 * @arg @ref LL_ADC_CHANNEL_10 01615 * @arg @ref LL_ADC_CHANNEL_11 01616 * @arg @ref LL_ADC_CHANNEL_12 01617 * @arg @ref LL_ADC_CHANNEL_13 01618 * @arg @ref LL_ADC_CHANNEL_14 01619 * @arg @ref LL_ADC_CHANNEL_15 01620 * @arg @ref LL_ADC_CHANNEL_16 01621 * @arg @ref LL_ADC_CHANNEL_17 01622 * @arg @ref LL_ADC_CHANNEL_18 01623 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01624 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01625 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01626 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01627 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01628 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01629 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01630 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01631 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01632 * 01633 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01634 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01635 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01636 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01637 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01638 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01639 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01640 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01641 * @retval Returned value can be one of the following values: 01642 * @arg @ref LL_ADC_CHANNEL_0 01643 * @arg @ref LL_ADC_CHANNEL_1 01644 * @arg @ref LL_ADC_CHANNEL_2 01645 * @arg @ref LL_ADC_CHANNEL_3 01646 * @arg @ref LL_ADC_CHANNEL_4 01647 * @arg @ref LL_ADC_CHANNEL_5 01648 * @arg @ref LL_ADC_CHANNEL_6 01649 * @arg @ref LL_ADC_CHANNEL_7 01650 * @arg @ref LL_ADC_CHANNEL_8 01651 * @arg @ref LL_ADC_CHANNEL_9 01652 * @arg @ref LL_ADC_CHANNEL_10 01653 * @arg @ref LL_ADC_CHANNEL_11 01654 * @arg @ref LL_ADC_CHANNEL_12 01655 * @arg @ref LL_ADC_CHANNEL_13 01656 * @arg @ref LL_ADC_CHANNEL_14 01657 * @arg @ref LL_ADC_CHANNEL_15 01658 * @arg @ref LL_ADC_CHANNEL_16 01659 * @arg @ref LL_ADC_CHANNEL_17 01660 * @arg @ref LL_ADC_CHANNEL_18 01661 */ 01662 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 01663 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) 01664 01665 /** 01666 * @brief Helper macro to determine whether the internal channel 01667 * selected is available on the ADC instance selected. 01668 * @note The channel parameter must be a value defined from parameter 01669 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01670 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01671 * must not be a value defined from parameter definition of 01672 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 01673 * or a value from functions where a channel number is 01674 * returned from ADC registers, 01675 * because internal and external channels share the same channel 01676 * number in ADC registers. The differentiation is made only with 01677 * parameters definitions of driver. 01678 * @param __ADC_INSTANCE__ ADC instance 01679 * @param __CHANNEL__ This parameter can be one of the following values: 01680 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01681 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01682 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01683 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01684 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01685 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01686 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01687 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01688 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01689 * 01690 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01691 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01692 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01693 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01694 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01695 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01696 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 01697 * Value "1" if the internal channel selected is available on the ADC instance selected. 01698 */ 01699 #if defined (ADC1) && defined (ADC2) && defined (ADC3) 01700 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01701 (((__ADC_INSTANCE__) == ADC1) \ 01702 ? ( \ 01703 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01704 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 01705 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ 01706 ) \ 01707 : \ 01708 ((__ADC_INSTANCE__) == ADC2) \ 01709 ? ( \ 01710 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01711 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \ 01712 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \ 01713 ) \ 01714 : \ 01715 ((__ADC_INSTANCE__) == ADC3) \ 01716 ? ( \ 01717 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01718 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 01719 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ 01720 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) || \ 01721 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \ 01722 ) \ 01723 : \ 01724 (0U) \ 01725 ) 01726 #elif defined (ADC1) && defined (ADC2) 01727 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01728 (((__ADC_INSTANCE__) == ADC1) \ 01729 ? ( \ 01730 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01731 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 01732 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ 01733 ) \ 01734 : \ 01735 ((__ADC_INSTANCE__) == ADC2) \ 01736 ? ( \ 01737 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01738 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \ 01739 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \ 01740 ) \ 01741 : \ 01742 (0U) \ 01743 ) 01744 #elif defined (ADC1) 01745 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01746 ( \ 01747 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01748 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 01749 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ 01750 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1) || \ 01751 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2) \ 01752 ) 01753 #endif 01754 01755 /** 01756 * @brief Helper macro to define ADC analog watchdog parameter: 01757 * define a single channel to monitor with analog watchdog 01758 * from sequencer channel and groups definition. 01759 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). 01760 * Example: 01761 * LL_ADC_SetAnalogWDMonitChannels( 01762 * ADC1, LL_ADC_AWD1, 01763 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) 01764 * @param __CHANNEL__ This parameter can be one of the following values: 01765 * @arg @ref LL_ADC_CHANNEL_0 01766 * @arg @ref LL_ADC_CHANNEL_1 (7) 01767 * @arg @ref LL_ADC_CHANNEL_2 (7) 01768 * @arg @ref LL_ADC_CHANNEL_3 (7) 01769 * @arg @ref LL_ADC_CHANNEL_4 (7) 01770 * @arg @ref LL_ADC_CHANNEL_5 (7) 01771 * @arg @ref LL_ADC_CHANNEL_6 01772 * @arg @ref LL_ADC_CHANNEL_7 01773 * @arg @ref LL_ADC_CHANNEL_8 01774 * @arg @ref LL_ADC_CHANNEL_9 01775 * @arg @ref LL_ADC_CHANNEL_10 01776 * @arg @ref LL_ADC_CHANNEL_11 01777 * @arg @ref LL_ADC_CHANNEL_12 01778 * @arg @ref LL_ADC_CHANNEL_13 01779 * @arg @ref LL_ADC_CHANNEL_14 01780 * @arg @ref LL_ADC_CHANNEL_15 01781 * @arg @ref LL_ADC_CHANNEL_16 01782 * @arg @ref LL_ADC_CHANNEL_17 01783 * @arg @ref LL_ADC_CHANNEL_18 01784 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01785 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01786 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01787 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01788 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01789 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01790 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01791 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01792 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01793 * 01794 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01795 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01796 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01797 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01798 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01799 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01800 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01801 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 01802 * (1, 2, 3, 4) For ADC channel read back from ADC register, 01803 * comparison with internal channel parameter to be done 01804 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01805 * @param __GROUP__ This parameter can be one of the following values: 01806 * @arg @ref LL_ADC_GROUP_REGULAR 01807 * @arg @ref LL_ADC_GROUP_INJECTED 01808 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED 01809 * @retval Returned value can be one of the following values: 01810 * @arg @ref LL_ADC_AWD_DISABLE 01811 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) 01812 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) 01813 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 01814 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) 01815 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) 01816 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 01817 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) 01818 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) 01819 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 01820 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) 01821 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) 01822 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 01823 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) 01824 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) 01825 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 01826 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) 01827 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) 01828 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 01829 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) 01830 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) 01831 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 01832 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) 01833 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) 01834 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 01835 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) 01836 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) 01837 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 01838 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) 01839 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) 01840 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 01841 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) 01842 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) 01843 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 01844 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) 01845 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) 01846 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 01847 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) 01848 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) 01849 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 01850 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) 01851 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) 01852 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 01853 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) 01854 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) 01855 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 01856 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) 01857 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) 01858 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 01859 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) 01860 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) 01861 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 01862 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) 01863 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) 01864 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 01865 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) 01866 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) 01867 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 01868 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) 01869 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) 01870 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 01871 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1) 01872 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1) 01873 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 01874 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4) 01875 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4) 01876 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4) 01877 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4) 01878 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4) 01879 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4) 01880 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5) 01881 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5) 01882 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5) 01883 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5) 01884 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5) 01885 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5) 01886 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6) 01887 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6) 01888 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6) 01889 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6) 01890 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6) 01891 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6) 01892 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6) 01893 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6) 01894 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6) 01895 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6) 01896 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6) 01897 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6) 01898 * 01899 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n 01900 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01901 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01902 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01903 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. 01904 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01905 * (6) On STM32L4, parameter available on devices with several ADC instances. 01906 */ 01907 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ 01908 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ 01909 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ 01910 : \ 01911 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ 01912 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ 01913 : \ 01914 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ 01915 ) 01916 01917 /** 01918 * @brief Helper macro to set the value of ADC analog watchdog threshold high 01919 * or low in function of ADC resolution, when ADC resolution is 01920 * different of 12 bits. 01921 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() 01922 * or @ref LL_ADC_SetAnalogWDThresholds(). 01923 * Example, with a ADC resolution of 8 bits, to set the value of 01924 * analog watchdog threshold high (on 8 bits): 01925 * LL_ADC_SetAnalogWDThresholds 01926 * (< ADCx param >, 01927 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) 01928 * ); 01929 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01930 * @arg @ref LL_ADC_RESOLUTION_12B 01931 * @arg @ref LL_ADC_RESOLUTION_10B 01932 * @arg @ref LL_ADC_RESOLUTION_8B 01933 * @arg @ref LL_ADC_RESOLUTION_6B 01934 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF 01935 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01936 */ 01937 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ 01938 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) 01939 01940 /** 01941 * @brief Helper macro to get the value of ADC analog watchdog threshold high 01942 * or low in function of ADC resolution, when ADC resolution is 01943 * different of 12 bits. 01944 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). 01945 * Example, with a ADC resolution of 8 bits, to get the value of 01946 * analog watchdog threshold high (on 8 bits): 01947 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION 01948 * (LL_ADC_RESOLUTION_8B, 01949 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) 01950 * ); 01951 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01952 * @arg @ref LL_ADC_RESOLUTION_12B 01953 * @arg @ref LL_ADC_RESOLUTION_10B 01954 * @arg @ref LL_ADC_RESOLUTION_8B 01955 * @arg @ref LL_ADC_RESOLUTION_6B 01956 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF 01957 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01958 */ 01959 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ 01960 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) 01961 01962 /** 01963 * @brief Helper macro to get the ADC analog watchdog threshold high 01964 * or low from raw value containing both thresholds concatenated. 01965 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). 01966 * Example, to get analog watchdog threshold high from the register raw value: 01967 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>); 01968 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: 01969 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 01970 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 01971 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 01972 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01973 */ 01974 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ 01975 (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW) 01976 01977 /** 01978 * @brief Helper macro to set the ADC calibration value with both single ended 01979 * and differential modes calibration factors concatenated. 01980 * @note To be used with function @ref LL_ADC_SetCalibrationFactor(). 01981 * Example, to set calibration factors single ended to 0x55 01982 * and differential ended to 0x2A: 01983 * LL_ADC_SetCalibrationFactor( 01984 * ADC1, 01985 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A)) 01986 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F 01987 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F 01988 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 01989 */ 01990 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ 01991 (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__)) 01992 01993 #if defined(ADC_MULTIMODE_SUPPORT) 01994 /** 01995 * @brief Helper macro to get the ADC multimode conversion data of ADC master 01996 * or ADC slave from raw value with both ADC conversion data concatenated. 01997 * @note This macro is intended to be used when multimode transfer by DMA 01998 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 01999 * In this case the transferred data need to processed with this macro 02000 * to separate the conversion data of ADC master and ADC slave. 02001 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 02002 * @arg @ref LL_ADC_MULTI_MASTER 02003 * @arg @ref LL_ADC_MULTI_SLAVE 02004 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 02005 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 02006 */ 02007 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 02008 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) 02009 #endif 02010 02011 /** 02012 * @brief Helper macro to select the ADC common instance 02013 * to which is belonging the selected ADC instance. 02014 * @note ADC common register instance can be used for: 02015 * - Set parameters common to several ADC instances 02016 * - Multimode (for devices with several ADC instances) 02017 * Refer to functions having argument "ADCxy_COMMON" as parameter. 02018 * @param __ADCx__ ADC instance 02019 * @retval ADC common register instance 02020 */ 02021 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 02022 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 02023 (ADC123_COMMON) 02024 #elif defined(ADC1) && defined(ADC2) 02025 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 02026 (ADC12_COMMON) 02027 #else 02028 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 02029 (ADC1_COMMON) 02030 #endif 02031 02032 /** 02033 * @brief Helper macro to check if all ADC instances sharing the same 02034 * ADC common instance are disabled. 02035 * @note This check is required by functions with setting conditioned to 02036 * ADC state: 02037 * All ADC instances of the ADC common group must be disabled. 02038 * Refer to functions having argument "ADCxy_COMMON" as parameter. 02039 * @note On devices with only 1 ADC common instance, parameter of this macro 02040 * is useless and can be ignored (parameter kept for compatibility 02041 * with devices featuring several ADC common instances). 02042 * @param __ADCXY_COMMON__ ADC common instance 02043 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 02044 * @retval Value "0" if all ADC instances sharing the same ADC common instance 02045 * are disabled. 02046 * Value "1" if at least one ADC instance sharing the same ADC common instance 02047 * is enabled. 02048 */ 02049 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 02050 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 02051 (LL_ADC_IsEnabled(ADC1) | \ 02052 LL_ADC_IsEnabled(ADC2) | \ 02053 LL_ADC_IsEnabled(ADC3) ) 02054 #elif defined(ADC1) && defined(ADC2) 02055 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 02056 (LL_ADC_IsEnabled(ADC1) | \ 02057 LL_ADC_IsEnabled(ADC2) ) 02058 #else 02059 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 02060 (LL_ADC_IsEnabled(ADC1)) 02061 #endif 02062 02063 /** 02064 * @brief Helper macro to define the ADC conversion data full-scale digital 02065 * value corresponding to the selected ADC resolution. 02066 * @note ADC conversion data full-scale corresponds to voltage range 02067 * determined by analog voltage references Vref+ and Vref- 02068 * (refer to reference manual). 02069 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 02070 * @arg @ref LL_ADC_RESOLUTION_12B 02071 * @arg @ref LL_ADC_RESOLUTION_10B 02072 * @arg @ref LL_ADC_RESOLUTION_8B 02073 * @arg @ref LL_ADC_RESOLUTION_6B 02074 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 02075 */ 02076 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 02077 (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) 02078 02079 /** 02080 * @brief Helper macro to convert the ADC conversion data from 02081 * a resolution to another resolution. 02082 * @param __DATA__ ADC conversion data to be converted 02083 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 02084 * This parameter can be one of the following values: 02085 * @arg @ref LL_ADC_RESOLUTION_12B 02086 * @arg @ref LL_ADC_RESOLUTION_10B 02087 * @arg @ref LL_ADC_RESOLUTION_8B 02088 * @arg @ref LL_ADC_RESOLUTION_6B 02089 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 02090 * This parameter can be one of the following values: 02091 * @arg @ref LL_ADC_RESOLUTION_12B 02092 * @arg @ref LL_ADC_RESOLUTION_10B 02093 * @arg @ref LL_ADC_RESOLUTION_8B 02094 * @arg @ref LL_ADC_RESOLUTION_6B 02095 * @retval ADC conversion data to the requested resolution 02096 */ 02097 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 02098 __ADC_RESOLUTION_CURRENT__,\ 02099 __ADC_RESOLUTION_TARGET__) \ 02100 (((__DATA__) \ 02101 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) \ 02102 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)) \ 02103 ) 02104 02105 /** 02106 * @brief Helper macro to calculate the voltage (unit: mVolt) 02107 * corresponding to a ADC conversion data (unit: digital value). 02108 * @note Analog reference voltage (Vref+) must be either known from 02109 * user board environment or can be calculated using ADC measurement 02110 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 02111 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 02112 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 02113 * (unit: digital value). 02114 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 02115 * @arg @ref LL_ADC_RESOLUTION_12B 02116 * @arg @ref LL_ADC_RESOLUTION_10B 02117 * @arg @ref LL_ADC_RESOLUTION_8B 02118 * @arg @ref LL_ADC_RESOLUTION_6B 02119 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 02120 */ 02121 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 02122 __ADC_DATA__,\ 02123 __ADC_RESOLUTION__) \ 02124 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ 02125 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 02126 ) 02127 02128 /* Legacy define */ 02129 #define __LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE() 02130 02131 /** 02132 * @brief Helper macro to calculate analog reference voltage (Vref+) 02133 * (unit: mVolt) from ADC conversion data of internal voltage 02134 * reference VrefInt. 02135 * @note Computation is using VrefInt calibration value 02136 * stored in system memory for each device during production. 02137 * @note This voltage depends on user board environment: voltage level 02138 * connected to pin Vref+. 02139 * On devices with small package, the pin Vref+ is not present 02140 * and internally bonded to pin Vdda. 02141 * @note On this STM32 serie, calibration data of internal voltage reference 02142 * VrefInt corresponds to a resolution of 12 bits, 02143 * this is the recommended ADC resolution to convert voltage of 02144 * internal voltage reference VrefInt. 02145 * Otherwise, this macro performs the processing to scale 02146 * ADC conversion data to 12 bits. 02147 * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits) 02148 * of internal voltage reference VrefInt (unit: digital value). 02149 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 02150 * @arg @ref LL_ADC_RESOLUTION_12B 02151 * @arg @ref LL_ADC_RESOLUTION_10B 02152 * @arg @ref LL_ADC_RESOLUTION_8B 02153 * @arg @ref LL_ADC_RESOLUTION_6B 02154 * @retval Analog reference voltage (unit: mV) 02155 */ 02156 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 02157 __ADC_RESOLUTION__) \ 02158 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ 02159 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ 02160 (__ADC_RESOLUTION__), \ 02161 LL_ADC_RESOLUTION_12B) \ 02162 ) 02163 02164 /** 02165 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 02166 * from ADC conversion data of internal temperature sensor. 02167 * @note Computation is using temperature sensor calibration values 02168 * stored in system memory for each device during production. 02169 * @note Calculation formula: 02170 * Temperature = ((TS_ADC_DATA - TS_CAL1) 02171 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 02172 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 02173 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 02174 * Avg_Slope = (TS_CAL2 - TS_CAL1) 02175 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 02176 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 02177 * TEMP_DEGC_CAL1 (calibrated in factory) 02178 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 02179 * TEMP_DEGC_CAL2 (calibrated in factory) 02180 * Caution: Calculation relevancy under reserve that calibration 02181 * parameters are correct (address and data). 02182 * To calculate temperature using temperature sensor 02183 * datasheet typical values (generic values less, therefore 02184 * less accurate than calibrated values), 02185 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 02186 * @note As calculation input, the analog reference voltage (Vref+) must be 02187 * defined as it impacts the ADC LSB equivalent voltage. 02188 * @note Analog reference voltage (Vref+) must be either known from 02189 * user board environment or can be calculated using ADC measurement 02190 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 02191 * @note On this STM32 serie, calibration data of temperature sensor 02192 * corresponds to a resolution of 12 bits, 02193 * this is the recommended ADC resolution to convert voltage of 02194 * temperature sensor. 02195 * Otherwise, this macro performs the processing to scale 02196 * ADC conversion data to 12 bits. 02197 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 02198 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 02199 * temperature sensor (unit: digital value). 02200 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 02201 * sensor voltage has been measured. 02202 * This parameter can be one of the following values: 02203 * @arg @ref LL_ADC_RESOLUTION_12B 02204 * @arg @ref LL_ADC_RESOLUTION_10B 02205 * @arg @ref LL_ADC_RESOLUTION_8B 02206 * @arg @ref LL_ADC_RESOLUTION_6B 02207 * @retval Temperature (unit: degree Celsius) 02208 */ 02209 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 02210 __TEMPSENSOR_ADC_DATA__,\ 02211 __ADC_RESOLUTION__) \ 02212 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ 02213 (__ADC_RESOLUTION__), \ 02214 LL_ADC_RESOLUTION_12B) \ 02215 * (__VREFANALOG_VOLTAGE__)) \ 02216 / TEMPSENSOR_CAL_VREFANALOG) \ 02217 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ 02218 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ 02219 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ 02220 ) + TEMPSENSOR_CAL1_TEMP \ 02221 ) 02222 02223 /** 02224 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 02225 * from ADC conversion data of internal temperature sensor. 02226 * @note Computation is using temperature sensor typical values 02227 * (refer to device datasheet). 02228 * @note Calculation formula: 02229 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 02230 * / Avg_Slope + CALx_TEMP 02231 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 02232 * (unit: digital value) 02233 * Avg_Slope = temperature sensor slope 02234 * (unit: uV/Degree Celsius) 02235 * TS_TYP_CALx_VOLT = temperature sensor digital value at 02236 * temperature CALx_TEMP (unit: mV) 02237 * Caution: Calculation relevancy under reserve the temperature sensor 02238 * of the current device has characteristics in line with 02239 * datasheet typical values. 02240 * If temperature sensor calibration values are available on 02241 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 02242 * temperature calculation will be more accurate using 02243 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 02244 * @note As calculation input, the analog reference voltage (Vref+) must be 02245 * defined as it impacts the ADC LSB equivalent voltage. 02246 * @note Analog reference voltage (Vref+) must be either known from 02247 * user board environment or can be calculated using ADC measurement 02248 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 02249 * @note ADC measurement data must correspond to a resolution of 12bits 02250 * (full scale digital value 4095). If not the case, the data must be 02251 * preliminarily rescaled to an equivalent resolution of 12 bits. 02252 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 02253 * On STM32L4, refer to device datasheet parameter "Avg_Slope". 02254 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 02255 * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 02256 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 02257 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 02258 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 02259 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 02260 * This parameter can be one of the following values: 02261 * @arg @ref LL_ADC_RESOLUTION_12B 02262 * @arg @ref LL_ADC_RESOLUTION_10B 02263 * @arg @ref LL_ADC_RESOLUTION_8B 02264 * @arg @ref LL_ADC_RESOLUTION_6B 02265 * @retval Temperature (unit: degree Celsius) 02266 */ 02267 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 02268 __TEMPSENSOR_TYP_CALX_V__,\ 02269 __TEMPSENSOR_CALX_TEMP__,\ 02270 __VREFANALOG_VOLTAGE__,\ 02271 __TEMPSENSOR_ADC_DATA__,\ 02272 __ADC_RESOLUTION__) \ 02273 ((( ( \ 02274 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ 02275 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ 02276 * 1000) \ 02277 - \ 02278 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ 02279 * 1000) \ 02280 ) \ 02281 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ 02282 ) + (__TEMPSENSOR_CALX_TEMP__) \ 02283 ) 02284 02285 /** 02286 * @} 02287 */ 02288 02289 /** 02290 * @} 02291 */ 02292 02293 02294 /* Exported functions --------------------------------------------------------*/ 02295 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions 02296 * @{ 02297 */ 02298 02299 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management 02300 * @{ 02301 */ 02302 /* Note: LL ADC functions to set DMA transfer are located into sections of */ 02303 /* configuration of ADC instance, groups and multimode (if available): */ 02304 /* @ref LL_ADC_REG_SetDMATransfer(), ... */ 02305 02306 /** 02307 * @brief Function to help to configure DMA transfer from ADC: retrieve the 02308 * ADC register address from ADC instance and a list of ADC registers 02309 * intended to be used (most commonly) with DMA transfer. 02310 * @note These ADC registers are data registers: 02311 * when ADC conversion data is available in ADC data registers, 02312 * ADC generates a DMA transfer request. 02313 * @note This macro is intended to be used with LL DMA driver, refer to 02314 * function "LL_DMA_ConfigAddresses()". 02315 * Example: 02316 * LL_DMA_ConfigAddresses(DMA1, 02317 * LL_DMA_CHANNEL_1, 02318 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), 02319 * (uint32_t)&< array or variable >, 02320 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); 02321 * @note For devices with several ADC: in multimode, some devices 02322 * use a different data register outside of ADC instance scope 02323 * (common data register). This macro manages this register difference, 02324 * only ADC instance has to be set as parameter. 02325 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n 02326 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n 02327 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr 02328 * @param ADCx ADC instance 02329 * @param Register This parameter can be one of the following values: 02330 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA 02331 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) 02332 * 02333 * (1) Available on devices with several ADC instances. 02334 * @retval ADC register address 02335 */ 02336 #if defined(ADC_MULTIMODE_SUPPORT) 02337 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 02338 { 02339 register uint32_t data_reg_addr = 0U; 02340 02341 if (Register == LL_ADC_DMA_REG_REGULAR_DATA) 02342 { 02343 /* Retrieve address of register DR */ 02344 data_reg_addr = (uint32_t)&(ADCx->DR); 02345 } 02346 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ 02347 { 02348 /* Retrieve address of register CDR */ 02349 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); 02350 } 02351 02352 return data_reg_addr; 02353 } 02354 #else 02355 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 02356 { 02357 /* Retrieve address of register DR */ 02358 return (uint32_t)&(ADCx->DR); 02359 } 02360 #endif 02361 02362 /** 02363 * @} 02364 */ 02365 02366 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances 02367 * @{ 02368 */ 02369 02370 /** 02371 * @brief Set parameter common to several ADC: Clock source and prescaler. 02372 * @note On this STM32 serie, if ADC group injected is used, some 02373 * clock ratio constraints between ADC clock and AHB clock 02374 * must be respected. 02375 * Refer to reference manual. 02376 * @note On this STM32 serie, setting of this feature is conditioned to 02377 * ADC state: 02378 * All ADC instances of the ADC common group must be disabled. 02379 * This check can be done with function @ref LL_ADC_IsEnabled() for each 02380 * ADC instance or by using helper macro helper macro 02381 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). 02382 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n 02383 * CCR PRESC LL_ADC_SetCommonClock 02384 * @param ADCxy_COMMON ADC common instance 02385 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 02386 * @param CommonClock This parameter can be one of the following values: 02387 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 02388 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 02389 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 02390 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 02391 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 02392 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 02393 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 02394 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 02395 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 02396 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 02397 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 02398 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 02399 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 02400 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 02401 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 02402 * @retval None 02403 */ 02404 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) 02405 { 02406 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 02407 } 02408 02409 /** 02410 * @brief Get parameter common to several ADC: Clock source and prescaler. 02411 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n 02412 * CCR PRESC LL_ADC_GetCommonClock 02413 * @param ADCxy_COMMON ADC common instance 02414 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 02415 * @retval Returned value can be one of the following values: 02416 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 02417 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 02418 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 02419 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 02420 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 02421 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 02422 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 02423 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 02424 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 02425 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 02426 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 02427 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 02428 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 02429 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 02430 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 02431 */ 02432 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) 02433 { 02434 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); 02435 } 02436 02437 /** 02438 * @brief Set parameter common to several ADC: measurement path to internal 02439 * channels (VrefInt, temperature sensor, ...). 02440 * @note One or several values can be selected. 02441 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 02442 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 02443 * @note Stabilization time of measurement path to internal channel: 02444 * After enabling internal paths, before starting ADC conversion, 02445 * a delay is required for internal voltage reference and 02446 * temperature sensor stabilization time. 02447 * Refer to device datasheet. 02448 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. 02449 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. 02450 * @note ADC internal channel sampling time constraint: 02451 * For ADC conversion of internal channels, 02452 * a sampling time minimum value is required. 02453 * Refer to device datasheet. 02454 * @note On this STM32 serie, setting of this feature is conditioned to 02455 * ADC state: 02456 * All ADC instances of the ADC common group must be disabled. 02457 * This check can be done with function @ref LL_ADC_IsEnabled() for each 02458 * ADC instance or by using helper macro helper macro 02459 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). 02460 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n 02461 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n 02462 * CCR VBATEN LL_ADC_SetCommonPathInternalCh 02463 * @param ADCxy_COMMON ADC common instance 02464 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 02465 * @param PathInternal This parameter can be a combination of the following values: 02466 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 02467 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 02468 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 02469 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT 02470 * @retval None 02471 */ 02472 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) 02473 { 02474 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 02475 } 02476 02477 /** 02478 * @brief Get parameter common to several ADC: measurement path to internal 02479 * channels (VrefInt, temperature sensor, ...). 02480 * @note One or several values can be selected. 02481 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 02482 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 02483 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n 02484 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n 02485 * CCR VBATEN LL_ADC_GetCommonPathInternalCh 02486 * @param ADCxy_COMMON ADC common instance 02487 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 02488 * @retval Returned value can be a combination of the following values: 02489 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 02490 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 02491 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 02492 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT 02493 */ 02494 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) 02495 { 02496 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 02497 } 02498 02499 /** 02500 * @} 02501 */ 02502 02503 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance 02504 * @{ 02505 */ 02506 02507 /** 02508 * @brief Set ADC calibration factor in the mode single-ended 02509 * or differential (for devices with differential mode available). 02510 * @note This function is intended to set calibration parameters 02511 * without having to perform a new calibration using 02512 * @ref LL_ADC_StartCalibration(). 02513 * @note For devices with differential mode available: 02514 * Calibration of offset is specific to each of 02515 * single-ended and differential modes 02516 * (calibration factor must be specified for each of these 02517 * differential modes, if used afterwards and if the application 02518 * requires their calibration). 02519 * @note In case of setting calibration factors of both modes single ended 02520 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): 02521 * both calibration factors must be concatenated. 02522 * To perform this processing, use helper macro 02523 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). 02524 * @note On this STM32 serie, setting of this feature is conditioned to 02525 * ADC state: 02526 * ADC must be enabled, without calibration on going, without conversion 02527 * on going on group regular. 02528 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n 02529 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor 02530 * @param ADCx ADC instance 02531 * @param SingleDiff This parameter can be one of the following values: 02532 * @arg @ref LL_ADC_SINGLE_ENDED 02533 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED 02534 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED 02535 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F 02536 * @retval None 02537 */ 02538 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) 02539 { 02540 MODIFY_REG(ADCx->CALFACT, 02541 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, 02542 CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); 02543 } 02544 02545 /** 02546 * @brief Get ADC calibration factor in the mode single-ended 02547 * or differential (for devices with differential mode available). 02548 * @note Calibration factors are set by hardware after performing 02549 * a calibration run using function @ref LL_ADC_StartCalibration(). 02550 * @note For devices with differential mode available: 02551 * Calibration of offset is specific to each of 02552 * single-ended and differential modes 02553 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n 02554 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor 02555 * @param ADCx ADC instance 02556 * @param SingleDiff This parameter can be one of the following values: 02557 * @arg @ref LL_ADC_SINGLE_ENDED 02558 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED 02559 * @retval Value between Min_Data=0x00 and Max_Data=0x7F 02560 */ 02561 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) 02562 { 02563 /* Retrieve bits with position in register depending on parameter */ 02564 /* "SingleDiff". */ 02565 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ 02566 /* containing other bits reserved for other purpose. */ 02567 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); 02568 } 02569 02570 /** 02571 * @brief Set ADC resolution. 02572 * Refer to reference manual for alignments formats 02573 * dependencies to ADC resolutions. 02574 * @note On this STM32 serie, setting of this feature is conditioned to 02575 * ADC state: 02576 * ADC must be disabled or enabled without conversion on going 02577 * on either groups regular or injected. 02578 * @rmtoll CFGR RES LL_ADC_SetResolution 02579 * @param ADCx ADC instance 02580 * @param Resolution This parameter can be one of the following values: 02581 * @arg @ref LL_ADC_RESOLUTION_12B 02582 * @arg @ref LL_ADC_RESOLUTION_10B 02583 * @arg @ref LL_ADC_RESOLUTION_8B 02584 * @arg @ref LL_ADC_RESOLUTION_6B 02585 * @retval None 02586 */ 02587 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) 02588 { 02589 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution); 02590 } 02591 02592 /** 02593 * @brief Get ADC resolution. 02594 * Refer to reference manual for alignments formats 02595 * dependencies to ADC resolutions. 02596 * @rmtoll CFGR RES LL_ADC_GetResolution 02597 * @param ADCx ADC instance 02598 * @retval Returned value can be one of the following values: 02599 * @arg @ref LL_ADC_RESOLUTION_12B 02600 * @arg @ref LL_ADC_RESOLUTION_10B 02601 * @arg @ref LL_ADC_RESOLUTION_8B 02602 * @arg @ref LL_ADC_RESOLUTION_6B 02603 */ 02604 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) 02605 { 02606 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)); 02607 } 02608 02609 /** 02610 * @brief Set ADC conversion data alignment. 02611 * @note Refer to reference manual for alignments formats 02612 * dependencies to ADC resolutions. 02613 * @note On this STM32 serie, setting of this feature is conditioned to 02614 * ADC state: 02615 * ADC must be disabled or enabled without conversion on going 02616 * on either groups regular or injected. 02617 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment 02618 * @param ADCx ADC instance 02619 * @param DataAlignment This parameter can be one of the following values: 02620 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 02621 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 02622 * @retval None 02623 */ 02624 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) 02625 { 02626 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment); 02627 } 02628 02629 /** 02630 * @brief Get ADC conversion data alignment. 02631 * @note Refer to reference manual for alignments formats 02632 * dependencies to ADC resolutions. 02633 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment 02634 * @param ADCx ADC instance 02635 * @retval Returned value can be one of the following values: 02636 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 02637 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 02638 */ 02639 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) 02640 { 02641 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN)); 02642 } 02643 02644 /** 02645 * @brief Set ADC low power mode. 02646 * @note Description of ADC low power modes: 02647 * - ADC low power mode "auto wait": Dynamic low power mode, 02648 * ADC conversions occurrences are limited to the minimum necessary 02649 * in order to reduce power consumption. 02650 * New ADC conversion starts only when the previous 02651 * unitary conversion data (for ADC group regular) 02652 * or previous sequence conversions data (for ADC group injected) 02653 * has been retrieved by user software. 02654 * In the meantime, ADC remains idle: does not performs any 02655 * other conversion. 02656 * This mode allows to automatically adapt the ADC conversions 02657 * triggers to the speed of the software that reads the data. 02658 * Moreover, this avoids risk of overrun for low frequency 02659 * applications. 02660 * How to use this low power mode: 02661 * - Do not use with interruption or DMA since these modes 02662 * have to clear immediately the EOC flag to free the 02663 * IRQ vector sequencer. 02664 * - Do use with polling: 1. Start conversion, 02665 * 2. Later on, when conversion data is needed: poll for end of 02666 * conversion to ensure that conversion is completed and 02667 * retrieve ADC conversion data. This will trig another 02668 * ADC conversion start. 02669 * - ADC low power mode "auto power-off" (feature available on 02670 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): 02671 * the ADC automatically powers-off after a conversion and 02672 * automatically wakes up when a new conversion is triggered 02673 * (with startup time between trigger and start of sampling). 02674 * This feature can be combined with low power mode "auto wait". 02675 * @note With ADC low power mode "auto wait", the ADC conversion data read 02676 * is corresponding to previous ADC conversion start, independently 02677 * of delay during which ADC was idle. 02678 * Therefore, the ADC conversion data may be outdated: does not 02679 * correspond to the current voltage level on the selected 02680 * ADC channel. 02681 * @note On this STM32 serie, setting of this feature is conditioned to 02682 * ADC state: 02683 * ADC must be disabled or enabled without conversion on going 02684 * on either groups regular or injected. 02685 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode 02686 * @param ADCx ADC instance 02687 * @param LowPowerMode This parameter can be one of the following values: 02688 * @arg @ref LL_ADC_LP_MODE_NONE 02689 * @arg @ref LL_ADC_LP_AUTOWAIT 02690 * @retval None 02691 */ 02692 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) 02693 { 02694 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode); 02695 } 02696 02697 /** 02698 * @brief Get ADC low power mode: 02699 * @note Description of ADC low power modes: 02700 * - ADC low power mode "auto wait": Dynamic low power mode, 02701 * ADC conversions occurrences are limited to the minimum necessary 02702 * in order to reduce power consumption. 02703 * New ADC conversion starts only when the previous 02704 * unitary conversion data (for ADC group regular) 02705 * or previous sequence conversions data (for ADC group injected) 02706 * has been retrieved by user software. 02707 * In the meantime, ADC remains idle: does not performs any 02708 * other conversion. 02709 * This mode allows to automatically adapt the ADC conversions 02710 * triggers to the speed of the software that reads the data. 02711 * Moreover, this avoids risk of overrun for low frequency 02712 * applications. 02713 * How to use this low power mode: 02714 * - Do not use with interruption or DMA since these modes 02715 * have to clear immediately the EOC flag to free the 02716 * IRQ vector sequencer. 02717 * - Do use with polling: 1. Start conversion, 02718 * 2. Later on, when conversion data is needed: poll for end of 02719 * conversion to ensure that conversion is completed and 02720 * retrieve ADC conversion data. This will trig another 02721 * ADC conversion start. 02722 * - ADC low power mode "auto power-off" (feature available on 02723 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): 02724 * the ADC automatically powers-off after a conversion and 02725 * automatically wakes up when a new conversion is triggered 02726 * (with startup time between trigger and start of sampling). 02727 * This feature can be combined with low power mode "auto wait". 02728 * @note With ADC low power mode "auto wait", the ADC conversion data read 02729 * is corresponding to previous ADC conversion start, independently 02730 * of delay during which ADC was idle. 02731 * Therefore, the ADC conversion data may be outdated: does not 02732 * correspond to the current voltage level on the selected 02733 * ADC channel. 02734 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode 02735 * @param ADCx ADC instance 02736 * @retval Returned value can be one of the following values: 02737 * @arg @ref LL_ADC_LP_MODE_NONE 02738 * @arg @ref LL_ADC_LP_AUTOWAIT 02739 */ 02740 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) 02741 { 02742 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); 02743 } 02744 02745 /** 02746 * @brief Set ADC selected offset number 1, 2, 3 or 4. 02747 * @note This function set the 2 items of offset configuration: 02748 * - ADC channel to which the offset programmed will be applied 02749 * (independently of channel mapped on ADC group regular 02750 * or group injected) 02751 * - Offset level (offset to be subtracted from the raw 02752 * converted data). 02753 * @note Caution: Offset format is dependent to ADC resolution: 02754 * offset has to be left-aligned on bit 11, the LSB (right bits) 02755 * are set to 0. 02756 * @note This function enables the offset, by default. It can be forced 02757 * to disable state using function LL_ADC_SetOffsetState(). 02758 * @note If a channel is mapped on several offsets numbers, only the offset 02759 * with the lowest value is considered for the subtraction. 02760 * @note On this STM32 serie, setting of this feature is conditioned to 02761 * ADC state: 02762 * ADC must be disabled or enabled without conversion on going 02763 * on either groups regular or injected. 02764 * @note On STM32L4, some fast channels are available: fast analog inputs 02765 * coming from GPIO pads (ADC_IN1..5). 02766 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n 02767 * OFR1 OFFSET1 LL_ADC_SetOffset\n 02768 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n 02769 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n 02770 * OFR2 OFFSET2 LL_ADC_SetOffset\n 02771 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n 02772 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n 02773 * OFR3 OFFSET3 LL_ADC_SetOffset\n 02774 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n 02775 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n 02776 * OFR4 OFFSET4 LL_ADC_SetOffset\n 02777 * OFR4 OFFSET4_EN LL_ADC_SetOffset 02778 * @param ADCx ADC instance 02779 * @param Offsety This parameter can be one of the following values: 02780 * @arg @ref LL_ADC_OFFSET_1 02781 * @arg @ref LL_ADC_OFFSET_2 02782 * @arg @ref LL_ADC_OFFSET_3 02783 * @arg @ref LL_ADC_OFFSET_4 02784 * @param Channel This parameter can be one of the following values: 02785 * @arg @ref LL_ADC_CHANNEL_0 02786 * @arg @ref LL_ADC_CHANNEL_1 (7) 02787 * @arg @ref LL_ADC_CHANNEL_2 (7) 02788 * @arg @ref LL_ADC_CHANNEL_3 (7) 02789 * @arg @ref LL_ADC_CHANNEL_4 (7) 02790 * @arg @ref LL_ADC_CHANNEL_5 (7) 02791 * @arg @ref LL_ADC_CHANNEL_6 02792 * @arg @ref LL_ADC_CHANNEL_7 02793 * @arg @ref LL_ADC_CHANNEL_8 02794 * @arg @ref LL_ADC_CHANNEL_9 02795 * @arg @ref LL_ADC_CHANNEL_10 02796 * @arg @ref LL_ADC_CHANNEL_11 02797 * @arg @ref LL_ADC_CHANNEL_12 02798 * @arg @ref LL_ADC_CHANNEL_13 02799 * @arg @ref LL_ADC_CHANNEL_14 02800 * @arg @ref LL_ADC_CHANNEL_15 02801 * @arg @ref LL_ADC_CHANNEL_16 02802 * @arg @ref LL_ADC_CHANNEL_17 02803 * @arg @ref LL_ADC_CHANNEL_18 02804 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02805 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 02806 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 02807 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 02808 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 02809 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 02810 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 02811 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 02812 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 02813 * 02814 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 02815 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 02816 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 02817 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 02818 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 02819 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 02820 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 02821 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 02822 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF 02823 * @retval None 02824 */ 02825 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) 02826 { 02827 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 02828 02829 MODIFY_REG(*preg, 02830 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, 02831 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); 02832 } 02833 02834 /** 02835 * @brief Get for the ADC selected offset number 1, 2, 3 or 4: 02836 * Channel to which the offset programmed will be applied 02837 * (independently of channel mapped on ADC group regular 02838 * or group injected) 02839 * @note Usage of the returned channel number: 02840 * - To reinject this channel into another function LL_ADC_xxx: 02841 * the returned channel number is only partly formatted on definition 02842 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 02843 * with parts of literals LL_ADC_CHANNEL_x or using 02844 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02845 * Then the selected literal LL_ADC_CHANNEL_x can be used 02846 * as parameter for another function. 02847 * - To get the channel number in decimal format: 02848 * process the returned value with the helper macro 02849 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02850 * @note On STM32L4, some fast channels are available: fast analog inputs 02851 * coming from GPIO pads (ADC_IN1..5). 02852 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n 02853 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n 02854 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n 02855 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel 02856 * @param ADCx ADC instance 02857 * @param Offsety This parameter can be one of the following values: 02858 * @arg @ref LL_ADC_OFFSET_1 02859 * @arg @ref LL_ADC_OFFSET_2 02860 * @arg @ref LL_ADC_OFFSET_3 02861 * @arg @ref LL_ADC_OFFSET_4 02862 * @retval Returned value can be one of the following values: 02863 * @arg @ref LL_ADC_CHANNEL_0 02864 * @arg @ref LL_ADC_CHANNEL_1 (7) 02865 * @arg @ref LL_ADC_CHANNEL_2 (7) 02866 * @arg @ref LL_ADC_CHANNEL_3 (7) 02867 * @arg @ref LL_ADC_CHANNEL_4 (7) 02868 * @arg @ref LL_ADC_CHANNEL_5 (7) 02869 * @arg @ref LL_ADC_CHANNEL_6 02870 * @arg @ref LL_ADC_CHANNEL_7 02871 * @arg @ref LL_ADC_CHANNEL_8 02872 * @arg @ref LL_ADC_CHANNEL_9 02873 * @arg @ref LL_ADC_CHANNEL_10 02874 * @arg @ref LL_ADC_CHANNEL_11 02875 * @arg @ref LL_ADC_CHANNEL_12 02876 * @arg @ref LL_ADC_CHANNEL_13 02877 * @arg @ref LL_ADC_CHANNEL_14 02878 * @arg @ref LL_ADC_CHANNEL_15 02879 * @arg @ref LL_ADC_CHANNEL_16 02880 * @arg @ref LL_ADC_CHANNEL_17 02881 * @arg @ref LL_ADC_CHANNEL_18 02882 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02883 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 02884 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 02885 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 02886 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 02887 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 02888 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 02889 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 02890 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 02891 * 02892 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 02893 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 02894 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 02895 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 02896 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 02897 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 02898 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 02899 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 02900 * (1, 2, 3, 4) For ADC channel read back from ADC register, 02901 * comparison with internal channel parameter to be done 02902 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 02903 */ 02904 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) 02905 { 02906 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 02907 02908 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 02909 } 02910 02911 /** 02912 * @brief Get for the ADC selected offset number 1, 2, 3 or 4: 02913 * Offset level (offset to be subtracted from the raw 02914 * converted data). 02915 * @note Caution: Offset format is dependent to ADC resolution: 02916 * offset has to be left-aligned on bit 11, the LSB (right bits) 02917 * are set to 0. 02918 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n 02919 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n 02920 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n 02921 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel 02922 * @param ADCx ADC instance 02923 * @param Offsety This parameter can be one of the following values: 02924 * @arg @ref LL_ADC_OFFSET_1 02925 * @arg @ref LL_ADC_OFFSET_2 02926 * @arg @ref LL_ADC_OFFSET_3 02927 * @arg @ref LL_ADC_OFFSET_4 02928 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 02929 */ 02930 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) 02931 { 02932 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 02933 02934 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); 02935 } 02936 02937 /** 02938 * @brief Set for the ADC selected offset number 1, 2, 3 or 4: 02939 * force offset state disable or enable 02940 * without modifying offset channel or offset value. 02941 * @note This function should be needed only in case of offset to be 02942 * enabled-disabled dynamically, and should not be needed in other cases: 02943 * function LL_ADC_SetOffset() automatically enables the offset. 02944 * @note On this STM32 serie, setting of this feature is conditioned to 02945 * ADC state: 02946 * ADC must be disabled or enabled without conversion on going 02947 * on either groups regular or injected. 02948 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n 02949 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n 02950 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n 02951 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState 02952 * @param ADCx ADC instance 02953 * @param Offsety This parameter can be one of the following values: 02954 * @arg @ref LL_ADC_OFFSET_1 02955 * @arg @ref LL_ADC_OFFSET_2 02956 * @arg @ref LL_ADC_OFFSET_3 02957 * @arg @ref LL_ADC_OFFSET_4 02958 * @param OffsetState This parameter can be one of the following values: 02959 * @arg @ref LL_ADC_OFFSET_DISABLE 02960 * @arg @ref LL_ADC_OFFSET_ENABLE 02961 * @retval None 02962 */ 02963 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) 02964 { 02965 register uint32_t *preg = (uint32_t *)((uint32_t) 02966 ((uint32_t)(&ADCx->OFR1) + (Offsety*4U))); 02967 02968 MODIFY_REG(*preg, 02969 ADC_OFR1_OFFSET1_EN, 02970 OffsetState); 02971 } 02972 02973 /** 02974 * @brief Get for the ADC selected offset number 1, 2, 3 or 4: 02975 * offset state disabled or enabled. 02976 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n 02977 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n 02978 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n 02979 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState 02980 * @param ADCx ADC instance 02981 * @param Offsety This parameter can be one of the following values: 02982 * @arg @ref LL_ADC_OFFSET_1 02983 * @arg @ref LL_ADC_OFFSET_2 02984 * @arg @ref LL_ADC_OFFSET_3 02985 * @arg @ref LL_ADC_OFFSET_4 02986 * @retval Returned value can be one of the following values: 02987 * @arg @ref LL_ADC_OFFSET_DISABLE 02988 * @arg @ref LL_ADC_OFFSET_ENABLE 02989 */ 02990 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) 02991 { 02992 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 02993 02994 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); 02995 } 02996 02997 /** 02998 * @} 02999 */ 03000 03001 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular 03002 * @{ 03003 */ 03004 03005 /** 03006 * @brief Set ADC group regular conversion trigger source: 03007 * internal (SW start) or from external IP (timer event, 03008 * external interrupt line). 03009 * @note On this STM32 serie, setting trigger source to external trigger 03010 * also set trigger polarity to rising edge 03011 * (default setting for compatibility with some ADC on other 03012 * STM32 families having this setting set by HW default value). 03013 * In case of need to modify trigger edge, use 03014 * function @ref LL_ADC_REG_SetTriggerEdge(). 03015 * @note Availability of parameters of trigger sources from timer 03016 * depends on timers availability on the selected device. 03017 * @note On this STM32 serie, setting of this feature is conditioned to 03018 * ADC state: 03019 * ADC must be disabled or enabled without conversion on going 03020 * on group regular. 03021 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n 03022 * CFGR EXTEN LL_ADC_REG_SetTriggerSource 03023 * @param ADCx ADC instance 03024 * @param TriggerSource This parameter can be one of the following values: 03025 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 03026 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO 03027 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 03028 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 03029 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 03030 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 03031 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO 03032 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 03033 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO 03034 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 03035 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO 03036 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 03037 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO 03038 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO 03039 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 03040 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO 03041 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 03042 * @retval None 03043 */ 03044 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 03045 { 03046 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource); 03047 } 03048 03049 /** 03050 * @brief Get ADC group regular conversion trigger source: 03051 * internal (SW start) or from external IP (timer event, 03052 * external interrupt line). 03053 * @note To determine whether group regular trigger source is 03054 * internal (SW start) or external, without detail 03055 * of which peripheral is selected as external trigger, 03056 * (equivalent to 03057 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") 03058 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. 03059 * @note Availability of parameters of trigger sources from timer 03060 * depends on timers availability on the selected device. 03061 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n 03062 * CFGR EXTEN LL_ADC_REG_GetTriggerSource 03063 * @param ADCx ADC instance 03064 * @retval Returned value can be one of the following values: 03065 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 03066 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO 03067 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 03068 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 03069 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 03070 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 03071 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO 03072 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 03073 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO 03074 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 03075 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO 03076 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 03077 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO 03078 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO 03079 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 03080 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO 03081 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 03082 */ 03083 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) 03084 { 03085 register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); 03086 03087 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ 03088 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ 03089 register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); 03090 03091 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ 03092 /* to match with triggers literals definition. */ 03093 return ((TriggerSource 03094 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL) 03095 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN) 03096 ); 03097 } 03098 03099 /** 03100 * @brief Get ADC group regular conversion trigger source internal (SW start) 03101 or external. 03102 * @note In case of group regular trigger source set to external trigger, 03103 * to determine which peripheral is selected as external trigger, 03104 * use function @ref LL_ADC_REG_GetTriggerSource(). 03105 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart 03106 * @param ADCx ADC instance 03107 * @retval Value "0" if trigger source external trigger 03108 * Value "1" if trigger source SW start. 03109 */ 03110 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 03111 { 03112 return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)); 03113 } 03114 03115 /** 03116 * @brief Set ADC group regular conversion trigger polarity. 03117 * @note Applicable only for trigger source set to external trigger. 03118 * @note On this STM32 serie, setting of this feature is conditioned to 03119 * ADC state: 03120 * ADC must be disabled or enabled without conversion on going 03121 * on group regular. 03122 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge 03123 * @param ADCx ADC instance 03124 * @param ExternalTriggerEdge This parameter can be one of the following values: 03125 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 03126 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING 03127 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING 03128 * @retval None 03129 */ 03130 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 03131 { 03132 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge); 03133 } 03134 03135 /** 03136 * @brief Get ADC group regular conversion trigger polarity. 03137 * @note Applicable only for trigger source set to external trigger. 03138 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge 03139 * @param ADCx ADC instance 03140 * @retval Returned value can be one of the following values: 03141 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 03142 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING 03143 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING 03144 */ 03145 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) 03146 { 03147 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); 03148 } 03149 03150 03151 /** 03152 * @brief Set ADC group regular sequencer length and scan direction. 03153 * @note Description of ADC group regular sequencer features: 03154 * - For devices with sequencer fully configurable 03155 * (function "LL_ADC_REG_SetSequencerRanks()" available): 03156 * sequencer length and each rank affectation to a channel 03157 * are configurable. 03158 * This function performs configuration of: 03159 * - Sequence length: Number of ranks in the scan sequence. 03160 * - Sequence direction: Unless specified in parameters, sequencer 03161 * scan direction is forward (from rank 1 to rank n). 03162 * Sequencer ranks are selected using 03163 * function "LL_ADC_REG_SetSequencerRanks()". 03164 * - For devices with sequencer not fully configurable 03165 * (function "LL_ADC_REG_SetSequencerChannels()" available): 03166 * sequencer length and each rank affectation to a channel 03167 * are defined by channel number. 03168 * This function performs configuration of: 03169 * - Sequence length: Number of ranks in the scan sequence is 03170 * defined by number of channels set in the sequence, 03171 * rank of each channel is fixed by channel HW number. 03172 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 03173 * - Sequence direction: Unless specified in parameters, sequencer 03174 * scan direction is forward (from lowest channel number to 03175 * highest channel number). 03176 * Sequencer ranks are selected using 03177 * function "LL_ADC_REG_SetSequencerChannels()". 03178 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 03179 * ADC conversion on only 1 channel. 03180 * @note On this STM32 serie, setting of this feature is conditioned to 03181 * ADC state: 03182 * ADC must be disabled or enabled without conversion on going 03183 * on group regular. 03184 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 03185 * @param ADCx ADC instance 03186 * @param SequencerNbRanks This parameter can be one of the following values: 03187 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 03188 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 03189 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 03190 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 03191 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 03192 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 03193 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 03194 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 03195 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 03196 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 03197 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 03198 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 03199 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 03200 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 03201 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 03202 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 03203 * @retval None 03204 */ 03205 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 03206 { 03207 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); 03208 } 03209 03210 /** 03211 * @brief Get ADC group regular sequencer length and scan direction. 03212 * @note Description of ADC group regular sequencer features: 03213 * - For devices with sequencer fully configurable 03214 * (function "LL_ADC_REG_SetSequencerRanks()" available): 03215 * sequencer length and each rank affectation to a channel 03216 * are configurable. 03217 * This function retrieves: 03218 * - Sequence length: Number of ranks in the scan sequence. 03219 * - Sequence direction: Unless specified in parameters, sequencer 03220 * scan direction is forward (from rank 1 to rank n). 03221 * Sequencer ranks are selected using 03222 * function "LL_ADC_REG_SetSequencerRanks()". 03223 * - For devices with sequencer not fully configurable 03224 * (function "LL_ADC_REG_SetSequencerChannels()" available): 03225 * sequencer length and each rank affectation to a channel 03226 * are defined by channel number. 03227 * This function retrieves: 03228 * - Sequence length: Number of ranks in the scan sequence is 03229 * defined by number of channels set in the sequence, 03230 * rank of each channel is fixed by channel HW number. 03231 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 03232 * - Sequence direction: Unless specified in parameters, sequencer 03233 * scan direction is forward (from lowest channel number to 03234 * highest channel number). 03235 * Sequencer ranks are selected using 03236 * function "LL_ADC_REG_SetSequencerChannels()". 03237 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 03238 * ADC conversion on only 1 channel. 03239 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength 03240 * @param ADCx ADC instance 03241 * @retval Returned value can be one of the following values: 03242 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 03243 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 03244 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 03245 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 03246 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 03247 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 03248 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 03249 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 03250 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 03251 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 03252 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 03253 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 03254 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 03255 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 03256 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 03257 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 03258 */ 03259 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) 03260 { 03261 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); 03262 } 03263 03264 /** 03265 * @brief Set ADC group regular sequencer discontinuous mode: 03266 * sequence subdivided and scan conversions interrupted every selected 03267 * number of ranks. 03268 * @note It is not possible to enable both ADC group regular 03269 * continuous mode and sequencer discontinuous mode. 03270 * @note It is not possible to enable both ADC auto-injected mode 03271 * and ADC group regular sequencer discontinuous mode. 03272 * @note On this STM32 serie, setting of this feature is conditioned to 03273 * ADC state: 03274 * ADC must be disabled or enabled without conversion on going 03275 * on group regular. 03276 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n 03277 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont 03278 * @param ADCx ADC instance 03279 * @param SeqDiscont This parameter can be one of the following values: 03280 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 03281 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 03282 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 03283 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 03284 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 03285 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 03286 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 03287 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 03288 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 03289 * @retval None 03290 */ 03291 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 03292 { 03293 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont); 03294 } 03295 03296 /** 03297 * @brief Get ADC group regular sequencer discontinuous mode: 03298 * sequence subdivided and scan conversions interrupted every selected 03299 * number of ranks. 03300 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n 03301 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont 03302 * @param ADCx ADC instance 03303 * @retval Returned value can be one of the following values: 03304 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 03305 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 03306 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 03307 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 03308 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 03309 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 03310 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 03311 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 03312 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 03313 */ 03314 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) 03315 { 03316 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); 03317 } 03318 03319 /** 03320 * @brief Set ADC group regular sequence: channel on the selected 03321 * scan sequence rank. 03322 * @note This function performs configuration of: 03323 * - Channels ordering into each rank of scan sequence: 03324 * whatever channel can be placed into whatever rank. 03325 * @note On this STM32 serie, ADC group regular sequencer is 03326 * fully configurable: sequencer length and each rank 03327 * affectation to a channel are configurable. 03328 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 03329 * @note Depending on devices and packages, some channels may not be available. 03330 * Refer to device datasheet for channels availability. 03331 * @note On this STM32 serie, to measure internal channels (VrefInt, 03332 * TempSensor, ...), measurement paths to internal channels must be 03333 * enabled separately. 03334 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 03335 * @note On this STM32 serie, setting of this feature is conditioned to 03336 * ADC state: 03337 * ADC must be disabled or enabled without conversion on going 03338 * on group regular. 03339 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n 03340 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n 03341 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n 03342 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n 03343 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n 03344 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n 03345 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n 03346 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n 03347 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n 03348 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n 03349 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n 03350 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n 03351 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n 03352 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n 03353 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n 03354 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks 03355 * @param ADCx ADC instance 03356 * @param Rank This parameter can be one of the following values: 03357 * @arg @ref LL_ADC_REG_RANK_1 03358 * @arg @ref LL_ADC_REG_RANK_2 03359 * @arg @ref LL_ADC_REG_RANK_3 03360 * @arg @ref LL_ADC_REG_RANK_4 03361 * @arg @ref LL_ADC_REG_RANK_5 03362 * @arg @ref LL_ADC_REG_RANK_6 03363 * @arg @ref LL_ADC_REG_RANK_7 03364 * @arg @ref LL_ADC_REG_RANK_8 03365 * @arg @ref LL_ADC_REG_RANK_9 03366 * @arg @ref LL_ADC_REG_RANK_10 03367 * @arg @ref LL_ADC_REG_RANK_11 03368 * @arg @ref LL_ADC_REG_RANK_12 03369 * @arg @ref LL_ADC_REG_RANK_13 03370 * @arg @ref LL_ADC_REG_RANK_14 03371 * @arg @ref LL_ADC_REG_RANK_15 03372 * @arg @ref LL_ADC_REG_RANK_16 03373 * @param Channel This parameter can be one of the following values: 03374 * @arg @ref LL_ADC_CHANNEL_0 03375 * @arg @ref LL_ADC_CHANNEL_1 (7) 03376 * @arg @ref LL_ADC_CHANNEL_2 (7) 03377 * @arg @ref LL_ADC_CHANNEL_3 (7) 03378 * @arg @ref LL_ADC_CHANNEL_4 (7) 03379 * @arg @ref LL_ADC_CHANNEL_5 (7) 03380 * @arg @ref LL_ADC_CHANNEL_6 03381 * @arg @ref LL_ADC_CHANNEL_7 03382 * @arg @ref LL_ADC_CHANNEL_8 03383 * @arg @ref LL_ADC_CHANNEL_9 03384 * @arg @ref LL_ADC_CHANNEL_10 03385 * @arg @ref LL_ADC_CHANNEL_11 03386 * @arg @ref LL_ADC_CHANNEL_12 03387 * @arg @ref LL_ADC_CHANNEL_13 03388 * @arg @ref LL_ADC_CHANNEL_14 03389 * @arg @ref LL_ADC_CHANNEL_15 03390 * @arg @ref LL_ADC_CHANNEL_16 03391 * @arg @ref LL_ADC_CHANNEL_17 03392 * @arg @ref LL_ADC_CHANNEL_18 03393 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03394 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 03395 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 03396 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 03397 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 03398 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 03399 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 03400 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 03401 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 03402 * 03403 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 03404 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 03405 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 03406 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 03407 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 03408 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 03409 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 03410 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 03411 * @retval None 03412 */ 03413 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 03414 { 03415 /* Set bits with content of parameter "Channel" with bits position */ 03416 /* in register and register position depending on parameter "Rank". */ 03417 /* Parameters "Rank" and "Channel" are used with masks because containing */ 03418 /* other bits reserved for other purpose. */ 03419 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 03420 03421 MODIFY_REG(*preg, 03422 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), 03423 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))); 03424 } 03425 03426 /** 03427 * @brief Get ADC group regular sequence: channel on the selected 03428 * scan sequence rank. 03429 * @note On this STM32 serie, ADC group regular sequencer is 03430 * fully configurable: sequencer length and each rank 03431 * affectation to a channel are configurable. 03432 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 03433 * @note Depending on devices and packages, some channels may not be available. 03434 * Refer to device datasheet for channels availability. 03435 * @note Usage of the returned channel number: 03436 * - To reinject this channel into another function LL_ADC_xxx: 03437 * the returned channel number is only partly formatted on definition 03438 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 03439 * with parts of literals LL_ADC_CHANNEL_x or using 03440 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03441 * Then the selected literal LL_ADC_CHANNEL_x can be used 03442 * as parameter for another function. 03443 * - To get the channel number in decimal format: 03444 * process the returned value with the helper macro 03445 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03446 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n 03447 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n 03448 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n 03449 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n 03450 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n 03451 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n 03452 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n 03453 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n 03454 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n 03455 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n 03456 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n 03457 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n 03458 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n 03459 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n 03460 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n 03461 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks 03462 * @param ADCx ADC instance 03463 * @param Rank This parameter can be one of the following values: 03464 * @arg @ref LL_ADC_REG_RANK_1 03465 * @arg @ref LL_ADC_REG_RANK_2 03466 * @arg @ref LL_ADC_REG_RANK_3 03467 * @arg @ref LL_ADC_REG_RANK_4 03468 * @arg @ref LL_ADC_REG_RANK_5 03469 * @arg @ref LL_ADC_REG_RANK_6 03470 * @arg @ref LL_ADC_REG_RANK_7 03471 * @arg @ref LL_ADC_REG_RANK_8 03472 * @arg @ref LL_ADC_REG_RANK_9 03473 * @arg @ref LL_ADC_REG_RANK_10 03474 * @arg @ref LL_ADC_REG_RANK_11 03475 * @arg @ref LL_ADC_REG_RANK_12 03476 * @arg @ref LL_ADC_REG_RANK_13 03477 * @arg @ref LL_ADC_REG_RANK_14 03478 * @arg @ref LL_ADC_REG_RANK_15 03479 * @arg @ref LL_ADC_REG_RANK_16 03480 * @retval Returned value can be one of the following values: 03481 * @arg @ref LL_ADC_CHANNEL_0 03482 * @arg @ref LL_ADC_CHANNEL_1 (7) 03483 * @arg @ref LL_ADC_CHANNEL_2 (7) 03484 * @arg @ref LL_ADC_CHANNEL_3 (7) 03485 * @arg @ref LL_ADC_CHANNEL_4 (7) 03486 * @arg @ref LL_ADC_CHANNEL_5 (7) 03487 * @arg @ref LL_ADC_CHANNEL_6 03488 * @arg @ref LL_ADC_CHANNEL_7 03489 * @arg @ref LL_ADC_CHANNEL_8 03490 * @arg @ref LL_ADC_CHANNEL_9 03491 * @arg @ref LL_ADC_CHANNEL_10 03492 * @arg @ref LL_ADC_CHANNEL_11 03493 * @arg @ref LL_ADC_CHANNEL_12 03494 * @arg @ref LL_ADC_CHANNEL_13 03495 * @arg @ref LL_ADC_CHANNEL_14 03496 * @arg @ref LL_ADC_CHANNEL_15 03497 * @arg @ref LL_ADC_CHANNEL_16 03498 * @arg @ref LL_ADC_CHANNEL_17 03499 * @arg @ref LL_ADC_CHANNEL_18 03500 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03501 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 03502 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 03503 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 03504 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 03505 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 03506 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 03507 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 03508 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 03509 * 03510 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 03511 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 03512 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 03513 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 03514 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 03515 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 03516 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 03517 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 03518 * (1, 2, 3, 4) For ADC channel read back from ADC register, 03519 * comparison with internal channel parameter to be done 03520 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 03521 */ 03522 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 03523 { 03524 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 03525 03526 return (uint32_t) (READ_BIT(*preg, 03527 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) 03528 << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)) 03529 ); 03530 } 03531 03532 /** 03533 * @brief Set ADC continuous conversion mode on ADC group regular. 03534 * @note Description of ADC continuous conversion mode: 03535 * - single mode: one conversion per trigger 03536 * - continuous mode: after the first trigger, following 03537 * conversions launched successively automatically. 03538 * @note It is not possible to enable both ADC group regular 03539 * continuous mode and sequencer discontinuous mode. 03540 * @note On this STM32 serie, setting of this feature is conditioned to 03541 * ADC state: 03542 * ADC must be disabled or enabled without conversion on going 03543 * on group regular. 03544 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode 03545 * @param ADCx ADC instance 03546 * @param Continuous This parameter can be one of the following values: 03547 * @arg @ref LL_ADC_REG_CONV_SINGLE 03548 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 03549 * @retval None 03550 */ 03551 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) 03552 { 03553 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous); 03554 } 03555 03556 /** 03557 * @brief Get ADC continuous conversion mode on ADC group regular. 03558 * @note Description of ADC continuous conversion mode: 03559 * - single mode: one conversion per trigger 03560 * - continuous mode: after the first trigger, following 03561 * conversions launched successively automatically. 03562 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode 03563 * @param ADCx ADC instance 03564 * @retval Returned value can be one of the following values: 03565 * @arg @ref LL_ADC_REG_CONV_SINGLE 03566 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 03567 */ 03568 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) 03569 { 03570 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); 03571 } 03572 03573 /** 03574 * @brief Set ADC group regular conversion data transfer: no transfer or 03575 * transfer by DMA, and DMA requests mode. 03576 * @note If transfer by DMA selected, specifies the DMA requests 03577 * mode: 03578 * - Limited mode (One shot mode): DMA transfer requests are stopped 03579 * when number of DMA data transfers (number of 03580 * ADC conversions) is reached. 03581 * This ADC mode is intended to be used with DMA mode non-circular. 03582 * - Unlimited mode: DMA transfer requests are unlimited, 03583 * whatever number of DMA data transfers (number of 03584 * ADC conversions). 03585 * This ADC mode is intended to be used with DMA mode circular. 03586 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 03587 * mode non-circular: 03588 * when DMA transfers size will be reached, DMA will stop transfers of 03589 * ADC conversions data ADC will raise an overrun error 03590 * (overrun flag and interruption if enabled). 03591 * @note For devices with several ADC instances: ADC multimode DMA 03592 * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). 03593 * @note To configure DMA source address (peripheral address), 03594 * use function @ref LL_ADC_DMA_GetRegAddr(). 03595 * @note On this STM32 serie, setting of this feature is conditioned to 03596 * ADC state: 03597 * ADC must be disabled or enabled without conversion on going 03598 * on either groups regular or injected. 03599 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n 03600 * CFGR DMACFG LL_ADC_REG_SetDMATransfer 03601 * @param ADCx ADC instance 03602 * @param DMATransfer This parameter can be one of the following values: 03603 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 03604 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED 03605 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 03606 * @retval None 03607 */ 03608 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) 03609 { 03610 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer); 03611 } 03612 03613 /** 03614 * @brief Get ADC group regular conversion data transfer: no transfer or 03615 * transfer by DMA, and DMA requests mode. 03616 * @note If transfer by DMA selected, specifies the DMA requests 03617 * mode: 03618 * - Limited mode (One shot mode): DMA transfer requests are stopped 03619 * when number of DMA data transfers (number of 03620 * ADC conversions) is reached. 03621 * This ADC mode is intended to be used with DMA mode non-circular. 03622 * - Unlimited mode: DMA transfer requests are unlimited, 03623 * whatever number of DMA data transfers (number of 03624 * ADC conversions). 03625 * This ADC mode is intended to be used with DMA mode circular. 03626 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 03627 * mode non-circular: 03628 * when DMA transfers size will be reached, DMA will stop transfers of 03629 * ADC conversions data ADC will raise an overrun error 03630 * (overrun flag and interruption if enabled). 03631 * @note For devices with several ADC instances: ADC multimode DMA 03632 * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). 03633 * @note To configure DMA source address (peripheral address), 03634 * use function @ref LL_ADC_DMA_GetRegAddr(). 03635 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n 03636 * CFGR DMACFG LL_ADC_REG_GetDMATransfer 03637 * @param ADCx ADC instance 03638 * @retval Returned value can be one of the following values: 03639 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 03640 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED 03641 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 03642 */ 03643 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) 03644 { 03645 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG)); 03646 } 03647 03648 03649 /** 03650 * @brief Set ADC group regular behavior in case of overrun: 03651 * data preserved or overwritten. 03652 * @note Compatibility with devices without feature overrun: 03653 * other devices without this feature have a behavior 03654 * equivalent to data overwritten. 03655 * The default setting of overrun is data preserved. 03656 * Therefore, for compatibility with all devices, parameter 03657 * overrun should be set to data overwritten. 03658 * @note On this STM32 serie, setting of this feature is conditioned to 03659 * ADC state: 03660 * ADC must be disabled or enabled without conversion on going 03661 * on group regular. 03662 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun 03663 * @param ADCx ADC instance 03664 * @param Overrun This parameter can be one of the following values: 03665 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED 03666 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN 03667 * @retval None 03668 */ 03669 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) 03670 { 03671 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun); 03672 } 03673 03674 /** 03675 * @brief Get ADC group regular behavior in case of overrun: 03676 * data preserved or overwritten. 03677 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun 03678 * @param ADCx ADC instance 03679 * @retval Returned value can be one of the following values: 03680 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED 03681 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN 03682 */ 03683 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) 03684 { 03685 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); 03686 } 03687 03688 /** 03689 * @} 03690 */ 03691 03692 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected 03693 * @{ 03694 */ 03695 03696 /** 03697 * @brief Set ADC group injected conversion trigger source: 03698 * internal (SW start) or from external IP (timer event, 03699 * external interrupt line). 03700 * @note On this STM32 serie, setting trigger source to external trigger 03701 * also set trigger polarity to rising edge 03702 * (default setting for compatibility with some ADC on other 03703 * STM32 families having this setting set by HW default value). 03704 * In case of need to modify trigger edge, use 03705 * function @ref LL_ADC_INJ_SetTriggerEdge(). 03706 * @note Availability of parameters of trigger sources from timer 03707 * depends on timers availability on the selected device. 03708 * @note On this STM32 serie, setting of this feature is conditioned to 03709 * ADC state: 03710 * ADC must not be disabled. Can be enabled with or without conversion 03711 * on going on either groups regular or injected. 03712 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n 03713 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource 03714 * @param ADCx ADC instance 03715 * @param TriggerSource This parameter can be one of the following values: 03716 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 03717 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 03718 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 03719 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 03720 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 03721 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 03722 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO 03723 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 03724 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 03725 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 03726 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 03727 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO 03728 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 03729 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO 03730 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 03731 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO 03732 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 03733 * @retval None 03734 */ 03735 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 03736 { 03737 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource); 03738 } 03739 03740 /** 03741 * @brief Get ADC group injected conversion trigger source: 03742 * internal (SW start) or from external IP (timer event, 03743 * external interrupt line). 03744 * @note To determine whether group injected trigger source is 03745 * internal (SW start) or external, without detail 03746 * of which peripheral is selected as external trigger, 03747 * (equivalent to 03748 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") 03749 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. 03750 * @note Availability of parameters of trigger sources from timer 03751 * depends on timers availability on the selected device. 03752 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n 03753 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource 03754 * @param ADCx ADC instance 03755 * @retval Returned value can be one of the following values: 03756 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 03757 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 03758 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 03759 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 03760 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 03761 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 03762 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO 03763 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 03764 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 03765 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 03766 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 03767 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO 03768 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 03769 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO 03770 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 03771 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO 03772 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 03773 */ 03774 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) 03775 { 03776 register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); 03777 03778 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ 03779 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ 03780 register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); 03781 03782 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ 03783 /* to match with triggers literals definition. */ 03784 return ((TriggerSource 03785 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL) 03786 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN) 03787 ); 03788 } 03789 03790 /** 03791 * @brief Get ADC group injected conversion trigger source internal (SW start) 03792 or external 03793 * @note In case of group injected trigger source set to external trigger, 03794 * to determine which peripheral is selected as external trigger, 03795 * use function @ref LL_ADC_INJ_GetTriggerSource. 03796 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart 03797 * @param ADCx ADC instance 03798 * @retval Value "0" if trigger source external trigger 03799 * Value "1" if trigger source SW start. 03800 */ 03801 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 03802 { 03803 return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)); 03804 } 03805 03806 /** 03807 * @brief Set ADC group injected conversion trigger polarity. 03808 * Applicable only for trigger source set to external trigger. 03809 * @note On this STM32 serie, setting of this feature is conditioned to 03810 * ADC state: 03811 * ADC must not be disabled. Can be enabled with or without conversion 03812 * on going on either groups regular or injected. 03813 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge 03814 * @param ADCx ADC instance 03815 * @param ExternalTriggerEdge This parameter can be one of the following values: 03816 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 03817 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 03818 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 03819 * @retval None 03820 */ 03821 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 03822 { 03823 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge); 03824 } 03825 03826 /** 03827 * @brief Get ADC group injected conversion trigger polarity. 03828 * Applicable only for trigger source set to external trigger. 03829 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge 03830 * @param ADCx ADC instance 03831 * @retval Returned value can be one of the following values: 03832 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 03833 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 03834 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 03835 */ 03836 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) 03837 { 03838 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); 03839 } 03840 03841 /** 03842 * @brief Set ADC group injected sequencer length and scan direction. 03843 * @note This function performs configuration of: 03844 * - Sequence length: Number of ranks in the scan sequence. 03845 * - Sequence direction: Unless specified in parameters, sequencer 03846 * scan direction is forward (from rank 1 to rank n). 03847 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 03848 * ADC conversion on only 1 channel. 03849 * @note On this STM32 serie, setting of this feature is conditioned to 03850 * ADC state: 03851 * ADC must not be disabled. Can be enabled with or without conversion 03852 * on going on either groups regular or injected. 03853 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength 03854 * @param ADCx ADC instance 03855 * @param SequencerNbRanks This parameter can be one of the following values: 03856 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 03857 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 03858 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 03859 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 03860 * @retval None 03861 */ 03862 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 03863 { 03864 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); 03865 } 03866 03867 /** 03868 * @brief Get ADC group injected sequencer length and scan direction. 03869 * @note This function retrieves: 03870 * - Sequence length: Number of ranks in the scan sequence. 03871 * - Sequence direction: Unless specified in parameters, sequencer 03872 * scan direction is forward (from rank 1 to rank n). 03873 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 03874 * ADC conversion on only 1 channel. 03875 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength 03876 * @param ADCx ADC instance 03877 * @retval Returned value can be one of the following values: 03878 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 03879 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 03880 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 03881 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 03882 */ 03883 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) 03884 { 03885 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); 03886 } 03887 03888 /** 03889 * @brief Set ADC group injected sequencer discontinuous mode: 03890 * sequence subdivided and scan conversions interrupted every selected 03891 * number of ranks. 03892 * @note It is not possible to enable both ADC group injected 03893 * auto-injected mode and sequencer discontinuous mode. 03894 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont 03895 * @param ADCx ADC instance 03896 * @param SeqDiscont This parameter can be one of the following values: 03897 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 03898 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 03899 * @retval None 03900 */ 03901 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 03902 { 03903 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont); 03904 } 03905 03906 /** 03907 * @brief Get ADC group injected sequencer discontinuous mode: 03908 * sequence subdivided and scan conversions interrupted every selected 03909 * number of ranks. 03910 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont 03911 * @param ADCx ADC instance 03912 * @retval Returned value can be one of the following values: 03913 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 03914 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 03915 */ 03916 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) 03917 { 03918 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); 03919 } 03920 03921 /** 03922 * @brief Set ADC group injected sequence: channel on the selected 03923 * sequence rank. 03924 * @note Depending on devices and packages, some channels may not be available. 03925 * Refer to device datasheet for channels availability. 03926 * @note On this STM32 serie, to measure internal channels (VrefInt, 03927 * TempSensor, ...), measurement paths to internal channels must be 03928 * enabled separately. 03929 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 03930 * @note On this STM32 serie, some fast channels are available: fast analog inputs 03931 * coming from GPIO pads (ADC_IN1..5). 03932 * @note On this STM32 serie, setting of this feature is conditioned to 03933 * ADC state: 03934 * ADC must not be disabled. Can be enabled with or without conversion 03935 * on going on either groups regular or injected. 03936 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 03937 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 03938 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 03939 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 03940 * @param ADCx ADC instance 03941 * @param Rank This parameter can be one of the following values: 03942 * @arg @ref LL_ADC_INJ_RANK_1 03943 * @arg @ref LL_ADC_INJ_RANK_2 03944 * @arg @ref LL_ADC_INJ_RANK_3 03945 * @arg @ref LL_ADC_INJ_RANK_4 03946 * @param Channel This parameter can be one of the following values: 03947 * @arg @ref LL_ADC_CHANNEL_0 03948 * @arg @ref LL_ADC_CHANNEL_1 (7) 03949 * @arg @ref LL_ADC_CHANNEL_2 (7) 03950 * @arg @ref LL_ADC_CHANNEL_3 (7) 03951 * @arg @ref LL_ADC_CHANNEL_4 (7) 03952 * @arg @ref LL_ADC_CHANNEL_5 (7) 03953 * @arg @ref LL_ADC_CHANNEL_6 03954 * @arg @ref LL_ADC_CHANNEL_7 03955 * @arg @ref LL_ADC_CHANNEL_8 03956 * @arg @ref LL_ADC_CHANNEL_9 03957 * @arg @ref LL_ADC_CHANNEL_10 03958 * @arg @ref LL_ADC_CHANNEL_11 03959 * @arg @ref LL_ADC_CHANNEL_12 03960 * @arg @ref LL_ADC_CHANNEL_13 03961 * @arg @ref LL_ADC_CHANNEL_14 03962 * @arg @ref LL_ADC_CHANNEL_15 03963 * @arg @ref LL_ADC_CHANNEL_16 03964 * @arg @ref LL_ADC_CHANNEL_17 03965 * @arg @ref LL_ADC_CHANNEL_18 03966 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03967 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 03968 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 03969 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 03970 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 03971 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 03972 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 03973 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 03974 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 03975 * 03976 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 03977 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 03978 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 03979 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 03980 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 03981 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 03982 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 03983 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 03984 * @retval None 03985 */ 03986 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 03987 { 03988 /* Set bits with content of parameter "Channel" with bits position */ 03989 /* in register depending on parameter "Rank". */ 03990 /* Parameters "Rank" and "Channel" are used with masks because containing */ 03991 /* other bits reserved for other purpose. */ 03992 MODIFY_REG(ADCx->JSQR, 03993 ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)), 03994 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))); 03995 } 03996 03997 /** 03998 * @brief Get ADC group injected sequence: channel on the selected 03999 * sequence rank. 04000 * @note Depending on devices and packages, some channels may not be available. 04001 * Refer to device datasheet for channels availability. 04002 * @note Usage of the returned channel number: 04003 * - To reinject this channel into another function LL_ADC_xxx: 04004 * the returned channel number is only partly formatted on definition 04005 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 04006 * with parts of literals LL_ADC_CHANNEL_x or using 04007 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 04008 * Then the selected literal LL_ADC_CHANNEL_x can be used 04009 * as parameter for another function. 04010 * - To get the channel number in decimal format: 04011 * process the returned value with the helper macro 04012 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 04013 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n 04014 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n 04015 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n 04016 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks 04017 * @param ADCx ADC instance 04018 * @param Rank This parameter can be one of the following values: 04019 * @arg @ref LL_ADC_INJ_RANK_1 04020 * @arg @ref LL_ADC_INJ_RANK_2 04021 * @arg @ref LL_ADC_INJ_RANK_3 04022 * @arg @ref LL_ADC_INJ_RANK_4 04023 * @retval Returned value can be one of the following values: 04024 * @arg @ref LL_ADC_CHANNEL_0 04025 * @arg @ref LL_ADC_CHANNEL_1 (7) 04026 * @arg @ref LL_ADC_CHANNEL_2 (7) 04027 * @arg @ref LL_ADC_CHANNEL_3 (7) 04028 * @arg @ref LL_ADC_CHANNEL_4 (7) 04029 * @arg @ref LL_ADC_CHANNEL_5 (7) 04030 * @arg @ref LL_ADC_CHANNEL_6 04031 * @arg @ref LL_ADC_CHANNEL_7 04032 * @arg @ref LL_ADC_CHANNEL_8 04033 * @arg @ref LL_ADC_CHANNEL_9 04034 * @arg @ref LL_ADC_CHANNEL_10 04035 * @arg @ref LL_ADC_CHANNEL_11 04036 * @arg @ref LL_ADC_CHANNEL_12 04037 * @arg @ref LL_ADC_CHANNEL_13 04038 * @arg @ref LL_ADC_CHANNEL_14 04039 * @arg @ref LL_ADC_CHANNEL_15 04040 * @arg @ref LL_ADC_CHANNEL_16 04041 * @arg @ref LL_ADC_CHANNEL_17 04042 * @arg @ref LL_ADC_CHANNEL_18 04043 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04044 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04045 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04046 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04047 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04048 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04049 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04050 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04051 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04052 * 04053 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04054 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04055 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04056 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04057 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04058 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04059 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04060 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 04061 * (1, 2, 3, 4) For ADC channel read back from ADC register, 04062 * comparison with internal channel parameter to be done 04063 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 04064 */ 04065 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 04066 { 04067 return (uint32_t)(READ_BIT(ADCx->JSQR, 04068 ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))) 04069 << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) 04070 ); 04071 } 04072 04073 /** 04074 * @brief Set ADC group injected conversion trigger: 04075 * independent or from ADC group regular. 04076 * @note This mode can be used to extend number of data registers 04077 * updated after one ADC conversion trigger and with data 04078 * permanently kept (not erased by successive conversions of scan of 04079 * ADC sequencer ranks), up to 5 data registers: 04080 * 1 data register on ADC group regular, 4 data registers 04081 * on ADC group injected. 04082 * @note If ADC group injected injected trigger source is set to an 04083 * external trigger, this feature must be must be set to 04084 * independent trigger. 04085 * ADC group injected automatic trigger is compliant only with 04086 * group injected trigger source set to SW start, without any 04087 * further action on ADC group injected conversion start or stop: 04088 * in this case, ADC group injected is controlled only 04089 * from ADC group regular. 04090 * @note It is not possible to enable both ADC group injected 04091 * auto-injected mode and sequencer discontinuous mode. 04092 * @note On this STM32 serie, setting of this feature is conditioned to 04093 * ADC state: 04094 * ADC must be disabled or enabled without conversion on going 04095 * on either groups regular or injected. 04096 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto 04097 * @param ADCx ADC instance 04098 * @param TrigAuto This parameter can be one of the following values: 04099 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 04100 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 04101 * @retval None 04102 */ 04103 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) 04104 { 04105 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto); 04106 } 04107 04108 /** 04109 * @brief Get ADC group injected conversion trigger: 04110 * independent or from ADC group regular. 04111 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto 04112 * @param ADCx ADC instance 04113 * @retval Returned value can be one of the following values: 04114 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 04115 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 04116 */ 04117 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) 04118 { 04119 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); 04120 } 04121 04122 /** 04123 * @brief Set ADC group injected contexts queue mode. 04124 * @note A context is a setting of group injected sequencer: 04125 * - group injected trigger 04126 * - sequencer length 04127 * - sequencer ranks 04128 * If contexts queue is disabled: 04129 * - only 1 sequence can be configured 04130 * and is active perpetually. 04131 * If contexts queue is enabled: 04132 * - up to 2 contexts can be queued 04133 * and are checked in and out as a FIFO stack (first-in, first-out). 04134 * - If a new context is set when queues is full, error is triggered 04135 * by interruption "Injected Queue Overflow". 04136 * - Two behaviors are possible when all contexts have been processed: 04137 * the contexts queue can maintain the last context active perpetually 04138 * or can be empty and injected group triggers are disabled. 04139 * - Triggers can be only external (not internal SW start) 04140 * - Caution: The sequence must be fully configured in one time 04141 * (one write of register JSQR makes a check-in of a new context 04142 * into the queue). 04143 * Therefore functions to set separately injected trigger and 04144 * sequencer channels cannot be used, register JSQR must be set 04145 * using function @ref LL_ADC_INJ_ConfigQueueContext(). 04146 * @note This parameter can be modified only when no conversion is on going 04147 * on either groups regular or injected. 04148 * @note A modification of the context mode (bit JQDIS) causes the contexts 04149 * queue to be flushed and the register JSQR is cleared. 04150 * @note On this STM32 serie, setting of this feature is conditioned to 04151 * ADC state: 04152 * ADC must be disabled or enabled without conversion on going 04153 * on either groups regular or injected. 04154 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n 04155 * CFGR JQDIS LL_ADC_INJ_SetQueueMode 04156 * @param ADCx ADC instance 04157 * @param QueueMode This parameter can be one of the following values: 04158 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE 04159 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE 04160 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY 04161 * @retval None 04162 */ 04163 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode) 04164 { 04165 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode); 04166 } 04167 04168 /** 04169 * @brief Get ADC group injected context queue mode. 04170 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n 04171 * CFGR JQDIS LL_ADC_INJ_GetQueueMode 04172 * @param ADCx ADC instance 04173 * @retval Returned value can be one of the following values: 04174 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE 04175 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE 04176 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY 04177 */ 04178 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) 04179 { 04180 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); 04181 } 04182 04183 /** 04184 * @brief Set one context on ADC group injected that will be checked in 04185 * contexts queue. 04186 * @note A context is a setting of group injected sequencer: 04187 * - group injected trigger 04188 * - sequencer length 04189 * - sequencer ranks 04190 * This function is intended to be used when contexts queue is enabled, 04191 * because the sequence must be fully configured in one time 04192 * (functions to set separately injected trigger and sequencer channels 04193 * cannot be used): 04194 * Refer to function @ref LL_ADC_INJ_SetQueueMode(). 04195 * @note In the contexts queue, only the active context can be read. 04196 * The parameters of this function can be read using functions: 04197 * @arg @ref LL_ADC_INJ_GetTriggerSource() 04198 * @arg @ref LL_ADC_INJ_GetTriggerEdge() 04199 * @arg @ref LL_ADC_INJ_GetSequencerRanks() 04200 * @note On this STM32 serie, to measure internal channels (VrefInt, 04201 * TempSensor, ...), measurement paths to internal channels must be 04202 * enabled separately. 04203 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 04204 * @note On this STM32 serie, some fast channels are available: fast analog inputs 04205 * coming from GPIO pads (ADC_IN1..5). 04206 * @note On this STM32 serie, setting of this feature is conditioned to 04207 * ADC state: 04208 * ADC must not be disabled. Can be enabled with or without conversion 04209 * on going on either groups regular or injected. 04210 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n 04211 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n 04212 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n 04213 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n 04214 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n 04215 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n 04216 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext 04217 * @param ADCx ADC instance 04218 * @param TriggerSource This parameter can be one of the following values: 04219 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 04220 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 04221 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 04222 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 04223 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 04224 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 04225 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO 04226 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 04227 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 04228 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 04229 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 04230 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO 04231 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 04232 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO 04233 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 04234 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO 04235 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 04236 * @param ExternalTriggerEdge This parameter can be one of the following values: 04237 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 04238 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 04239 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 04240 * 04241 * Note: This parameter is discarded in case of SW start: 04242 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE". 04243 * @param SequencerNbRanks This parameter can be one of the following values: 04244 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 04245 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 04246 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 04247 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 04248 * @param Rank1_Channel This parameter can be one of the following values: 04249 * @arg @ref LL_ADC_CHANNEL_0 04250 * @arg @ref LL_ADC_CHANNEL_1 (7) 04251 * @arg @ref LL_ADC_CHANNEL_2 (7) 04252 * @arg @ref LL_ADC_CHANNEL_3 (7) 04253 * @arg @ref LL_ADC_CHANNEL_4 (7) 04254 * @arg @ref LL_ADC_CHANNEL_5 (7) 04255 * @arg @ref LL_ADC_CHANNEL_6 04256 * @arg @ref LL_ADC_CHANNEL_7 04257 * @arg @ref LL_ADC_CHANNEL_8 04258 * @arg @ref LL_ADC_CHANNEL_9 04259 * @arg @ref LL_ADC_CHANNEL_10 04260 * @arg @ref LL_ADC_CHANNEL_11 04261 * @arg @ref LL_ADC_CHANNEL_12 04262 * @arg @ref LL_ADC_CHANNEL_13 04263 * @arg @ref LL_ADC_CHANNEL_14 04264 * @arg @ref LL_ADC_CHANNEL_15 04265 * @arg @ref LL_ADC_CHANNEL_16 04266 * @arg @ref LL_ADC_CHANNEL_17 04267 * @arg @ref LL_ADC_CHANNEL_18 04268 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04269 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04270 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04271 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04272 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04273 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04274 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04275 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04276 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04277 * 04278 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04279 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04280 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04281 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04282 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04283 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04284 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04285 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04286 * @param Rank2_Channel This parameter can be one of the following values: 04287 * @arg @ref LL_ADC_CHANNEL_0 04288 * @arg @ref LL_ADC_CHANNEL_1 (7) 04289 * @arg @ref LL_ADC_CHANNEL_2 (7) 04290 * @arg @ref LL_ADC_CHANNEL_3 (7) 04291 * @arg @ref LL_ADC_CHANNEL_4 (7) 04292 * @arg @ref LL_ADC_CHANNEL_5 (7) 04293 * @arg @ref LL_ADC_CHANNEL_6 04294 * @arg @ref LL_ADC_CHANNEL_7 04295 * @arg @ref LL_ADC_CHANNEL_8 04296 * @arg @ref LL_ADC_CHANNEL_9 04297 * @arg @ref LL_ADC_CHANNEL_10 04298 * @arg @ref LL_ADC_CHANNEL_11 04299 * @arg @ref LL_ADC_CHANNEL_12 04300 * @arg @ref LL_ADC_CHANNEL_13 04301 * @arg @ref LL_ADC_CHANNEL_14 04302 * @arg @ref LL_ADC_CHANNEL_15 04303 * @arg @ref LL_ADC_CHANNEL_16 04304 * @arg @ref LL_ADC_CHANNEL_17 04305 * @arg @ref LL_ADC_CHANNEL_18 04306 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04307 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04308 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04309 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04310 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04311 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04312 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04313 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04314 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04315 * 04316 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04317 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04318 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04319 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04320 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04321 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04322 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04323 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04324 * @param Rank3_Channel This parameter can be one of the following values: 04325 * @arg @ref LL_ADC_CHANNEL_0 04326 * @arg @ref LL_ADC_CHANNEL_1 (7) 04327 * @arg @ref LL_ADC_CHANNEL_2 (7) 04328 * @arg @ref LL_ADC_CHANNEL_3 (7) 04329 * @arg @ref LL_ADC_CHANNEL_4 (7) 04330 * @arg @ref LL_ADC_CHANNEL_5 (7) 04331 * @arg @ref LL_ADC_CHANNEL_6 04332 * @arg @ref LL_ADC_CHANNEL_7 04333 * @arg @ref LL_ADC_CHANNEL_8 04334 * @arg @ref LL_ADC_CHANNEL_9 04335 * @arg @ref LL_ADC_CHANNEL_10 04336 * @arg @ref LL_ADC_CHANNEL_11 04337 * @arg @ref LL_ADC_CHANNEL_12 04338 * @arg @ref LL_ADC_CHANNEL_13 04339 * @arg @ref LL_ADC_CHANNEL_14 04340 * @arg @ref LL_ADC_CHANNEL_15 04341 * @arg @ref LL_ADC_CHANNEL_16 04342 * @arg @ref LL_ADC_CHANNEL_17 04343 * @arg @ref LL_ADC_CHANNEL_18 04344 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04345 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04346 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04347 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04348 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04349 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04350 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04351 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04352 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04353 * 04354 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04355 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04356 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04357 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04358 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04359 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04360 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04361 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04362 * @param Rank4_Channel This parameter can be one of the following values: 04363 * @arg @ref LL_ADC_CHANNEL_0 04364 * @arg @ref LL_ADC_CHANNEL_1 (7) 04365 * @arg @ref LL_ADC_CHANNEL_2 (7) 04366 * @arg @ref LL_ADC_CHANNEL_3 (7) 04367 * @arg @ref LL_ADC_CHANNEL_4 (7) 04368 * @arg @ref LL_ADC_CHANNEL_5 (7) 04369 * @arg @ref LL_ADC_CHANNEL_6 04370 * @arg @ref LL_ADC_CHANNEL_7 04371 * @arg @ref LL_ADC_CHANNEL_8 04372 * @arg @ref LL_ADC_CHANNEL_9 04373 * @arg @ref LL_ADC_CHANNEL_10 04374 * @arg @ref LL_ADC_CHANNEL_11 04375 * @arg @ref LL_ADC_CHANNEL_12 04376 * @arg @ref LL_ADC_CHANNEL_13 04377 * @arg @ref LL_ADC_CHANNEL_14 04378 * @arg @ref LL_ADC_CHANNEL_15 04379 * @arg @ref LL_ADC_CHANNEL_16 04380 * @arg @ref LL_ADC_CHANNEL_17 04381 * @arg @ref LL_ADC_CHANNEL_18 04382 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04383 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04384 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04385 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04386 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04387 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04388 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04389 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04390 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04391 * 04392 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04393 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04394 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04395 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04396 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04397 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04398 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04399 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04400 * @retval None 04401 */ 04402 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, 04403 uint32_t TriggerSource, 04404 uint32_t ExternalTriggerEdge, 04405 uint32_t SequencerNbRanks, 04406 uint32_t Rank1_Channel, 04407 uint32_t Rank2_Channel, 04408 uint32_t Rank3_Channel, 04409 uint32_t Rank4_Channel) 04410 { 04411 /* Set bits with content of parameter "Rankx_Channel" with bits position */ 04412 /* in register depending on literal "LL_ADC_INJ_RANK_x". */ 04413 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ 04414 /* because containing other bits reserved for other purpose. */ 04415 /* If parameter "TriggerSource" is set to SW start, then parameter */ 04416 /* "ExternalTriggerEdge" is discarded. */ 04417 MODIFY_REG(ADCx->JSQR , 04418 ADC_JSQR_JEXTSEL | 04419 ADC_JSQR_JEXTEN | 04420 ADC_JSQR_JSQ4 | 04421 ADC_JSQR_JSQ3 | 04422 ADC_JSQR_JSQ2 | 04423 ADC_JSQR_JSQ1 | 04424 ADC_JSQR_JL , 04425 TriggerSource | 04426 (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) | 04427 ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) | 04428 ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) | 04429 ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) | 04430 ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) | 04431 SequencerNbRanks 04432 ); 04433 } 04434 04435 /** 04436 * @} 04437 */ 04438 04439 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels 04440 * @{ 04441 */ 04442 04443 /** 04444 * @brief Set sampling time of the selected ADC channel 04445 * Unit: ADC clock cycles. 04446 * @note On this device, sampling time is on channel scope: independently 04447 * of channel mapped on ADC group regular or injected. 04448 * @note In case of internal channel (VrefInt, TempSensor, ...) to be 04449 * converted: 04450 * sampling time constraints must be respected (sampling time can be 04451 * adjusted in function of ADC clock frequency and sampling time 04452 * setting). 04453 * Refer to device datasheet for timings values (parameters TS_vrefint, 04454 * TS_temp, ...). 04455 * @note Conversion time is the addition of sampling time and processing time. 04456 * On this STM32 serie, ADC processing time is: 04457 * - 12.5 ADC clock cycles at ADC resolution 12 bits 04458 * - 10.5 ADC clock cycles at ADC resolution 10 bits 04459 * - 8.5 ADC clock cycles at ADC resolution 8 bits 04460 * - 6.5 ADC clock cycles at ADC resolution 6 bits 04461 * @note In case of ADC conversion of internal channel (VrefInt, 04462 * temperature sensor, ...), a sampling time minimum value 04463 * is required. 04464 * Refer to device datasheet. 04465 * @note On this STM32 serie, setting of this feature is conditioned to 04466 * ADC state: 04467 * ADC must be disabled or enabled without conversion on going 04468 * on either groups regular or injected. 04469 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n 04470 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n 04471 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n 04472 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n 04473 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n 04474 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n 04475 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n 04476 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n 04477 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n 04478 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n 04479 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n 04480 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n 04481 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n 04482 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n 04483 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n 04484 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n 04485 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n 04486 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n 04487 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime 04488 * @param ADCx ADC instance 04489 * @param Channel This parameter can be one of the following values: 04490 * @arg @ref LL_ADC_CHANNEL_0 04491 * @arg @ref LL_ADC_CHANNEL_1 (7) 04492 * @arg @ref LL_ADC_CHANNEL_2 (7) 04493 * @arg @ref LL_ADC_CHANNEL_3 (7) 04494 * @arg @ref LL_ADC_CHANNEL_4 (7) 04495 * @arg @ref LL_ADC_CHANNEL_5 (7) 04496 * @arg @ref LL_ADC_CHANNEL_6 04497 * @arg @ref LL_ADC_CHANNEL_7 04498 * @arg @ref LL_ADC_CHANNEL_8 04499 * @arg @ref LL_ADC_CHANNEL_9 04500 * @arg @ref LL_ADC_CHANNEL_10 04501 * @arg @ref LL_ADC_CHANNEL_11 04502 * @arg @ref LL_ADC_CHANNEL_12 04503 * @arg @ref LL_ADC_CHANNEL_13 04504 * @arg @ref LL_ADC_CHANNEL_14 04505 * @arg @ref LL_ADC_CHANNEL_15 04506 * @arg @ref LL_ADC_CHANNEL_16 04507 * @arg @ref LL_ADC_CHANNEL_17 04508 * @arg @ref LL_ADC_CHANNEL_18 04509 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04510 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04511 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04512 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04513 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04514 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04515 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04516 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04517 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04518 * 04519 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04520 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04521 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04522 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04523 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04524 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04525 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04526 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04527 * @param SamplingTime This parameter can be one of the following values: 04528 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 04529 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 04530 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 04531 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 04532 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 04533 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 04534 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 04535 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 04536 * @retval None 04537 */ 04538 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) 04539 { 04540 /* Set bits with content of parameter "SamplingTime" with bits position */ 04541 /* in register and register position depending on parameter "Channel". */ 04542 /* Parameter "Channel" is used with masks because containing */ 04543 /* other bits reserved for other purpose. */ 04544 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 04545 04546 MODIFY_REG(*preg, 04547 ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), 04548 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); 04549 } 04550 04551 /** 04552 * @brief Get sampling time of the selected ADC channel 04553 * Unit: ADC clock cycles. 04554 * @note On this device, sampling time is on channel scope: independently 04555 * of channel mapped on ADC group regular or injected. 04556 * @note Conversion time is the addition of sampling time and processing time. 04557 * On this STM32 serie, ADC processing time is: 04558 * - 12.5 ADC clock cycles at ADC resolution 12 bits 04559 * - 10.5 ADC clock cycles at ADC resolution 10 bits 04560 * - 8.5 ADC clock cycles at ADC resolution 8 bits 04561 * - 6.5 ADC clock cycles at ADC resolution 6 bits 04562 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n 04563 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n 04564 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n 04565 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n 04566 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n 04567 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n 04568 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n 04569 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n 04570 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n 04571 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n 04572 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n 04573 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n 04574 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n 04575 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n 04576 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n 04577 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n 04578 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n 04579 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n 04580 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime 04581 * @param ADCx ADC instance 04582 * @param Channel This parameter can be one of the following values: 04583 * @arg @ref LL_ADC_CHANNEL_0 04584 * @arg @ref LL_ADC_CHANNEL_1 (7) 04585 * @arg @ref LL_ADC_CHANNEL_2 (7) 04586 * @arg @ref LL_ADC_CHANNEL_3 (7) 04587 * @arg @ref LL_ADC_CHANNEL_4 (7) 04588 * @arg @ref LL_ADC_CHANNEL_5 (7) 04589 * @arg @ref LL_ADC_CHANNEL_6 04590 * @arg @ref LL_ADC_CHANNEL_7 04591 * @arg @ref LL_ADC_CHANNEL_8 04592 * @arg @ref LL_ADC_CHANNEL_9 04593 * @arg @ref LL_ADC_CHANNEL_10 04594 * @arg @ref LL_ADC_CHANNEL_11 04595 * @arg @ref LL_ADC_CHANNEL_12 04596 * @arg @ref LL_ADC_CHANNEL_13 04597 * @arg @ref LL_ADC_CHANNEL_14 04598 * @arg @ref LL_ADC_CHANNEL_15 04599 * @arg @ref LL_ADC_CHANNEL_16 04600 * @arg @ref LL_ADC_CHANNEL_17 04601 * @arg @ref LL_ADC_CHANNEL_18 04602 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04603 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04604 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04605 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04606 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04607 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04608 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04609 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04610 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04611 * 04612 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04613 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04614 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04615 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04616 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04617 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04618 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04619 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04620 * @retval Returned value can be one of the following values: 04621 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 04622 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 04623 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 04624 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 04625 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 04626 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 04627 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 04628 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 04629 */ 04630 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) 04631 { 04632 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 04633 04634 return (uint32_t)(READ_BIT(*preg, 04635 ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) 04636 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) 04637 ); 04638 } 04639 04640 /** 04641 * @brief Set mode single-ended or differential input of the selected 04642 * ADC channel. 04643 * @note Channel ending is on channel scope: independently of channel mapped 04644 * on ADC group regular or injected. 04645 * In differential mode: Differential measurement is carried out 04646 * between the selected channel 'i' (positive input) and 04647 * channel 'i+1' (negative input). Only channel 'i' has to be 04648 * configured, channel 'i+1' is configured automatically. 04649 * @note Refer to Reference Manual to ensure the selected channel is 04650 * available in differential mode. 04651 * For example, internal channels (VrefInt, TempSensor, ...) are 04652 * not available in differential mode. 04653 * @note When configuring a channel 'i' in differential mode, 04654 * the channel 'i+1' is not usable separately. 04655 * @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) 04656 * are internally fixed to single-ended inputs configuration. 04657 * @note For ADC channels configured in differential mode, both inputs 04658 * should be biased at (Vref+)/2 +/-200mV. 04659 * (Vref+ is the analog voltage reference) 04660 * @note On this STM32 serie, setting of this feature is conditioned to 04661 * ADC state: 04662 * ADC must be ADC disabled. 04663 * @note One or several values can be selected. 04664 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) 04665 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime 04666 * @param ADCx ADC instance 04667 * @param Channel This parameter can be one of the following values: 04668 * @arg @ref LL_ADC_CHANNEL_1 04669 * @arg @ref LL_ADC_CHANNEL_2 04670 * @arg @ref LL_ADC_CHANNEL_3 04671 * @arg @ref LL_ADC_CHANNEL_4 04672 * @arg @ref LL_ADC_CHANNEL_5 04673 * @arg @ref LL_ADC_CHANNEL_6 04674 * @arg @ref LL_ADC_CHANNEL_7 04675 * @arg @ref LL_ADC_CHANNEL_8 04676 * @arg @ref LL_ADC_CHANNEL_9 04677 * @arg @ref LL_ADC_CHANNEL_10 04678 * @arg @ref LL_ADC_CHANNEL_11 04679 * @arg @ref LL_ADC_CHANNEL_12 04680 * @arg @ref LL_ADC_CHANNEL_13 04681 * @arg @ref LL_ADC_CHANNEL_14 04682 * @param SingleDiff This parameter can be a combination of the following values: 04683 * @arg @ref LL_ADC_SINGLE_ENDED 04684 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED 04685 * @retval None 04686 */ 04687 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) 04688 { 04689 /* Bits of channels in single or differential mode are set only for */ 04690 /* differential mode (for single mode, mask of bits allowed to be set is */ 04691 /* shifted out of range of bits of channels in single or differential mode. */ 04692 MODIFY_REG(ADCx->DIFSEL, 04693 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, 04694 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); 04695 } 04696 04697 /** 04698 * @brief Get mode single-ended or differential input of the selected 04699 * ADC channel. 04700 * @note When configuring a channel 'i' in differential mode, 04701 * the channel 'i+1' is not usable separately. 04702 * Therefore, to ensure a channel is configured in single-ended mode, 04703 * the configuration of channel itself and the channel 'i-1' must be 04704 * read back (to ensure that the selected channel channel has not been 04705 * configured in differential mode by the previous channel). 04706 * @note Refer to Reference Manual to ensure the selected channel is 04707 * available in differential mode. 04708 * For example, internal channels (VrefInt, TempSensor, ...) are 04709 * not available in differential mode. 04710 * @note When configuring a channel 'i' in differential mode, 04711 * the channel 'i+1' is not usable separately. 04712 * @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) 04713 * are internally fixed to single-ended inputs configuration. 04714 * @note One or several values can be selected. In this case, the value 04715 * returned is null if all channels are in single ended-mode. 04716 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) 04717 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime 04718 * @param ADCx ADC instance 04719 * @param Channel This parameter can be a combination of the following values: 04720 * @arg @ref LL_ADC_CHANNEL_0 04721 * @arg @ref LL_ADC_CHANNEL_1 04722 * @arg @ref LL_ADC_CHANNEL_2 04723 * @arg @ref LL_ADC_CHANNEL_3 04724 * @arg @ref LL_ADC_CHANNEL_4 04725 * @arg @ref LL_ADC_CHANNEL_5 04726 * @arg @ref LL_ADC_CHANNEL_6 04727 * @arg @ref LL_ADC_CHANNEL_7 04728 * @arg @ref LL_ADC_CHANNEL_8 04729 * @arg @ref LL_ADC_CHANNEL_9 04730 * @arg @ref LL_ADC_CHANNEL_10 04731 * @arg @ref LL_ADC_CHANNEL_11 04732 * @arg @ref LL_ADC_CHANNEL_12 04733 * @arg @ref LL_ADC_CHANNEL_13 04734 * @arg @ref LL_ADC_CHANNEL_14 04735 * @retval 0: channel in single-ended mode, else: channel in differential mode 04736 */ 04737 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) 04738 { 04739 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); 04740 } 04741 04742 /** 04743 * @} 04744 */ 04745 04746 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog 04747 * @{ 04748 */ 04749 04750 /** 04751 * @brief Set ADC analog watchdog monitored channels: 04752 * a single channel, multiple channels or all channels, 04753 * on ADC groups regular and-or injected. 04754 * @note Once monitored channels are selected, analog watchdog 04755 * is enabled. 04756 * @note In case of need to define a single channel to monitor 04757 * with analog watchdog from sequencer channel definition, 04758 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). 04759 * @note On this STM32 serie, there are 2 kinds of analog watchdog 04760 * instance: 04761 * - AWD standard (instance AWD1): 04762 * - channels monitored: can monitor 1 channel or all channels. 04763 * - groups monitored: ADC groups regular and-or injected. 04764 * - resolution: resolution is not limited (corresponds to 04765 * ADC resolution configured). 04766 * - AWD flexible (instances AWD2, AWD3): 04767 * - channels monitored: flexible on channels monitored, selection is 04768 * channel wise, from from 1 to all channels. 04769 * Specificity of this analog watchdog: Multiple channels can 04770 * be selected. For example: 04771 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) 04772 * - groups monitored: not selection possible (monitoring on both 04773 * groups regular and injected). 04774 * Channels selected are monitored on groups regular and injected: 04775 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters 04776 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) 04777 * - resolution: resolution is limited to 8 bits: if ADC resolution is 04778 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits 04779 * the 2 LSB are ignored. 04780 * @note On this STM32 serie, setting of this feature is conditioned to 04781 * ADC state: 04782 * ADC must be disabled or enabled without conversion on going 04783 * on either groups regular or injected. 04784 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n 04785 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n 04786 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n 04787 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n 04788 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n 04789 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels 04790 * @param ADCx ADC instance 04791 * @param AWDy This parameter can be one of the following values: 04792 * @arg @ref LL_ADC_AWD1 04793 * @arg @ref LL_ADC_AWD2 04794 * @arg @ref LL_ADC_AWD3 04795 * @param AWDChannelGroup This parameter can be one of the following values: 04796 * @arg @ref LL_ADC_AWD_DISABLE 04797 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) 04798 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) 04799 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 04800 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) 04801 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) 04802 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 04803 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) 04804 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) 04805 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 04806 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) 04807 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) 04808 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 04809 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) 04810 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) 04811 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 04812 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) 04813 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) 04814 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 04815 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) 04816 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) 04817 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 04818 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) 04819 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) 04820 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 04821 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) 04822 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) 04823 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 04824 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) 04825 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) 04826 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 04827 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) 04828 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) 04829 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 04830 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) 04831 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) 04832 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 04833 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) 04834 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) 04835 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 04836 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) 04837 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) 04838 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 04839 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) 04840 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) 04841 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 04842 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) 04843 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) 04844 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 04845 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) 04846 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) 04847 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 04848 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) 04849 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) 04850 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 04851 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) 04852 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) 04853 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 04854 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) 04855 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) 04856 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 04857 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1) 04858 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1) 04859 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 04860 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4) 04861 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4) 04862 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4) 04863 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4) 04864 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4) 04865 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4) 04866 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5) 04867 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5) 04868 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5) 04869 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5) 04870 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5) 04871 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5) 04872 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6) 04873 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6) 04874 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6) 04875 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6) 04876 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6) 04877 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6) 04878 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6) 04879 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6) 04880 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6) 04881 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6) 04882 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6) 04883 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6) 04884 * 04885 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n 04886 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04887 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04888 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04889 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. 04890 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04891 * (6) On STM32L4, parameter available on devices with several ADC instances. 04892 * @retval None 04893 */ 04894 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) 04895 { 04896 /* Set bits with content of parameter "AWDChannelGroup" with bits position */ 04897 /* in register and register position depending on parameter "AWDy". */ 04898 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ 04899 /* containing other bits reserved for other purpose. */ 04900 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) 04901 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); 04902 04903 MODIFY_REG(*preg, 04904 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), 04905 AWDChannelGroup & AWDy); 04906 } 04907 04908 /** 04909 * @brief Get ADC analog watchdog monitored channel. 04910 * @note Usage of the returned channel number: 04911 * - To reinject this channel into another function LL_ADC_xxx: 04912 * the returned channel number is only partly formatted on definition 04913 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 04914 * with parts of literals LL_ADC_CHANNEL_x or using 04915 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 04916 * Then the selected literal LL_ADC_CHANNEL_x can be used 04917 * as parameter for another function. 04918 * - To get the channel number in decimal format: 04919 * process the returned value with the helper macro 04920 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 04921 * Applicable only when the analog watchdog is set to monitor 04922 * one channel. 04923 * @note On this STM32 serie, there are 2 kinds of analog watchdog 04924 * instance: 04925 * - AWD standard (instance AWD1): 04926 * - channels monitored: can monitor 1 channel or all channels. 04927 * - groups monitored: ADC groups regular and-or injected. 04928 * - resolution: resolution is not limited (corresponds to 04929 * ADC resolution configured). 04930 * - AWD flexible (instances AWD2, AWD3): 04931 * - channels monitored: flexible on channels monitored, selection is 04932 * channel wise, from from 1 to all channels. 04933 * Specificity of this analog watchdog: Multiple channels can 04934 * be selected. For example: 04935 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) 04936 * - groups monitored: not selection possible (monitoring on both 04937 * groups regular and injected). 04938 * Channels selected are monitored on groups regular and injected: 04939 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters 04940 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) 04941 * - resolution: resolution is limited to 8 bits: if ADC resolution is 04942 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits 04943 * the 2 LSB are ignored. 04944 * @note On this STM32 serie, setting of this feature is conditioned to 04945 * ADC state: 04946 * ADC must be disabled or enabled without conversion on going 04947 * on either groups regular or injected. 04948 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n 04949 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n 04950 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n 04951 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n 04952 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n 04953 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels 04954 * @param ADCx ADC instance 04955 * @param AWDy This parameter can be one of the following values: 04956 * @arg @ref LL_ADC_AWD1 04957 * @arg @ref LL_ADC_AWD2 (1) 04958 * @arg @ref LL_ADC_AWD3 (1) 04959 * 04960 * (1) On this AWD number, monitored channel can be retrieved 04961 * if only 1 channel is programmed (or none or all channels). 04962 * This function cannot retrieve monitored channel if 04963 * multiple channels are programmed simultaneously 04964 * by bitfield. 04965 * @retval Returned value can be one of the following values: 04966 * @arg @ref LL_ADC_AWD_DISABLE 04967 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) 04968 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) 04969 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 04970 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) 04971 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) 04972 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 04973 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) 04974 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) 04975 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 04976 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) 04977 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) 04978 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 04979 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) 04980 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) 04981 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 04982 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) 04983 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) 04984 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 04985 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) 04986 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) 04987 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 04988 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) 04989 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) 04990 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 04991 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) 04992 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) 04993 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 04994 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) 04995 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) 04996 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 04997 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) 04998 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) 04999 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 05000 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) 05001 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) 05002 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 05003 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) 05004 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) 05005 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 05006 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) 05007 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) 05008 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 05009 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) 05010 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) 05011 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 05012 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) 05013 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) 05014 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 05015 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) 05016 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) 05017 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 05018 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) 05019 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) 05020 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 05021 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) 05022 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) 05023 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 05024 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) 05025 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) 05026 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 05027 * 05028 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1. 05029 */ 05030 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) 05031 { 05032 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) 05033 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); 05034 05035 /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */ 05036 /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK. */ 05037 register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK)); 05038 05039 /* Set variable of AWD1 monitored channel according to AWD1 features */ 05040 /* and ADC channel definition: */ 05041 /* - channel ID with number */ 05042 /* - channel ID with bitfield */ 05043 /* - AWD1 single or all channels */ 05044 /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of */ 05045 /* AWD2 or AWD3 selected). */ 05046 register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS); 05047 05048 register uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup 05049 | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle) 05050 | (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & ((uint32_t)0x00000001U))) 05051 ) 05052 * (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) | ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS)) 05053 ); 05054 05055 /* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3 */ 05056 /* features and ADC channel definition: */ 05057 /* - channel ID with number */ 05058 /* - channel ID with bitfield */ 05059 /* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to */ 05060 /* shift AWD1 equivalent single-all channels out of register) */ 05061 /* - AWD2-3 enable or disable */ 05062 /* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3, */ 05063 /* channel can be read back if only 1 channel monitoring */ 05064 /* is activated, therefore the channel monitoring value channel "3" */ 05065 /* is not not supported by this function, there is no risk of */ 05066 /* conflict. */ 05067 register uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */ 05068 05069 register uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup 05070 | ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) 05071 | ((ADC_CFGR_AWD1SGL) >> ((((uint32_t)0x00000001U) >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U)) 05072 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) 05073 ) >> AWD23Enabled 05074 ) >> (((AWDy & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS) << 5U)); 05075 05076 return (AWD1ChannelGroup | AWD23ChannelGroup); 05077 } 05078 05079 /** 05080 * @brief Set ADC analog watchdog thresholds value of both thresholds 05081 * high and low. 05082 * @note If value of only one threshold high or low must be set, 05083 * use function @ref LL_ADC_SetAnalogWDThresholds(). 05084 * @note In case of ADC resolution different of 12 bits, 05085 * analog watchdog thresholds data require a specific shift. 05086 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). 05087 * @note On this STM32 serie, there are 2 kinds of analog watchdog 05088 * instance: 05089 * - AWD standard (instance AWD1): 05090 * - channels monitored: can monitor 1 channel or all channels. 05091 * - groups monitored: ADC groups regular and-or injected. 05092 * - resolution: resolution is not limited (corresponds to 05093 * ADC resolution configured). 05094 * - AWD flexible (instances AWD2, AWD3): 05095 * - channels monitored: flexible on channels monitored, selection is 05096 * channel wise, from from 1 to all channels. 05097 * Specificity of this analog watchdog: Multiple channels can 05098 * be selected. For example: 05099 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) 05100 * - groups monitored: not selection possible (monitoring on both 05101 * groups regular and injected). 05102 * Channels selected are monitored on groups regular and injected: 05103 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters 05104 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) 05105 * - resolution: resolution is limited to 8 bits: if ADC resolution is 05106 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits 05107 * the 2 LSB are ignored. 05108 * @note On this STM32 serie, setting of this feature is conditioned to 05109 * ADC state: 05110 * ADC must be disabled or enabled without conversion on going 05111 * on either groups regular or injected. 05112 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n 05113 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n 05114 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n 05115 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n 05116 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n 05117 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds 05118 * @param ADCx ADC instance 05119 * @param AWDy This parameter can be one of the following values: 05120 * @arg @ref LL_ADC_AWD1 05121 * @arg @ref LL_ADC_AWD2 05122 * @arg @ref LL_ADC_AWD3 05123 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF 05124 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF 05125 * @retval None 05126 */ 05127 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue) 05128 { 05129 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ 05130 /* position in register and register position depending on parameter */ 05131 /* "AWDy". */ 05132 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ 05133 /* containing other bits reserved for other purpose. */ 05134 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); 05135 05136 MODIFY_REG(*preg, 05137 ADC_TR1_HT1 | ADC_TR1_LT1, 05138 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); 05139 } 05140 05141 /** 05142 * @brief Set ADC analog watchdog threshold value of threshold 05143 * high or low. 05144 * @note If values of both thresholds high or low must be set, 05145 * use function @ref LL_ADC_ConfigAnalogWDThresholds(). 05146 * @note In case of ADC resolution different of 12 bits, 05147 * analog watchdog thresholds data require a specific shift. 05148 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). 05149 * @note On this STM32 serie, there are 2 kinds of analog watchdog 05150 * instance: 05151 * - AWD standard (instance AWD1): 05152 * - channels monitored: can monitor 1 channel or all channels. 05153 * - groups monitored: ADC groups regular and-or injected. 05154 * - resolution: resolution is not limited (corresponds to 05155 * ADC resolution configured). 05156 * - AWD flexible (instances AWD2, AWD3): 05157 * - channels monitored: flexible on channels monitored, selection is 05158 * channel wise, from from 1 to all channels. 05159 * Specificity of this analog watchdog: Multiple channels can 05160 * be selected. For example: 05161 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) 05162 * - groups monitored: not selection possible (monitoring on both 05163 * groups regular and injected). 05164 * Channels selected are monitored on groups regular and injected: 05165 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters 05166 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) 05167 * - resolution: resolution is limited to 8 bits: if ADC resolution is 05168 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits 05169 * the 2 LSB are ignored. 05170 * @note On this STM32 serie, setting of this feature is conditioned to 05171 * ADC state: 05172 * ADC must be disabled or enabled without conversion on going 05173 * on either groups regular or injected. 05174 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n 05175 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n 05176 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n 05177 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n 05178 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n 05179 * TR3 LT3 LL_ADC_SetAnalogWDThresholds 05180 * @param ADCx ADC instance 05181 * @param AWDy This parameter can be one of the following values: 05182 * @arg @ref LL_ADC_AWD1 05183 * @arg @ref LL_ADC_AWD2 05184 * @arg @ref LL_ADC_AWD3 05185 * @param AWDThresholdsHighLow This parameter can be one of the following values: 05186 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 05187 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 05188 * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF 05189 * @retval None 05190 */ 05191 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) 05192 { 05193 /* Set bits with content of parameter "AWDThresholdValue" with bits */ 05194 /* position in register and register position depending on parameters */ 05195 /* "AWDThresholdsHighLow" and "AWDy". */ 05196 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ 05197 /* containing other bits reserved for other purpose. */ 05198 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); 05199 05200 MODIFY_REG(*preg, 05201 AWDThresholdsHighLow, 05202 AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow)); 05203 } 05204 05205 /** 05206 * @brief Get ADC analog watchdog threshold value of threshold high, 05207 * threshold low or raw data with ADC thresholds high and low 05208 * concatenated. 05209 * @note If raw data with ADC thresholds high and low is retrieved, 05210 * the data of each threshold high or low can be isolated 05211 * using helper macro: 05212 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). 05213 * @note In case of ADC resolution different of 12 bits, 05214 * analog watchdog thresholds data require a specific shift. 05215 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). 05216 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n 05217 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n 05218 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n 05219 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n 05220 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n 05221 * TR3 LT3 LL_ADC_GetAnalogWDThresholds 05222 * @param ADCx ADC instance 05223 * @param AWDy This parameter can be one of the following values: 05224 * @arg @ref LL_ADC_AWD1 05225 * @arg @ref LL_ADC_AWD2 05226 * @arg @ref LL_ADC_AWD3 05227 * @param AWDThresholdsHighLow This parameter can be one of the following values: 05228 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 05229 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 05230 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW 05231 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 05232 */ 05233 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) 05234 { 05235 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); 05236 05237 return (uint32_t)(READ_BIT(*preg, 05238 (AWDThresholdsHighLow | ADC_TR1_LT1)) 05239 >> POSITION_VAL(AWDThresholdsHighLow) 05240 ); 05241 } 05242 05243 /** 05244 * @} 05245 */ 05246 05247 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling 05248 * @{ 05249 */ 05250 05251 /** 05252 * @brief Set ADC oversampling scope: ADC groups regular and-or injected 05253 * (availability of ADC group injected depends on STM32 families). 05254 * @note If both groups regular and injected are selected, 05255 * specify behavior of ADC group injected interrupting 05256 * group regular: when ADC group injected is triggered, 05257 * the oversampling on ADC group regular is either 05258 * temporary stopped and continued, or resumed from start 05259 * (oversampler buffer reset). 05260 * @note On this STM32 serie, setting of this feature is conditioned to 05261 * ADC state: 05262 * ADC must be disabled or enabled without conversion on going 05263 * on either groups regular or injected. 05264 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n 05265 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n 05266 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope 05267 * @param ADCx ADC instance 05268 * @param OvsScope This parameter can be one of the following values: 05269 * @arg @ref LL_ADC_OVS_DISABLE 05270 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED 05271 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED 05272 * @arg @ref LL_ADC_OVS_GRP_INJECTED 05273 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED 05274 * @retval None 05275 */ 05276 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) 05277 { 05278 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); 05279 } 05280 05281 /** 05282 * @brief Get ADC oversampling scope: ADC groups regular and-or injected 05283 * (availability of ADC group injected depends on STM32 families). 05284 * @note If both groups regular and injected are selected, 05285 * specify behavior of ADC group injected interrupting 05286 * group regular: when ADC group injected is triggered, 05287 * the oversampling on ADC group regular is either 05288 * temporary stopped and continued, or resumed from start 05289 * (oversampler buffer reset). 05290 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n 05291 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n 05292 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope 05293 * @param ADCx ADC instance 05294 * @retval Returned value can be one of the following values: 05295 * @arg @ref LL_ADC_OVS_DISABLE 05296 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED 05297 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED 05298 * @arg @ref LL_ADC_OVS_GRP_INJECTED 05299 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED 05300 */ 05301 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) 05302 { 05303 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); 05304 } 05305 05306 /** 05307 * @brief Set ADC oversampling discontinuous mode (triggered mode) 05308 * on the selected ADC group. 05309 * @note Number of oversampled conversions are done either in: 05310 * - continuous mode (all conversions of oversampling ratio 05311 * are done from 1 trigger) 05312 * - discontinuous mode (each conversion of oversampling ratio 05313 * needs a trigger) 05314 * @note On this STM32 serie, setting of this feature is conditioned to 05315 * ADC state: 05316 * ADC must be disabled or enabled without conversion on going 05317 * on group regular. 05318 * @note On this STM32 serie, oversampling discontinuous mode 05319 * (triggered mode) can be used only when oversampling is 05320 * set on group regular only and in resumed mode. 05321 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont 05322 * @param ADCx ADC instance 05323 * @param OverSamplingDiscont This parameter can be one of the following values: 05324 * @arg @ref LL_ADC_OVS_REG_CONT 05325 * @arg @ref LL_ADC_OVS_REG_DISCONT 05326 * @retval None 05327 */ 05328 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) 05329 { 05330 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont); 05331 } 05332 05333 /** 05334 * @brief Get ADC oversampling discontinuous mode (triggered mode) 05335 * on the selected ADC group. 05336 * @note Number of oversampled conversions are done either in: 05337 * - continuous mode (all conversions of oversampling ratio 05338 * are done from 1 trigger) 05339 * - discontinuous mode (each conversion of oversampling ratio 05340 * needs a trigger) 05341 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont 05342 * @param ADCx ADC instance 05343 * @retval Returned value can be one of the following values: 05344 * @arg @ref LL_ADC_OVS_REG_CONT 05345 * @arg @ref LL_ADC_OVS_REG_DISCONT 05346 */ 05347 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) 05348 { 05349 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); 05350 } 05351 05352 /** 05353 * @brief Set ADC oversampling 05354 * (impacting both ADC groups regular and injected) 05355 * @note This function set the 2 items of oversampling configuration: 05356 * - ratio 05357 * - shift 05358 * @note On this STM32 serie, setting of this feature is conditioned to 05359 * ADC state: 05360 * ADC must be disabled or enabled without conversion on going 05361 * on either groups regular or injected. 05362 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n 05363 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift 05364 * @param ADCx ADC instance 05365 * @param Ratio This parameter can be one of the following values: 05366 * @arg @ref LL_ADC_OVS_RATIO_2 05367 * @arg @ref LL_ADC_OVS_RATIO_4 05368 * @arg @ref LL_ADC_OVS_RATIO_8 05369 * @arg @ref LL_ADC_OVS_RATIO_16 05370 * @arg @ref LL_ADC_OVS_RATIO_32 05371 * @arg @ref LL_ADC_OVS_RATIO_64 05372 * @arg @ref LL_ADC_OVS_RATIO_128 05373 * @arg @ref LL_ADC_OVS_RATIO_256 05374 * @param Shift This parameter can be one of the following values: 05375 * @arg @ref LL_ADC_OVS_SHIFT_NONE 05376 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 05377 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 05378 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 05379 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 05380 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 05381 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 05382 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 05383 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 05384 * @retval None 05385 */ 05386 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) 05387 { 05388 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); 05389 } 05390 05391 /** 05392 * @brief Get ADC oversampling ratio 05393 * (impacting both ADC groups regular and injected) 05394 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio 05395 * @param ADCx ADC instance 05396 * @retval Ratio This parameter can be one of the following values: 05397 * @arg @ref LL_ADC_OVS_RATIO_2 05398 * @arg @ref LL_ADC_OVS_RATIO_4 05399 * @arg @ref LL_ADC_OVS_RATIO_8 05400 * @arg @ref LL_ADC_OVS_RATIO_16 05401 * @arg @ref LL_ADC_OVS_RATIO_32 05402 * @arg @ref LL_ADC_OVS_RATIO_64 05403 * @arg @ref LL_ADC_OVS_RATIO_128 05404 * @arg @ref LL_ADC_OVS_RATIO_256 05405 */ 05406 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) 05407 { 05408 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); 05409 } 05410 05411 /** 05412 * @brief Get ADC oversampling shift 05413 * (impacting both ADC groups regular and injected) 05414 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift 05415 * @param ADCx ADC instance 05416 * @retval Shift This parameter can be one of the following values: 05417 * @arg @ref LL_ADC_OVS_SHIFT_NONE 05418 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 05419 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 05420 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 05421 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 05422 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 05423 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 05424 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 05425 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 05426 */ 05427 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) 05428 { 05429 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); 05430 } 05431 05432 /** 05433 * @} 05434 */ 05435 05436 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode 05437 * @{ 05438 */ 05439 05440 #if defined(ADC_MULTIMODE_SUPPORT) 05441 /** 05442 * @brief Set ADC multimode configuration to operate in independent mode 05443 * or multimode (for devices with several ADC instances). 05444 * @note If multimode configuration: the selected ADC instance is 05445 * either master or slave depending on hardware. 05446 * Refer to reference manual. 05447 * @note On this STM32 serie, setting of this feature is conditioned to 05448 * ADC state: 05449 * All ADC instances of the ADC common group must be disabled. 05450 * This check can be done with function @ref LL_ADC_IsEnabled() for each 05451 * ADC instance or by using helper macro 05452 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). 05453 * @rmtoll CCR DUAL LL_ADC_SetMultimode 05454 * @param ADCxy_COMMON ADC common instance 05455 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05456 * @param Multimode This parameter can be one of the following values: 05457 * @arg @ref LL_ADC_MULTI_INDEPENDENT 05458 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 05459 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL 05460 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 05461 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 05462 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 05463 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 05464 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM 05465 * @retval None 05466 */ 05467 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) 05468 { 05469 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode); 05470 } 05471 05472 /** 05473 * @brief Get ADC multimode configuration to operate in independent mode 05474 * or multimode (for devices with several ADC instances). 05475 * @note If multimode configuration: the selected ADC instance is 05476 * either master or slave depending on hardware. 05477 * Refer to reference manual. 05478 * @rmtoll CCR DUAL LL_ADC_GetMultimode 05479 * @param ADCxy_COMMON ADC common instance 05480 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05481 * @retval Returned value can be one of the following values: 05482 * @arg @ref LL_ADC_MULTI_INDEPENDENT 05483 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 05484 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL 05485 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 05486 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 05487 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 05488 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 05489 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM 05490 */ 05491 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) 05492 { 05493 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 05494 } 05495 05496 /** 05497 * @brief Set ADC multimode conversion data transfer: no transfer 05498 * or transfer by DMA. 05499 * @note If ADC multimode transfer by DMA is not selected: 05500 * each ADC uses its own DMA channel, with its individual 05501 * DMA transfer settings. 05502 * If ADC multimode transfer by DMA is selected: 05503 * One DMA channel is used for both ADC (DMA of ADC master) 05504 * Specifies the DMA requests mode: 05505 * - Limited mode (One shot mode): DMA transfer requests are stopped 05506 * when number of DMA data transfers (number of 05507 * ADC conversions) is reached. 05508 * This ADC mode is intended to be used with DMA mode non-circular. 05509 * - Unlimited mode: DMA transfer requests are unlimited, 05510 * whatever number of DMA data transfers (number of 05511 * ADC conversions). 05512 * This ADC mode is intended to be used with DMA mode circular. 05513 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 05514 * mode non-circular: 05515 * when DMA transfers size will be reached, DMA will stop transfers of 05516 * ADC conversions data ADC will raise an overrun error 05517 * (overrun flag and interruption if enabled). 05518 * @note How to retrieve multimode conversion data: 05519 * Whatever multimode transfer by DMA setting: using function 05520 * @ref LL_ADC_REG_ReadMultiConversionData32(). 05521 * If ADC multimode transfer by DMA is selected: conversion data 05522 * is a raw data with ADC master and slave concatenated. 05523 * A macro is available to get the conversion data of 05524 * ADC master or ADC slave: see helper macro 05525 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 05526 * @note On this STM32 serie, setting of this feature is conditioned to 05527 * ADC state: 05528 * All ADC instances of the ADC common group must be disabled 05529 * or enabled without conversion on going on group regular. 05530 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n 05531 * CCR DMACFG LL_ADC_SetMultiDMATransfer 05532 * @param ADCxy_COMMON ADC common instance 05533 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05534 * @param MultiDMATransfer This parameter can be one of the following values: 05535 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC 05536 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B 05537 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B 05538 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B 05539 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B 05540 * @retval None 05541 */ 05542 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) 05543 { 05544 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer); 05545 } 05546 05547 /** 05548 * @brief Get ADC multimode conversion data transfer: no transfer 05549 * or transfer by DMA. 05550 * @note If ADC multimode transfer by DMA is not selected: 05551 * each ADC uses its own DMA channel, with its individual 05552 * DMA transfer settings. 05553 * If ADC multimode transfer by DMA is selected: 05554 * One DMA channel is used for both ADC (DMA of ADC master) 05555 * Specifies the DMA requests mode: 05556 * - Limited mode (One shot mode): DMA transfer requests are stopped 05557 * when number of DMA data transfers (number of 05558 * ADC conversions) is reached. 05559 * This ADC mode is intended to be used with DMA mode non-circular. 05560 * - Unlimited mode: DMA transfer requests are unlimited, 05561 * whatever number of DMA data transfers (number of 05562 * ADC conversions). 05563 * This ADC mode is intended to be used with DMA mode circular. 05564 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 05565 * mode non-circular: 05566 * when DMA transfers size will be reached, DMA will stop transfers of 05567 * ADC conversions data ADC will raise an overrun error 05568 * (overrun flag and interruption if enabled). 05569 * @note How to retrieve multimode conversion data: 05570 * Whatever multimode transfer by DMA setting: using function 05571 * @ref LL_ADC_REG_ReadMultiConversionData32(). 05572 * If ADC multimode transfer by DMA is selected: conversion data 05573 * is a raw data with ADC master and slave concatenated. 05574 * A macro is available to get the conversion data of 05575 * ADC master or ADC slave: see helper macro 05576 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 05577 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n 05578 * CCR DMACFG LL_ADC_GetMultiDMATransfer 05579 * @param ADCxy_COMMON ADC common instance 05580 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05581 * @retval Returned value can be one of the following values: 05582 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC 05583 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B 05584 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B 05585 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B 05586 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B 05587 */ 05588 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) 05589 { 05590 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG)); 05591 } 05592 05593 /** 05594 * @brief Set ADC multimode delay between 2 sampling phases. 05595 * @note The sampling delay range depends on ADC resolution: 05596 * - ADC resolution 12 bits can have maximum delay of 12 cycles. 05597 * - ADC resolution 10 bits can have maximum delay of 10 cycles. 05598 * - ADC resolution 8 bits can have maximum delay of 8 cycles. 05599 * - ADC resolution 6 bits can have maximum delay of 6 cycles. 05600 * @note On this STM32 serie, setting of this feature is conditioned to 05601 * ADC state: 05602 * All ADC instances of the ADC common group must be disabled. 05603 * This check can be done with function @ref LL_ADC_IsEnabled() for each 05604 * ADC instance or by using helper macro helper macro 05605 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). 05606 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay 05607 * @param ADCxy_COMMON ADC common instance 05608 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05609 * @param MultiTwoSamplingDelay This parameter can be one of the following values: 05610 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE 05611 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES 05612 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES 05613 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES 05614 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 05615 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) 05616 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) 05617 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) 05618 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) 05619 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) 05620 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) 05621 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) 05622 * 05623 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n 05624 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n 05625 * (3) Parameter available only if ADC resolution is 12 bits. 05626 * @retval None 05627 */ 05628 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) 05629 { 05630 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); 05631 } 05632 05633 /** 05634 * @brief Get ADC multimode delay between 2 sampling phases. 05635 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay 05636 * @param ADCxy_COMMON ADC common instance 05637 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05638 * @retval Returned value can be one of the following values: 05639 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE 05640 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES 05641 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES 05642 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES 05643 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 05644 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) 05645 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) 05646 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) 05647 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) 05648 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) 05649 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) 05650 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) 05651 * 05652 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n 05653 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n 05654 * (3) Parameter available only if ADC resolution is 12 bits. 05655 */ 05656 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) 05657 { 05658 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); 05659 } 05660 #endif /* ADC_MULTIMODE_SUPPORT */ 05661 05662 /** 05663 * @} 05664 */ 05665 /** @defgroup ADC_LL_EF_Configuration_Leg_Functions Configuration of ADC alternate functions name 05666 * @{ 05667 */ 05668 /* Old functions name kept for legacy purpose, to be replaced by the */ 05669 /* current functions name. */ 05670 __STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 05671 { 05672 LL_ADC_REG_SetTrigSource(ADCx, TriggerSource); 05673 } 05674 __STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 05675 { 05676 LL_ADC_INJ_SetTrigSource(ADCx, TriggerSource); 05677 } 05678 05679 /** 05680 * @} 05681 */ 05682 05683 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance 05684 * @{ 05685 */ 05686 05687 /** 05688 * @brief Put ADC instance in deep power down state. 05689 * @note In case of ADC calibration necessary: When ADC is in deep-power-down 05690 * state, the internal analog calibration is lost. After exiting from 05691 * deep power down, calibration must be relaunched or calibration factor 05692 * (preliminarily saved) must be set back into calibration register. 05693 * @note On this STM32 serie, setting of this feature is conditioned to 05694 * ADC state: 05695 * ADC must be ADC disabled. 05696 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown 05697 * @param ADCx ADC instance 05698 * @retval None 05699 */ 05700 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) 05701 { 05702 /* Note: Write register with some additional bits forced to state reset */ 05703 /* instead of modifying only the selected bit for this function, */ 05704 /* to not interfere with bits with HW property "rs". */ 05705 MODIFY_REG(ADCx->CR, 05706 ADC_CR_BITS_PROPERTY_RS, 05707 ADC_CR_DEEPPWD); 05708 } 05709 05710 /** 05711 * @brief Disable ADC deep power down mode. 05712 * @note In case of ADC calibration necessary: When ADC is in deep-power-down 05713 * state, the internal analog calibration is lost. After exiting from 05714 * deep power down, calibration must be relaunched or calibration factor 05715 * (preliminarily saved) must be set back into calibration register. 05716 * @note On this STM32 serie, setting of this feature is conditioned to 05717 * ADC state: 05718 * ADC must be ADC disabled. 05719 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown 05720 * @param ADCx ADC instance 05721 * @retval None 05722 */ 05723 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) 05724 { 05725 /* Note: Write register with some additional bits forced to state reset */ 05726 /* instead of modifying only the selected bit for this function, */ 05727 /* to not interfere with bits with HW property "rs". */ 05728 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 05729 } 05730 05731 /** 05732 * @brief Get the selected ADC instance deep power down state. 05733 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled 05734 * @param ADCx ADC instance 05735 * @retval 0: deep power down is disabled, 1: deep power down is enabled. 05736 */ 05737 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) 05738 { 05739 return (READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)); 05740 } 05741 05742 /** 05743 * @brief Enable ADC instance internal voltage regulator. 05744 * @note On this STM32 serie, after ADC internal voltage regulator enable, 05745 * a delay for ADC internal voltage regulator stabilization 05746 * is required before performing a ADC calibration or ADC enable. 05747 * Refer to device datasheet, parameter tADCVREG_STUP. 05748 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. 05749 * @note On this STM32 serie, setting of this feature is conditioned to 05750 * ADC state: 05751 * ADC must be ADC disabled. 05752 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator 05753 * @param ADCx ADC instance 05754 * @retval None 05755 */ 05756 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) 05757 { 05758 /* Note: Write register with some additional bits forced to state reset */ 05759 /* instead of modifying only the selected bit for this function, */ 05760 /* to not interfere with bits with HW property "rs". */ 05761 MODIFY_REG(ADCx->CR, 05762 ADC_CR_BITS_PROPERTY_RS, 05763 ADC_CR_ADVREGEN); 05764 } 05765 05766 /** 05767 * @brief Disable ADC internal voltage regulator. 05768 * @note On this STM32 serie, setting of this feature is conditioned to 05769 * ADC state: 05770 * ADC must be ADC disabled. 05771 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator 05772 * @param ADCx ADC instance 05773 * @retval None 05774 */ 05775 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) 05776 { 05777 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); 05778 } 05779 05780 /** 05781 * @brief Get the selected ADC instance internal voltage regulator state. 05782 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled 05783 * @param ADCx ADC instance 05784 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. 05785 */ 05786 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) 05787 { 05788 return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)); 05789 } 05790 05791 /** 05792 * @brief Enable the selected ADC instance. 05793 * @note On this STM32 serie, after ADC enable, a delay for 05794 * ADC internal analog stabilization is required before performing a 05795 * ADC conversion start. 05796 * Refer to device datasheet, parameter tSTAB. 05797 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC 05798 * is enabled and when conversion clock is active. 05799 * (not only core clock: this ADC has a dual clock domain) 05800 * @note On this STM32 serie, setting of this feature is conditioned to 05801 * ADC state: 05802 * ADC must be ADC disabled and ADC internal voltage regulator enabled. 05803 * @rmtoll CR ADEN LL_ADC_Enable 05804 * @param ADCx ADC instance 05805 * @retval None 05806 */ 05807 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) 05808 { 05809 /* Note: Write register with some additional bits forced to state reset */ 05810 /* instead of modifying only the selected bit for this function, */ 05811 /* to not interfere with bits with HW property "rs". */ 05812 MODIFY_REG(ADCx->CR, 05813 ADC_CR_BITS_PROPERTY_RS, 05814 ADC_CR_ADEN); 05815 } 05816 05817 /** 05818 * @brief Disable the selected ADC instance. 05819 * @note On this STM32 serie, setting of this feature is conditioned to 05820 * ADC state: 05821 * ADC must be not disabled. Must be enabled without conversion on going 05822 * on either groups regular or injected. 05823 * @rmtoll CR ADDIS LL_ADC_Disable 05824 * @param ADCx ADC instance 05825 * @retval None 05826 */ 05827 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) 05828 { 05829 /* Note: Write register with some additional bits forced to state reset */ 05830 /* instead of modifying only the selected bit for this function, */ 05831 /* to not interfere with bits with HW property "rs". */ 05832 MODIFY_REG(ADCx->CR, 05833 ADC_CR_BITS_PROPERTY_RS, 05834 ADC_CR_ADDIS); 05835 } 05836 05837 /** 05838 * @brief Get the selected ADC instance enable state. 05839 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC 05840 * is enabled and when conversion clock is active. 05841 * (not only core clock: this ADC has a dual clock domain) 05842 * @rmtoll CR ADEN LL_ADC_IsEnabled 05843 * @param ADCx ADC instance 05844 * @retval 0: ADC is disabled, 1: ADC is enabled. 05845 */ 05846 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) 05847 { 05848 return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)); 05849 } 05850 05851 /** 05852 * @brief Get the selected ADC instance disable state. 05853 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing 05854 * @param ADCx ADC instance 05855 * @retval 0: no ADC disable command on going. 05856 */ 05857 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) 05858 { 05859 return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)); 05860 } 05861 05862 /** 05863 * @brief Start ADC calibration in the mode single-ended 05864 * or differential (for devices with differential mode available). 05865 * @note On this STM32 serie, a minimum number of ADC clock cycles 05866 * are required between ADC end of calibration and ADC enable. 05867 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. 05868 * @note For devices with differential mode available: 05869 * Calibration of offset is specific to each of 05870 * single-ended and differential modes 05871 * (calibration run must be performed for each of these 05872 * differential modes, if used afterwards and if the application 05873 * requires their calibration). 05874 * @note On this STM32 serie, setting of this feature is conditioned to 05875 * ADC state: 05876 * ADC must be ADC disabled. 05877 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n 05878 * CR ADCALDIF LL_ADC_StartCalibration 05879 * @param ADCx ADC instance 05880 * @param SingleDiff This parameter can be one of the following values: 05881 * @arg @ref LL_ADC_SINGLE_ENDED 05882 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED 05883 * @retval None 05884 */ 05885 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff) 05886 { 05887 /* Note: Write register with some additional bits forced to state reset */ 05888 /* instead of modifying only the selected bit for this function, */ 05889 /* to not interfere with bits with HW property "rs". */ 05890 MODIFY_REG(ADCx->CR, 05891 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS, 05892 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK)); 05893 } 05894 05895 /** 05896 * @brief Get ADC calibration state. 05897 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing 05898 * @param ADCx ADC instance 05899 * @retval 0: calibration complete, 1: calibration in progress. 05900 */ 05901 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) 05902 { 05903 return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)); 05904 } 05905 05906 /** 05907 * @} 05908 */ 05909 05910 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular 05911 * @{ 05912 */ 05913 05914 /** 05915 * @brief Start ADC group regular conversion. 05916 * @note On this STM32 serie, this function is relevant for both 05917 * internal trigger (SW start) and external trigger: 05918 * - If ADC trigger has been set to software start, ADC conversion 05919 * starts immediately. 05920 * - If ADC trigger has been set to external trigger, ADC conversion 05921 * will start at next trigger event (on the selected trigger edge) 05922 * following the ADC start conversion command. 05923 * @note On this STM32 serie, setting of this feature is conditioned to 05924 * ADC state: 05925 * ADC must be enabled without conversion on going on group regular, 05926 * without conversion stop command on going on group regular. 05927 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion 05928 * @param ADCx ADC instance 05929 * @retval None 05930 */ 05931 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) 05932 { 05933 /* Note: Write register with some additional bits forced to state reset */ 05934 /* instead of modifying only the selected bit for this function, */ 05935 /* to not interfere with bits with HW property "rs". */ 05936 MODIFY_REG(ADCx->CR, 05937 ADC_CR_BITS_PROPERTY_RS, 05938 ADC_CR_ADSTART); 05939 } 05940 05941 /** 05942 * @brief Stop ADC group regular conversion. 05943 * @note On this STM32 serie, setting of this feature is conditioned to 05944 * ADC state: 05945 * ADC must be enabled with conversion on going on group regular, 05946 * without ADC disable command on going. 05947 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion 05948 * @param ADCx ADC instance 05949 * @retval None 05950 */ 05951 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) 05952 { 05953 /* Note: Write register with some additional bits forced to state reset */ 05954 /* instead of modifying only the selected bit for this function, */ 05955 /* to not interfere with bits with HW property "rs". */ 05956 MODIFY_REG(ADCx->CR, 05957 ADC_CR_BITS_PROPERTY_RS, 05958 ADC_CR_ADSTP); 05959 } 05960 05961 /** 05962 * @brief Get ADC group regular conversion state. 05963 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing 05964 * @param ADCx ADC instance 05965 * @retval 0: no conversion is on going on ADC group regular. 05966 */ 05967 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) 05968 { 05969 return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)); 05970 } 05971 05972 /** 05973 * @brief Get ADC group regular command of conversion stop state 05974 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing 05975 * @param ADCx ADC instance 05976 * @retval 0: no command of conversion stop is on going on ADC group regular. 05977 */ 05978 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) 05979 { 05980 return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)); 05981 } 05982 05983 /** 05984 * @brief Get ADC group regular conversion data, range fit for 05985 * all ADC configurations: all ADC resolutions and 05986 * all oversampling increased data width (for devices 05987 * with feature oversampling). 05988 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 05989 * @param ADCx ADC instance 05990 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 05991 */ 05992 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) 05993 { 05994 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); 05995 } 05996 05997 /** 05998 * @brief Get ADC group regular conversion data, range fit for 05999 * ADC resolution 12 bits. 06000 * @note For devices with feature oversampling: Oversampling 06001 * can increase data width, function for extended range 06002 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 06003 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 06004 * @param ADCx ADC instance 06005 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 06006 */ 06007 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) 06008 { 06009 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); 06010 } 06011 06012 /** 06013 * @brief Get ADC group regular conversion data, range fit for 06014 * ADC resolution 10 bits. 06015 * @note For devices with feature oversampling: Oversampling 06016 * can increase data width, function for extended range 06017 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 06018 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 06019 * @param ADCx ADC instance 06020 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 06021 */ 06022 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) 06023 { 06024 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); 06025 } 06026 06027 /** 06028 * @brief Get ADC group regular conversion data, range fit for 06029 * ADC resolution 8 bits. 06030 * @note For devices with feature oversampling: Oversampling 06031 * can increase data width, function for extended range 06032 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 06033 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 06034 * @param ADCx ADC instance 06035 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 06036 */ 06037 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) 06038 { 06039 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); 06040 } 06041 06042 /** 06043 * @brief Get ADC group regular conversion data, range fit for 06044 * ADC resolution 6 bits. 06045 * @note For devices with feature oversampling: Oversampling 06046 * can increase data width, function for extended range 06047 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 06048 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 06049 * @param ADCx ADC instance 06050 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 06051 */ 06052 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) 06053 { 06054 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); 06055 } 06056 06057 #if defined(ADC_MULTIMODE_SUPPORT) 06058 /** 06059 * @brief Get ADC multimode conversion data of ADC master, ADC slave 06060 * or raw data with ADC master and slave concatenated. 06061 * @note If raw data with ADC master and slave concatenated is retrieved, 06062 * a macro is available to get the conversion data of 06063 * ADC master or ADC slave: see helper macro 06064 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 06065 * (however this macro is mainly intended for multimode 06066 * transfer by DMA, because this function can do the same 06067 * by getting multimode conversion data of ADC master or ADC slave 06068 * separately). 06069 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n 06070 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32 06071 * @param ADCxy_COMMON ADC common instance 06072 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06073 * @param ConversionData This parameter can be one of the following values: 06074 * @arg @ref LL_ADC_MULTI_MASTER 06075 * @arg @ref LL_ADC_MULTI_SLAVE 06076 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE 06077 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 06078 */ 06079 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) 06080 { 06081 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, 06082 ConversionData) 06083 >> POSITION_VAL(ConversionData) 06084 ); 06085 } 06086 #endif /* ADC_MULTIMODE_SUPPORT */ 06087 06088 /** 06089 * @} 06090 */ 06091 06092 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected 06093 * @{ 06094 */ 06095 06096 /** 06097 * @brief Start ADC group injected conversion. 06098 * @note On this STM32 serie, this function is relevant for both 06099 * internal trigger (SW start) and external trigger: 06100 * - If ADC trigger has been set to software start, ADC conversion 06101 * starts immediately. 06102 * - If ADC trigger has been set to external trigger, ADC conversion 06103 * will start at next trigger event (on the selected trigger edge) 06104 * following the ADC start conversion command. 06105 * @note On this STM32 serie, setting of this feature is conditioned to 06106 * ADC state: 06107 * ADC must be enabled without conversion on going on group injected, 06108 * without conversion stop command on going on group injected. 06109 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion 06110 * @param ADCx ADC instance 06111 * @retval None 06112 */ 06113 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) 06114 { 06115 /* Note: Write register with some additional bits forced to state reset */ 06116 /* instead of modifying only the selected bit for this function, */ 06117 /* to not interfere with bits with HW property "rs". */ 06118 MODIFY_REG(ADCx->CR, 06119 ADC_CR_BITS_PROPERTY_RS, 06120 ADC_CR_JADSTART); 06121 } 06122 06123 /** 06124 * @brief Stop ADC group injected conversion. 06125 * @note On this STM32 serie, setting of this feature is conditioned to 06126 * ADC state: 06127 * ADC must be enabled with conversion on going on group injected, 06128 * without ADC disable command on going. 06129 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion 06130 * @param ADCx ADC instance 06131 * @retval None 06132 */ 06133 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) 06134 { 06135 /* Note: Write register with some additional bits forced to state reset */ 06136 /* instead of modifying only the selected bit for this function, */ 06137 /* to not interfere with bits with HW property "rs". */ 06138 MODIFY_REG(ADCx->CR, 06139 ADC_CR_BITS_PROPERTY_RS, 06140 ADC_CR_JADSTP); 06141 } 06142 06143 /** 06144 * @brief Get ADC group injected conversion state. 06145 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing 06146 * @param ADCx ADC instance 06147 * @retval 0: no conversion is on going on ADC group injected. 06148 */ 06149 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) 06150 { 06151 return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)); 06152 } 06153 06154 /** 06155 * @brief Get ADC group injected command of conversion stop state 06156 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing 06157 * @param ADCx ADC instance 06158 * @retval 0: no command of conversion stop is on going on ADC group injected. 06159 */ 06160 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) 06161 { 06162 return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)); 06163 } 06164 06165 /** 06166 * @brief Get ADC group regular conversion data, range fit for 06167 * all ADC configurations: all ADC resolutions and 06168 * all oversampling increased data width (for devices 06169 * with feature oversampling). 06170 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n 06171 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n 06172 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n 06173 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 06174 * @param ADCx ADC instance 06175 * @param Rank This parameter can be one of the following values: 06176 * @arg @ref LL_ADC_INJ_RANK_1 06177 * @arg @ref LL_ADC_INJ_RANK_2 06178 * @arg @ref LL_ADC_INJ_RANK_3 06179 * @arg @ref LL_ADC_INJ_RANK_4 06180 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 06181 */ 06182 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) 06183 { 06184 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 06185 06186 return (uint32_t)(READ_BIT(*preg, 06187 ADC_JDR1_JDATA) 06188 ); 06189 } 06190 06191 /** 06192 * @brief Get ADC group injected conversion data, range fit for 06193 * ADC resolution 12 bits. 06194 * @note For devices with feature oversampling: Oversampling 06195 * can increase data width, function for extended range 06196 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 06197 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n 06198 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n 06199 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n 06200 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 06201 * @param ADCx ADC instance 06202 * @param Rank This parameter can be one of the following values: 06203 * @arg @ref LL_ADC_INJ_RANK_1 06204 * @arg @ref LL_ADC_INJ_RANK_2 06205 * @arg @ref LL_ADC_INJ_RANK_3 06206 * @arg @ref LL_ADC_INJ_RANK_4 06207 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 06208 */ 06209 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) 06210 { 06211 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 06212 06213 return (uint16_t)(READ_BIT(*preg, 06214 ADC_JDR1_JDATA) 06215 ); 06216 } 06217 06218 /** 06219 * @brief Get ADC group injected conversion data, range fit for 06220 * ADC resolution 10 bits. 06221 * @note For devices with feature oversampling: Oversampling 06222 * can increase data width, function for extended range 06223 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 06224 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n 06225 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n 06226 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n 06227 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 06228 * @param ADCx ADC instance 06229 * @param Rank This parameter can be one of the following values: 06230 * @arg @ref LL_ADC_INJ_RANK_1 06231 * @arg @ref LL_ADC_INJ_RANK_2 06232 * @arg @ref LL_ADC_INJ_RANK_3 06233 * @arg @ref LL_ADC_INJ_RANK_4 06234 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 06235 */ 06236 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) 06237 { 06238 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 06239 06240 return (uint16_t)(READ_BIT(*preg, 06241 ADC_JDR1_JDATA) 06242 ); 06243 } 06244 06245 /** 06246 * @brief Get ADC group injected conversion data, range fit for 06247 * ADC resolution 8 bits. 06248 * @note For devices with feature oversampling: Oversampling 06249 * can increase data width, function for extended range 06250 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 06251 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n 06252 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n 06253 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n 06254 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 06255 * @param ADCx ADC instance 06256 * @param Rank This parameter can be one of the following values: 06257 * @arg @ref LL_ADC_INJ_RANK_1 06258 * @arg @ref LL_ADC_INJ_RANK_2 06259 * @arg @ref LL_ADC_INJ_RANK_3 06260 * @arg @ref LL_ADC_INJ_RANK_4 06261 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 06262 */ 06263 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) 06264 { 06265 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 06266 06267 return (uint8_t)(READ_BIT(*preg, 06268 ADC_JDR1_JDATA) 06269 ); 06270 } 06271 06272 /** 06273 * @brief Get ADC group injected conversion data, range fit for 06274 * ADC resolution 6 bits. 06275 * @note For devices with feature oversampling: Oversampling 06276 * can increase data width, function for extended range 06277 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 06278 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n 06279 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n 06280 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n 06281 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 06282 * @param ADCx ADC instance 06283 * @param Rank This parameter can be one of the following values: 06284 * @arg @ref LL_ADC_INJ_RANK_1 06285 * @arg @ref LL_ADC_INJ_RANK_2 06286 * @arg @ref LL_ADC_INJ_RANK_3 06287 * @arg @ref LL_ADC_INJ_RANK_4 06288 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 06289 */ 06290 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) 06291 { 06292 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 06293 06294 return (uint8_t)(READ_BIT(*preg, 06295 ADC_JDR1_JDATA) 06296 ); 06297 } 06298 06299 /** 06300 * @} 06301 */ 06302 06303 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management 06304 * @{ 06305 */ 06306 06307 /** 06308 * @brief Get flag ADC ready. 06309 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC 06310 * is enabled and when conversion clock is active. 06311 * (not only core clock: this ADC has a dual clock domain) 06312 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY 06313 * @param ADCx ADC instance 06314 * @retval State of bit (1 or 0). 06315 */ 06316 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) 06317 { 06318 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)); 06319 } 06320 06321 /** 06322 * @brief Get flag ADC group regular end of unitary conversion. 06323 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC 06324 * @param ADCx ADC instance 06325 * @retval State of bit (1 or 0). 06326 */ 06327 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) 06328 { 06329 return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)); 06330 } 06331 06332 /** 06333 * @brief Get flag ADC group regular end of sequence conversions. 06334 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS 06335 * @param ADCx ADC instance 06336 * @retval State of bit (1 or 0). 06337 */ 06338 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) 06339 { 06340 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); 06341 } 06342 06343 /** 06344 * @brief Get flag ADC group regular overrun. 06345 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR 06346 * @param ADCx ADC instance 06347 * @retval State of bit (1 or 0). 06348 */ 06349 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) 06350 { 06351 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); 06352 } 06353 06354 /** 06355 * @brief Get flag ADC group regular end of sampling phase. 06356 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP 06357 * @param ADCx ADC instance 06358 * @retval State of bit (1 or 0). 06359 */ 06360 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) 06361 { 06362 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)); 06363 } 06364 06365 /** 06366 * @brief Get flag ADC group injected end of unitary conversion. 06367 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC 06368 * @param ADCx ADC instance 06369 * @retval State of bit (1 or 0). 06370 */ 06371 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) 06372 { 06373 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)); 06374 } 06375 06376 /** 06377 * @brief Get flag ADC group injected end of sequence conversions. 06378 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS 06379 * @param ADCx ADC instance 06380 * @retval State of bit (1 or 0). 06381 */ 06382 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) 06383 { 06384 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); 06385 } 06386 06387 /** 06388 * @brief Get flag ADC group injected contexts queue overflow. 06389 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF 06390 * @param ADCx ADC instance 06391 * @retval State of bit (1 or 0). 06392 */ 06393 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) 06394 { 06395 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)); 06396 } 06397 06398 /** 06399 * @brief Get flag ADC analog watchdog 1 flag 06400 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 06401 * @param ADCx ADC instance 06402 * @retval State of bit (1 or 0). 06403 */ 06404 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) 06405 { 06406 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 06407 } 06408 06409 /** 06410 * @brief Get flag ADC analog watchdog 2. 06411 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2 06412 * @param ADCx ADC instance 06413 * @retval State of bit (1 or 0). 06414 */ 06415 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) 06416 { 06417 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)); 06418 } 06419 06420 /** 06421 * @brief Get flag ADC analog watchdog 3. 06422 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3 06423 * @param ADCx ADC instance 06424 * @retval State of bit (1 or 0). 06425 */ 06426 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) 06427 { 06428 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)); 06429 } 06430 06431 /** 06432 * @brief Clear flag ADC ready. 06433 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC 06434 * is enabled and when conversion clock is active. 06435 * (not only core clock: this ADC has a dual clock domain) 06436 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY 06437 * @param ADCx ADC instance 06438 * @retval None 06439 */ 06440 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) 06441 { 06442 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); 06443 } 06444 06445 /** 06446 * @brief Clear flag ADC group regular end of unitary conversion. 06447 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC 06448 * @param ADCx ADC instance 06449 * @retval None 06450 */ 06451 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) 06452 { 06453 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); 06454 } 06455 06456 /** 06457 * @brief Clear flag ADC group regular end of sequence conversions. 06458 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS 06459 * @param ADCx ADC instance 06460 * @retval None 06461 */ 06462 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) 06463 { 06464 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); 06465 } 06466 06467 /** 06468 * @brief Clear flag ADC group regular overrun. 06469 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR 06470 * @param ADCx ADC instance 06471 * @retval None 06472 */ 06473 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) 06474 { 06475 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); 06476 } 06477 06478 /** 06479 * @brief Clear flag ADC group regular end of sampling phase. 06480 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP 06481 * @param ADCx ADC instance 06482 * @retval None 06483 */ 06484 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) 06485 { 06486 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); 06487 } 06488 06489 /** 06490 * @brief Clear flag ADC group injected end of unitary conversion. 06491 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC 06492 * @param ADCx ADC instance 06493 * @retval None 06494 */ 06495 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx) 06496 { 06497 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC); 06498 } 06499 06500 /** 06501 * @brief Clear flag ADC group injected end of sequence conversions. 06502 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS 06503 * @param ADCx ADC instance 06504 * @retval None 06505 */ 06506 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) 06507 { 06508 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS); 06509 } 06510 06511 /** 06512 * @brief Clear flag ADC group injected contexts queue overflow. 06513 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF 06514 * @param ADCx ADC instance 06515 * @retval None 06516 */ 06517 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx) 06518 { 06519 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF); 06520 } 06521 06522 /** 06523 * @brief Clear flag ADC analog watchdog 1. 06524 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 06525 * @param ADCx ADC instance 06526 * @retval None 06527 */ 06528 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) 06529 { 06530 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); 06531 } 06532 06533 /** 06534 * @brief Clear flag ADC analog watchdog 2. 06535 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2 06536 * @param ADCx ADC instance 06537 * @retval None 06538 */ 06539 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) 06540 { 06541 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2); 06542 } 06543 06544 /** 06545 * @brief Clear flag ADC analog watchdog 3. 06546 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3 06547 * @param ADCx ADC instance 06548 * @retval None 06549 */ 06550 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) 06551 { 06552 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); 06553 } 06554 06555 #if defined(ADC_MULTIMODE_SUPPORT) 06556 /** 06557 * @brief Get flag multimode ADC ready of the ADC master. 06558 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY 06559 * @param ADCxy_COMMON ADC common instance 06560 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06561 * @retval State of bit (1 or 0). 06562 */ 06563 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) 06564 { 06565 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)); 06566 } 06567 06568 /** 06569 * @brief Get flag multimode ADC ready of the ADC slave. 06570 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY 06571 * @param ADCxy_COMMON ADC common instance 06572 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06573 * @retval State of bit (1 or 0). 06574 */ 06575 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) 06576 { 06577 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)); 06578 } 06579 06580 /** 06581 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master. 06582 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC 06583 * @param ADCxy_COMMON ADC common instance 06584 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06585 * @retval State of bit (1 or 0). 06586 */ 06587 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) 06588 { 06589 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); 06590 } 06591 06592 /** 06593 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave. 06594 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC 06595 * @param ADCxy_COMMON ADC common instance 06596 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06597 * @retval State of bit (1 or 0). 06598 */ 06599 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) 06600 { 06601 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); 06602 } 06603 06604 /** 06605 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. 06606 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS 06607 * @param ADCxy_COMMON ADC common instance 06608 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06609 * @retval State of bit (1 or 0). 06610 */ 06611 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) 06612 { 06613 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)); 06614 } 06615 06616 /** 06617 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. 06618 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS 06619 * @param ADCxy_COMMON ADC common instance 06620 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06621 * @retval State of bit (1 or 0). 06622 */ 06623 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) 06624 { 06625 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); 06626 } 06627 06628 /** 06629 * @brief Get flag multimode ADC group regular overrun of the ADC master. 06630 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR 06631 * @param ADCxy_COMMON ADC common instance 06632 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06633 * @retval State of bit (1 or 0). 06634 */ 06635 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 06636 { 06637 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); 06638 } 06639 06640 /** 06641 * @brief Get flag multimode ADC group regular overrun of the ADC slave. 06642 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR 06643 * @param ADCxy_COMMON ADC common instance 06644 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06645 * @retval State of bit (1 or 0). 06646 */ 06647 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 06648 { 06649 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)); 06650 } 06651 06652 /** 06653 * @brief Get flag multimode ADC group regular end of sampling of the ADC master. 06654 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP 06655 * @param ADCxy_COMMON ADC common instance 06656 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06657 * @retval State of bit (1 or 0). 06658 */ 06659 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) 06660 { 06661 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)); 06662 } 06663 06664 /** 06665 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave. 06666 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP 06667 * @param ADCxy_COMMON ADC common instance 06668 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06669 * @retval State of bit (1 or 0). 06670 */ 06671 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) 06672 { 06673 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)); 06674 } 06675 06676 /** 06677 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master. 06678 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC 06679 * @param ADCxy_COMMON ADC common instance 06680 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06681 * @retval State of bit (1 or 0). 06682 */ 06683 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) 06684 { 06685 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)); 06686 } 06687 06688 /** 06689 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave. 06690 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC 06691 * @param ADCxy_COMMON ADC common instance 06692 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06693 * @retval State of bit (1 or 0). 06694 */ 06695 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) 06696 { 06697 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)); 06698 } 06699 06700 /** 06701 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. 06702 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS 06703 * @param ADCxy_COMMON ADC common instance 06704 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06705 * @retval State of bit (1 or 0). 06706 */ 06707 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 06708 { 06709 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)); 06710 } 06711 06712 /** 06713 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. 06714 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS 06715 * @param ADCxy_COMMON ADC common instance 06716 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06717 * @retval State of bit (1 or 0). 06718 */ 06719 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 06720 { 06721 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); 06722 } 06723 06724 /** 06725 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master. 06726 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF 06727 * @param ADCxy_COMMON ADC common instance 06728 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06729 * @retval State of bit (1 or 0). 06730 */ 06731 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) 06732 { 06733 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)); 06734 } 06735 06736 /** 06737 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave. 06738 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF 06739 * @param ADCxy_COMMON ADC common instance 06740 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06741 * @retval State of bit (1 or 0). 06742 */ 06743 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) 06744 { 06745 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)); 06746 } 06747 06748 /** 06749 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. 06750 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1 06751 * @param ADCxy_COMMON ADC common instance 06752 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06753 * @retval State of bit (1 or 0). 06754 */ 06755 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 06756 { 06757 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); 06758 } 06759 06760 /** 06761 * @brief Get flag multimode analog watchdog 1 of the ADC slave. 06762 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1 06763 * @param ADCxy_COMMON ADC common instance 06764 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06765 * @retval State of bit (1 or 0). 06766 */ 06767 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 06768 { 06769 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)); 06770 } 06771 06772 /** 06773 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master. 06774 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2 06775 * @param ADCxy_COMMON ADC common instance 06776 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06777 * @retval State of bit (1 or 0). 06778 */ 06779 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) 06780 { 06781 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)); 06782 } 06783 06784 /** 06785 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave. 06786 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2 06787 * @param ADCxy_COMMON ADC common instance 06788 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06789 * @retval State of bit (1 or 0). 06790 */ 06791 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) 06792 { 06793 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)); 06794 } 06795 06796 /** 06797 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master. 06798 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3 06799 * @param ADCxy_COMMON ADC common instance 06800 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06801 * @retval State of bit (1 or 0). 06802 */ 06803 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) 06804 { 06805 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)); 06806 } 06807 06808 /** 06809 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave. 06810 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3 06811 * @param ADCxy_COMMON ADC common instance 06812 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06813 * @retval State of bit (1 or 0). 06814 */ 06815 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) 06816 { 06817 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)); 06818 } 06819 #endif /* ADC_MULTIMODE_SUPPORT */ 06820 06821 /** 06822 * @} 06823 */ 06824 06825 /** @defgroup ADC_LL_EF_IT_Management ADC IT management 06826 * @{ 06827 */ 06828 06829 /** 06830 * @brief Enable ADC ready. 06831 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY 06832 * @param ADCx ADC instance 06833 * @retval None 06834 */ 06835 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) 06836 { 06837 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); 06838 } 06839 06840 /** 06841 * @brief Enable interruption ADC group regular end of unitary conversion. 06842 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC 06843 * @param ADCx ADC instance 06844 * @retval None 06845 */ 06846 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) 06847 { 06848 SET_BIT(ADCx->IER, LL_ADC_IT_EOC); 06849 } 06850 06851 /** 06852 * @brief Enable interruption ADC group regular end of sequence conversions. 06853 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS 06854 * @param ADCx ADC instance 06855 * @retval None 06856 */ 06857 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) 06858 { 06859 SET_BIT(ADCx->IER, LL_ADC_IT_EOS); 06860 } 06861 06862 /** 06863 * @brief Enable ADC group regular interruption overrun. 06864 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR 06865 * @param ADCx ADC instance 06866 * @retval None 06867 */ 06868 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) 06869 { 06870 SET_BIT(ADCx->IER, LL_ADC_IT_OVR); 06871 } 06872 06873 /** 06874 * @brief Enable interruption ADC group regular end of sampling. 06875 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP 06876 * @param ADCx ADC instance 06877 * @retval None 06878 */ 06879 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) 06880 { 06881 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); 06882 } 06883 06884 /** 06885 * @brief Enable interruption ADC group injected end of unitary conversion. 06886 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC 06887 * @param ADCx ADC instance 06888 * @retval None 06889 */ 06890 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx) 06891 { 06892 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC); 06893 } 06894 06895 /** 06896 * @brief Enable interruption ADC group injected end of sequence conversions. 06897 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS 06898 * @param ADCx ADC instance 06899 * @retval None 06900 */ 06901 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) 06902 { 06903 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS); 06904 } 06905 06906 /** 06907 * @brief Enable interruption ADC group injected context queue overflow. 06908 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF 06909 * @param ADCx ADC instance 06910 * @retval None 06911 */ 06912 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx) 06913 { 06914 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF); 06915 } 06916 06917 /** 06918 * @brief Enable interruption ADC analog watchdog 1. 06919 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 06920 * @param ADCx ADC instance 06921 * @retval None 06922 */ 06923 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) 06924 { 06925 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1); 06926 } 06927 06928 /** 06929 * @brief Enable interruption ADC analog watchdog 2. 06930 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2 06931 * @param ADCx ADC instance 06932 * @retval None 06933 */ 06934 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) 06935 { 06936 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2); 06937 } 06938 06939 /** 06940 * @brief Enable interruption ADC analog watchdog 3. 06941 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3 06942 * @param ADCx ADC instance 06943 * @retval None 06944 */ 06945 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) 06946 { 06947 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); 06948 } 06949 06950 /** 06951 * @brief Disable interruption ADC ready. 06952 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY 06953 * @param ADCx ADC instance 06954 * @retval None 06955 */ 06956 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) 06957 { 06958 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); 06959 } 06960 06961 /** 06962 * @brief Disable interruption ADC group regular end of unitary conversion. 06963 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC 06964 * @param ADCx ADC instance 06965 * @retval None 06966 */ 06967 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) 06968 { 06969 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); 06970 } 06971 06972 /** 06973 * @brief Disable interruption ADC group regular end of sequence conversions. 06974 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS 06975 * @param ADCx ADC instance 06976 * @retval None 06977 */ 06978 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) 06979 { 06980 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); 06981 } 06982 06983 /** 06984 * @brief Disable interruption ADC group regular overrun. 06985 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR 06986 * @param ADCx ADC instance 06987 * @retval None 06988 */ 06989 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) 06990 { 06991 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); 06992 } 06993 06994 /** 06995 * @brief Disable interruption ADC group regular end of sampling. 06996 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP 06997 * @param ADCx ADC instance 06998 * @retval None 06999 */ 07000 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) 07001 { 07002 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); 07003 } 07004 07005 /** 07006 * @brief Disable interruption ADC group regular end of unitary conversion. 07007 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC 07008 * @param ADCx ADC instance 07009 * @retval None 07010 */ 07011 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx) 07012 { 07013 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC); 07014 } 07015 07016 /** 07017 * @brief Disable interruption ADC group injected end of sequence conversions. 07018 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS 07019 * @param ADCx ADC instance 07020 * @retval None 07021 */ 07022 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) 07023 { 07024 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS); 07025 } 07026 07027 /** 07028 * @brief Disable interruption ADC group injected context queue overflow. 07029 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF 07030 * @param ADCx ADC instance 07031 * @retval None 07032 */ 07033 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx) 07034 { 07035 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF); 07036 } 07037 07038 /** 07039 * @brief Disable interruption ADC analog watchdog 1. 07040 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 07041 * @param ADCx ADC instance 07042 * @retval None 07043 */ 07044 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) 07045 { 07046 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1); 07047 } 07048 07049 /** 07050 * @brief Disable interruption ADC analog watchdog 2. 07051 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2 07052 * @param ADCx ADC instance 07053 * @retval None 07054 */ 07055 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) 07056 { 07057 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2); 07058 } 07059 07060 /** 07061 * @brief Disable interruption ADC analog watchdog 3. 07062 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3 07063 * @param ADCx ADC instance 07064 * @retval None 07065 */ 07066 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) 07067 { 07068 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); 07069 } 07070 07071 /** 07072 * @brief Get state of interruption ADC ready 07073 * (0: interrupt disabled, 1: interrupt enabled). 07074 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY 07075 * @param ADCx ADC instance 07076 * @retval State of bit (1 or 0). 07077 */ 07078 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) 07079 { 07080 return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)); 07081 } 07082 07083 /** 07084 * @brief Get state of interruption ADC group regular end of unitary conversion 07085 * (0: interrupt disabled, 1: interrupt enabled). 07086 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC 07087 * @param ADCx ADC instance 07088 * @retval State of bit (1 or 0). 07089 */ 07090 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) 07091 { 07092 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)); 07093 } 07094 07095 /** 07096 * @brief Get state of interruption ADC group regular end of sequence conversions 07097 * (0: interrupt disabled, 1: interrupt enabled). 07098 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS 07099 * @param ADCx ADC instance 07100 * @retval State of bit (1 or 0). 07101 */ 07102 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) 07103 { 07104 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); 07105 } 07106 07107 /** 07108 * @brief Get state of interruption ADC group regular overrun 07109 * (0: interrupt disabled, 1: interrupt enabled). 07110 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR 07111 * @param ADCx ADC instance 07112 * @retval State of bit (1 or 0). 07113 */ 07114 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) 07115 { 07116 return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); 07117 } 07118 07119 /** 07120 * @brief Get state of interruption ADC group regular end of sampling 07121 * (0: interrupt disabled, 1: interrupt enabled). 07122 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP 07123 * @param ADCx ADC instance 07124 * @retval State of bit (1 or 0). 07125 */ 07126 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) 07127 { 07128 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)); 07129 } 07130 07131 /** 07132 * @brief Get state of interruption ADC group injected end of unitary conversion 07133 * (0: interrupt disabled, 1: interrupt enabled). 07134 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC 07135 * @param ADCx ADC instance 07136 * @retval State of bit (1 or 0). 07137 */ 07138 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) 07139 { 07140 return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)); 07141 } 07142 07143 /** 07144 * @brief Get state of interruption ADC group injected end of sequence conversions 07145 * (0: interrupt disabled, 1: interrupt enabled). 07146 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS 07147 * @param ADCx ADC instance 07148 * @retval State of bit (1 or 0). 07149 */ 07150 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) 07151 { 07152 return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); 07153 } 07154 07155 /** 07156 * @brief Get state of interruption ADC group injected context queue overflow interrupt state 07157 * (0: interrupt disabled, 1: interrupt enabled). 07158 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF 07159 * @param ADCx ADC instance 07160 * @retval State of bit (1 or 0). 07161 */ 07162 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) 07163 { 07164 return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)); 07165 } 07166 07167 /** 07168 * @brief Get state of interruption ADC analog watchdog 1 07169 * (0: interrupt disabled, 1: interrupt enabled). 07170 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1 07171 * @param ADCx ADC instance 07172 * @retval State of bit (1 or 0). 07173 */ 07174 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) 07175 { 07176 return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); 07177 } 07178 07179 /** 07180 * @brief Get state of interruption Get ADC analog watchdog 2 07181 * (0: interrupt disabled, 1: interrupt enabled). 07182 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2 07183 * @param ADCx ADC instance 07184 * @retval State of bit (1 or 0). 07185 */ 07186 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) 07187 { 07188 return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)); 07189 } 07190 07191 /** 07192 * @brief Get state of interruption Get ADC analog watchdog 3 07193 * (0: interrupt disabled, 1: interrupt enabled). 07194 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3 07195 * @param ADCx ADC instance 07196 * @retval State of bit (1 or 0). 07197 */ 07198 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) 07199 { 07200 return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)); 07201 } 07202 07203 /** 07204 * @} 07205 */ 07206 07207 #if defined(USE_FULL_LL_DRIVER) 07208 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions 07209 * @{ 07210 */ 07211 07212 /* Initialization of some features of ADC common parameters and multimode */ 07213 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); 07214 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 07215 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 07216 07217 /* De-initialization of ADC instance, ADC group regular and ADC group injected */ 07218 /* (availability of ADC group injected depends on STM32 families) */ 07219 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); 07220 07221 /* Initialization of some features of ADC instance */ 07222 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); 07223 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); 07224 07225 /* Initialization of some features of ADC instance and ADC group regular */ 07226 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 07227 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 07228 07229 /* Initialization of some features of ADC instance and ADC group injected */ 07230 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 07231 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 07232 07233 /** 07234 * @} 07235 */ 07236 #endif /* USE_FULL_LL_DRIVER */ 07237 07238 /** 07239 * @} 07240 */ 07241 07242 /** 07243 * @} 07244 */ 07245 07246 #endif /* ADC1 || ADC2 || ADC3 */ 07247 07248 /** 07249 * @} 07250 */ 07251 07252 #ifdef __cplusplus 07253 } 07254 #endif 07255 07256 #endif /* __STM32L4xx_LL_ADC_H */ 07257 07258 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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