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stm32l4xx_hal_tsc.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_tsc.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of TSC HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_HAL_TSC_H 00040 #define __STM32L4xx_HAL_TSC_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_hal_def.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup TSC 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup TSC_Exported_Types TSC Exported Types 00059 * @{ 00060 */ 00061 00062 /** 00063 * @brief TSC state structure definition 00064 */ 00065 typedef enum 00066 { 00067 HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */ 00068 HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */ 00069 HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */ 00070 HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */ 00071 } HAL_TSC_StateTypeDef; 00072 00073 /** 00074 * @brief TSC group status structure definition 00075 */ 00076 typedef enum 00077 { 00078 TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */ 00079 TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */ 00080 } TSC_GroupStatusTypeDef; 00081 00082 /** 00083 * @brief TSC init structure definition 00084 */ 00085 typedef struct 00086 { 00087 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 00088 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 00089 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 00090 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 00091 uint32_t SpreadSpectrum; /*!< Spread spectrum activation 00092 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 00093 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 00094 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 00095 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 00096 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 00097 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 00098 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 00099 uint32_t MaxCountValue; /*!< Max count value 00100 This parameter can be a value of @ref TSC_MaxCount_Value */ 00101 uint32_t IODefaultMode; /*!< IO default mode 00102 This parameter can be a value of @ref TSC_IO_Default_Mode */ 00103 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 00104 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 00105 uint32_t AcquisitionMode; /*!< Acquisition mode 00106 This parameter can be a value of @ref TSC_Acquisition_Mode */ 00107 uint32_t MaxCountInterrupt; /*!< Max count interrupt activation 00108 This parameter can be set to ENABLE or DISABLE. */ 00109 uint32_t ChannelIOs; /*!< Channel IOs mask */ 00110 uint32_t ShieldIOs; /*!< Shield IOs mask */ 00111 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 00112 } TSC_InitTypeDef; 00113 00114 /** 00115 * @brief TSC IOs configuration structure definition 00116 */ 00117 typedef struct 00118 { 00119 uint32_t ChannelIOs; /*!< Channel IOs mask */ 00120 uint32_t ShieldIOs; /*!< Shield IOs mask */ 00121 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 00122 } TSC_IOConfigTypeDef; 00123 00124 /** 00125 * @brief TSC handle Structure definition 00126 */ 00127 typedef struct 00128 { 00129 TSC_TypeDef *Instance; /*!< Register base address */ 00130 TSC_InitTypeDef Init; /*!< Initialization parameters */ 00131 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 00132 HAL_LockTypeDef Lock; /*!< Lock feature */ 00133 } TSC_HandleTypeDef; 00134 00135 /** 00136 * @} 00137 */ 00138 00139 /* Exported constants --------------------------------------------------------*/ 00140 /** @defgroup TSC_Exported_Constants TSC Exported Constants 00141 * @{ 00142 */ 00143 00144 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 00145 * @{ 00146 */ 00147 #define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28)) 00148 #define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28)) 00149 #define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28)) 00150 #define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28)) 00151 #define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28)) 00152 #define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28)) 00153 #define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28)) 00154 #define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28)) 00155 #define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28)) 00156 #define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28)) 00157 #define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28)) 00158 #define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28)) 00159 #define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28)) 00160 #define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28)) 00161 #define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28)) 00162 #define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28)) 00163 /** 00164 * @} 00165 */ 00166 00167 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 00168 * @{ 00169 */ 00170 #define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24)) 00171 #define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24)) 00172 #define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24)) 00173 #define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24)) 00174 #define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24)) 00175 #define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24)) 00176 #define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24)) 00177 #define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24)) 00178 #define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24)) 00179 #define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24)) 00180 #define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24)) 00181 #define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24)) 00182 #define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24)) 00183 #define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24)) 00184 #define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24)) 00185 #define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24)) 00186 /** 00187 * @} 00188 */ 00189 00190 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 00191 * @{ 00192 */ 00193 #define TSC_SS_PRESC_DIV1 ((uint32_t)0) 00194 #define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC) 00195 /** 00196 * @} 00197 */ 00198 00199 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 00200 * @{ 00201 */ 00202 #define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12)) 00203 #define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12)) 00204 #define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12)) 00205 #define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12)) 00206 #define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12)) 00207 #define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12)) 00208 #define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12)) 00209 #define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12)) 00210 /** 00211 * @} 00212 */ 00213 00214 /** @defgroup TSC_MaxCount_Value Max Count Value 00215 * @{ 00216 */ 00217 #define TSC_MCV_255 ((uint32_t)(0 << 5)) 00218 #define TSC_MCV_511 ((uint32_t)(1 << 5)) 00219 #define TSC_MCV_1023 ((uint32_t)(2 << 5)) 00220 #define TSC_MCV_2047 ((uint32_t)(3 << 5)) 00221 #define TSC_MCV_4095 ((uint32_t)(4 << 5)) 00222 #define TSC_MCV_8191 ((uint32_t)(5 << 5)) 00223 #define TSC_MCV_16383 ((uint32_t)(6 << 5)) 00224 /** 00225 * @} 00226 */ 00227 00228 /** @defgroup TSC_IO_Default_Mode IO Default Mode 00229 * @{ 00230 */ 00231 #define TSC_IODEF_OUT_PP_LOW ((uint32_t)0) 00232 #define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF) 00233 /** 00234 * @} 00235 */ 00236 00237 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 00238 * @{ 00239 */ 00240 #define TSC_SYNC_POLARITY_FALLING ((uint32_t)0) 00241 #define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL) 00242 /** 00243 * @} 00244 */ 00245 00246 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 00247 * @{ 00248 */ 00249 #define TSC_ACQ_MODE_NORMAL ((uint32_t)0) 00250 #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM) 00251 /** 00252 * @} 00253 */ 00254 00255 /** @defgroup TSC_IO_Mode IO Mode 00256 * @{ 00257 */ 00258 #define TSC_IOMODE_UNUSED ((uint32_t)0) 00259 #define TSC_IOMODE_CHANNEL ((uint32_t)1) 00260 #define TSC_IOMODE_SHIELD ((uint32_t)2) 00261 #define TSC_IOMODE_SAMPLING ((uint32_t)3) 00262 /** 00263 * @} 00264 */ 00265 00266 /** @defgroup TSC_interrupts_definition Interrupts definition 00267 * @{ 00268 */ 00269 #define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE) 00270 #define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE) 00271 /** 00272 * @} 00273 */ 00274 00275 /** @defgroup TSC_flags_definition Flags definition 00276 * @{ 00277 */ 00278 #define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF) 00279 #define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF) 00280 /** 00281 * @} 00282 */ 00283 00284 /** @defgroup TSC_Group_definition Group definition 00285 * @{ 00286 */ 00287 #define TSC_NB_OF_GROUPS (8) 00288 00289 #define TSC_GROUP1 ((uint32_t)0x00000001) 00290 #define TSC_GROUP2 ((uint32_t)0x00000002) 00291 #define TSC_GROUP3 ((uint32_t)0x00000004) 00292 #define TSC_GROUP4 ((uint32_t)0x00000008) 00293 #define TSC_GROUP5 ((uint32_t)0x00000010) 00294 #define TSC_GROUP6 ((uint32_t)0x00000020) 00295 #define TSC_GROUP7 ((uint32_t)0x00000040) 00296 #define TSC_GROUP8 ((uint32_t)0x00000080) 00297 #define TSC_ALL_GROUPS ((uint32_t)0x000000FF) 00298 00299 #define TSC_GROUP1_IDX ((uint32_t)0) 00300 #define TSC_GROUP2_IDX ((uint32_t)1) 00301 #define TSC_GROUP3_IDX ((uint32_t)2) 00302 #define TSC_GROUP4_IDX ((uint32_t)3) 00303 #define TSC_GROUP5_IDX ((uint32_t)4) 00304 #define TSC_GROUP6_IDX ((uint32_t)5) 00305 #define TSC_GROUP7_IDX ((uint32_t)6) 00306 #define TSC_GROUP8_IDX ((uint32_t)7) 00307 00308 #define TSC_GROUP1_IO1 ((uint32_t)0x00000001) 00309 #define TSC_GROUP1_IO2 ((uint32_t)0x00000002) 00310 #define TSC_GROUP1_IO3 ((uint32_t)0x00000004) 00311 #define TSC_GROUP1_IO4 ((uint32_t)0x00000008) 00312 #define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F) 00313 00314 #define TSC_GROUP2_IO1 ((uint32_t)0x00000010) 00315 #define TSC_GROUP2_IO2 ((uint32_t)0x00000020) 00316 #define TSC_GROUP2_IO3 ((uint32_t)0x00000040) 00317 #define TSC_GROUP2_IO4 ((uint32_t)0x00000080) 00318 #define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0) 00319 00320 #define TSC_GROUP3_IO1 ((uint32_t)0x00000100) 00321 #define TSC_GROUP3_IO2 ((uint32_t)0x00000200) 00322 #define TSC_GROUP3_IO3 ((uint32_t)0x00000400) 00323 #define TSC_GROUP3_IO4 ((uint32_t)0x00000800) 00324 #define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00) 00325 00326 #define TSC_GROUP4_IO1 ((uint32_t)0x00001000) 00327 #define TSC_GROUP4_IO2 ((uint32_t)0x00002000) 00328 #define TSC_GROUP4_IO3 ((uint32_t)0x00004000) 00329 #define TSC_GROUP4_IO4 ((uint32_t)0x00008000) 00330 #define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000) 00331 00332 #define TSC_GROUP5_IO1 ((uint32_t)0x00010000) 00333 #define TSC_GROUP5_IO2 ((uint32_t)0x00020000) 00334 #define TSC_GROUP5_IO3 ((uint32_t)0x00040000) 00335 #define TSC_GROUP5_IO4 ((uint32_t)0x00080000) 00336 #define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000) 00337 00338 #define TSC_GROUP6_IO1 ((uint32_t)0x00100000) 00339 #define TSC_GROUP6_IO2 ((uint32_t)0x00200000) 00340 #define TSC_GROUP6_IO3 ((uint32_t)0x00400000) 00341 #define TSC_GROUP6_IO4 ((uint32_t)0x00800000) 00342 #define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000) 00343 00344 #define TSC_GROUP7_IO1 ((uint32_t)0x01000000) 00345 #define TSC_GROUP7_IO2 ((uint32_t)0x02000000) 00346 #define TSC_GROUP7_IO3 ((uint32_t)0x04000000) 00347 #define TSC_GROUP7_IO4 ((uint32_t)0x08000000) 00348 #define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000) 00349 00350 #define TSC_GROUP8_IO1 ((uint32_t)0x10000000) 00351 #define TSC_GROUP8_IO2 ((uint32_t)0x20000000) 00352 #define TSC_GROUP8_IO3 ((uint32_t)0x40000000) 00353 #define TSC_GROUP8_IO4 ((uint32_t)0x80000000) 00354 #define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000) 00355 00356 #define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF) 00357 /** 00358 * @} 00359 */ 00360 00361 /** 00362 * @} 00363 */ 00364 00365 /* Exported macros -----------------------------------------------------------*/ 00366 00367 /** @defgroup TSC_Exported_Macros TSC Exported Macros 00368 * @{ 00369 */ 00370 00371 /** @brief Reset TSC handle state. 00372 * @param __HANDLE__: TSC handle 00373 * @retval None 00374 */ 00375 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 00376 00377 /** 00378 * @brief Enable the TSC peripheral. 00379 * @param __HANDLE__: TSC handle 00380 * @retval None 00381 */ 00382 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 00383 00384 /** 00385 * @brief Disable the TSC peripheral. 00386 * @param __HANDLE__: TSC handle 00387 * @retval None 00388 */ 00389 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) 00390 00391 /** 00392 * @brief Start acquisition. 00393 * @param __HANDLE__: TSC handle 00394 * @retval None 00395 */ 00396 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 00397 00398 /** 00399 * @brief Stop acquisition. 00400 * @param __HANDLE__: TSC handle 00401 * @retval None 00402 */ 00403 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) 00404 00405 /** 00406 * @brief Set IO default mode to output push-pull low. 00407 * @param __HANDLE__: TSC handle 00408 * @retval None 00409 */ 00410 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) 00411 00412 /** 00413 * @brief Set IO default mode to input floating. 00414 * @param __HANDLE__: TSC handle 00415 * @retval None 00416 */ 00417 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 00418 00419 /** 00420 * @brief Set synchronization polarity to falling edge. 00421 * @param __HANDLE__: TSC handle 00422 * @retval None 00423 */ 00424 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) 00425 00426 /** 00427 * @brief Set synchronization polarity to rising edge and high level. 00428 * @param __HANDLE__: TSC handle 00429 * @retval None 00430 */ 00431 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 00432 00433 /** 00434 * @brief Enable TSC interrupt. 00435 * @param __HANDLE__: TSC handle 00436 * @param __INTERRUPT__: TSC interrupt 00437 * @retval None 00438 */ 00439 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 00440 00441 /** 00442 * @brief Disable TSC interrupt. 00443 * @param __HANDLE__: TSC handle 00444 * @param __INTERRUPT__: TSC interrupt 00445 * @retval None 00446 */ 00447 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) 00448 00449 /** @brief Check whether the specified TSC interrupt source is enabled or not. 00450 * @param __HANDLE__: TSC Handle 00451 * @param __INTERRUPT__: TSC interrupt 00452 * @retval SET or RESET 00453 */ 00454 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00455 00456 /** 00457 * @brief Check whether the specified TSC flag is set or not. 00458 * @param __HANDLE__: TSC handle 00459 * @param __FLAG__: TSC flag 00460 * @retval SET or RESET 00461 */ 00462 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 00463 00464 /** 00465 * @brief Clear the TSC's pending flag. 00466 * @param __HANDLE__: TSC handle 00467 * @param __FLAG__: TSC flag 00468 * @retval None 00469 */ 00470 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 00471 00472 /** 00473 * @brief Enable schmitt trigger hysteresis on a group of IOs. 00474 * @param __HANDLE__: TSC handle 00475 * @param __GX_IOY_MASK__: IOs mask 00476 * @retval None 00477 */ 00478 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 00479 00480 /** 00481 * @brief Disable schmitt trigger hysteresis on a group of IOs. 00482 * @param __HANDLE__: TSC handle 00483 * @param __GX_IOY_MASK__: IOs mask 00484 * @retval None 00485 */ 00486 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) 00487 00488 /** 00489 * @brief Open analog switch on a group of IOs. 00490 * @param __HANDLE__: TSC handle 00491 * @param __GX_IOY_MASK__: IOs mask 00492 * @retval None 00493 */ 00494 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) 00495 00496 /** 00497 * @brief Close analog switch on a group of IOs. 00498 * @param __HANDLE__: TSC handle 00499 * @param __GX_IOY_MASK__: IOs mask 00500 * @retval None 00501 */ 00502 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 00503 00504 /** 00505 * @brief Enable a group of IOs in channel mode. 00506 * @param __HANDLE__: TSC handle 00507 * @param __GX_IOY_MASK__: IOs mask 00508 * @retval None 00509 */ 00510 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 00511 00512 /** 00513 * @brief Disable a group of channel IOs. 00514 * @param __HANDLE__: TSC handle 00515 * @param __GX_IOY_MASK__: IOs mask 00516 * @retval None 00517 */ 00518 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) 00519 00520 /** 00521 * @brief Enable a group of IOs in sampling mode. 00522 * @param __HANDLE__: TSC handle 00523 * @param __GX_IOY_MASK__: IOs mask 00524 * @retval None 00525 */ 00526 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 00527 00528 /** 00529 * @brief Disable a group of sampling IOs. 00530 * @param __HANDLE__: TSC handle 00531 * @param __GX_IOY_MASK__: IOs mask 00532 * @retval None 00533 */ 00534 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__))) 00535 00536 /** 00537 * @brief Enable acquisition groups. 00538 * @param __HANDLE__: TSC handle 00539 * @param __GX_MASK__: Groups mask 00540 * @retval None 00541 */ 00542 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 00543 00544 /** 00545 * @brief Disable acquisition groups. 00546 * @param __HANDLE__: TSC handle 00547 * @param __GX_MASK__: Groups mask 00548 * @retval None 00549 */ 00550 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__))) 00551 00552 /** @brief Gets acquisition group status. 00553 * @param __HANDLE__: TSC Handle 00554 * @param __GX_INDEX__: Group index 00555 * @retval SET or RESET 00556 */ 00557 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 00558 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 00559 00560 /** 00561 * @} 00562 */ 00563 00564 /* Private macros ------------------------------------------------------------*/ 00565 00566 /** @defgroup TSC_Private_Macros TSC Private Macros 00567 * @{ 00568 */ 00569 00570 #define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \ 00571 ((VAL) == TSC_CTPH_2CYCLES) || \ 00572 ((VAL) == TSC_CTPH_3CYCLES) || \ 00573 ((VAL) == TSC_CTPH_4CYCLES) || \ 00574 ((VAL) == TSC_CTPH_5CYCLES) || \ 00575 ((VAL) == TSC_CTPH_6CYCLES) || \ 00576 ((VAL) == TSC_CTPH_7CYCLES) || \ 00577 ((VAL) == TSC_CTPH_8CYCLES) || \ 00578 ((VAL) == TSC_CTPH_9CYCLES) || \ 00579 ((VAL) == TSC_CTPH_10CYCLES) || \ 00580 ((VAL) == TSC_CTPH_11CYCLES) || \ 00581 ((VAL) == TSC_CTPH_12CYCLES) || \ 00582 ((VAL) == TSC_CTPH_13CYCLES) || \ 00583 ((VAL) == TSC_CTPH_14CYCLES) || \ 00584 ((VAL) == TSC_CTPH_15CYCLES) || \ 00585 ((VAL) == TSC_CTPH_16CYCLES)) 00586 00587 #define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \ 00588 ((VAL) == TSC_CTPL_2CYCLES) || \ 00589 ((VAL) == TSC_CTPL_3CYCLES) || \ 00590 ((VAL) == TSC_CTPL_4CYCLES) || \ 00591 ((VAL) == TSC_CTPL_5CYCLES) || \ 00592 ((VAL) == TSC_CTPL_6CYCLES) || \ 00593 ((VAL) == TSC_CTPL_7CYCLES) || \ 00594 ((VAL) == TSC_CTPL_8CYCLES) || \ 00595 ((VAL) == TSC_CTPL_9CYCLES) || \ 00596 ((VAL) == TSC_CTPL_10CYCLES) || \ 00597 ((VAL) == TSC_CTPL_11CYCLES) || \ 00598 ((VAL) == TSC_CTPL_12CYCLES) || \ 00599 ((VAL) == TSC_CTPL_13CYCLES) || \ 00600 ((VAL) == TSC_CTPL_14CYCLES) || \ 00601 ((VAL) == TSC_CTPL_15CYCLES) || \ 00602 ((VAL) == TSC_CTPL_16CYCLES)) 00603 00604 #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) 00605 00606 #define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128))) 00607 00608 #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2)) 00609 00610 #define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \ 00611 ((VAL) == TSC_PG_PRESC_DIV2) || \ 00612 ((VAL) == TSC_PG_PRESC_DIV4) || \ 00613 ((VAL) == TSC_PG_PRESC_DIV8) || \ 00614 ((VAL) == TSC_PG_PRESC_DIV16) || \ 00615 ((VAL) == TSC_PG_PRESC_DIV32) || \ 00616 ((VAL) == TSC_PG_PRESC_DIV64) || \ 00617 ((VAL) == TSC_PG_PRESC_DIV128)) 00618 00619 #define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \ 00620 ((VAL) == TSC_MCV_511) || \ 00621 ((VAL) == TSC_MCV_1023) || \ 00622 ((VAL) == TSC_MCV_2047) || \ 00623 ((VAL) == TSC_MCV_4095) || \ 00624 ((VAL) == TSC_MCV_8191) || \ 00625 ((VAL) == TSC_MCV_16383)) 00626 00627 #define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT)) 00628 00629 #define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING)) 00630 00631 #define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO)) 00632 00633 #define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \ 00634 ((VAL) == TSC_IOMODE_CHANNEL) || \ 00635 ((VAL) == TSC_IOMODE_SHIELD) || \ 00636 ((VAL) == TSC_IOMODE_SAMPLING)) 00637 00638 #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) 00639 00640 #define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS))) 00641 00642 /** 00643 * @} 00644 */ 00645 00646 /* Exported functions --------------------------------------------------------*/ 00647 /** @addtogroup TSC_Exported_Functions 00648 * @{ 00649 */ 00650 00651 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 00652 * @{ 00653 */ 00654 /* Initialization and de-initialization functions *****************************/ 00655 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc); 00656 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 00657 void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc); 00658 void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc); 00659 /** 00660 * @} 00661 */ 00662 00663 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 00664 * @{ 00665 */ 00666 /* IO operation functions *****************************************************/ 00667 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc); 00668 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc); 00669 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc); 00670 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc); 00671 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc); 00672 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index); 00673 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index); 00674 /** 00675 * @} 00676 */ 00677 00678 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 00679 * @{ 00680 */ 00681 /* Peripheral Control functions ***********************************************/ 00682 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config); 00683 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice); 00684 /** 00685 * @} 00686 */ 00687 00688 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 00689 * @{ 00690 */ 00691 /* Peripheral State and Error functions ***************************************/ 00692 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc); 00693 /** 00694 * @} 00695 */ 00696 00697 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 00698 * @{ 00699 */ 00700 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 00701 void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc); 00702 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc); 00703 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc); 00704 /** 00705 * @} 00706 */ 00707 00708 /** 00709 * @} 00710 */ 00711 00712 /** 00713 * @} 00714 */ 00715 00716 /** 00717 * @} 00718 */ 00719 00720 #ifdef __cplusplus 00721 } 00722 #endif 00723 00724 #endif /* __STM32L4xx_HAL_TSC_H */ 00725 00726 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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