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stm32l4xx_hal_smbus.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_smbus.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of SMBUS HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_HAL_SMBUS_H 00040 #define __STM32L4xx_HAL_SMBUS_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_hal_def.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup SMBUS 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types 00059 * @{ 00060 */ 00061 00062 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition 00063 * @brief SMBUS Configuration Structure definition 00064 * @{ 00065 */ 00066 typedef struct 00067 { 00068 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. 00069 This parameter calculated by referring to SMBUS initialization 00070 section in Reference manual */ 00071 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 00072 This parameter can be a value of @ref SMBUS_Analog_Filter */ 00073 00074 uint32_t OwnAddress1; /*!< Specifies the first device own address. 00075 This parameter can be a 7-bit or 10-bit address. */ 00076 00077 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 00078 This parameter can be a value of @ref SMBUS_addressing_mode */ 00079 00080 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 00081 This parameter can be a value of @ref SMBUS_dual_addressing_mode */ 00082 00083 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 00084 This parameter can be a 7-bit address. */ 00085 00086 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected 00087 This parameter can be a value of @ref SMBUS_own_address2_masks. */ 00088 00089 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 00090 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ 00091 00092 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 00093 This parameter can be a value of @ref SMBUS_nostretch_mode */ 00094 00095 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 00096 This parameter can be a value of @ref SMBUS_packet_error_check_mode */ 00097 00098 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 00099 This parameter can be a value of @ref SMBUS_peripheral_mode */ 00100 00101 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. 00102 (Enable bits and different timeout values) 00103 This parameter calculated by referring to SMBUS initialization 00104 section in Reference manual */ 00105 } SMBUS_InitTypeDef; 00106 /** 00107 * @} 00108 */ 00109 00110 /** @defgroup HAL_state_definition HAL state definition 00111 * @brief HAL State definition 00112 * @{ 00113 */ 00114 #define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */ 00115 #define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */ 00116 #define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */ 00117 #define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */ 00118 #define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */ 00119 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */ 00120 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */ 00121 #define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */ 00122 #define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */ 00123 #define HAL_SMBUS_STATE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */ 00124 /** 00125 * @} 00126 */ 00127 00128 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition 00129 * @brief SMBUS Error Code definition 00130 * @{ 00131 */ 00132 #define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ 00133 #define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */ 00134 #define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */ 00135 #define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */ 00136 #define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */ 00137 #define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */ 00138 #define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */ 00139 #define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */ 00140 #define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */ 00141 /** 00142 * @} 00143 */ 00144 00145 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition 00146 * @brief SMBUS handle Structure definition 00147 * @{ 00148 */ 00149 typedef struct 00150 { 00151 I2C_TypeDef *Instance; /*!< SMBUS registers base address */ 00152 00153 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ 00154 00155 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ 00156 00157 uint16_t XferSize; /*!< SMBUS transfer size */ 00158 00159 __IO uint16_t XferCount; /*!< SMBUS transfer counter */ 00160 00161 __IO uint32_t XferOptions; /*!< SMBUS transfer options */ 00162 00163 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ 00164 00165 HAL_LockTypeDef Lock; /*!< SMBUS locking object */ 00166 00167 __IO uint32_t State; /*!< SMBUS communication state */ 00168 00169 __IO uint32_t ErrorCode; /*!< SMBUS Error code */ 00170 00171 }SMBUS_HandleTypeDef; 00172 /** 00173 * @} 00174 */ 00175 00176 /** 00177 * @} 00178 */ 00179 /* Exported constants --------------------------------------------------------*/ 00180 00181 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants 00182 * @{ 00183 */ 00184 00185 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter 00186 * @{ 00187 */ 00188 #define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) 00189 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 00190 /** 00191 * @} 00192 */ 00193 00194 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode 00195 * @{ 00196 */ 00197 #define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) 00198 #define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) 00199 /** 00200 * @} 00201 */ 00202 00203 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode 00204 * @{ 00205 */ 00206 00207 #define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000) 00208 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN 00209 /** 00210 * @} 00211 */ 00212 00213 /** @defgroup SMBUS_own_address2_masks SMBUS own address2 masks 00214 * @{ 00215 */ 00216 00217 #define SMBUS_OA2_NOMASK ((uint8_t)0x00) 00218 #define SMBUS_OA2_MASK01 ((uint8_t)0x01) 00219 #define SMBUS_OA2_MASK02 ((uint8_t)0x02) 00220 #define SMBUS_OA2_MASK03 ((uint8_t)0x03) 00221 #define SMBUS_OA2_MASK04 ((uint8_t)0x04) 00222 #define SMBUS_OA2_MASK05 ((uint8_t)0x05) 00223 #define SMBUS_OA2_MASK06 ((uint8_t)0x06) 00224 #define SMBUS_OA2_MASK07 ((uint8_t)0x07) 00225 /** 00226 * @} 00227 */ 00228 00229 00230 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode 00231 * @{ 00232 */ 00233 #define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000) 00234 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN 00235 /** 00236 * @} 00237 */ 00238 00239 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode 00240 * @{ 00241 */ 00242 #define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000) 00243 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH 00244 /** 00245 * @} 00246 */ 00247 00248 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode 00249 * @{ 00250 */ 00251 #define SMBUS_PEC_DISABLE ((uint32_t)0x00000000) 00252 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN 00253 /** 00254 * @} 00255 */ 00256 00257 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode 00258 * @{ 00259 */ 00260 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN) 00261 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000) 00262 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN) 00263 /** 00264 * @} 00265 */ 00266 00267 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition 00268 * @{ 00269 */ 00270 00271 #define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000) 00272 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD 00273 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND 00274 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE 00275 /** 00276 * @} 00277 */ 00278 00279 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition 00280 * @{ 00281 */ 00282 00283 #define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000) 00284 #define SMBUS_GENERATE_STOP I2C_CR2_STOP 00285 #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) 00286 #define SMBUS_GENERATE_START_WRITE I2C_CR2_START 00287 /** 00288 * @} 00289 */ 00290 00291 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition 00292 * @{ 00293 */ 00294 00295 #define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE)) 00296 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) 00297 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 00298 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 00299 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 00300 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 00301 /** 00302 * @} 00303 */ 00304 00305 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition 00306 * @brief SMBUS Interrupt definition 00307 * Elements values convention: 0xXXXXXXXX 00308 * - XXXXXXXX : Interrupt control mask 00309 * @{ 00310 */ 00311 #define SMBUS_IT_ERRI I2C_CR1_ERRIE 00312 #define SMBUS_IT_TCI I2C_CR1_TCIE 00313 #define SMBUS_IT_STOPI I2C_CR1_STOPIE 00314 #define SMBUS_IT_NACKI I2C_CR1_NACKIE 00315 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE 00316 #define SMBUS_IT_RXI I2C_CR1_RXIE 00317 #define SMBUS_IT_TXI I2C_CR1_TXIE 00318 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) 00319 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) 00320 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) 00321 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) 00322 /** 00323 * @} 00324 */ 00325 00326 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition 00327 * @brief Flag definition 00328 * Elements values convention: 0xXXXXYYYY 00329 * - XXXXXXXX : Flag mask 00330 * @{ 00331 */ 00332 00333 #define SMBUS_FLAG_TXE I2C_ISR_TXE 00334 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS 00335 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE 00336 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR 00337 #define SMBUS_FLAG_AF I2C_ISR_NACKF 00338 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF 00339 #define SMBUS_FLAG_TC I2C_ISR_TC 00340 #define SMBUS_FLAG_TCR I2C_ISR_TCR 00341 #define SMBUS_FLAG_BERR I2C_ISR_BERR 00342 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO 00343 #define SMBUS_FLAG_OVR I2C_ISR_OVR 00344 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR 00345 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT 00346 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT 00347 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY 00348 #define SMBUS_FLAG_DIR I2C_ISR_DIR 00349 /** 00350 * @} 00351 */ 00352 00353 /** 00354 * @} 00355 */ 00356 00357 /* Exported macros ------------------------------------------------------------*/ 00358 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros 00359 * @{ 00360 */ 00361 00362 /** @brief Reset SMBUS handle state. 00363 * @param __HANDLE__: specifies the SMBUS Handle. 00364 * @retval None 00365 */ 00366 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) 00367 00368 /** @brief Enable the specified SMBUS interrupts. 00369 * @param __HANDLE__: specifies the SMBUS Handle. 00370 * @param __INTERRUPT__: specifies the interrupt source to enable. 00371 * This parameter can be one of the following values: 00372 * @arg SMBUS_IT_ERRI: Errors interrupt enable 00373 * @arg SMBUS_IT_TCI: Transfer complete interrupt enable 00374 * @arg SMBUS_IT_STOPI: STOP detection interrupt enable 00375 * @arg SMBUS_IT_NACKI: NACK received interrupt enable 00376 * @arg SMBUS_IT_ADDRI: Address match interrupt enable 00377 * @arg SMBUS_IT_RXI: RX interrupt enable 00378 * @arg SMBUS_IT_TXI: TX interrupt enable 00379 * 00380 * @retval None 00381 */ 00382 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 00383 00384 /** @brief Disable the specified SMBUS interrupts. 00385 * @param __HANDLE__: specifies the SMBUS Handle. 00386 * @param __INTERRUPT__: specifies the interrupt source to disable. 00387 * This parameter can be one of the following values: 00388 * @arg SMBUS_IT_ERRI: Errors interrupt enable 00389 * @arg SMBUS_IT_TCI: Transfer complete interrupt enable 00390 * @arg SMBUS_IT_STOPI: STOP detection interrupt enable 00391 * @arg SMBUS_IT_NACKI: NACK received interrupt enable 00392 * @arg SMBUS_IT_ADDRI: Address match interrupt enable 00393 * @arg SMBUS_IT_RXI: RX interrupt enable 00394 * @arg SMBUS_IT_TXI: TX interrupt enable 00395 * 00396 * @retval None 00397 */ 00398 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 00399 00400 /** @brief Check whether the specified SMBUS interrupt source is enabled or not. 00401 * @param __HANDLE__: specifies the SMBUS Handle. 00402 * @param __INTERRUPT__: specifies the SMBUS interrupt source to check. 00403 * This parameter can be one of the following values: 00404 * @arg SMBUS_IT_ERRI: Errors interrupt enable 00405 * @arg SMBUS_IT_TCI: Transfer complete interrupt enable 00406 * @arg SMBUS_IT_STOPI: STOP detection interrupt enable 00407 * @arg SMBUS_IT_NACKI: NACK received interrupt enable 00408 * @arg SMBUS_IT_ADDRI: Address match interrupt enable 00409 * @arg SMBUS_IT_RXI: RX interrupt enable 00410 * @arg SMBUS_IT_TXI: TX interrupt enable 00411 * 00412 * @retval The new state of __IT__ (TRUE or FALSE). 00413 */ 00414 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00415 00416 /** @brief Check whether the specified SMBUS flag is set or not. 00417 * @param __HANDLE__: specifies the SMBUS Handle. 00418 * @param __FLAG__: specifies the flag to check. 00419 * This parameter can be one of the following values: 00420 * @arg SMBUS_FLAG_TXE: Transmit data register empty 00421 * @arg SMBUS_FLAG_TXIS: Transmit interrupt status 00422 * @arg SMBUS_FLAG_RXNE: Receive data register not empty 00423 * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) 00424 * @arg SMBUS_FLAG_AF: NACK received flag 00425 * @arg SMBUS_FLAG_STOPF: STOP detection flag 00426 * @arg SMBUS_FLAG_TC: Transfer complete (master mode) 00427 * @arg SMBUS_FLAG_TCR: Transfer complete reload 00428 * @arg SMBUS_FLAG_BERR: Bus error 00429 * @arg SMBUS_FLAG_ARLO: Arbitration lost 00430 * @arg SMBUS_FLAG_OVR: Overrun/Underrun 00431 * @arg SMBUS_FLAG_PECERR: PEC error in reception 00432 * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag 00433 * @arg SMBUS_FLAG_ALERT: SMBus alert 00434 * @arg SMBUS_FLAG_BUSY: Bus busy 00435 * @arg SMBUS_FLAG_DIR: Transfer direction (slave mode) 00436 * 00437 * @retval The new state of __FLAG__ (TRUE or FALSE). 00438 */ 00439 #define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF) 00440 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) 00441 00442 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. 00443 * @param __HANDLE__: specifies the SMBUS Handle. 00444 * @param __FLAG__: specifies the flag to clear. 00445 * This parameter can be any combination of the following values: 00446 * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) 00447 * @arg SMBUS_FLAG_AF: NACK received flag 00448 * @arg SMBUS_FLAG_STOPF: STOP detection flag 00449 * @arg SMBUS_FLAG_BERR: Bus error 00450 * @arg SMBUS_FLAG_ARLO: Arbitration lost 00451 * @arg SMBUS_FLAG_OVR: Overrun/Underrun 00452 * @arg SMBUS_FLAG_PECERR: PEC error in reception 00453 * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag 00454 * @arg SMBUS_FLAG_ALERT: SMBus alert 00455 * 00456 * @retval None 00457 */ 00458 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 00459 00460 /** @brief Enable the specified SMBUS peripheral. 00461 * @param __HANDLE__: specifies the SMBUS Handle. 00462 * @retval None 00463 */ 00464 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 00465 00466 /** @brief Disable the specified SMBUS peripheral. 00467 * @param __HANDLE__: specifies the SMBUS Handle. 00468 * @retval None 00469 */ 00470 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 00471 00472 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. 00473 * @param __HANDLE__: specifies the SMBUS Handle. 00474 * @retval None 00475 */ 00476 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) 00477 00478 /** 00479 * @} 00480 */ 00481 00482 00483 /* Private constants ---------------------------------------------------------*/ 00484 00485 /* Private macros ------------------------------------------------------------*/ 00486 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros 00487 * @{ 00488 */ 00489 00490 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ 00491 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) 00492 00493 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ 00494 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) 00495 00496 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ 00497 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) 00498 00499 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ 00500 ((MASK) == SMBUS_OA2_MASK01) || \ 00501 ((MASK) == SMBUS_OA2_MASK02) || \ 00502 ((MASK) == SMBUS_OA2_MASK03) || \ 00503 ((MASK) == SMBUS_OA2_MASK04) || \ 00504 ((MASK) == SMBUS_OA2_MASK05) || \ 00505 ((MASK) == SMBUS_OA2_MASK06) || \ 00506 ((MASK) == SMBUS_OA2_MASK07)) 00507 00508 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ 00509 ((CALL) == SMBUS_GENERALCALL_ENABLE)) 00510 00511 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ 00512 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) 00513 00514 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ 00515 ((PEC) == SMBUS_PEC_ENABLE)) 00516 00517 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ 00518 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ 00519 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) 00520 00521 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ 00522 ((MODE) == SMBUS_AUTOEND_MODE) || \ 00523 ((MODE) == SMBUS_SOFTEND_MODE) || \ 00524 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ 00525 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ 00526 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ 00527 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) 00528 00529 00530 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ 00531 ((REQUEST) == SMBUS_GENERATE_START_READ) || \ 00532 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ 00533 ((REQUEST) == SMBUS_NO_STARTSTOP)) 00534 00535 00536 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ 00537 ((REQUEST) == SMBUS_NEXT_FRAME) || \ 00538 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 00539 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ 00540 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 00541 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) 00542 00543 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) 00544 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) 00545 00546 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ 00547 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) 00548 00549 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) 00550 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) 00551 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) 00552 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) 00553 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) 00554 00555 #define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR) 00556 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) 00557 00558 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) 00559 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) 00560 00561 /** 00562 * @} 00563 */ 00564 00565 /* Private Functions ---------------------------------------------------------*/ 00566 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions 00567 * @{ 00568 */ 00569 /* Private functions are defined in stm32l4xx_hal_smbus.c file */ 00570 /** 00571 * @} 00572 */ 00573 00574 /* Exported functions --------------------------------------------------------*/ 00575 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions 00576 * @{ 00577 */ 00578 00579 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 00580 * @{ 00581 */ 00582 00583 /* Initialization and de-initialization functions **********************************/ 00584 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); 00585 HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); 00586 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); 00587 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); 00588 00589 /** 00590 * @} 00591 */ 00592 00593 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions 00594 * @{ 00595 */ 00596 00597 /* IO operation functions *****************************************************/ 00598 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 00599 * @{ 00600 */ 00601 /******* Blocking mode: Polling */ 00602 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); 00603 /** 00604 * @} 00605 */ 00606 00607 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 00608 * @{ 00609 */ 00610 /******* Non-Blocking mode: Interrupt */ 00611 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00612 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00613 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); 00614 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00615 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00616 00617 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 00618 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 00619 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); 00620 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); 00621 /** 00622 * @} 00623 */ 00624 00625 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 00626 * @{ 00627 */ 00628 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 00629 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 00630 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 00631 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00632 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00633 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00634 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00635 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 00636 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00637 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); 00638 00639 /** 00640 * @} 00641 */ 00642 00643 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 00644 * @{ 00645 */ 00646 00647 /* Peripheral State and Errors functions **************************************************/ 00648 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); 00649 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); 00650 00651 /** 00652 * @} 00653 */ 00654 00655 /** 00656 * @} 00657 */ 00658 00659 00660 00661 /** 00662 * @} 00663 */ 00664 00665 /** 00666 * @} 00667 */ 00668 00669 /** 00670 * @} 00671 */ 00672 #ifdef __cplusplus 00673 } 00674 #endif 00675 00676 00677 #endif /* __STM32L4xx_HAL_SMBUS_H */ 00678 00679 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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