stm32l4xx_hal_rcc_ex.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of RCC HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_RCC_EX_H
00040 #define __STM32L4xx_HAL_RCC_EX_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048 
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052 
00053 /** @addtogroup RCCEx
00054   * @{
00055   */
00056 
00057 /* Exported types ------------------------------------------------------------*/ 
00058 
00059 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00060   * @{
00061   */
00062 
00063 /**
00064   * @brief  PLLSAI1 Clock structure definition
00065   */
00066 typedef struct
00067 {
00068 
00069   uint32_t PLLSAI1Source;    /*!< PLLSAI1Source: PLLSAI1 entry clock source.
00070                                   This parameter must be a value of @ref RCC_PLL_Clock_Source */
00071 
00072   uint32_t PLLSAI1M;         /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
00073                                   This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
00074 
00075   uint32_t PLLSAI1N;         /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
00076                                   This parameter must be a number between 8 and 86 or 127 depending on devices. */
00077 
00078   uint32_t PLLSAI1P;         /*!< PLLSAI1P: specifies the division factor for SAI clock.
00079                                   This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
00080 
00081   uint32_t PLLSAI1Q;         /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
00082                                   This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
00083 
00084   uint32_t PLLSAI1R;         /*!< PLLSAI1R: specifies the division factor for ADC clock.
00085                                   This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
00086 
00087   uint32_t PLLSAI1ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
00088                                   This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
00089 }RCC_PLLSAI1InitTypeDef;
00090 
00091 #if defined(RCC_PLLSAI2_SUPPORT)
00092 
00093 /**
00094   * @brief  PLLSAI2 Clock structure definition
00095   */
00096 typedef struct
00097 {
00098 
00099   uint32_t PLLSAI2Source;    /*!< PLLSAI2Source: PLLSAI2 entry clock source.
00100                                   This parameter must be a value of @ref RCC_PLL_Clock_Source */
00101 
00102   uint32_t PLLSAI2M;         /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
00103                                   This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
00104 
00105   uint32_t PLLSAI2N;         /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
00106                                   This parameter must be a number between 8 and 86 or 127 depending on devices. */
00107 
00108   uint32_t PLLSAI2P;         /*!< PLLSAI2P: specifies the division factor for SAI clock.
00109                                   This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
00110 
00111   uint32_t PLLSAI2R;         /*!< PLLSAI2R: specifies the division factor for ADC clock.
00112                                   This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
00113 
00114   uint32_t PLLSAI2ClockOut;  /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
00115                                   This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
00116 }RCC_PLLSAI2InitTypeDef;
00117 
00118 #endif /* RCC_PLLSAI2_SUPPORT */
00119 
00120 /**
00121   * @brief  RCC extended clocks structure definition
00122   */
00123 typedef struct
00124 {
00125   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
00126                                         This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00127 
00128   RCC_PLLSAI1InitTypeDef PLLSAI1;  /*!< PLLSAI1 structure parameters.
00129                                         This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
00130 
00131 #if defined(RCC_PLLSAI2_SUPPORT)
00132 
00133   RCC_PLLSAI2InitTypeDef PLLSAI2;  /*!< PLLSAI2 structure parameters.
00134                                         This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
00135 
00136 #endif /* RCC_PLLSAI2_SUPPORT */
00137 
00138   uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.
00139                                         This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00140 
00141   uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.
00142                                         This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
00143 
00144 #if defined(USART3)
00145 
00146   uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source.
00147                                         This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
00148 
00149 #endif /* USART3 */
00150 
00151 #if defined(UART4)
00152 
00153   uint32_t Uart4ClockSelection;    /*!< Specifies UART4 clock source.
00154                                         This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
00155 
00156 #endif /* UART4 */
00157 
00158 #if defined(UART5)
00159 
00160   uint32_t Uart5ClockSelection;    /*!< Specifies UART5 clock source.
00161                                         This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
00162 
00163 #endif /* UART5 */
00164 
00165   uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.
00166                                         This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
00167 
00168   uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.
00169                                         This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
00170 
00171 #if defined(I2C2)
00172 
00173   uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source.
00174                                         This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
00175 
00176 #endif /* I2C2 */
00177 
00178   uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.
00179                                         This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
00180 
00181   uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.
00182                                         This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
00183 
00184   uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source.
00185                                         This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
00186 
00187   uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source.
00188                                         This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
00189 
00190 #if defined(SAI2)
00191 
00192   uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 clock source.
00193                                         This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
00194 
00195 #endif /* SAI2 */
00196 
00197 #if defined(USB_OTG_FS) || defined(USB)
00198 
00199   uint32_t UsbClockSelection;      /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
00200                                         This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00201 
00202 #endif /* USB_OTG_FS || USB */
00203 
00204 #if defined(SDMMC1)
00205 
00206   uint32_t Sdmmc1ClockSelection;   /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
00207                                         This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
00208 
00209 #endif /* SDMMC1 */
00210 
00211   uint32_t RngClockSelection;      /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
00212                                         This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
00213 
00214   uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source.
00215                                         This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
00216 
00217 #if defined(SWPMI1)
00218 
00219   uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 clock source.
00220                                         This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
00221 
00222 #endif /* SWPMI1 */
00223 
00224 #if defined(DFSDM1_Filter0)
00225 
00226   uint32_t Dfsdm1ClockSelection;   /*!< Specifies DFSDM1 clock source.
00227                                         This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
00228 
00229 #endif /* DFSDM1_Filter0 */
00230 
00231   uint32_t RTCClockSelection;      /*!< Specifies RTC clock source.
00232                                         This parameter can be a value of @ref RCC_RTC_Clock_Source */
00233 }RCC_PeriphCLKInitTypeDef;
00234 
00235 #if defined(CRS)
00236 
00237 /** 
00238   * @brief RCC_CRS Init structure definition  
00239   */
00240 typedef struct
00241 {
00242   uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
00243                                      This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
00244 
00245   uint32_t Source;                /*!< Specifies the SYNC signal source.
00246                                      This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
00247 
00248   uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
00249                                      This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
00250 
00251   uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
00252                                       It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
00253                                      This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
00254 
00255   uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
00256                                      This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
00257 
00258   uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
00259                                      This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
00260 
00261 }RCC_CRSInitTypeDef;
00262 
00263 /** 
00264   * @brief RCC_CRS Synchronization structure definition  
00265   */
00266 typedef struct
00267 {
00268   uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
00269                                      This parameter must be a number between 0 and 0xFFFF */
00270 
00271   uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
00272                                      This parameter must be a number between 0 and 0x3F */
00273 
00274   uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter 
00275                                                                     value latched in the time of the last SYNC event.
00276                                     This parameter must be a number between 0 and 0xFFFF */
00277 
00278   uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 
00279                                                                     frequency error counter latched in the time of the last SYNC event. 
00280                                                                     It shows whether the actual frequency is below or above the target.
00281                                     This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
00282 
00283 }RCC_CRSSynchroInfoTypeDef;
00284 
00285 #endif /* CRS */
00286 /**
00287   * @}
00288   */
00289 
00290 /* Exported constants --------------------------------------------------------*/
00291 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
00292   * @{
00293   */
00294 
00295 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
00296   * @{
00297   */
00298 #define RCC_LSCOSOURCE_LSI             (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */
00299 #define RCC_LSCOSOURCE_LSE             RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock output */
00300 /**
00301   * @}
00302   */
00303 
00304 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
00305   * @{
00306   */
00307 #define RCC_PERIPHCLK_USART1           ((uint32_t)0x00000001U)
00308 #define RCC_PERIPHCLK_USART2           ((uint32_t)0x00000002U)
00309 #if defined(USART3)
00310 #define RCC_PERIPHCLK_USART3           ((uint32_t)0x00000004U)
00311 #endif
00312 #if defined(UART4)
00313 #define RCC_PERIPHCLK_UART4            ((uint32_t)0x00000008U)
00314 #endif
00315 #if defined(UART5)
00316 #define RCC_PERIPHCLK_UART5            ((uint32_t)0x00000010U)
00317 #endif
00318 #define RCC_PERIPHCLK_LPUART1          ((uint32_t)0x00000020U)
00319 #define RCC_PERIPHCLK_I2C1             ((uint32_t)0x00000040U)
00320 #if defined(I2C2)
00321 #define RCC_PERIPHCLK_I2C2             ((uint32_t)0x00000080U)
00322 #endif
00323 #define RCC_PERIPHCLK_I2C3             ((uint32_t)0x00000100U)
00324 #define RCC_PERIPHCLK_LPTIM1           ((uint32_t)0x00000200U)
00325 #define RCC_PERIPHCLK_LPTIM2           ((uint32_t)0x00000400U)
00326 #define RCC_PERIPHCLK_SAI1             ((uint32_t)0x00000800U)
00327 #if defined(SAI2)
00328 #define RCC_PERIPHCLK_SAI2             ((uint32_t)0x00001000U)
00329 #endif
00330 #if defined(USB_OTG_FS) || defined(USB)
00331 #define RCC_PERIPHCLK_USB              ((uint32_t)0x00002000U)
00332 #endif
00333 #define RCC_PERIPHCLK_ADC              ((uint32_t)0x00004000U)
00334 #define RCC_PERIPHCLK_SWPMI1           ((uint32_t)0x00008000U)
00335 #if defined(DFSDM1_Filter0)
00336 #define RCC_PERIPHCLK_DFSDM1           ((uint32_t)0x00010000U)
00337 #endif
00338 #define RCC_PERIPHCLK_RTC              ((uint32_t)0x00020000U)
00339 #define RCC_PERIPHCLK_RNG              ((uint32_t)0x00040000U)
00340 #if defined(SDMMC1)
00341 #define RCC_PERIPHCLK_SDMMC1           ((uint32_t)0x00080000U)
00342 #endif
00343 /**
00344   * @}
00345   */
00346 
00347 
00348 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
00349   * @{
00350   */
00351 #define RCC_USART1CLKSOURCE_PCLK2      ((uint32_t)0x00000000U)
00352 #define RCC_USART1CLKSOURCE_SYSCLK     RCC_CCIPR_USART1SEL_0
00353 #define RCC_USART1CLKSOURCE_HSI        RCC_CCIPR_USART1SEL_1
00354 #define RCC_USART1CLKSOURCE_LSE        (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
00355 /**
00356   * @}
00357   */
00358 
00359 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
00360   * @{
00361   */
00362 #define RCC_USART2CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
00363 #define RCC_USART2CLKSOURCE_SYSCLK     RCC_CCIPR_USART2SEL_0
00364 #define RCC_USART2CLKSOURCE_HSI        RCC_CCIPR_USART2SEL_1
00365 #define RCC_USART2CLKSOURCE_LSE        (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
00366 /**
00367   * @}
00368   */
00369 
00370 #if defined(USART3)
00371 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
00372   * @{
00373   */
00374 #define RCC_USART3CLKSOURCE_PCLK1      ((uint32_t)0x00000000U)
00375 #define RCC_USART3CLKSOURCE_SYSCLK     RCC_CCIPR_USART3SEL_0
00376 #define RCC_USART3CLKSOURCE_HSI        RCC_CCIPR_USART3SEL_1
00377 #define RCC_USART3CLKSOURCE_LSE        (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
00378 /**
00379   * @}
00380   */
00381 #endif /* USART3 */
00382 
00383 #if defined(UART4)
00384 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
00385   * @{
00386   */
00387 #define RCC_UART4CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
00388 #define RCC_UART4CLKSOURCE_SYSCLK      RCC_CCIPR_UART4SEL_0
00389 #define RCC_UART4CLKSOURCE_HSI         RCC_CCIPR_UART4SEL_1
00390 #define RCC_UART4CLKSOURCE_LSE         (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
00391 /**
00392   * @}
00393   */
00394 #endif /* UART4 */
00395 
00396 #if defined(UART5)
00397 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
00398   * @{
00399   */
00400 #define RCC_UART5CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)
00401 #define RCC_UART5CLKSOURCE_SYSCLK      RCC_CCIPR_UART5SEL_0
00402 #define RCC_UART5CLKSOURCE_HSI         RCC_CCIPR_UART5SEL_1
00403 #define RCC_UART5CLKSOURCE_LSE         (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
00404 /**
00405   * @}
00406   */
00407 #endif /* UART5 */
00408 
00409 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
00410   * @{
00411   */
00412 #define RCC_LPUART1CLKSOURCE_PCLK1     ((uint32_t)0x00000000U)
00413 #define RCC_LPUART1CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0
00414 #define RCC_LPUART1CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1
00415 #define RCC_LPUART1CLKSOURCE_LSE       (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
00416 /**
00417   * @}
00418   */
00419 
00420 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
00421   * @{
00422   */
00423 #define RCC_I2C1CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
00424 #define RCC_I2C1CLKSOURCE_SYSCLK       RCC_CCIPR_I2C1SEL_0
00425 #define RCC_I2C1CLKSOURCE_HSI          RCC_CCIPR_I2C1SEL_1
00426 /**
00427   * @}
00428   */
00429 
00430 #if defined(I2C2)
00431 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
00432   * @{
00433   */
00434 #define RCC_I2C2CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
00435 #define RCC_I2C2CLKSOURCE_SYSCLK       RCC_CCIPR_I2C2SEL_0
00436 #define RCC_I2C2CLKSOURCE_HSI          RCC_CCIPR_I2C2SEL_1
00437 /**
00438   * @}
00439   */
00440 #endif /* I2C2 */
00441 
00442 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
00443   * @{
00444   */
00445 #define RCC_I2C3CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)
00446 #define RCC_I2C3CLKSOURCE_SYSCLK       RCC_CCIPR_I2C3SEL_0
00447 #define RCC_I2C3CLKSOURCE_HSI          RCC_CCIPR_I2C3SEL_1
00448 /**
00449   * @}
00450   */
00451 
00452 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
00453   * @{
00454   */
00455 #define RCC_SAI1CLKSOURCE_PLLSAI1      ((uint32_t)0x00000000U)
00456 #if defined(RCC_PLLSAI2_SUPPORT)
00457 #define RCC_SAI1CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI1SEL_0
00458 #endif /* RCC_PLLSAI2_SUPPORT */
00459 #define RCC_SAI1CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_1
00460 #define RCC_SAI1CLKSOURCE_PIN          RCC_CCIPR_SAI1SEL
00461 /**
00462   * @}
00463   */
00464 
00465 #if defined(SAI2)
00466 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
00467   * @{
00468   */
00469 #define RCC_SAI2CLKSOURCE_PLLSAI1      ((uint32_t)0x00000000U)
00470 #define RCC_SAI2CLKSOURCE_PLLSAI2      RCC_CCIPR_SAI2SEL_0
00471 #define RCC_SAI2CLKSOURCE_PLL          RCC_CCIPR_SAI2SEL_1
00472 #define RCC_SAI2CLKSOURCE_PIN          RCC_CCIPR_SAI2SEL
00473 /**
00474   * @}
00475   */
00476 #endif /* SAI2 */
00477 
00478 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
00479   * @{
00480   */
00481 #define RCC_LPTIM1CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
00482 #define RCC_LPTIM1CLKSOURCE_LSI        RCC_CCIPR_LPTIM1SEL_0
00483 #define RCC_LPTIM1CLKSOURCE_HSI        RCC_CCIPR_LPTIM1SEL_1
00484 #define RCC_LPTIM1CLKSOURCE_LSE        RCC_CCIPR_LPTIM1SEL
00485 /**
00486   * @}
00487   */
00488 
00489 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
00490   * @{
00491   */
00492 #define RCC_LPTIM2CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
00493 #define RCC_LPTIM2CLKSOURCE_LSI        RCC_CCIPR_LPTIM2SEL_0
00494 #define RCC_LPTIM2CLKSOURCE_HSI        RCC_CCIPR_LPTIM2SEL_1
00495 #define RCC_LPTIM2CLKSOURCE_LSE        RCC_CCIPR_LPTIM2SEL
00496 /**
00497   * @}
00498   */
00499 
00500 #if defined(SDMMC1)
00501 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
00502   * @{
00503   */
00504 #if defined(RCC_HSI48_SUPPORT)
00505 #define RCC_SDMMC1CLKSOURCE_HSI48      ((uint32_t)0x00000000U)
00506 #else
00507 #define RCC_SDMMC1CLKSOURCE_NONE       ((uint32_t)0x00000000U)
00508 #endif /* RCC_HSI48_SUPPORT */
00509 #define RCC_SDMMC1CLKSOURCE_PLLSAI1    RCC_CCIPR_CLK48SEL_0
00510 #define RCC_SDMMC1CLKSOURCE_PLL        RCC_CCIPR_CLK48SEL_1
00511 #define RCC_SDMMC1CLKSOURCE_MSI        RCC_CCIPR_CLK48SEL
00512 /**
00513   * @}
00514   */
00515 #endif /* SDMMC1 */
00516 
00517 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
00518   * @{
00519   */
00520 #if defined(RCC_HSI48_SUPPORT)
00521 #define RCC_RNGCLKSOURCE_HSI48         ((uint32_t)0x00000000U)
00522 #else
00523 #define RCC_RNGCLKSOURCE_NONE          ((uint32_t)0x00000000U)
00524 #endif /* RCC_HSI48_SUPPORT */
00525 #define RCC_RNGCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0
00526 #define RCC_RNGCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
00527 #define RCC_RNGCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL
00528 /**
00529   * @}
00530   */
00531 
00532 #if defined(USB_OTG_FS) || defined(USB)
00533 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
00534   * @{
00535   */
00536 #if defined(RCC_HSI48_SUPPORT)
00537 #define RCC_USBCLKSOURCE_HSI48         ((uint32_t)0x00000000U)
00538 #else
00539 #define RCC_USBCLKSOURCE_NONE          ((uint32_t)0x00000000U)
00540 #endif /* RCC_HSI48_SUPPORT */
00541 #define RCC_USBCLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0
00542 #define RCC_USBCLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1
00543 #define RCC_USBCLKSOURCE_MSI           RCC_CCIPR_CLK48SEL
00544 /**
00545   * @}
00546   */
00547 #endif /* USB_OTG_FS || USB */
00548 
00549 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
00550   * @{
00551   */
00552 #define RCC_ADCCLKSOURCE_NONE        ((uint32_t)0x00000000U)
00553 #define RCC_ADCCLKSOURCE_PLLSAI1      RCC_CCIPR_ADCSEL_0
00554 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00555 #define RCC_ADCCLKSOURCE_PLLSAI2      RCC_CCIPR_ADCSEL_1
00556 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00557 #define RCC_ADCCLKSOURCE_SYSCLK       RCC_CCIPR_ADCSEL
00558 /**
00559   * @}
00560   */
00561 
00562 #if defined(SWPMI1)
00563 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
00564   * @{
00565   */
00566 #define RCC_SWPMI1CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
00567 #define RCC_SWPMI1CLKSOURCE_HSI        RCC_CCIPR_SWPMI1SEL
00568 /**
00569   * @}
00570   */
00571 #endif /* SWPMI1 */
00572 
00573 #if defined(DFSDM1_Filter0)
00574 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
00575   * @{
00576   */
00577 #define RCC_DFSDM1CLKSOURCE_PCLK       ((uint32_t)0x00000000U)
00578 #define RCC_DFSDM1CLKSOURCE_SYSCLK     RCC_CCIPR_DFSDM1SEL
00579 /**
00580   * @}
00581   */
00582 #endif /* DFSDM1_Filter0 */
00583 
00584 /** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
00585   * @{
00586   */
00587 #define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM19        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
00588 /**
00589   * @}
00590   */
00591 
00592 #if defined(CRS)
00593 
00594 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
00595   * @{
00596   */
00597 #define RCC_CRS_NONE                   ((uint32_t)0x00000000U)
00598 #define RCC_CRS_TIMEOUT                ((uint32_t)0x00000001U)
00599 #define RCC_CRS_SYNCOK                 ((uint32_t)0x00000002U)
00600 #define RCC_CRS_SYNCWARN               ((uint32_t)0x00000004U)
00601 #define RCC_CRS_SYNCERR                ((uint32_t)0x00000008U)
00602 #define RCC_CRS_SYNCMISS               ((uint32_t)0x00000010U)
00603 #define RCC_CRS_TRIMOVF                ((uint32_t)0x00000020U)
00604 /**
00605   * @}
00606   */
00607 
00608 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
00609   * @{
00610   */
00611 #define RCC_CRS_SYNC_SOURCE_GPIO       ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
00612 #define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
00613 #define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
00614 /**
00615   * @}
00616   */
00617 
00618 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
00619   * @{
00620   */
00621 #define RCC_CRS_SYNC_DIV1        ((uint32_t)0x00000000U)                   /*!< Synchro Signal not divided (default) */
00622 #define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
00623 #define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
00624 #define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
00625 #define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
00626 #define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
00627 #define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
00628 #define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
00629 /**
00630   * @}
00631   */
00632 
00633 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
00634   * @{
00635   */
00636 #define RCC_CRS_SYNC_POLARITY_RISING   ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
00637 #define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
00638 /**
00639   * @}
00640   */
00641 
00642 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
00643   * @{
00644   */
00645 #define RCC_CRS_RELOADVALUE_DEFAULT    ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 
00646                                                                     to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
00647 /**
00648   * @}
00649   */
00650   
00651 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
00652   * @{
00653   */
00654 #define RCC_CRS_ERRORLIMIT_DEFAULT     ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
00655 /**
00656   * @}
00657   */
00658 
00659 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
00660   * @{
00661   */
00662 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 
00663                                                                       The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
00664                                                                       corresponds to a higher output frequency */  
00665 /**
00666   * @}
00667   */
00668 
00669 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
00670   * @{
00671   */
00672 #define RCC_CRS_FREQERRORDIR_UP        ((uint32_t)0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
00673 #define RCC_CRS_FREQERRORDIR_DOWN      ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
00674 /**
00675   * @}
00676   */
00677 
00678 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
00679   * @{
00680   */
00681 #define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
00682 #define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
00683 #define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
00684 #define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
00685 #define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
00686 #define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
00687 #define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE           /*!< Trimming overflow or underflow */
00688 
00689 /**
00690   * @}
00691   */
00692   
00693 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
00694   * @{
00695   */
00696 #define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
00697 #define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
00698 #define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
00699 #define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
00700 #define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
00701 #define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
00702 #define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
00703 
00704 /**
00705   * @}
00706   */
00707 
00708 #endif /* CRS */
00709 
00710 /**
00711   * @}
00712   */
00713 
00714 /* Exported macros -----------------------------------------------------------*/
00715 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
00716  * @{
00717  */
00718 
00719 
00720 /**
00721   * @brief  Macro to configure the PLLSAI1 clock multiplication and division factors.
00722   *
00723   * @note   This function must be used only when the PLLSAI1 is disabled.
00724   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00725   *         __HAL_RCC_PLL_CONFIG() macro)
00726   *
00727   * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
00728   *         This parameter must be a number between 8 and 86.
00729   * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO
00730   *         output frequency is between 64 and 344 MHz.
00731   *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
00732   *
00733   * @param  __PLLSAI1P__ specifies the division factor for SAI clock.
00734   *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
00735   *         else (2 to 31).
00736   *         SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
00737   *
00738   * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
00739   *         This parameter must be in the range (2, 4, 6 or 8).
00740   *         USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
00741   *
00742   * @param  __PLLSAI1R__ specifies the division factor for SAR ADC clock.
00743   *         This parameter must be in the range (2, 4, 6 or 8).
00744   *         ADC clock frequency = f(PLLSAI1) / PLLSAI1R
00745   *
00746   * @retval None
00747   */
00748 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
00749 
00750 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
00751                   WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
00752                    ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
00753                    ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \
00754                    ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)))
00755 
00756 #else
00757 
00758 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
00759                   WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
00760                    (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
00761                    ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
00762                    ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
00763                     
00764 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
00765 
00766 /**
00767   * @brief  Macro to configure the PLLSAI1 clock multiplication factor N.
00768   *
00769   * @note   This function must be used only when the PLLSAI1 is disabled.
00770   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00771   *         __HAL_RCC_PLL_CONFIG() macro)
00772   *
00773   * @param  __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
00774   *          This parameter must be a number between 8 and 86.
00775   * @note   You have to set the PLLSAI1N parameter correctly to ensure that the VCO
00776   *         output frequency is between 64 and 344 MHz.
00777   *         Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
00778   *
00779   * @retval None
00780   */
00781 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
00782                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
00783 
00784 /** @brief  Macro to configure the PLLSAI1 clock division factor P.
00785   *
00786   * @note   This function must be used only when the PLLSAI1 is disabled.
00787   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00788   *         __HAL_RCC_PLL_CONFIG() macro)
00789   *
00790   * @param  __PLLSAI1P__ specifies the division factor for SAI clock.
00791   *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
00792   *         else (2 to 31).
00793   *         Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
00794   *
00795   * @retval None
00796   */
00797 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
00798 
00799 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
00800                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))
00801                     
00802 #else
00803 
00804 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
00805                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
00806 
00807 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
00808 
00809 /** @brief  Macro to configure the PLLSAI1 clock division factor Q.
00810   *
00811   * @note   This function must be used only when the PLLSAI1 is disabled.
00812   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00813   *         __HAL_RCC_PLL_CONFIG() macro)
00814   *
00815   * @param  __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
00816   *         This parameter must be in the range (2, 4, 6 or 8).
00817   *         Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
00818   *
00819   * @retval None
00820   */
00821 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
00822                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
00823 
00824 /** @brief  Macro to configure the PLLSAI1 clock division factor R.
00825   *
00826   * @note   This function must be used only when the PLLSAI1 is disabled.
00827   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00828   *         __HAL_RCC_PLL_CONFIG() macro)
00829   *
00830   * @param  __PLLSAI1R__ specifies the division factor for ADC clock.
00831   *         This parameter must be in the range (2, 4, 6 or 8)
00832   *         Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
00833   *
00834   * @retval None
00835   */
00836 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
00837                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
00838 
00839 /**
00840   * @brief  Macros to enable or disable the PLLSAI1.
00841   * @note   The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
00842   * @retval None
00843   */
00844 
00845 #define __HAL_RCC_PLLSAI1_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
00846 
00847 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
00848 
00849 /**
00850   * @brief  Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
00851   * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.
00852   *         This is mainly used to save Power.
00853   * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
00854   *         This parameter can be one or a combination of the following values:
00855   *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve
00856   *                                   high-quality audio performance on SAI interface in case.
00857   *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),
00858   *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
00859   *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.
00860   * @retval None
00861   */
00862 
00863 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__)   SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
00864 
00865 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__)  CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
00866 
00867 /**
00868   * @brief  Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
00869   * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
00870   *         This parameter can be one of the following values:
00871   *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve
00872   *                                   high-quality audio performance on SAI interface in case.
00873   *            @arg @ref RCC_PLLSAI1_48M2CLK  This clock is used to generate the clock for the USB OTG FS (48 MHz),
00874   *                                   the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
00875   *            @arg @ref RCC_PLLSAI1_ADC1CLK  Clock used to clock ADC peripheral.
00876   * @retval SET / RESET
00877   */
00878 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__)  READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
00879 
00880 #if defined(RCC_PLLSAI2_SUPPORT)
00881 
00882 /**
00883   * @brief  Macro to configure the PLLSAI2 clock multiplication and division factors.
00884   *
00885   * @note   This function must be used only when the PLLSAI2 is disabled.
00886   * @note   PLLSAI2 clock source is common with the main PLL (configured through
00887   *         __HAL_RCC_PLL_CONFIG() macro)
00888   *
00889   * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
00890   *          This parameter must be a number between 8 and 86.
00891   * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO
00892   *         output frequency is between 64 and 344 MHz.
00893   *
00894   * @param  __PLLSAI2P__ specifies the division factor for SAI clock.
00895   *         This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
00896   *         else (2 to 31).
00897   *         SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
00898   *
00899   * @param  __PLLSAI2R__ specifies the division factor for SAR ADC clock.
00900   *         This parameter must be in the range (2, 4, 6 or 8).
00901   *
00902   * @retval None
00903   */
00904 
00905 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 
00906 
00907 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
00908                   WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
00909                    ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \
00910                    ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)))
00911 
00912 #else
00913 
00914 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
00915                   WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
00916                     (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
00917                     ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
00918                     
00919 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
00920 
00921 
00922 /**
00923   * @brief  Macro to configure the PLLSAI2 clock multiplication factor N.
00924   *
00925   * @note   This function must be used only when the PLLSAI2 is disabled.
00926   * @note   PLLSAI2 clock source is common with the main PLL (configured through
00927   *         __HAL_RCC_PLL_CONFIG() macro)
00928   *
00929   * @param  __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
00930   *          This parameter must be a number between 8 and 86.
00931   * @note   You have to set the PLLSAI2N parameter correctly to ensure that the VCO
00932   *         output frequency is between 64 and 344 MHz.
00933   *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
00934   *
00935   * @retval None
00936   */
00937 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
00938                   MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
00939 
00940 /** @brief  Macro to configure the PLLSAI2 clock division factor P.
00941   *
00942   * @note   This function must be used only when the PLLSAI2 is disabled.
00943   * @note   PLLSAI2 clock source is common with the main PLL (configured through
00944   *         __HAL_RCC_PLL_CONFIG() macro)
00945   *
00946   * @param  __PLLSAI2P__ specifies the division factor.
00947   *         This parameter must be a number in the range (7 or 17).
00948   *         Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
00949   *
00950   * @retval None
00951   */
00952 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
00953                   MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
00954 
00955 /** @brief  Macro to configure the PLLSAI2 clock division factor R.
00956   *
00957   * @note   This function must be used only when the PLLSAI2 is disabled.
00958   * @note   PLLSAI2 clock source is common with the main PLL (configured through
00959   *         __HAL_RCC_PLL_CONFIG() macro)
00960   *
00961   * @param  __PLLSAI2R__ specifies the division factor.
00962   *         This parameter must be in the range (2, 4, 6 or 8).
00963   *         Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
00964   *
00965   * @retval None
00966   */
00967 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
00968                   MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
00969 
00970 /**
00971   * @brief  Macros to enable or disable the PLLSAI2.
00972   * @note   The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
00973   * @retval None
00974   */
00975 
00976 #define __HAL_RCC_PLLSAI2_ENABLE()  SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
00977 
00978 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
00979 
00980 /**
00981   * @brief  Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
00982   * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.
00983   *         This is mainly used to save Power.
00984   * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
00985   *         This parameter can be one or a combination of the following values:
00986   *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve
00987   *                                   high-quality audio performance on SAI interface in case.
00988   *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.
00989   * @retval None
00990   */
00991 
00992 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__)  SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
00993 
00994 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
00995 
00996 /**
00997   * @brief  Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
00998   * @param  __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
00999   *          This parameter can be one of the following values:
01000   *            @arg @ref RCC_PLLSAI2_SAI2CLK  This clock is used to generate an accurate clock to achieve
01001   *                                   high-quality audio performance on SAI interface in case.
01002   *            @arg @ref RCC_PLLSAI2_ADC2CLK  Clock used to clock ADC peripheral.
01003   * @retval SET / RESET
01004   */
01005 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__)  READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
01006 
01007 #endif /* RCC_PLLSAI2_SUPPORT */
01008 
01009 /**
01010   * @brief  Macro to configure the SAI1 clock source.
01011   * @param  __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
01012   *         from the PLLSAI1, system PLL or external clock (through a dedicated pin).
01013   *          This parameter can be one of the following values:
01014   *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
01015   @if STM32L486xx
01016   *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
01017   @endif
01018   *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
01019   *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)
01020   *
01021   @if STM32L443xx
01022   * @note  HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
01023   @endif
01024   *
01025   * @retval None
01026   */
01027 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
01028                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
01029 
01030 /** @brief  Macro to get the SAI1 clock source.
01031   * @retval The clock source can be one of the following values:
01032   *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1  SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
01033   @if STM32L486xx
01034   *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2  SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
01035   @endif
01036   *             @arg @ref RCC_SAI1CLKSOURCE_PLL  SAI1 clock  = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
01037   *             @arg @ref RCC_SAI1CLKSOURCE_PIN  SAI1 clock = External Clock (SAI1_EXTCLK)
01038   *
01039   * @note  Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 
01040   *        clock source when PLLs are disabled for devices without PLLSAI2.
01041   *
01042   */
01043 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
01044 
01045 #if defined(SAI2)
01046 
01047 /**
01048   * @brief  Macro to configure the SAI2 clock source.
01049   * @param  __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
01050   *         from the PLLSAI2, system PLL or external clock (through a dedicated pin).
01051   *          This parameter can be one of the following values:
01052   *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
01053   *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
01054   *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)
01055   *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)
01056   *
01057   * @retval None
01058   */
01059 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
01060                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
01061 
01062 /** @brief  Macro to get the SAI2 clock source.
01063   * @retval The clock source can be one of the following values:
01064   *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1  SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
01065   *             @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2  SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
01066   *             @arg @ref RCC_SAI2CLKSOURCE_PLL  SAI2 clock  = PLL "P" clock (PLLSAI3CLK)
01067   *             @arg @ref RCC_SAI2CLKSOURCE_PIN  SAI2 clock = External Clock (SAI2_EXTCLK)
01068   */
01069 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
01070 
01071 #endif /* SAI2 */
01072 
01073 /** @brief  Macro to configure the I2C1 clock (I2C1CLK).
01074   *
01075   * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
01076   *          This parameter can be one of the following values:
01077   *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
01078   *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
01079   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
01080   * @retval None
01081   */
01082 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
01083                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
01084 
01085 /** @brief  Macro to get the I2C1 clock source.
01086   * @retval The clock source can be one of the following values:
01087   *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1  PCLK1 selected as I2C1 clock
01088   *            @arg @ref RCC_I2C1CLKSOURCE_HSI  HSI selected as I2C1 clock
01089   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
01090   */
01091 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
01092 
01093 #if defined(I2C2)
01094 
01095 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
01096   *
01097   * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
01098   *          This parameter can be one of the following values:
01099   *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
01100   *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
01101   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
01102   * @retval None
01103   */
01104 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
01105                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
01106 
01107 /** @brief  Macro to get the I2C2 clock source.
01108   * @retval The clock source can be one of the following values:
01109   *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1  PCLK1 selected as I2C2 clock
01110   *            @arg @ref RCC_I2C2CLKSOURCE_HSI  HSI selected as I2C2 clock
01111   *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
01112   */
01113 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
01114 
01115 #endif /* I2C2 */
01116 
01117 /** @brief  Macro to configure the I2C3 clock (I2C3CLK).
01118   *
01119   * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
01120   *          This parameter can be one of the following values:
01121   *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
01122   *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
01123   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
01124   * @retval None
01125   */
01126 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
01127                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
01128 
01129 /** @brief  Macro to get the I2C3 clock source.
01130   * @retval The clock source can be one of the following values:
01131   *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1  PCLK1 selected as I2C3 clock
01132   *            @arg @ref RCC_I2C3CLKSOURCE_HSI  HSI selected as I2C3 clock
01133   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
01134   */
01135 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
01136 
01137 /** @brief  Macro to configure the USART1 clock (USART1CLK).
01138   *
01139   * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
01140   *          This parameter can be one of the following values:
01141   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
01142   *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
01143   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
01144   *            @arg @ref RCC_USART1CLKSOURCE_LSE  SE selected as USART1 clock
01145   * @retval None
01146   */
01147 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
01148                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
01149 
01150 /** @brief  Macro to get the USART1 clock source.
01151   * @retval The clock source can be one of the following values:
01152   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
01153   *            @arg @ref RCC_USART1CLKSOURCE_HSI  HSI selected as USART1 clock
01154   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
01155   *            @arg @ref RCC_USART1CLKSOURCE_LSE  LSE selected as USART1 clock
01156   */
01157 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
01158 
01159 /** @brief  Macro to configure the USART2 clock (USART2CLK).
01160   *
01161   * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
01162   *          This parameter can be one of the following values:
01163   *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
01164   *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
01165   *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
01166   *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
01167   * @retval None
01168   */
01169 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
01170                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
01171 
01172 /** @brief  Macro to get the USART2 clock source.
01173   * @retval The clock source can be one of the following values:
01174   *            @arg @ref RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
01175   *            @arg @ref RCC_USART2CLKSOURCE_HSI  HSI selected as USART2 clock
01176   *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
01177   *            @arg @ref RCC_USART2CLKSOURCE_LSE  LSE selected as USART2 clock
01178   */
01179 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
01180 
01181 #if defined(USART3)
01182 
01183 /** @brief  Macro to configure the USART3 clock (USART3CLK).
01184   *
01185   * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.
01186   *          This parameter can be one of the following values:
01187   *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
01188   *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
01189   *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
01190   *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
01191   * @retval None
01192   */
01193 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
01194                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
01195 
01196 /** @brief  Macro to get the USART3 clock source.
01197   * @retval The clock source can be one of the following values:
01198   *            @arg @ref RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
01199   *            @arg @ref RCC_USART3CLKSOURCE_HSI  HSI selected as USART3 clock
01200   *            @arg @ref RCC_USART3CLKSOURCE_SYSCLK  System Clock selected as USART3 clock
01201   *            @arg @ref RCC_USART3CLKSOURCE_LSE  LSE selected as USART3 clock
01202   */
01203 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
01204 
01205 #endif /* USART3 */
01206 
01207 #if defined(UART4)
01208 
01209 /** @brief  Macro to configure the UART4 clock (UART4CLK).
01210   *
01211   * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.
01212   *          This parameter can be one of the following values:
01213   *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
01214   *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
01215   *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
01216   *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
01217   * @retval None
01218   */
01219 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
01220                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
01221 
01222 /** @brief  Macro to get the UART4 clock source.
01223   * @retval The clock source can be one of the following values:
01224   *            @arg @ref RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
01225   *            @arg @ref RCC_UART4CLKSOURCE_HSI  HSI selected as UART4 clock
01226   *            @arg @ref RCC_UART4CLKSOURCE_SYSCLK  System Clock selected as UART4 clock
01227   *            @arg @ref RCC_UART4CLKSOURCE_LSE  LSE selected as UART4 clock
01228   */
01229 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
01230 
01231 #endif /* UART4 */
01232 
01233 #if defined(UART5)
01234 
01235 /** @brief  Macro to configure the UART5 clock (UART5CLK).
01236   *
01237   * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.
01238   *          This parameter can be one of the following values:
01239   *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
01240   *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
01241   *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
01242   *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
01243   * @retval None
01244   */
01245 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
01246                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
01247 
01248 /** @brief  Macro to get the UART5 clock source.
01249   * @retval The clock source can be one of the following values:
01250   *            @arg @ref RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
01251   *            @arg @ref RCC_UART5CLKSOURCE_HSI  HSI selected as UART5 clock
01252   *            @arg @ref RCC_UART5CLKSOURCE_SYSCLK  System Clock selected as UART5 clock
01253   *            @arg @ref RCC_UART5CLKSOURCE_LSE  LSE selected as UART5 clock
01254   */
01255 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
01256 
01257 #endif /* UART5 */
01258 
01259 /** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).
01260   *
01261   * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
01262   *          This parameter can be one of the following values:
01263   *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
01264   *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
01265   *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
01266   *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
01267   * @retval None
01268   */
01269 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
01270                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
01271 
01272 /** @brief  Macro to get the LPUART1 clock source.
01273   * @retval The clock source can be one of the following values:
01274   *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1  PCLK1 selected as LPUART1 clock
01275   *            @arg @ref RCC_LPUART1CLKSOURCE_HSI  HSI selected as LPUART1 clock
01276   *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
01277   *            @arg @ref RCC_LPUART1CLKSOURCE_LSE  LSE selected as LPUART1 clock
01278   */
01279 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
01280 
01281 /** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
01282   *
01283   * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
01284   *          This parameter can be one of the following values:
01285   *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK  PCLK selected as LPTIM1 clock
01286   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPTIM1 clock
01287   *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  LSI selected as LPTIM1 clock
01288   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPTIM1 clock
01289   * @retval None
01290   */
01291 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
01292                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
01293 
01294 /** @brief  Macro to get the LPTIM1 clock source.
01295   * @retval The clock source can be one of the following values:
01296   *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK  PCLK selected as LPUART1 clock
01297   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI  HSI selected as LPUART1 clock
01298   *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI  System Clock selected as LPUART1 clock
01299   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE  LSE selected as LPUART1 clock
01300   */
01301 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
01302 
01303 /** @brief  Macro to configure the LPTIM2 clock (LPTIM2CLK).
01304   *
01305   * @param  __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
01306   *          This parameter can be one of the following values:
01307   *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK  PCLK selected as LPTIM2 clock
01308   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPTIM2 clock
01309   *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  LSI selected as LPTIM2 clock
01310   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPTIM2 clock
01311   * @retval None
01312   */
01313 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
01314                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
01315 
01316 /** @brief  Macro to get the LPTIM2 clock source.
01317   * @retval The clock source can be one of the following values:
01318   *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK  PCLK selected as LPUART1 clock
01319   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI  HSI selected as LPUART1 clock
01320   *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI  System Clock selected as LPUART1 clock
01321   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE  LSE selected as LPUART1 clock
01322   */
01323 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
01324 
01325 #if defined(SDMMC1)
01326 
01327 /** @brief  Macro to configure the SDMMC1 clock.
01328   *
01329   @if STM32L486xx
01330   * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
01331   @endif
01332   *
01333   @if STM32L443xx
01334   * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
01335   @endif
01336   *
01337   * @param  __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
01338   *         This parameter can be one of the following values:
01339   @if STM32L486xx
01340   *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock for devices without HSI48
01341   *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
01342   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as SDMMC1 clock
01343   @endif
01344   @if STM32L443xx
01345   *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48
01346   *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
01347   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as SDMMC1 clock
01348   @endif
01349   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL Clock selected as SDMMC1 clock
01350   * @retval None
01351   */
01352 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
01353                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
01354 
01355 /** @brief  Macro to get the SDMMC1 clock.
01356   * @retval The clock source can be one of the following values:
01357   @if STM32L486xx
01358   *            @arg @ref RCC_SDMMC1CLKSOURCE_NONE  No clock selected as SDMMC1 clock for devices without HSI48
01359   *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
01360   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
01361   @endif
01362   @if STM32L443xx
01363   *            @arg @ref RCC_SDMMC1CLKSOURCE_HSI48  HSI48 selected as SDMMC1 clock for devices with HSI48
01364   *            @arg @ref RCC_SDMMC1CLKSOURCE_MSI  MSI selected as SDMMC1 clock
01365   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
01366   @endif
01367   *            @arg @ref RCC_SDMMC1CLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
01368   */
01369 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
01370 
01371 #endif /* SDMMC1 */
01372 
01373 /** @brief  Macro to configure the RNG clock.
01374   *
01375   * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
01376   *
01377   * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.
01378   *         This parameter can be one of the following values:
01379   @if STM32L486xx
01380   *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock for devices without HSI48
01381   @endif
01382   @if STM32L443xx
01383   *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48
01384   @endif
01385   *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock
01386   *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as RNG clock
01387   *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL Clock selected as RNG clock
01388   * @retval None
01389   */
01390 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
01391                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
01392 
01393 /** @brief  Macro to get the RNG clock.
01394   * @retval The clock source can be one of the following values:
01395   @if STM32L486xx
01396   *            @arg @ref RCC_RNGCLKSOURCE_NONE  No clock selected as RNG clock for devices without HSI48
01397   @endif
01398   @if STM32L443xx
01399   *            @arg @ref RCC_RNGCLKSOURCE_HSI48  HSI48 selected as RNG clock clock for devices with HSI48
01400   @endif
01401   *            @arg @ref RCC_RNGCLKSOURCE_MSI  MSI selected as RNG clock
01402   *            @arg @ref RCC_RNGCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
01403   *            @arg @ref RCC_RNGCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as RNG clock
01404   */
01405 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
01406 
01407 #if defined(USB_OTG_FS) || defined(USB)
01408 
01409 /** @brief  Macro to configure the USB clock (USBCLK).
01410   *
01411   * @note  USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
01412   *
01413   * @param  __USB_CLKSOURCE__ specifies the USB clock source.
01414   *         This parameter can be one of the following values:
01415   @if STM32L486xx
01416   *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock for devices without HSI48
01417   @endif
01418   @if STM32L443xx
01419   *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
01420   @endif
01421   *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock
01422   *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
01423   *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
01424   * @retval None
01425   */
01426 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
01427                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
01428 
01429 /** @brief  Macro to get the USB clock source.
01430   * @retval The clock source can be one of the following values:
01431   @if STM32L486xx
01432   *            @arg @ref RCC_USBCLKSOURCE_NONE  No clock selected as 48MHz clock for devices without HSI48
01433   @endif
01434   @if STM32L443xx
01435   *            @arg @ref RCC_USBCLKSOURCE_HSI48  HSI48 selected as 48MHz clock for devices with HSI48
01436   @endif
01437   *            @arg @ref RCC_USBCLKSOURCE_MSI  MSI selected as USB clock
01438   *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
01439   *            @arg @ref RCC_USBCLKSOURCE_PLL  PLL "Q" clock (PLL48M1CLK) selected as USB clock
01440   */
01441 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
01442 
01443 #endif /* USB_OTG_FS || USB */
01444 
01445 /** @brief  Macro to configure the ADC interface clock.
01446   * @param  __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
01447   *         This parameter can be one of the following values:
01448   *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock
01449   *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock
01450   @if STM32L486xx
01451   *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
01452   @endif
01453   *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
01454   * @retval None
01455   */
01456 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
01457                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
01458 
01459 /** @brief  Macro to get the ADC clock source.
01460   * @retval The clock source can be one of the following values:
01461   *            @arg @ref RCC_ADCCLKSOURCE_NONE  No clock selected as ADC clock
01462   *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock
01463   @if STM32L486xx
01464   *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI2  PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
01465   @endif
01466   *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
01467   */
01468 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
01469 
01470 #if defined(SWPMI1)
01471 
01472 /** @brief  Macro to configure the SWPMI1 clock.
01473   * @param  __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
01474   *         This parameter can be one of the following values:
01475   *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK  PCLK Clock selected as SWPMI1 clock
01476   *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock
01477   * @retval None
01478   */
01479 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
01480                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
01481 
01482 /** @brief  Macro to get the SWPMI1 clock source.
01483   * @retval The clock source can be one of the following values:
01484   *            @arg @ref RCC_SWPMI1CLKSOURCE_PCLK  PCLK Clock selected as SWPMI1 clock
01485   *            @arg @ref RCC_SWPMI1CLKSOURCE_HSI  HSI Clock selected as SWPMI1 clock
01486   */
01487 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
01488 
01489 #endif /* SWPMI1 */
01490 
01491 #if defined(DFSDM1_Filter0)
01492 /** @brief  Macro to configure the DFSDM1 clock.
01493   * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
01494   *         This parameter can be one of the following values:
01495   *            @arg @ref RCC_DFSDM1CLKSOURCE_PCLK  PCLK Clock selected as DFSDM1 clock
01496   *            @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK  System Clock selected as DFSDM1 clock
01497   * @retval None
01498   */
01499 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
01500                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
01501 
01502 /** @brief  Macro to get the DFSDM1 clock source.
01503   * @retval The clock source can be one of the following values:
01504   *            @arg @ref RCC_DFSDM1CLKSOURCE_PCLK  PCLK Clock selected as DFSDM1 clock
01505   *            @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK  System Clock selected as DFSDM1 clock
01506   */
01507 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))
01508 
01509 #endif /* DFSDM1_Filter0 */
01510 
01511 
01512 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
01513   * @brief macros to manage the specified RCC Flags and interrupts.
01514   * @{
01515   */
01516 
01517 /** @brief Enable PLLSAI1RDY interrupt.
01518   * @retval None
01519   */
01520 #define __HAL_RCC_PLLSAI1_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
01521 
01522 /** @brief Disable PLLSAI1RDY interrupt.
01523   * @retval None
01524   */
01525 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
01526 
01527 /** @brief Clear the PLLSAI1RDY interrupt pending bit.
01528   * @retval None
01529   */
01530 #define __HAL_RCC_PLLSAI1_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
01531 
01532 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
01533   * @retval TRUE or FALSE.
01534   */
01535 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
01536 
01537 /** @brief  Check whether the PLLSAI1RDY flag is set or not.
01538   * @retval TRUE or FALSE.
01539   */
01540 #define __HAL_RCC_PLLSAI1_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
01541 
01542 #if defined(RCC_PLLSAI2_SUPPORT)
01543 
01544 /** @brief Enable PLLSAI2RDY interrupt.
01545   * @retval None
01546   */
01547 #define __HAL_RCC_PLLSAI2_ENABLE_IT()  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
01548 
01549 /** @brief Disable PLLSAI2RDY interrupt.
01550   * @retval None
01551   */
01552 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
01553 
01554 /** @brief Clear the PLLSAI2RDY interrupt pending bit.
01555   * @retval None
01556   */
01557 #define __HAL_RCC_PLLSAI2_CLEAR_IT()   WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
01558 
01559 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
01560   * @retval TRUE or FALSE.
01561   */
01562 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE()     (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
01563 
01564 /** @brief  Check whether the PLLSAI2RDY flag is set or not.
01565   * @retval TRUE or FALSE.
01566   */
01567 #define __HAL_RCC_PLLSAI2_GET_FLAG()   (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
01568 
01569 #endif /* RCC_PLLSAI2_SUPPORT */
01570 
01571 
01572 /**
01573   * @brief Enable the RCC LSE CSS Extended Interrupt Line.
01574   * @retval None
01575   */
01576 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
01577 
01578 /**
01579   * @brief Disable the RCC LSE CSS Extended Interrupt Line.
01580   * @retval None
01581   */
01582 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
01583 
01584 /**
01585   * @brief Enable the RCC LSE CSS Event Line.
01586   * @retval None.
01587   */
01588 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
01589 
01590 /**
01591   * @brief Disable the RCC LSE CSS Event Line.
01592   * @retval None.
01593   */
01594 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
01595 
01596 
01597 /**
01598   * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
01599   * @retval None.
01600   */
01601 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
01602 
01603 
01604 /**
01605   * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
01606   * @retval None.
01607   */
01608 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
01609 
01610 
01611 /**
01612   * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
01613   * @retval None.
01614   */
01615 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
01616 
01617 /**
01618   * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
01619   * @retval None.
01620   */
01621 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
01622 
01623 /**
01624   * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
01625   * @retval None.
01626   */
01627 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
01628   do {                                                      \
01629     __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
01630     __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
01631   } while(0)  
01632   
01633 /**
01634   * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
01635   * @retval None.
01636   */
01637 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
01638   do {                                                       \
01639     __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
01640     __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
01641   } while(0)  
01642 
01643 /**
01644   * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
01645   * @retval EXTI RCC LSE CSS Line Status.
01646   */
01647 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
01648 
01649 /**
01650   * @brief Clear the RCC LSE CSS EXTI flag.
01651   * @retval None.
01652   */
01653 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
01654 
01655 /**
01656   * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
01657   * @retval None.
01658   */
01659 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
01660 
01661 
01662 #if defined(CRS)
01663 
01664 /**
01665   * @brief  Enable the specified CRS interrupts.
01666   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
01667   *          This parameter can be any combination of the following values:
01668   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01669   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01670   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01671   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01672   * @retval None
01673   */
01674 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
01675 
01676 /**
01677   * @brief  Disable the specified CRS interrupts.
01678   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
01679   *          This parameter can be any combination of the following values:
01680   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01681   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01682   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01683   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01684   * @retval None
01685   */
01686 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
01687 
01688 /** @brief  Check whether the CRS interrupt has occurred or not.
01689   * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
01690   *         This parameter can be one of the following values:
01691   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01692   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01693   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01694   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01695   * @retval The new state of __INTERRUPT__ (SET or RESET).
01696   */
01697 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
01698 
01699 /** @brief  Clear the CRS interrupt pending bits
01700   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01701   *         This parameter can be any combination of the following values:
01702   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01703   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01704   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01705   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01706   *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
01707   *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
01708   *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
01709   */
01710 /* CRS IT Error Mask */
01711 #define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
01712 
01713 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
01714                                                  if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
01715                                                  { \
01716                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
01717                                                  } \
01718                                                  else \
01719                                                  { \
01720                                                    WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
01721                                                  } \
01722                                                } while(0)
01723 
01724 /**
01725   * @brief  Check whether the specified CRS flag is set or not.
01726   * @param  __FLAG__ specifies the flag to check.
01727   *          This parameter can be one of the following values:
01728   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
01729   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
01730   *              @arg @ref RCC_CRS_FLAG_ERR  Error
01731   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
01732   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
01733   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
01734   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
01735   * @retval The new state of _FLAG_ (TRUE or FALSE).
01736   */
01737 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
01738 
01739 /**
01740   * @brief  Clear the CRS specified FLAG.
01741   * @param __FLAG__ specifies the flag to clear.
01742   *          This parameter can be one of the following values:
01743   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
01744   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
01745   *              @arg @ref RCC_CRS_FLAG_ERR  Error
01746   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
01747   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
01748   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
01749   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
01750   * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
01751   * @retval None
01752   */
01753 
01754 /* CRS Flag Error Mask */
01755 #define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
01756 
01757 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
01758                                                  if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
01759                                                  { \
01760                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
01761                                                  } \
01762                                                  else \
01763                                                  { \
01764                                                    WRITE_REG(CRS->ICR, (__FLAG__)); \
01765                                                  } \
01766                                                } while(0)
01767 
01768 #endif /* CRS */
01769 
01770 /**
01771   * @}
01772   */
01773 
01774 #if defined(CRS)
01775 
01776 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
01777   * @{
01778   */  
01779 /**
01780   * @brief  Enable the oscillator clock for frequency error counter.
01781   * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
01782   * @retval None
01783   */
01784 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
01785 
01786 /**
01787   * @brief  Disable the oscillator clock for frequency error counter.
01788   * @retval None
01789   */
01790 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
01791 
01792 /**
01793   * @brief  Enable the automatic hardware adjustement of TRIM bits.
01794   * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
01795   * @retval None
01796   */
01797 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
01798 
01799 /**
01800   * @brief  Enable or disable the automatic hardware adjustement of TRIM bits.
01801   * @retval None
01802   */
01803 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
01804 
01805 /**
01806   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
01807   * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency 
01808   *             of the synchronization source after prescaling. It is then decreased by one in order to 
01809   *             reach the expected synchronization on the zero value. The formula is the following:
01810   *             RELOAD = (fTARGET / fSYNC) -1
01811   * @param  __FTARGET__ Target frequency (value in Hz)
01812   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
01813   * @retval None
01814   */
01815 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
01816 
01817 /**
01818   * @}
01819   */
01820 
01821 #endif /* CRS */
01822 
01823 /**
01824   * @}
01825   */
01826 
01827 /* Exported functions --------------------------------------------------------*/
01828 /** @addtogroup RCCEx_Exported_Functions
01829   * @{
01830   */
01831 
01832 /** @addtogroup RCCEx_Exported_Functions_Group1
01833   * @{
01834   */
01835 
01836 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01837 void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01838 uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
01839 
01840 /**
01841   * @}
01842   */
01843 
01844 /** @addtogroup RCCEx_Exported_Functions_Group2
01845   * @{
01846   */
01847 
01848 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init);
01849 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
01850 
01851 #if defined(RCC_PLLSAI2_SUPPORT)
01852 
01853 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef  *PLLSAI2Init);
01854 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
01855 
01856 #endif /* RCC_PLLSAI2_SUPPORT */
01857 
01858 void              HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
01859 void              HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
01860 void              HAL_RCCEx_EnableLSECSS(void);
01861 void              HAL_RCCEx_DisableLSECSS(void);
01862 void              HAL_RCCEx_EnableLSECSS_IT(void);
01863 void              HAL_RCCEx_LSECSS_IRQHandler(void);
01864 void              HAL_RCCEx_LSECSS_Callback(void);
01865 void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
01866 void              HAL_RCCEx_DisableLSCO(void);
01867 void              HAL_RCCEx_EnableMSIPLLMode(void);
01868 void              HAL_RCCEx_DisableMSIPLLMode(void);
01869 
01870 /**
01871   * @}
01872   */
01873 
01874 #if defined(CRS)
01875 
01876 /** @addtogroup RCCEx_Exported_Functions_Group3
01877   * @{
01878   */
01879 
01880 void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
01881 void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
01882 void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
01883 uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
01884 void              HAL_RCCEx_CRS_IRQHandler(void);
01885 void              HAL_RCCEx_CRS_SyncOkCallback(void);
01886 void              HAL_RCCEx_CRS_SyncWarnCallback(void);
01887 void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);
01888 void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
01889 
01890 /**
01891   * @}
01892   */
01893 
01894 #endif /* CRS */
01895 
01896 /**
01897   * @}
01898   */
01899 
01900 /* Private macros ------------------------------------------------------------*/
01901 /** @addtogroup RCCEx_Private_Macros
01902   * @{
01903   */
01904 
01905 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
01906                                        ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
01907 
01908 #if defined(STM32L431xx)
01909 
01910 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01911                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01912                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01913                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01914                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01915                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01916                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01917                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
01918                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01919                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01920                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
01921                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01922                 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
01923                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01924                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
01925                 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
01926 
01927 #elif defined(STM32L432xx) || defined(STM32L442xx)
01928 
01929 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01930                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01931                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01932                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01933                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01934                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
01935                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01936                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01937                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
01938                 (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
01939                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01940                 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
01941                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01942                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG))
01943 
01944 #elif defined(STM32L433xx) || defined(STM32L443xx)
01945 
01946 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01947                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01948                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01949                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01950                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01951                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01952                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01953                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
01954                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01955                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01956                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
01957                 (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
01958                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01959                 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
01960                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01961                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
01962                 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
01963 
01964 #elif defined(STM32L471xx)
01965 
01966 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01967                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01968                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01969                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01970                 (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
01971                 (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \
01972                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01973                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01974                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01975                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
01976                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
01977                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
01978                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
01979                 (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \
01980                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
01981                 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
01982                 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \
01983                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
01984                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
01985                 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
01986 
01987 #else
01988 
01989 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
01990                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)  == RCC_PERIPHCLK_USART1)  || \
01991                 (((__SELECTION__) & RCC_PERIPHCLK_USART2)  == RCC_PERIPHCLK_USART2)  || \
01992                 (((__SELECTION__) & RCC_PERIPHCLK_USART3)  == RCC_PERIPHCLK_USART3)  || \
01993                 (((__SELECTION__) & RCC_PERIPHCLK_UART4)   == RCC_PERIPHCLK_UART4)   || \
01994                 (((__SELECTION__) & RCC_PERIPHCLK_UART5)   == RCC_PERIPHCLK_UART5)   || \
01995                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
01996                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)    == RCC_PERIPHCLK_I2C1)    || \
01997                 (((__SELECTION__) & RCC_PERIPHCLK_I2C2)    == RCC_PERIPHCLK_I2C2)    || \
01998                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)    == RCC_PERIPHCLK_I2C3)    || \
01999                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)  == RCC_PERIPHCLK_LPTIM1)  || \
02000                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)  == RCC_PERIPHCLK_LPTIM2)  || \
02001                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)    == RCC_PERIPHCLK_SAI1)    || \
02002                 (((__SELECTION__) & RCC_PERIPHCLK_SAI2)    == RCC_PERIPHCLK_SAI2)    || \
02003                 (((__SELECTION__) & RCC_PERIPHCLK_USB)     == RCC_PERIPHCLK_USB)     || \
02004                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)     == RCC_PERIPHCLK_ADC)     || \
02005                 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1)  == RCC_PERIPHCLK_SWPMI1)  || \
02006                 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1)  == RCC_PERIPHCLK_DFSDM1)  || \
02007                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)     == RCC_PERIPHCLK_RTC)     || \
02008                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)     == RCC_PERIPHCLK_RNG)     || \
02009                 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)  == RCC_PERIPHCLK_SDMMC1))
02010 
02011 #endif /* STM32L431xx */
02012 
02013 #define IS_RCC_USART1CLKSOURCE(__SOURCE__)  \
02014                (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
02015                 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
02016                 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
02017                 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
02018 
02019 #define IS_RCC_USART2CLKSOURCE(__SOURCE__)  \
02020                (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
02021                 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
02022                 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
02023                 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
02024 
02025 #if defined(USART3)
02026 
02027 #define IS_RCC_USART3CLKSOURCE(__SOURCE__)  \
02028                (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1)  || \
02029                 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
02030                 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)    || \
02031                 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
02032 
02033 #endif /* USART3 */
02034 
02035 #if defined(UART4)
02036 
02037 #define IS_RCC_UART4CLKSOURCE(__SOURCE__)  \
02038                (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1)  || \
02039                 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
02040                 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)    || \
02041                 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
02042 
02043 #endif /* UART4 */
02044 
02045 #if defined(UART5)
02046 
02047 #define IS_RCC_UART5CLKSOURCE(__SOURCE__)  \
02048                (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1)  || \
02049                 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
02050                 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)    || \
02051                 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
02052 
02053 #endif /* UART5 */
02054 
02055 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  \
02056                (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
02057                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
02058                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
02059                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
02060 
02061 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__)   \
02062                (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
02063                 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
02064                 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
02065 
02066 #if defined(I2C2)
02067 
02068 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__)   \
02069                (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
02070                 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
02071                 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
02072 
02073 #endif /* I2C2 */
02074 
02075 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__)   \
02076                (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
02077                 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
02078                 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
02079 
02080 #if defined(RCC_PLLSAI2_SUPPORT)
02081 
02082 #define IS_RCC_SAI1CLK(__SOURCE__)   \
02083                (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
02084                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
02085                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
02086                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
02087 
02088 #else
02089 
02090 #define IS_RCC_SAI1CLK(__SOURCE__)   \
02091                (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
02092                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)     || \
02093                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
02094 
02095 #endif /* RCC_PLLSAI2_SUPPORT */
02096 
02097 #if defined(RCC_PLLSAI2_SUPPORT)
02098 
02099 #define IS_RCC_SAI2CLK(__SOURCE__)   \
02100                (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
02101                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
02102                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)     || \
02103                 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
02104 
02105 #endif /* RCC_PLLSAI2_SUPPORT */
02106 
02107 #define IS_RCC_LPTIM1CLK(__SOURCE__)  \
02108                (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) || \
02109                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)  || \
02110                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)  || \
02111                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
02112 
02113 #define IS_RCC_LPTIM2CLK(__SOURCE__)  \
02114                (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) || \
02115                 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)  || \
02116                 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)  || \
02117                 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
02118 
02119 #if defined(SDMMC1)
02120 #if defined(RCC_HSI48_SUPPORT)
02121 
02122 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \
02123                (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48)   || \
02124                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
02125                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \
02126                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
02127 
02128 #else
02129 
02130 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)  \
02131                (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE)    || \
02132                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
02133                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL)     || \
02134                 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
02135 
02136 #endif /* RCC_HSI48_SUPPORT */
02137 #endif /* SDMMC1 */
02138 
02139 #if defined(RCC_HSI48_SUPPORT)
02140 
02141 #define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
02142                (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \
02143                 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
02144                 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
02145                 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
02146 
02147 #else
02148 
02149 #define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
02150                (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE)    || \
02151                 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
02152                 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
02153                 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
02154 
02155 #endif /* RCC_HSI48_SUPPORT */
02156 
02157 #if defined(USB_OTG_FS) || defined(USB)
02158 #if defined(RCC_HSI48_SUPPORT)
02159 
02160 #define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
02161                (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \
02162                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
02163                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
02164                 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
02165 
02166 #else
02167 
02168 #define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
02169                (((__SOURCE__) == RCC_USBCLKSOURCE_NONE)    || \
02170                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
02171                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
02172                 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
02173 
02174 #endif /* RCC_HSI48_SUPPORT */
02175 #endif /* USB_OTG_FS || USB */
02176 
02177 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
02178 
02179 #define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \
02180                (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \
02181                 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
02182                 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
02183                 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
02184 
02185 #else
02186 
02187 #define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \
02188                (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE)    || \
02189                 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
02190                 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
02191 
02192 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
02193 
02194 #if defined(SWPMI1)
02195 
02196 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__)  \
02197                (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) || \
02198                 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
02199 
02200 #endif /* SWPMI1 */
02201 
02202 #if defined(DFSDM1_Filter0)
02203 
02204 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__)  \
02205                (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK) || \
02206                 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
02207 
02208 #endif /* DFSDM1_Filter0 */
02209 
02210 #define IS_RCC_PLLSAI1SOURCE(__VALUE__)    IS_RCC_PLLSOURCE(__VALUE__)
02211 
02212 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
02213 
02214 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
02215 
02216 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
02217 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
02218 #else
02219 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
02220 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
02221 
02222 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
02223                                             ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
02224 
02225 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
02226                                             ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
02227 
02228 #if defined(RCC_PLLSAI2_SUPPORT)
02229 
02230 #define IS_RCC_PLLSAI2SOURCE(__VALUE__)    IS_RCC_PLLSOURCE(__VALUE__)
02231 
02232 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__)   ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
02233 
02234 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__)   ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
02235 
02236 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
02237 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
02238 #else
02239 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__)   (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
02240 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
02241 
02242 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__)   (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
02243                                             ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
02244 
02245 #endif /* RCC_PLLSAI2_SUPPORT */
02246 
02247 #if defined(CRS)
02248 
02249 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
02250                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
02251                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
02252 
02253 #define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
02254                                             ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
02255                                             ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
02256                                             ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
02257 
02258 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
02259                                                 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
02260                                                 
02261 #define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
02262 
02263 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
02264 
02265 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
02266 
02267 #define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
02268                                             ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
02269 
02270 #endif /* CRS */
02271 
02272 /**
02273   * @}
02274   */
02275 
02276 /**
02277   * @}
02278   */
02279 
02280 /**
02281   * @}
02282   */
02283 
02284 #ifdef __cplusplus
02285 }
02286 #endif
02287 
02288 #endif /* __STM32L4xx_HAL_RCC_EX_H */
02289 
02290 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/