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stm32l4xx_hal_pwr_ex.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_pwr_ex.c 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Extended PWR HAL module driver. 00008 * This file provides firmware functions to manage the following 00009 * functionalities of the Power Controller (PWR) peripheral: 00010 * + Extended Initialization and de-initialization functions 00011 * + Extended Peripheral Control functions 00012 * 00013 ****************************************************************************** 00014 * @attention 00015 * 00016 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00017 * 00018 * Redistribution and use in source and binary forms, with or without modification, 00019 * are permitted provided that the following conditions are met: 00020 * 1. Redistributions of source code must retain the above copyright notice, 00021 * this list of conditions and the following disclaimer. 00022 * 2. Redistributions in binary form must reproduce the above copyright notice, 00023 * this list of conditions and the following disclaimer in the documentation 00024 * and/or other materials provided with the distribution. 00025 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00026 * may be used to endorse or promote products derived from this software 00027 * without specific prior written permission. 00028 * 00029 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00030 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00031 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00032 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00033 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00034 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00035 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00036 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00037 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00038 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00039 * 00040 ****************************************************************************** 00041 */ 00042 00043 /* Includes ------------------------------------------------------------------*/ 00044 #include "stm32l4xx_hal.h" 00045 00046 /** @addtogroup STM32L4xx_HAL_Driver 00047 * @{ 00048 */ 00049 00050 /** @defgroup PWREx PWREx 00051 * @brief PWR Extended HAL module driver 00052 * @{ 00053 */ 00054 00055 #ifdef HAL_PWR_MODULE_ENABLED 00056 00057 /* Private typedef -----------------------------------------------------------*/ 00058 /* Private define ------------------------------------------------------------*/ 00059 00060 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00061 #define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1) 00062 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 00063 #define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1|PWR_GPIO_BIT_3) 00064 #endif 00065 00066 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines 00067 * @{ 00068 */ 00069 00070 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask 00071 * @{ 00072 */ 00073 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ 00074 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ 00075 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ 00076 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */ 00077 /** 00078 * @} 00079 */ 00080 00081 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value 00082 * @{ 00083 */ 00084 #define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */ 00085 /** 00086 * @} 00087 */ 00088 00089 00090 00091 /** 00092 * @} 00093 */ 00094 00095 00096 00097 /* Private macro -------------------------------------------------------------*/ 00098 /* Private variables ---------------------------------------------------------*/ 00099 /* Private function prototypes -----------------------------------------------*/ 00100 /* Exported functions --------------------------------------------------------*/ 00101 00102 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions 00103 * @{ 00104 */ 00105 00106 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 00107 * @brief Extended Peripheral Control functions 00108 * 00109 @verbatim 00110 =============================================================================== 00111 ##### Extended Peripheral Initialization and de-initialization functions ##### 00112 =============================================================================== 00113 [..] 00114 00115 @endverbatim 00116 * @{ 00117 */ 00118 00119 00120 /** 00121 * @brief Return Voltage Scaling Range. 00122 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) 00123 */ 00124 uint32_t HAL_PWREx_GetVoltageRange(void) 00125 { 00126 return (PWR->CR1 & PWR_CR1_VOS); 00127 } 00128 00129 00130 00131 /** 00132 * @brief Configure the main internal regulator output voltage. 00133 * @param VoltageScaling: specifies the regulator output voltage to achieve 00134 * a tradeoff between performance and power consumption. 00135 * This parameter can be one of the following values: 00136 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 00137 * typical output voltage at 1.2 V, 00138 * system frequency up to 80 MHz. 00139 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 00140 * typical output voltage at 1.0 V, 00141 * system frequency up to 26 MHz. 00142 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to 00143 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. 00144 * When moving from Range 2 to Range 1, the system frequency can be increased to 00145 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. 00146 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be 00147 * cleared before returning the status. If the flag is not cleared within 00148 * 50 microseconds, HAL_TIMEOUT status is reported. 00149 * @retval HAL Status 00150 */ 00151 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) 00152 { 00153 uint32_t wait_loop_index = 0; 00154 00155 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); 00156 00157 /* If Set Range 1 */ 00158 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 00159 { 00160 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) 00161 { 00162 /* Set Range 1 */ 00163 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 00164 00165 /* Wait until VOSF is cleared */ 00166 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); 00167 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) 00168 { 00169 wait_loop_index--; 00170 } 00171 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 00172 { 00173 return HAL_TIMEOUT; 00174 } 00175 } 00176 } 00177 else 00178 { 00179 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) 00180 { 00181 /* Set Range 2 */ 00182 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 00183 /* No need to wait for VOSF to be cleared for this transition */ 00184 } 00185 } 00186 00187 return HAL_OK; 00188 } 00189 00190 00191 /** 00192 * @brief Enable battery charging. 00193 * When VDD is present, charge the external battery on VBAT thru an internal resistor. 00194 * @param ResistorSelection: specifies the resistor impedance. 00195 * This parameter can be one of the following values: 00196 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor 00197 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor 00198 * @retval None 00199 */ 00200 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) 00201 { 00202 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); 00203 00204 /* Specify resistor selection */ 00205 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); 00206 00207 /* Enable battery charging */ 00208 SET_BIT(PWR->CR4, PWR_CR4_VBE); 00209 } 00210 00211 00212 /** 00213 * @brief Disable battery charging. 00214 * @retval None 00215 */ 00216 void HAL_PWREx_DisableBatteryCharging(void) 00217 { 00218 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); 00219 } 00220 00221 00222 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00223 /** 00224 * @brief Enable VDDUSB supply. 00225 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. 00226 * @retval None 00227 */ 00228 void HAL_PWREx_EnableVddUSB(void) 00229 { 00230 SET_BIT(PWR->CR2, PWR_CR2_USV); 00231 } 00232 00233 00234 /** 00235 * @brief Disable VDDUSB supply. 00236 * @retval None 00237 */ 00238 void HAL_PWREx_DisableVddUSB(void) 00239 { 00240 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); 00241 } 00242 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00243 00244 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00245 /** 00246 * @brief Enable VDDIO2 supply. 00247 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. 00248 * @retval None 00249 */ 00250 void HAL_PWREx_EnableVddIO2(void) 00251 { 00252 SET_BIT(PWR->CR2, PWR_CR2_IOSV); 00253 } 00254 00255 00256 /** 00257 * @brief Disable VDDIO2 supply. 00258 * @retval None 00259 */ 00260 void HAL_PWREx_DisableVddIO2(void) 00261 { 00262 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); 00263 } 00264 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00265 00266 00267 /** 00268 * @brief Enable Internal Wake-up Line. 00269 * @retval None 00270 */ 00271 void HAL_PWREx_EnableInternalWakeUpLine(void) 00272 { 00273 SET_BIT(PWR->CR3, PWR_CR3_EIWF); 00274 } 00275 00276 00277 /** 00278 * @brief Disable Internal Wake-up Line. 00279 * @retval None 00280 */ 00281 void HAL_PWREx_DisableInternalWakeUpLine(void) 00282 { 00283 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); 00284 } 00285 00286 00287 00288 /** 00289 * @brief Enable GPIO pull-up state in Standby and Shutdown modes. 00290 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in 00291 * pull-up state in Standby and Shutdown modes. 00292 * @note This state is effective in Standby and Shutdown modes only if APC bit 00293 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. 00294 * @note The configuration is lost when exiting the Shutdown mode due to the 00295 * power-on reset, maintained when exiting the Standby mode. 00296 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding 00297 * PDy bit of PWR_PDCRx register is cleared unless it is reserved. 00298 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input 00299 * parameter at the same time are set. 00300 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H 00301 * to select the GPIO peripheral. 00302 * @param GPIONumber: Specify the I/O pins numbers. 00303 * This parameter can be one of the following values: 00304 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less 00305 * I/O pins are available) or the logical OR of several of them to set 00306 * several bits for a given port in a single API call. 00307 * @retval HAL Status 00308 */ 00309 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00310 { 00311 assert_param(IS_PWR_GPIO(GPIO)); 00312 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00313 00314 switch (GPIO) 00315 { 00316 case PWR_GPIO_A: 00317 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); 00318 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); 00319 break; 00320 case PWR_GPIO_B: 00321 SET_BIT(PWR->PUCRB, GPIONumber); 00322 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); 00323 break; 00324 case PWR_GPIO_C: 00325 SET_BIT(PWR->PUCRC, GPIONumber); 00326 CLEAR_BIT(PWR->PDCRC, GPIONumber); 00327 break; 00328 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00329 case PWR_GPIO_D: 00330 SET_BIT(PWR->PUCRD, GPIONumber); 00331 CLEAR_BIT(PWR->PDCRD, GPIONumber); 00332 break; 00333 case PWR_GPIO_E: 00334 SET_BIT(PWR->PUCRE, GPIONumber); 00335 CLEAR_BIT(PWR->PDCRE, GPIONumber); 00336 break; 00337 #endif 00338 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00339 case PWR_GPIO_F: 00340 SET_BIT(PWR->PUCRF, GPIONumber); 00341 CLEAR_BIT(PWR->PDCRF, GPIONumber); 00342 break; 00343 case PWR_GPIO_G: 00344 SET_BIT(PWR->PUCRG, GPIONumber); 00345 CLEAR_BIT(PWR->PDCRG, GPIONumber); 00346 break; 00347 #endif 00348 case PWR_GPIO_H: 00349 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00350 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00351 break; 00352 default: 00353 return HAL_ERROR; 00354 } 00355 00356 return HAL_OK; 00357 } 00358 00359 00360 /** 00361 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. 00362 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O 00363 * in pull-up state in Standby and Shutdown modes. 00364 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input 00365 * parameter at the same time are reset. 00366 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H 00367 * to select the GPIO peripheral. 00368 * @param GPIONumber: Specify the I/O pins numbers. 00369 * This parameter can be one of the following values: 00370 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less 00371 * I/O pins are available) or the logical OR of several of them to reset 00372 * several bits for a given port in a single API call. 00373 * @retval HAL Status 00374 */ 00375 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00376 { 00377 assert_param(IS_PWR_GPIO(GPIO)); 00378 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00379 00380 switch (GPIO) 00381 { 00382 case PWR_GPIO_A: 00383 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); 00384 break; 00385 case PWR_GPIO_B: 00386 CLEAR_BIT(PWR->PUCRB, GPIONumber); 00387 break; 00388 case PWR_GPIO_C: 00389 CLEAR_BIT(PWR->PUCRC, GPIONumber); 00390 break; 00391 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00392 case PWR_GPIO_D: 00393 CLEAR_BIT(PWR->PUCRD, GPIONumber); 00394 break; 00395 case PWR_GPIO_E: 00396 CLEAR_BIT(PWR->PUCRE, GPIONumber); 00397 break; 00398 #endif 00399 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00400 case PWR_GPIO_F: 00401 CLEAR_BIT(PWR->PUCRF, GPIONumber); 00402 break; 00403 case PWR_GPIO_G: 00404 CLEAR_BIT(PWR->PUCRG, GPIONumber); 00405 break; 00406 #endif 00407 case PWR_GPIO_H: 00408 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00409 break; 00410 default: 00411 return HAL_ERROR; 00412 } 00413 00414 return HAL_OK; 00415 } 00416 00417 00418 00419 /** 00420 * @brief Enable GPIO pull-down state in Standby and Shutdown modes. 00421 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in 00422 * pull-down state in Standby and Shutdown modes. 00423 * @note This state is effective in Standby and Shutdown modes only if APC bit 00424 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. 00425 * @note The configuration is lost when exiting the Shutdown mode due to the 00426 * power-on reset, maintained when exiting the Standby mode. 00427 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding 00428 * PUy bit of PWR_PUCRx register is cleared unless it is reserved. 00429 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input 00430 * parameter at the same time are set. 00431 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H 00432 * to select the GPIO peripheral. 00433 * @param GPIONumber: Specify the I/O pins numbers. 00434 * This parameter can be one of the following values: 00435 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less 00436 * I/O pins are available) or the logical OR of several of them to set 00437 * several bits for a given port in a single API call. 00438 * @retval HAL Status 00439 */ 00440 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 00441 { 00442 assert_param(IS_PWR_GPIO(GPIO)); 00443 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00444 00445 switch (GPIO) 00446 { 00447 case PWR_GPIO_A: 00448 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); 00449 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); 00450 break; 00451 case PWR_GPIO_B: 00452 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); 00453 CLEAR_BIT(PWR->PUCRB, GPIONumber); 00454 break; 00455 case PWR_GPIO_C: 00456 SET_BIT(PWR->PDCRC, GPIONumber); 00457 CLEAR_BIT(PWR->PUCRC, GPIONumber); 00458 break; 00459 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00460 case PWR_GPIO_D: 00461 SET_BIT(PWR->PDCRD, GPIONumber); 00462 CLEAR_BIT(PWR->PUCRD, GPIONumber); 00463 break; 00464 case PWR_GPIO_E: 00465 SET_BIT(PWR->PDCRE, GPIONumber); 00466 CLEAR_BIT(PWR->PUCRE, GPIONumber); 00467 break; 00468 #endif 00469 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00470 case PWR_GPIO_F: 00471 SET_BIT(PWR->PDCRF, GPIONumber); 00472 CLEAR_BIT(PWR->PUCRF, GPIONumber); 00473 break; 00474 case PWR_GPIO_G: 00475 SET_BIT(PWR->PDCRG, GPIONumber); 00476 CLEAR_BIT(PWR->PUCRG, GPIONumber); 00477 break; 00478 #endif 00479 case PWR_GPIO_H: 00480 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00481 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00482 break; 00483 default: 00484 return HAL_ERROR; 00485 } 00486 00487 return HAL_OK; 00488 } 00489 00490 00491 /** 00492 * @brief Disable GPIO pull-down state in Standby and Shutdown modes. 00493 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O 00494 * in pull-down state in Standby and Shutdown modes. 00495 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input 00496 * parameter at the same time are reset. 00497 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H 00498 * to select the GPIO peripheral. 00499 * @param GPIONumber: Specify the I/O pins numbers. 00500 * This parameter can be one of the following values: 00501 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less 00502 * I/O pins are available) or the logical OR of several of them to reset 00503 * several bits for a given port in a single API call. 00504 * @retval HAL Status 00505 */ 00506 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 00507 { 00508 assert_param(IS_PWR_GPIO(GPIO)); 00509 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00510 00511 switch (GPIO) 00512 { 00513 case PWR_GPIO_A: 00514 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); 00515 break; 00516 case PWR_GPIO_B: 00517 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); 00518 break; 00519 case PWR_GPIO_C: 00520 CLEAR_BIT(PWR->PDCRC, GPIONumber); 00521 break; 00522 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00523 case PWR_GPIO_D: 00524 CLEAR_BIT(PWR->PDCRD, GPIONumber); 00525 break; 00526 case PWR_GPIO_E: 00527 CLEAR_BIT(PWR->PDCRE, GPIONumber); 00528 break; 00529 #endif 00530 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00531 case PWR_GPIO_F: 00532 CLEAR_BIT(PWR->PDCRF, GPIONumber); 00533 break; 00534 case PWR_GPIO_G: 00535 CLEAR_BIT(PWR->PDCRG, GPIONumber); 00536 break; 00537 #endif 00538 case PWR_GPIO_H: 00539 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00540 break; 00541 default: 00542 return HAL_ERROR; 00543 } 00544 00545 return HAL_OK; 00546 } 00547 00548 00549 00550 /** 00551 * @brief Enable pull-up and pull-down configuration. 00552 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in 00553 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. 00554 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding 00555 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). 00556 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there 00557 * is no conflict when setting PUy or PDy bit. 00558 * @retval None 00559 */ 00560 void HAL_PWREx_EnablePullUpPullDownConfig(void) 00561 { 00562 SET_BIT(PWR->CR3, PWR_CR3_APC); 00563 } 00564 00565 00566 /** 00567 * @brief Disable pull-up and pull-down configuration. 00568 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in 00569 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. 00570 * @retval None 00571 */ 00572 void HAL_PWREx_DisablePullUpPullDownConfig(void) 00573 { 00574 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); 00575 } 00576 00577 00578 00579 /** 00580 * @brief Enable SRAM2 content retention in Standby mode. 00581 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in 00582 * Standby mode and its content is kept. 00583 * @retval None 00584 */ 00585 void HAL_PWREx_EnableSRAM2ContentRetention(void) 00586 { 00587 SET_BIT(PWR->CR3, PWR_CR3_RRS); 00588 } 00589 00590 00591 /** 00592 * @brief Disable SRAM2 content retention in Standby mode. 00593 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode 00594 * and its content is lost. 00595 * @retval None 00596 */ 00597 void HAL_PWREx_DisableSRAM2ContentRetention(void) 00598 { 00599 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); 00600 } 00601 00602 00603 00604 00605 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00606 /** 00607 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. 00608 * @retval None 00609 */ 00610 void HAL_PWREx_EnablePVM1(void) 00611 { 00612 SET_BIT(PWR->CR2, PWR_PVM_1); 00613 } 00614 00615 /** 00616 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. 00617 * @retval None 00618 */ 00619 void HAL_PWREx_DisablePVM1(void) 00620 { 00621 CLEAR_BIT(PWR->CR2, PWR_PVM_1); 00622 } 00623 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00624 00625 00626 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00627 /** 00628 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. 00629 * @retval None 00630 */ 00631 void HAL_PWREx_EnablePVM2(void) 00632 { 00633 SET_BIT(PWR->CR2, PWR_PVM_2); 00634 } 00635 00636 /** 00637 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. 00638 * @retval None 00639 */ 00640 void HAL_PWREx_DisablePVM2(void) 00641 { 00642 CLEAR_BIT(PWR->CR2, PWR_PVM_2); 00643 } 00644 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00645 00646 00647 /** 00648 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V. 00649 * @retval None 00650 */ 00651 void HAL_PWREx_EnablePVM3(void) 00652 { 00653 SET_BIT(PWR->CR2, PWR_PVM_3); 00654 } 00655 00656 /** 00657 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V. 00658 * @retval None 00659 */ 00660 void HAL_PWREx_DisablePVM3(void) 00661 { 00662 CLEAR_BIT(PWR->CR2, PWR_PVM_3); 00663 } 00664 00665 00666 /** 00667 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V. 00668 * @retval None 00669 */ 00670 void HAL_PWREx_EnablePVM4(void) 00671 { 00672 SET_BIT(PWR->CR2, PWR_PVM_4); 00673 } 00674 00675 /** 00676 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V. 00677 * @retval None 00678 */ 00679 void HAL_PWREx_DisablePVM4(void) 00680 { 00681 CLEAR_BIT(PWR->CR2, PWR_PVM_4); 00682 } 00683 00684 00685 00686 00687 /** 00688 * @brief Configure the Peripheral Voltage Monitoring (PVM). 00689 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the 00690 * PVM configuration information. 00691 * @note The API configures a single PVM according to the information contained 00692 * in the input structure. To configure several PVMs, the API must be singly 00693 * called for each PVM used. 00694 * @note Refer to the electrical characteristics of your device datasheet for 00695 * more details about the voltage thresholds corresponding to each 00696 * detection level and to each monitored supply. 00697 * @retval HAL status 00698 */ 00699 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) 00700 { 00701 /* Check the parameters */ 00702 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); 00703 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); 00704 00705 00706 /* Configure EXTI 35 to 38 interrupts if so required: 00707 scan thru PVMType to detect which PVMx is set and 00708 configure the corresponding EXTI line accordingly. */ 00709 switch (sConfigPVM->PVMType) 00710 { 00711 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00712 case PWR_PVM_1: 00713 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00714 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); 00715 __HAL_PWR_PVM1_EXTI_DISABLE_IT(); 00716 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); 00717 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); 00718 00719 /* Configure interrupt mode */ 00720 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00721 { 00722 __HAL_PWR_PVM1_EXTI_ENABLE_IT(); 00723 } 00724 00725 /* Configure event mode */ 00726 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00727 { 00728 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); 00729 } 00730 00731 /* Configure the edge */ 00732 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00733 { 00734 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); 00735 } 00736 00737 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00738 { 00739 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); 00740 } 00741 break; 00742 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00743 00744 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00745 case PWR_PVM_2: 00746 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00747 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); 00748 __HAL_PWR_PVM2_EXTI_DISABLE_IT(); 00749 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); 00750 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); 00751 00752 /* Configure interrupt mode */ 00753 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00754 { 00755 __HAL_PWR_PVM2_EXTI_ENABLE_IT(); 00756 } 00757 00758 /* Configure event mode */ 00759 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00760 { 00761 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); 00762 } 00763 00764 /* Configure the edge */ 00765 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00766 { 00767 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); 00768 } 00769 00770 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00771 { 00772 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); 00773 } 00774 break; 00775 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00776 00777 case PWR_PVM_3: 00778 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00779 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); 00780 __HAL_PWR_PVM3_EXTI_DISABLE_IT(); 00781 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); 00782 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); 00783 00784 /* Configure interrupt mode */ 00785 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00786 { 00787 __HAL_PWR_PVM3_EXTI_ENABLE_IT(); 00788 } 00789 00790 /* Configure event mode */ 00791 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00792 { 00793 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); 00794 } 00795 00796 /* Configure the edge */ 00797 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00798 { 00799 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); 00800 } 00801 00802 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00803 { 00804 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); 00805 } 00806 break; 00807 00808 case PWR_PVM_4: 00809 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00810 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); 00811 __HAL_PWR_PVM4_EXTI_DISABLE_IT(); 00812 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); 00813 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); 00814 00815 /* Configure interrupt mode */ 00816 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00817 { 00818 __HAL_PWR_PVM4_EXTI_ENABLE_IT(); 00819 } 00820 00821 /* Configure event mode */ 00822 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00823 { 00824 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); 00825 } 00826 00827 /* Configure the edge */ 00828 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00829 { 00830 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); 00831 } 00832 00833 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00834 { 00835 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); 00836 } 00837 break; 00838 00839 default: 00840 return HAL_ERROR; 00841 00842 } 00843 00844 00845 return HAL_OK; 00846 } 00847 00848 00849 00850 /** 00851 * @brief Enter Low-power Run mode 00852 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. 00853 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the 00854 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. 00855 * Additionally, the clock frequency must be reduced below 2 MHz. 00856 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must 00857 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. 00858 * @retval None 00859 */ 00860 void HAL_PWREx_EnableLowPowerRunMode(void) 00861 { 00862 /* Set Regulator parameter */ 00863 SET_BIT(PWR->CR1, PWR_CR1_LPR); 00864 } 00865 00866 00867 /** 00868 * @brief Exit Low-power Run mode. 00869 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that 00870 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode 00871 * returns HAL_TIMEOUT status). The system clock frequency can then be 00872 * increased above 2 MHz. 00873 * @retval HAL Status 00874 */ 00875 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) 00876 { 00877 uint32_t wait_loop_index = 0; 00878 00879 /* Clear LPR bit */ 00880 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); 00881 00882 /* Wait until REGLPF is reset */ 00883 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); 00884 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))) 00885 { 00886 wait_loop_index--; 00887 } 00888 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) 00889 { 00890 return HAL_TIMEOUT; 00891 } 00892 00893 return HAL_OK; 00894 } 00895 00896 00897 /** 00898 * @brief Enter Stop 0 mode. 00899 * @note In Stop 0 mode, main and low voltage regulators are ON. 00900 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. 00901 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, 00902 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 00903 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 00904 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 00905 * only to the peripheral requesting it. 00906 * SRAM1, SRAM2 and register contents are preserved. 00907 * The BOR is available. 00908 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, 00909 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register 00910 * is set; the MSI oscillator is selected if STOPWUCK is cleared. 00911 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption 00912 * is higher although the startup time is reduced. 00913 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. 00914 * This parameter can be one of the following values: 00915 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction 00916 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction 00917 * @retval None 00918 */ 00919 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) 00920 { 00921 /* Check the parameters */ 00922 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 00923 00924 /* Stop 0 mode with Main Regulator */ 00925 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0); 00926 00927 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00928 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00929 00930 /* Select Stop mode entry --------------------------------------------------*/ 00931 if(STOPEntry == PWR_STOPENTRY_WFI) 00932 { 00933 /* Request Wait For Interrupt */ 00934 __WFI(); 00935 } 00936 else 00937 { 00938 /* Request Wait For Event */ 00939 __SEV(); 00940 __WFE(); 00941 __WFE(); 00942 } 00943 00944 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 00945 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00946 } 00947 00948 00949 /** 00950 * @brief Enter Stop 1 mode. 00951 * @note In Stop 1 mode, only low power voltage regulator is ON. 00952 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. 00953 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, 00954 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 00955 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 00956 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 00957 * only to the peripheral requesting it. 00958 * SRAM1, SRAM2 and register contents are preserved. 00959 * The BOR is available. 00960 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, 00961 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register 00962 * is set; the MSI oscillator is selected if STOPWUCK is cleared. 00963 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. 00964 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. 00965 * This parameter can be one of the following values: 00966 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction 00967 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction 00968 * @retval None 00969 */ 00970 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) 00971 { 00972 /* Check the parameters */ 00973 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 00974 00975 /* Stop 1 mode with Low-Power Regulator */ 00976 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1); 00977 00978 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00979 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00980 00981 /* Select Stop mode entry --------------------------------------------------*/ 00982 if(STOPEntry == PWR_STOPENTRY_WFI) 00983 { 00984 /* Request Wait For Interrupt */ 00985 __WFI(); 00986 } 00987 else 00988 { 00989 /* Request Wait For Event */ 00990 __SEV(); 00991 __WFE(); 00992 __WFE(); 00993 } 00994 00995 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 00996 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00997 } 00998 00999 01000 /** 01001 * @brief Enter Stop 2 mode. 01002 * @note In Stop 2 mode, only low power voltage regulator is ON. 01003 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode. 01004 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, 01005 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability 01006 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after 01007 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only 01008 * to the peripheral requesting it. 01009 * SRAM1, SRAM2 and register contents are preserved. 01010 * The BOR is available. 01011 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. 01012 * Otherwise, Stop 1 mode is entered. 01013 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, 01014 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register 01015 * is set; the MSI oscillator is selected if STOPWUCK is cleared. 01016 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. 01017 * This parameter can be one of the following values: 01018 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction 01019 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction 01020 * @retval None 01021 */ 01022 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) 01023 { 01024 /* Check the parameter */ 01025 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 01026 01027 /* Set Stop mode 2 */ 01028 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2); 01029 01030 /* Set SLEEPDEEP bit of Cortex System Control Register */ 01031 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01032 01033 /* Select Stop mode entry --------------------------------------------------*/ 01034 if(STOPEntry == PWR_STOPENTRY_WFI) 01035 { 01036 /* Request Wait For Interrupt */ 01037 __WFI(); 01038 } 01039 else 01040 { 01041 /* Request Wait For Event */ 01042 __SEV(); 01043 __WFE(); 01044 __WFE(); 01045 } 01046 01047 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 01048 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01049 } 01050 01051 01052 01053 01054 01055 /** 01056 * @brief Enter Shutdown mode. 01057 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched 01058 * off. The voltage regulator is disabled and Vcore domain is powered off. 01059 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. 01060 * The BOR is not available. 01061 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. 01062 * @retval None 01063 */ 01064 void HAL_PWREx_EnterSHUTDOWNMode(void) 01065 { 01066 01067 /* Set Shutdown mode */ 01068 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); 01069 01070 /* Set SLEEPDEEP bit of Cortex System Control Register */ 01071 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01072 01073 /* This option is used to ensure that store operations are completed */ 01074 #if defined ( __CC_ARM) 01075 __force_stores(); 01076 #endif 01077 /* Request Wait For Interrupt */ 01078 __WFI(); 01079 } 01080 01081 01082 01083 01084 /** 01085 * @brief This function handles the PWR PVD/PVMx interrupt request. 01086 * @note This API should be called under the PVD_PVM_IRQHandler(). 01087 * @retval None 01088 */ 01089 void HAL_PWREx_PVD_PVM_IRQHandler(void) 01090 { 01091 /* Check PWR exti flag */ 01092 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 01093 { 01094 /* PWR PVD interrupt user callback */ 01095 HAL_PWR_PVDCallback(); 01096 01097 /* Clear PVD exti pending bit */ 01098 __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 01099 } 01100 /* Next, successively check PVMx exti flags */ 01101 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01102 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET) 01103 { 01104 /* PWR PVM1 interrupt user callback */ 01105 HAL_PWREx_PVM1Callback(); 01106 01107 /* Clear PVM1 exti pending bit */ 01108 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); 01109 } 01110 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01111 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01112 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET) 01113 { 01114 /* PWR PVM2 interrupt user callback */ 01115 HAL_PWREx_PVM2Callback(); 01116 01117 /* Clear PVM2 exti pending bit */ 01118 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); 01119 } 01120 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01121 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET) 01122 { 01123 /* PWR PVM3 interrupt user callback */ 01124 HAL_PWREx_PVM3Callback(); 01125 01126 /* Clear PVM3 exti pending bit */ 01127 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); 01128 } 01129 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET) 01130 { 01131 /* PWR PVM4 interrupt user callback */ 01132 HAL_PWREx_PVM4Callback(); 01133 01134 /* Clear PVM4 exti pending bit */ 01135 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); 01136 } 01137 } 01138 01139 01140 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01141 /** 01142 * @brief PWR PVM1 interrupt callback 01143 * @retval None 01144 */ 01145 __weak void HAL_PWREx_PVM1Callback(void) 01146 { 01147 /* NOTE : This function should not be modified; when the callback is needed, 01148 HAL_PWREx_PVM1Callback() API can be implemented in the user file 01149 */ 01150 } 01151 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01152 01153 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01154 /** 01155 * @brief PWR PVM2 interrupt callback 01156 * @retval None 01157 */ 01158 __weak void HAL_PWREx_PVM2Callback(void) 01159 { 01160 /* NOTE : This function should not be modified; when the callback is needed, 01161 HAL_PWREx_PVM2Callback() API can be implemented in the user file 01162 */ 01163 } 01164 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01165 01166 /** 01167 * @brief PWR PVM3 interrupt callback 01168 * @retval None 01169 */ 01170 __weak void HAL_PWREx_PVM3Callback(void) 01171 { 01172 /* NOTE : This function should not be modified; when the callback is needed, 01173 HAL_PWREx_PVM3Callback() API can be implemented in the user file 01174 */ 01175 } 01176 01177 /** 01178 * @brief PWR PVM4 interrupt callback 01179 * @retval None 01180 */ 01181 __weak void HAL_PWREx_PVM4Callback(void) 01182 { 01183 /* NOTE : This function should not be modified; when the callback is needed, 01184 HAL_PWREx_PVM4Callback() API can be implemented in the user file 01185 */ 01186 } 01187 01188 01189 /** 01190 * @} 01191 */ 01192 01193 /** 01194 * @} 01195 */ 01196 01197 #endif /* HAL_PWR_MODULE_ENABLED */ 01198 /** 01199 * @} 01200 */ 01201 01202 /** 01203 * @} 01204 */ 01205 01206 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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